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1965aae3 PA |
1 | #ifndef _ASM_X86_ACPI_H |
2 | #define _ASM_X86_ACPI_H | |
c1c30634 | 3 | |
0b80fc72 TG |
4 | /* |
5 | * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org> | |
7 | * | |
8 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
25 | */ | |
26 | #include <acpi/pdc_intel.h> | |
c1c30634 | 27 | |
0b80fc72 | 28 | #include <asm/numa.h> |
c1c30634 | 29 | #include <asm/processor.h> |
bde6f5f5 | 30 | #include <asm/mmu.h> |
4c1cbafb | 31 | #include <asm/mpspec.h> |
c1c30634 | 32 | |
0b80fc72 TG |
33 | #define COMPILER_DEPENDENT_INT64 long long |
34 | #define COMPILER_DEPENDENT_UINT64 unsigned long long | |
35 | ||
36 | /* | |
37 | * Calling conventions: | |
38 | * | |
39 | * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads) | |
40 | * ACPI_EXTERNAL_XFACE - External ACPI interfaces | |
41 | * ACPI_INTERNAL_XFACE - Internal ACPI interfaces | |
42 | * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces | |
43 | */ | |
44 | #define ACPI_SYSTEM_XFACE | |
45 | #define ACPI_EXTERNAL_XFACE | |
46 | #define ACPI_INTERNAL_XFACE | |
47 | #define ACPI_INTERNAL_VAR_XFACE | |
48 | ||
49 | /* Asm macros */ | |
50 | ||
51 | #define ACPI_ASM_MACROS | |
52 | #define BREAKPOINT3 | |
53 | #define ACPI_DISABLE_IRQS() local_irq_disable() | |
54 | #define ACPI_ENABLE_IRQS() local_irq_enable() | |
55 | #define ACPI_FLUSH_CPU_CACHE() wbinvd() | |
56 | ||
57 | int __acpi_acquire_global_lock(unsigned int *lock); | |
58 | int __acpi_release_global_lock(unsigned int *lock); | |
59 | ||
60 | #define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ | |
61 | ((Acq) = __acpi_acquire_global_lock(&facs->global_lock)) | |
62 | ||
63 | #define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ | |
64 | ((Acq) = __acpi_release_global_lock(&facs->global_lock)) | |
65 | ||
66 | /* | |
67 | * Math helper asm macros | |
68 | */ | |
69 | #define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \ | |
70 | asm("divl %2;" \ | |
8dbeeb24 JP |
71 | : "=a"(q32), "=d"(r32) \ |
72 | : "r"(d32), \ | |
0b80fc72 TG |
73 | "0"(n_lo), "1"(n_hi)) |
74 | ||
75 | ||
76 | #define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \ | |
77 | asm("shrl $1,%2 ;" \ | |
78 | "rcrl $1,%3;" \ | |
8dbeeb24 JP |
79 | : "=r"(n_hi), "=r"(n_lo) \ |
80 | : "0"(n_hi), "1"(n_lo)) | |
0b80fc72 TG |
81 | |
82 | #ifdef CONFIG_ACPI | |
83 | extern int acpi_lapic; | |
84 | extern int acpi_ioapic; | |
85 | extern int acpi_noirq; | |
86 | extern int acpi_strict; | |
87 | extern int acpi_disabled; | |
0b80fc72 TG |
88 | extern int acpi_pci_disabled; |
89 | extern int acpi_skip_timer_override; | |
90 | extern int acpi_use_timer_override; | |
7f74f8f2 | 91 | extern int acpi_fix_pin2_polarity; |
0b80fc72 | 92 | |
6697c052 HH |
93 | extern u8 acpi_sci_flags; |
94 | extern int acpi_sci_override_gsi; | |
95 | void acpi_pic_sci_set_trigger(unsigned int, u16); | |
96 | ||
90f6881e JF |
97 | extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi, |
98 | int trigger, int polarity); | |
99 | ||
0b80fc72 TG |
100 | static inline void disable_acpi(void) |
101 | { | |
102 | acpi_disabled = 1; | |
0b80fc72 TG |
103 | acpi_pci_disabled = 1; |
104 | acpi_noirq = 1; | |
105 | } | |
106 | ||
0b80fc72 TG |
107 | extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq); |
108 | ||
109 | static inline void acpi_noirq_set(void) { acpi_noirq = 1; } | |
110 | static inline void acpi_disable_pci(void) | |
111 | { | |
112 | acpi_pci_disabled = 1; | |
113 | acpi_noirq_set(); | |
114 | } | |
0b80fc72 | 115 | |
f1a2003e RW |
116 | /* Low-level suspend routine. */ |
117 | extern int acpi_suspend_lowlevel(void); | |
0b80fc72 | 118 | |
d1ee4335 | 119 | extern const unsigned char acpi_wakeup_code[]; |
0b80fc72 TG |
120 | |
121 | /* early initialization routine */ | |
196cf0d6 | 122 | extern void acpi_reserve_wakeup_memory(void); |
0b80fc72 | 123 | |
c1c30634 AS |
124 | /* |
125 | * Check if the CPU can handle C2 and deeper | |
126 | */ | |
127 | static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) | |
128 | { | |
129 | /* | |
130 | * Early models (<=5) of AMD Opterons are not supposed to go into | |
131 | * C2 state. | |
132 | * | |
133 | * Steppings 0x0A and later are good | |
134 | */ | |
135 | if (boot_cpu_data.x86 == 0x0F && | |
136 | boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
137 | boot_cpu_data.x86_model <= 0x05 && | |
138 | boot_cpu_data.x86_mask < 0x0A) | |
139 | return 1; | |
02c68a02 | 140 | else if (amd_e400_c1e_detected) |
a8d68290 | 141 | return 1; |
c1c30634 AS |
142 | else |
143 | return max_cstate; | |
144 | } | |
145 | ||
1d9cb470 AC |
146 | static inline bool arch_has_acpi_pdc(void) |
147 | { | |
148 | struct cpuinfo_x86 *c = &cpu_data(0); | |
149 | return (c->x86_vendor == X86_VENDOR_INTEL || | |
150 | c->x86_vendor == X86_VENDOR_CENTAUR); | |
151 | } | |
152 | ||
6c5807d7 AC |
153 | static inline void arch_acpi_set_pdc_bits(u32 *buf) |
154 | { | |
155 | struct cpuinfo_x86 *c = &cpu_data(0); | |
156 | ||
157 | buf[2] |= ACPI_PDC_C_CAPABILITY_SMP; | |
158 | ||
159 | if (cpu_has(c, X86_FEATURE_EST)) | |
160 | buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; | |
161 | ||
162 | if (cpu_has(c, X86_FEATURE_ACPI)) | |
163 | buf[2] |= ACPI_PDC_T_FFH; | |
164 | ||
165 | /* | |
166 | * If mwait/monitor is unsupported, C2/C3_FFH will be disabled | |
167 | */ | |
168 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
169 | buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); | |
170 | } | |
171 | ||
0b80fc72 TG |
172 | #else /* !CONFIG_ACPI */ |
173 | ||
174 | #define acpi_lapic 0 | |
175 | #define acpi_ioapic 0 | |
176 | static inline void acpi_noirq_set(void) { } | |
177 | static inline void acpi_disable_pci(void) { } | |
178 | static inline void disable_acpi(void) { } | |
179 | ||
180 | #endif /* !CONFIG_ACPI */ | |
181 | ||
182 | #define ARCH_HAS_POWER_INIT 1 | |
183 | ||
0b80fc72 TG |
184 | #ifdef CONFIG_ACPI_NUMA |
185 | extern int acpi_numa; | |
a9aec56a | 186 | extern int x86_acpi_numa_init(void); |
4e76f4e6 | 187 | #endif /* CONFIG_ACPI_NUMA */ |
0b80fc72 | 188 | |
bde6f5f5 VP |
189 | #define acpi_unlazy_tlb(x) leave_mm(x) |
190 | ||
1965aae3 | 191 | #endif /* _ASM_X86_ACPI_H */ |