[deliverable/linux.git] / arch / x86 / include / asm / apic.h

#ifndef _ASM_X86_APIC_H
#define _ASM_X86_APIC_H

#include <linux/cpumask.h>
#include <linux/pm.h>

#include <asm/alternative.h>
#include <asm/cpufeature.h>
#include <asm/apicdef.h>
#include <linux/atomic.h>
#include <asm/fixmap.h>
#include <asm/mpspec.h>
#include <asm/msr.h>
#include <asm/idle.h>

#define ARCH_APICTIMER_STOPS_ON_C3	1

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

/* Macros for apic_extnmi which controls external NMI masking */
#define APIC_EXTNMI_BSP		0 /* Default */
#define APIC_EXTNMI_ALL		1
#define APIC_EXTNMI_NONE	2

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)


#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
extern void generic_apic_probe(void);
#else
static inline void generic_apic_probe(void)
{
}
#endif

#ifdef CONFIG_X86_LOCAL_APIC

extern unsigned int apic_verbosity;
extern int local_apic_timer_c2_ok;

extern int disable_apic;
extern unsigned int lapic_timer_frequency;

#ifdef CONFIG_SMP
extern void __inquire_remote_apic(int apicid);
#else /* CONFIG_SMP */
static inline void __inquire_remote_apic(int apicid)
{
}
#endif /* CONFIG_SMP */

static inline void default_inquire_remote_apic(int apicid)
{
	if (apic_verbosity >= APIC_DEBUG)
		__inquire_remote_apic(apicid);
}

/*
 * With 82489DX we can't rely on apic feature bit
 * retrieved via cpuid but still have to deal with
 * such an apic chip so we assume that SMP configuration
 * is found from MP table (64bit case uses ACPI mostly
 * which set smp presence flag as well so we are safe
 * to use this helper too).
 */
static inline bool apic_from_smp_config(void)
{
	return smp_found_config && !disable_apic;
}

/*
 * Basic functions accessing APICs.
 */
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#endif

extern int setup_profiling_timer(unsigned int);

static inline void native_apic_mem_write(u32 reg, u32 v)
{
	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);

	alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
		       ASM_OUTPUT2("0" (v), "m" (*addr)));
}

static inline u32 native_apic_mem_read(u32 reg)
{
	return *((volatile u32 *)(APIC_BASE + reg));
}

extern void native_apic_wait_icr_idle(void);
extern u32 native_safe_apic_wait_icr_idle(void);
extern void native_apic_icr_write(u32 low, u32 id);
extern u64 native_apic_icr_read(void);

static inline bool apic_is_x2apic_enabled(void)
{
	u64 msr;

	if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
		return false;
	return msr & X2APIC_ENABLE;
}

extern void enable_IR_x2apic(void);

extern int get_physical_broadcast(void);

extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
extern void lapic_shutdown(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void setup_local_APIC(void);
extern void init_apic_mappings(void);
void register_lapic_address(unsigned long address);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern int APIC_init_uniprocessor(void);

#ifdef CONFIG_X86_64
static inline int apic_force_enable(unsigned long addr)
{
	return -1;
}
#else
extern int apic_force_enable(unsigned long addr);
#endif

extern int apic_bsp_setup(bool upmode);
extern void apic_ap_setup(void);

/*
 * On 32bit this is mach-xxx local
 */
#ifdef CONFIG_X86_64
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
	return 0;
}
#endif

extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);

#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok		1
static inline void init_apic_mappings(void) { }
static inline void disable_local_APIC(void) { }
# define setup_boot_APIC_clock x86_init_noop
# define setup_secondary_APIC_clock x86_init_noop
#endif /* !CONFIG_X86_LOCAL_APIC */

#ifdef CONFIG_X86_X2APIC
/*
 * Make previous memory operations globally visible before
 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 * mfence for this.
 */
static inline void x2apic_wrmsr_fence(void)
{
	asm volatile("mfence" : : : "memory");
}

static inline void native_apic_msr_write(u32 reg, u32 v)
{
	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
	    reg == APIC_LVR)
		return;

	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
}

static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
{
	wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
}

static inline u32 native_apic_msr_read(u32 reg)
{
	u64 msr;

	if (reg == APIC_DFR)
		return -1;

	rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
	return (u32)msr;
}

static inline void native_x2apic_wait_icr_idle(void)
{
	/* no need to wait for icr idle in x2apic */
	return;
}

static inline u32 native_safe_x2apic_wait_icr_idle(void)
{
	/* no need to wait for icr idle in x2apic */
	return 0;
}

static inline void native_x2apic_icr_write(u32 low, u32 id)
{
	wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
}

static inline u64 native_x2apic_icr_read(void)
{
	unsigned long val;

	rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
	return val;
}

extern int x2apic_mode;
extern int x2apic_phys;
extern void __init check_x2apic(void);
extern void x2apic_setup(void);
static inline int x2apic_enabled(void)
{
	return cpu_has_x2apic && apic_is_x2apic_enabled();
}

#define x2apic_supported()	(cpu_has_x2apic)
#else /* !CONFIG_X86_X2APIC */
static inline void check_x2apic(void) { }
static inline void x2apic_setup(void) { }
static inline int x2apic_enabled(void) { return 0; }

#define x2apic_mode		(0)
#define	x2apic_supported()	(0)
#endif /* !CONFIG_X86_X2APIC */

#ifdef CONFIG_X86_64
#define	SET_APIC_ID(x)		(apic->set_apic_id(x))
#else

#endif

/*
 * Copyright 2004 James Cleverdon, IBM.
 * Subject to the GNU Public License, v.2
 *
 * Generic APIC sub-arch data struct.
 *
 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 * James Cleverdon.
 */
struct apic {
	char *name;

	int (*probe)(void);
	int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
	int (*apic_id_valid)(int apicid);
	int (*apic_id_registered)(void);

	u32 irq_delivery_mode;
	u32 irq_dest_mode;

	const struct cpumask *(*target_cpus)(void);

	int disable_esr;

	int dest_logical;
	unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);

	void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
					 const struct cpumask *mask);
	void (*init_apic_ldr)(void);

	void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);

	void (*setup_apic_routing)(void);
	int (*cpu_present_to_apicid)(int mps_cpu);
	void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
	int (*check_phys_apicid_present)(int phys_apicid);
	int (*phys_pkg_id)(int cpuid_apic, int index_msb);

	unsigned int (*get_apic_id)(unsigned long x);
	unsigned long (*set_apic_id)(unsigned int id);
	unsigned long apic_id_mask;

	int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
				      const struct cpumask *andmask,
				      unsigned int *apicid);

	/* ipi */
	void (*send_IPI)(int cpu, int vector);
	void (*send_IPI_mask)(const struct cpumask *mask, int vector);
	void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
					 int vector);
	void (*send_IPI_allbutself)(int vector);
	void (*send_IPI_all)(int vector);
	void (*send_IPI_self)(int vector);

	/* wakeup_secondary_cpu */
	int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);

	void (*inquire_remote_apic)(int apicid);

	/* apic ops */
	u32 (*read)(u32 reg);
	void (*write)(u32 reg, u32 v);
	/*
	 * ->eoi_write() has the same signature as ->write().
	 *
	 * Drivers can support both ->eoi_write() and ->write() by passing the same
	 * callback value. Kernel can override ->eoi_write() and fall back
	 * on write for EOI.
	 */
	void (*eoi_write)(u32 reg, u32 v);
	u64 (*icr_read)(void);
	void (*icr_write)(u32 low, u32 high);
	void (*wait_icr_idle)(void);
	u32 (*safe_wait_icr_idle)(void);

#ifdef CONFIG_X86_32
	/*
	 * Called very early during boot from get_smp_config().  It should
	 * return the logical apicid.  x86_[bios]_cpu_to_apicid is
	 * initialized before this function is called.
	 *
	 * If logical apicid can't be determined that early, the function
	 * may return BAD_APICID.  Logical apicid will be configured after
	 * init_apic_ldr() while bringing up CPUs.  Note that NUMA affinity
	 * won't be applied properly during early boot in this case.
	 */
	int (*x86_32_early_logical_apicid)(int cpu);
#endif
};

/*
 * Pointer to the local APIC driver in use on this system (there's
 * always just one such driver in use - the kernel decides via an
 * early probing process which one it picks - and then sticks to it):
 */
extern struct apic *apic;

/*
 * APIC drivers are probed based on how they are listed in the .apicdrivers
 * section. So the order is important and enforced by the ordering
 * of different apic driver files in the Makefile.
 *
 * For the files having two apic drivers, we use apic_drivers()
 * to enforce the order with in them.
 */
#define apic_driver(sym)					\
	static const struct apic *__apicdrivers_##sym __used		\
	__aligned(sizeof(struct apic *))			\
	__section(.apicdrivers) = { &sym }

#define apic_drivers(sym1, sym2)					\
	static struct apic *__apicdrivers_##sym1##sym2[2] __used	\
	__aligned(sizeof(struct apic *))				\
	__section(.apicdrivers) = { &sym1, &sym2 }

extern struct apic *__apicdrivers[], *__apicdrivers_end[];

/*
 * APIC functionality to boot other CPUs - only used on SMP:
 */
#ifdef CONFIG_SMP
extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
#endif

#ifdef CONFIG_X86_LOCAL_APIC

static inline u32 apic_read(u32 reg)
{
	return apic->read(reg);
}

static inline void apic_write(u32 reg, u32 val)
{
	apic->write(reg, val);
}

static inline void apic_eoi(void)
{
	apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
}

static inline u64 apic_icr_read(void)
{
	return apic->icr_read();
}

static inline void apic_icr_write(u32 low, u32 high)
{
	apic->icr_write(low, high);
}

static inline void apic_wait_icr_idle(void)
{
	apic->wait_icr_idle();
}

static inline u32 safe_apic_wait_icr_idle(void)
{
	return apic->safe_wait_icr_idle();
}

extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));

#else /* CONFIG_X86_LOCAL_APIC */

static inline u32 apic_read(u32 reg) { return 0; }
static inline void apic_write(u32 reg, u32 val) { }
static inline void apic_eoi(void) { }
static inline u64 apic_icr_read(void) { return 0; }
static inline void apic_icr_write(u32 low, u32 high) { }
static inline void apic_wait_icr_idle(void) { }
static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}

#endif /* CONFIG_X86_LOCAL_APIC */

static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction
	 * ... yummie.
	 */
	apic_eoi();
}

static inline unsigned default_get_apic_id(unsigned long x)
{
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));

	if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
		return (x >> 24) & 0xFF;
	else
		return (x >> 24) & 0x0F;
}

/*
 * Warm reset vector position:
 */
#define TRAMPOLINE_PHYS_LOW		0x467
#define TRAMPOLINE_PHYS_HIGH		0x469

#ifdef CONFIG_X86_64
extern void apic_send_IPI_self(int vector);

DECLARE_PER_CPU(int, x2apic_extra_bits);

extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);
#endif

extern void generic_bigsmp_probe(void);


#ifdef CONFIG_X86_LOCAL_APIC

#include <asm/smp.h>

#define APIC_DFR_VALUE	(APIC_DFR_FLAT)

static inline const struct cpumask *default_target_cpus(void)
{
#ifdef CONFIG_SMP
	return cpu_online_mask;
#else
	return cpumask_of(0);
#endif
}

static inline const struct cpumask *online_target_cpus(void)
{
	return cpu_online_mask;
}

DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);


static inline unsigned int read_apic_id(void)
{
	unsigned int reg;

	reg = apic_read(APIC_ID);

	return apic->get_apic_id(reg);
}

static inline int default_apic_id_valid(int apicid)
{
	return (apicid < 255);
}

extern int default_acpi_madt_oem_check(char *, char *);

extern void default_setup_apic_routing(void);

extern struct apic apic_noop;

#ifdef CONFIG_X86_32

static inline int noop_x86_32_early_logical_apicid(int cpu)
{
	return BAD_APICID;
}

/*
 * Set up the logical destination ID.
 *
 * Intel recommends to set DFR, LDR and TPR before enabling
 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 * document number 292116).  So here it goes...
 */
extern void default_init_apic_ldr(void);

static inline int default_apic_id_registered(void)
{
	return physid_isset(read_apic_id(), phys_cpu_present_map);
}

static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
{
	return cpuid_apic >> index_msb;
}

#endif

static inline int
flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
			    const struct cpumask *andmask,
			    unsigned int *apicid)
{
	unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
				 cpumask_bits(andmask)[0] &
				 cpumask_bits(cpu_online_mask)[0] &
				 APIC_ALL_CPUS;

	if (likely(cpu_mask)) {
		*apicid = (unsigned int)cpu_mask;
		return 0;
	} else {
		return -EINVAL;
	}
}

extern int
default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
			       const struct cpumask *andmask,
			       unsigned int *apicid);

static inline void
flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
			      const struct cpumask *mask)
{
	/* Careful. Some cpus do not strictly honor the set of cpus
	 * specified in the interrupt destination when using lowest
	 * priority interrupt delivery mode.
	 *
	 * In particular there was a hyperthreading cpu observed to
	 * deliver interrupts to the wrong hyperthread when only one
	 * hyperthread was specified in the interrupt desitination.
	 */
	cpumask_clear(retmask);
	cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
}

static inline void
default_vector_allocation_domain(int cpu, struct cpumask *retmask,
				 const struct cpumask *mask)
{
	cpumask_copy(retmask, cpumask_of(cpu));
}

static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
{
	return physid_isset(apicid, *map);
}

static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
{
	*retmap = *phys_map;
}

static inline int __default_cpu_present_to_apicid(int mps_cpu)
{
	if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
	else
		return BAD_APICID;
}

static inline int
__default_check_phys_apicid_present(int phys_apicid)
{
	return physid_isset(phys_apicid, phys_cpu_present_map);
}

#ifdef CONFIG_X86_32
static inline int default_cpu_present_to_apicid(int mps_cpu)
{
	return __default_cpu_present_to_apicid(mps_cpu);
}

static inline int
default_check_phys_apicid_present(int phys_apicid)
{
	return __default_check_phys_apicid_present(phys_apicid);
}
#else
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);
#endif

#endif /* CONFIG_X86_LOCAL_APIC */
extern void irq_enter(void);
extern void irq_exit(void);

static inline void entering_irq(void)
{
	irq_enter();
	exit_idle();
}

static inline void entering_ack_irq(void)
{
	ack_APIC_irq();
	entering_irq();
}

static inline void ipi_entering_ack_irq(void)
{
	ack_APIC_irq();
	irq_enter();
}

static inline void exiting_irq(void)
{
	irq_exit();
}

static inline void exiting_ack_irq(void)
{
	irq_exit();
	/* Ack only at the end to avoid potential reentry */
	ack_APIC_irq();
}

extern void ioapic_zap_locks(void);

#endif /* _ASM_X86_APIC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_APIC_H
1965aae3 PA	2	#define _ASM_X86_APIC_H
67c5fc5c	3
e2780a68	4	#include <linux/cpumask.h>
e2780a68	5	#include <linux/pm.h>
593f4a78 MR	6
593f4a78 MR	7	#include <asm/alternative.h>
e2780a68	8	#include <asm/cpufeature.h>
e2780a68	9	#include <asm/apicdef.h>
60063497	10	#include <linux/atomic.h>
e2780a68 IM	11	#include <asm/fixmap.h>
e2780a68 IM	12	#include <asm/mpspec.h>
13c88fb5	13	#include <asm/msr.h>
eddc0e92	14	#include <asm/idle.h>
67c5fc5c TG	15
	16	#define ARCH_APICTIMER_STOPS_ON_C3 1
	17
67c5fc5c TG	18	/*
	19	* Debugging macros
	20	*/
	21	#define APIC_QUIET 0
	22	#define APIC_VERBOSE 1
	23	#define APIC_DEBUG 2
	24
b7c4948e HK	25	/* Macros for apic_extnmi which controls external NMI masking */
	26	#define APIC_EXTNMI_BSP 0 /* Default */
	27	#define APIC_EXTNMI_ALL 1
	28	#define APIC_EXTNMI_NONE 2
	29
67c5fc5c TG	30	/*
	31	* Define the default level of output to be very little
	32	* This can be turned up by using apic=verbose for more
	33	* information and apic=debug for _lots_ of information.
	34	* apic_verbosity is defined in apic.c
	35	*/
	36	#define apic_printk(v, s, a...) do { \
	37	if ((v) <= apic_verbosity) \
	38	printk(s, ##a); \
	39	} while (0)
	40
	41
160d8dac	42	#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
67c5fc5c	43	extern void generic_apic_probe(void);
160d8dac IM	44	#else
	45	static inline void generic_apic_probe(void)
	46	{
	47	}
	48	#endif
67c5fc5c TG	49
	50	#ifdef CONFIG_X86_LOCAL_APIC
	51
baa13188	52	extern unsigned int apic_verbosity;
67c5fc5c	53	extern int local_apic_timer_c2_ok;
67c5fc5c	54
3c999f14	55	extern int disable_apic;
1ade93ef	56	extern unsigned int lapic_timer_frequency;
0939e4fd IM	57
	58	#ifdef CONFIG_SMP
	59	extern void __inquire_remote_apic(int apicid);
	60	#else /* CONFIG_SMP */
	61	static inline void __inquire_remote_apic(int apicid)
	62	{
	63	}
	64	#endif /* CONFIG_SMP */
	65
	66	static inline void default_inquire_remote_apic(int apicid)
	67	{
	68	if (apic_verbosity >= APIC_DEBUG)
	69	__inquire_remote_apic(apicid);
	70	}
	71
8312136f CG	72	/*
	73	* With 82489DX we can't rely on apic feature bit
	74	* retrieved via cpuid but still have to deal with
	75	* such an apic chip so we assume that SMP configuration
	76	* is found from MP table (64bit case uses ACPI mostly
	77	* which set smp presence flag as well so we are safe
	78	* to use this helper too).
	79	*/
	80	static inline bool apic_from_smp_config(void)
	81	{
	82	return smp_found_config && !disable_apic;
	83	}
	84
67c5fc5c TG	85	/*
	86	* Basic functions accessing APICs.
	87	*/
	88	#ifdef CONFIG_PARAVIRT
	89	#include <asm/paravirt.h>
96a388de	90	#endif
67c5fc5c	91
2b97df06	92	extern int setup_profiling_timer(unsigned int);
aa7d8e25	93
1b374e4d	94	static inline void native_apic_mem_write(u32 reg, u32 v)
67c5fc5c	95	{
593f4a78	96	volatile u32 addr = (volatile u32 )(APIC_BASE + reg);
67c5fc5c	97
a930dc45	98	alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
593f4a78 MR	99	ASM_OUTPUT2("=r" (v), "=m" (*addr)),
593f4a78 MR	100	ASM_OUTPUT2("0" (v), "m" (*addr)));
67c5fc5c TG	101	}
67c5fc5c TG	102
1b374e4d	103	static inline u32 native_apic_mem_read(u32 reg)
67c5fc5c TG	104	{
	105	return ((volatile u32 )(APIC_BASE + reg));
	106	}
	107
c1eeb2de YL	108	extern void native_apic_wait_icr_idle(void);
	109	extern u32 native_safe_apic_wait_icr_idle(void);
	110	extern void native_apic_icr_write(u32 low, u32 id);
	111	extern u64 native_apic_icr_read(void);
	112
8d806960 TG	113	static inline bool apic_is_x2apic_enabled(void)
	114	{
	115	u64 msr;
	116
	117	if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
	118	return false;
	119	return msr & X2APIC_ENABLE;
	120	}
	121
e02ae387 PB	122	extern void enable_IR_x2apic(void);
	123
	124	extern int get_physical_broadcast(void);
	125
	126	extern int lapic_get_maxlvt(void);
	127	extern void clear_local_APIC(void);
	128	extern void disconnect_bsp_APIC(int virt_wire_setup);
	129	extern void disable_local_APIC(void);
	130	extern void lapic_shutdown(void);
	131	extern void sync_Arb_IDs(void);
	132	extern void init_bsp_APIC(void);
	133	extern void setup_local_APIC(void);
	134	extern void init_apic_mappings(void);
	135	void register_lapic_address(unsigned long address);
	136	extern void setup_boot_APIC_clock(void);
	137	extern void setup_secondary_APIC_clock(void);
	138	extern int APIC_init_uniprocessor(void);
	139
	140	#ifdef CONFIG_X86_64
	141	static inline int apic_force_enable(unsigned long addr)
	142	{
	143	return -1;
	144	}
	145	#else
	146	extern int apic_force_enable(unsigned long addr);
	147	#endif
	148
	149	extern int apic_bsp_setup(bool upmode);
	150	extern void apic_ap_setup(void);
	151
	152	/*
	153	* On 32bit this is mach-xxx local
	154	*/
	155	#ifdef CONFIG_X86_64
	156	extern int apic_is_clustered_box(void);
	157	#else
	158	static inline int apic_is_clustered_box(void)
	159	{
	160	return 0;
	161	}
	162	#endif
	163
	164	extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
	165
	166	#else /* !CONFIG_X86_LOCAL_APIC */
	167	static inline void lapic_shutdown(void) { }
	168	#define local_apic_timer_c2_ok 1
	169	static inline void init_apic_mappings(void) { }
	170	static inline void disable_local_APIC(void) { }
	171	# define setup_boot_APIC_clock x86_init_noop
	172	# define setup_secondary_APIC_clock x86_init_noop
	173	#endif /* !CONFIG_X86_LOCAL_APIC */
	174
d0b03bd1	175	#ifdef CONFIG_X86_X2APIC
ce4e240c SS	176	/*
	177	* Make previous memory operations globally visible before
	178	* sending the IPI through x2apic wrmsr. We need a serializing instruction or
	179	* mfence for this.
	180	*/
	181	static inline void x2apic_wrmsr_fence(void)
	182	{
	183	asm volatile("mfence" : : : "memory");
	184	}
	185
13c88fb5 SS	186	static inline void native_apic_msr_write(u32 reg, u32 v)
	187	{
	188	if (reg == APIC_DFR \|\| reg == APIC_ID \|\| reg == APIC_LDR \|\|
	189	reg == APIC_LVR)
	190	return;
	191
	192	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
	193	}
	194
0ab711ae MT	195	static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
	196	{
	197	wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
	198	}
	199
13c88fb5 SS	200	static inline u32 native_apic_msr_read(u32 reg)
13c88fb5 SS	201	{
0059b243	202	u64 msr;
13c88fb5 SS	203
	204	if (reg == APIC_DFR)
	205	return -1;
	206
0059b243 AK	207	rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
0059b243 AK	208	return (u32)msr;
13c88fb5 SS	209	}
13c88fb5 SS	210
c1eeb2de YL	211	static inline void native_x2apic_wait_icr_idle(void)
	212	{
	213	/* no need to wait for icr idle in x2apic */
	214	return;
	215	}
	216
	217	static inline u32 native_safe_x2apic_wait_icr_idle(void)
	218	{
	219	/* no need to wait for icr idle in x2apic */
	220	return 0;
	221	}
	222
	223	static inline void native_x2apic_icr_write(u32 low, u32 id)
	224	{
	225	wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 \| low);
	226	}
	227
	228	static inline u64 native_x2apic_icr_read(void)
	229	{
	230	unsigned long val;
	231
	232	rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
	233	return val;
	234	}
	235
81a46dd8	236	extern int x2apic_mode;
fc1edaf9	237	extern int x2apic_phys;
d524165c	238	extern void __init check_x2apic(void);
659006bf	239	extern void x2apic_setup(void);
a11b5abe YL	240	static inline int x2apic_enabled(void)
a11b5abe YL	241	{
8d806960	242	return cpu_has_x2apic && apic_is_x2apic_enabled();
a11b5abe	243	}
fc1edaf9 SS	244
fc1edaf9 SS	245	#define x2apic_supported() (cpu_has_x2apic)
e02ae387	246	#else /* !CONFIG_X86_X2APIC */
55eae7de	247	static inline void check_x2apic(void) { }
659006bf	248	static inline void x2apic_setup(void) { }
55eae7de	249	static inline int x2apic_enabled(void) { return 0; }
cf6567fe	250
81a46dd8	251	#define x2apic_mode (0)
81a46dd8	252	#define x2apic_supported() (0)
e02ae387	253	#endif /* !CONFIG_X86_X2APIC */
67c5fc5c	254
1f75ed0c IM	255	#ifdef CONFIG_X86_64
	256	#define SET_APIC_ID(x) (apic->set_apic_id(x))
	257	#else
	258
1f75ed0c IM	259	#endif
1f75ed0c IM	260
e2780a68 IM	261	/*
	262	* Copyright 2004 James Cleverdon, IBM.
	263	* Subject to the GNU Public License, v.2
	264	*
	265	* Generic APIC sub-arch data struct.
	266	*
	267	* Hacked for x86-64 by James Cleverdon from i386 architecture code by
	268	* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
	269	* James Cleverdon.
	270	*/
be163a15	271	struct apic {
e2780a68 IM	272	char *name;
	273
	274	int (*probe)(void);
	275	int (acpi_madt_oem_check)(char oem_id, char *oem_table_id);
fa63030e	276	int (*apic_id_valid)(int apicid);
e2780a68 IM	277	int (*apic_id_registered)(void);
	278
	279	u32 irq_delivery_mode;
	280	u32 irq_dest_mode;
	281
	282	const struct cpumask (target_cpus)(void);
	283
	284	int disable_esr;
	285
	286	int dest_logical;
7abc0753	287	unsigned long (check_apicid_used)(physid_mask_t map, int apicid);
e2780a68	288
1ac322d0 SS	289	void (vector_allocation_domain)(int cpu, struct cpumask retmask,
1ac322d0 SS	290	const struct cpumask *mask);
e2780a68 IM	291	void (*init_apic_ldr)(void);
e2780a68 IM	292
7abc0753	293	void (ioapic_phys_id_map)(physid_mask_t phys_map, physid_mask_t *retmap);
e2780a68 IM	294
e2780a68 IM	295	void (*setup_apic_routing)(void);
e2780a68	296	int (*cpu_present_to_apicid)(int mps_cpu);
7abc0753	297	void (apicid_to_cpu_present)(int phys_apicid, physid_mask_t retmap);
e11dadab	298	int (*check_phys_apicid_present)(int phys_apicid);
e2780a68 IM	299	int (*phys_pkg_id)(int cpuid_apic, int index_msb);
e2780a68 IM	300
e2780a68 IM	301	unsigned int (*get_apic_id)(unsigned long x);
	302	unsigned long (*set_apic_id)(unsigned int id);
	303	unsigned long apic_id_mask;
	304
ff164324 AG	305	int (cpu_mask_to_apicid_and)(const struct cpumask cpumask,
	306	const struct cpumask *andmask,
	307	unsigned int *apicid);
e2780a68 IM	308
e2780a68 IM	309	/* ipi */
539da787	310	void (*send_IPI)(int cpu, int vector);
e2780a68 IM	311	void (send_IPI_mask)(const struct cpumask mask, int vector);
	312	void (send_IPI_mask_allbutself)(const struct cpumask mask,
	313	int vector);
	314	void (*send_IPI_allbutself)(int vector);
	315	void (*send_IPI_all)(int vector);
	316	void (*send_IPI_self)(int vector);
	317
	318	/* wakeup_secondary_cpu */
1f5bcabf	319	int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
e2780a68	320
e2780a68 IM	321	void (*inquire_remote_apic)(int apicid);
	322
	323	/* apic ops */
	324	u32 (*read)(u32 reg);
	325	void (*write)(u32 reg, u32 v);
2a43195d MT	326	/*
	327	* ->eoi_write() has the same signature as ->write().
	328	*
	329	* Drivers can support both ->eoi_write() and ->write() by passing the same
	330	* callback value. Kernel can override ->eoi_write() and fall back
	331	* on write for EOI.
	332	*/
	333	void (*eoi_write)(u32 reg, u32 v);
e2780a68 IM	334	u64 (*icr_read)(void);
	335	void (*icr_write)(u32 low, u32 high);
	336	void (*wait_icr_idle)(void);
	337	u32 (*safe_wait_icr_idle)(void);
acb8bc09 TH	338
	339	#ifdef CONFIG_X86_32
	340	/*
	341	* Called very early during boot from get_smp_config(). It should
	342	* return the logical apicid. x86_[bios]_cpu_to_apicid is
	343	* initialized before this function is called.
	344	*
	345	* If logical apicid can't be determined that early, the function
	346	* may return BAD_APICID. Logical apicid will be configured after
	347	* init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
	348	* won't be applied properly during early boot in this case.
	349	*/
	350	int (*x86_32_early_logical_apicid)(int cpu);
	351	#endif
e2780a68 IM	352	};
e2780a68 IM	353
0917c01f IM	354	/*
	355	* Pointer to the local APIC driver in use on this system (there's
	356	* always just one such driver in use - the kernel decides via an
	357	* early probing process which one it picks - and then sticks to it):
	358	*/
be163a15	359	extern struct apic *apic;
0917c01f	360
107e0e0c SS	361	/*
	362	* APIC drivers are probed based on how they are listed in the .apicdrivers
	363	* section. So the order is important and enforced by the ordering
	364	* of different apic driver files in the Makefile.
	365	*
	366	* For the files having two apic drivers, we use apic_drivers()
	367	* to enforce the order with in them.
	368	*/
	369	#define apic_driver(sym) \
75fdd155	370	static const struct apic *__apicdrivers_##sym __used \
107e0e0c SS	371	__aligned(sizeof(struct apic *)) \
	372	__section(.apicdrivers) = { &sym }
	373
	374	#define apic_drivers(sym1, sym2) \
	375	static struct apic *__apicdrivers_##sym1##sym2[2] __used \
	376	__aligned(sizeof(struct apic *)) \
	377	__section(.apicdrivers) = { &sym1, &sym2 }
	378
	379	extern struct apic __apicdrivers[], __apicdrivers_end[];
	380
0917c01f IM	381	/*
	382	* APIC functionality to boot other CPUs - only used on SMP:
	383	*/
	384	#ifdef CONFIG_SMP
2b6163bf	385	extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
0917c01f	386	#endif
e2780a68	387
d674cd19	388	#ifdef CONFIG_X86_LOCAL_APIC
346b46be	389
e2780a68 IM	390	static inline u32 apic_read(u32 reg)
	391	{
	392	return apic->read(reg);
	393	}
	394
	395	static inline void apic_write(u32 reg, u32 val)
	396	{
	397	apic->write(reg, val);
	398	}
	399
2a43195d MT	400	static inline void apic_eoi(void)
	401	{
	402	apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
	403	}
	404
e2780a68 IM	405	static inline u64 apic_icr_read(void)
	406	{
	407	return apic->icr_read();
	408	}
	409
	410	static inline void apic_icr_write(u32 low, u32 high)
	411	{
	412	apic->icr_write(low, high);
	413	}
	414
	415	static inline void apic_wait_icr_idle(void)
	416	{
	417	apic->wait_icr_idle();
	418	}
	419
	420	static inline u32 safe_apic_wait_icr_idle(void)
	421	{
	422	return apic->safe_wait_icr_idle();
	423	}
	424
1551df64 MT	425	extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
1551df64 MT	426
d674cd19 CG	427	#else /* CONFIG_X86_LOCAL_APIC */
	428
	429	static inline u32 apic_read(u32 reg) { return 0; }
	430	static inline void apic_write(u32 reg, u32 val) { }
2a43195d	431	static inline void apic_eoi(void) { }
d674cd19 CG	432	static inline u64 apic_icr_read(void) { return 0; }
	433	static inline void apic_icr_write(u32 low, u32 high) { }
	434	static inline void apic_wait_icr_idle(void) { }
	435	static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
1551df64	436	static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
d674cd19 CG	437
d674cd19 CG	438	#endif /* CONFIG_X86_LOCAL_APIC */
e2780a68 IM	439
	440	static inline void ack_APIC_irq(void)
	441	{
	442	/*
	443	* ack_APIC_irq() actually gets compiled as a single instruction
	444	* ... yummie.
	445	*/
2a43195d	446	apic_eoi();
e2780a68 IM	447	}
	448
	449	static inline unsigned default_get_apic_id(unsigned long x)
	450	{
	451	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	452
42937e81	453	if (APIC_XAPIC(ver) \|\| boot_cpu_has(X86_FEATURE_EXTD_APICID))
e2780a68 IM	454	return (x >> 24) & 0xFF;
	455	else
	456	return (x >> 24) & 0x0F;
	457	}
	458
	459	/*
6ab1b27c	460	* Warm reset vector position:
e2780a68	461	*/
6ab1b27c DR	462	#define TRAMPOLINE_PHYS_LOW 0x467
6ab1b27c DR	463	#define TRAMPOLINE_PHYS_HIGH 0x469
e2780a68	464
2b6163bf	465	#ifdef CONFIG_X86_64
e2780a68 IM	466	extern void apic_send_IPI_self(int vector);
e2780a68 IM	467
e2780a68 IM	468	DECLARE_PER_CPU(int, x2apic_extra_bits);
	469
	470	extern int default_cpu_present_to_apicid(int mps_cpu);
e11dadab	471	extern int default_check_phys_apicid_present(int phys_apicid);
e2780a68 IM	472	#endif
e2780a68 IM	473
838312be	474	extern void generic_bigsmp_probe(void);
e2780a68 IM	475
	476
	477	#ifdef CONFIG_X86_LOCAL_APIC
	478
	479	#include <asm/smp.h>
	480
	481	#define APIC_DFR_VALUE (APIC_DFR_FLAT)
	482
	483	static inline const struct cpumask *default_target_cpus(void)
	484	{
	485	#ifdef CONFIG_SMP
	486	return cpu_online_mask;
	487	#else
	488	return cpumask_of(0);
	489	#endif
	490	}
	491
bf721d3a AG	492	static inline const struct cpumask *online_target_cpus(void)
	493	{
	494	return cpu_online_mask;
	495	}
	496
0816b0f0	497	DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
e2780a68 IM	498
	499
	500	static inline unsigned int read_apic_id(void)
	501	{
	502	unsigned int reg;
	503
	504	reg = apic_read(APIC_ID);
	505
	506	return apic->get_apic_id(reg);
	507	}
	508
fa63030e DB	509	static inline int default_apic_id_valid(int apicid)
fa63030e DB	510	{
b7157acf	511	return (apicid < 255);
fa63030e DB	512	}
fa63030e DB	513
a491cc90 JL	514	extern int default_acpi_madt_oem_check(char , char );
a491cc90 JL	515
e2780a68 IM	516	extern void default_setup_apic_routing(void);
e2780a68 IM	517
9844ab11 CG	518	extern struct apic apic_noop;
9844ab11 CG	519
e2780a68	520	#ifdef CONFIG_X86_32
2c1b284e	521
acb8bc09 TH	522	static inline int noop_x86_32_early_logical_apicid(int cpu)
	523	{
	524	return BAD_APICID;
	525	}
	526
e2780a68 IM	527	/*
	528	* Set up the logical destination ID.
	529	*
	530	* Intel recommends to set DFR, LDR and TPR before enabling
	531	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	532	* document number 292116). So here it goes...
	533	*/
	534	extern void default_init_apic_ldr(void);
	535
	536	static inline int default_apic_id_registered(void)
	537	{
	538	return physid_isset(read_apic_id(), phys_cpu_present_map);
	539	}
	540
f56e5034 YL	541	static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
	542	{
	543	return cpuid_apic >> index_msb;
	544	}
	545
f56e5034 YL	546	#endif
f56e5034 YL	547
ff164324	548	static inline int
a5a39156 AG	549	flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
	550	const struct cpumask *andmask,
	551	unsigned int *apicid)
e2780a68	552	{
a5a39156 AG	553	unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
	554	cpumask_bits(andmask)[0] &
	555	cpumask_bits(cpu_online_mask)[0] &
	556	APIC_ALL_CPUS;
	557
ff164324 AG	558	if (likely(cpu_mask)) {
	559	*apicid = (unsigned int)cpu_mask;
	560	return 0;
	561	} else {
	562	return -EINVAL;
	563	}
	564	}
	565
ff164324	566	extern int
6398268d	567	default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
ff164324 AG	568	const struct cpumask *andmask,
ff164324 AG	569	unsigned int *apicid);
6398268d	570
b39f25a8	571	static inline void
1ac322d0 SS	572	flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
1ac322d0 SS	573	const struct cpumask *mask)
9d8e1066 AG	574	{
	575	/* Careful. Some cpus do not strictly honor the set of cpus
	576	* specified in the interrupt destination when using lowest
	577	* priority interrupt delivery mode.
	578	*
	579	* In particular there was a hyperthreading cpu observed to
	580	* deliver interrupts to the wrong hyperthread when only one
	581	* hyperthread was specified in the interrupt desitination.
	582	*/
	583	cpumask_clear(retmask);
	584	cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
	585	}
	586
b39f25a8	587	static inline void
1ac322d0 SS	588	default_vector_allocation_domain(int cpu, struct cpumask *retmask,
1ac322d0 SS	589	const struct cpumask *mask)
9d8e1066 AG	590	{
	591	cpumask_copy(retmask, cpumask_of(cpu));
	592	}
	593
7abc0753	594	static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
e2780a68	595	{
7abc0753	596	return physid_isset(apicid, *map);
e2780a68 IM	597	}
e2780a68 IM	598
7abc0753	599	static inline void default_ioapic_phys_id_map(physid_mask_t phys_map, physid_mask_t retmap)
e2780a68	600	{
7abc0753	601	retmap = phys_map;
e2780a68 IM	602	}
e2780a68 IM	603
e2780a68 IM	604	static inline int __default_cpu_present_to_apicid(int mps_cpu)
	605	{
	606	if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
	607	return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
	608	else
	609	return BAD_APICID;
	610	}
	611
	612	static inline int
e11dadab	613	__default_check_phys_apicid_present(int phys_apicid)
e2780a68	614	{
e11dadab	615	return physid_isset(phys_apicid, phys_cpu_present_map);
e2780a68 IM	616	}
	617
	618	#ifdef CONFIG_X86_32
	619	static inline int default_cpu_present_to_apicid(int mps_cpu)
	620	{
	621	return __default_cpu_present_to_apicid(mps_cpu);
	622	}
	623
	624	static inline int
e11dadab	625	default_check_phys_apicid_present(int phys_apicid)
e2780a68	626	{
e11dadab	627	return __default_check_phys_apicid_present(phys_apicid);
e2780a68 IM	628	}
	629	#else
	630	extern int default_cpu_present_to_apicid(int mps_cpu);
e11dadab	631	extern int default_check_phys_apicid_present(int phys_apicid);
e2780a68 IM	632	#endif
e2780a68 IM	633
e2780a68	634	#endif /* CONFIG_X86_LOCAL_APIC */
eddc0e92 SA	635	extern void irq_enter(void);
	636	extern void irq_exit(void);
	637
	638	static inline void entering_irq(void)
	639	{
	640	irq_enter();
	641	exit_idle();
	642	}
	643
	644	static inline void entering_ack_irq(void)
	645	{
	646	ack_APIC_irq();
	647	entering_irq();
	648	}
	649
6dc17876 TG	650	static inline void ipi_entering_ack_irq(void)
	651	{
	652	ack_APIC_irq();
	653	irq_enter();
	654	}
	655
eddc0e92 SA	656	static inline void exiting_irq(void)
	657	{
	658	irq_exit();
	659	}
	660
	661	static inline void exiting_ack_irq(void)
	662	{
	663	irq_exit();
	664	/* Ack only at the end to avoid potential reentry */
	665	ack_APIC_irq();
	666	}
e2780a68	667
17405453 YY	668	extern void ioapic_zap_locks(void);
17405453 YY	669
1965aae3	670	#endif /* _ASM_X86_APIC_H */