[deliverable/linux.git] / arch / x86 / include / asm / dma-mapping.h

#ifndef _ASM_X86_DMA_MAPPING_H
#define _ASM_X86_DMA_MAPPING_H

/*
 * IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
 * Documentation/DMA-API.txt for documentation.
 */

#include <linux/kmemcheck.h>
#include <linux/scatterlist.h>
#include <linux/dma-debug.h>
#include <linux/dma-attrs.h>
#include <asm/io.h>
#include <asm/swiotlb.h>
#include <asm-generic/dma-coherent.h>
#include <linux/dma-contiguous.h>

#ifdef CONFIG_ISA
# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
#else
# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
#endif

#define DMA_ERROR_CODE	0

extern int iommu_merge;
extern struct device x86_dma_fallback_dev;
extern int panic_on_overflow;

extern struct dma_map_ops *dma_ops;

static inline struct dma_map_ops *get_dma_ops(struct device *dev)
{
#ifndef CONFIG_X86_DEV_DMA_OPS
	return dma_ops;
#else
	if (unlikely(!dev) || !dev->archdata.dma_ops)
		return dma_ops;
	else
		return dev->archdata.dma_ops;
#endif
}

#include <asm-generic/dma-mapping-common.h>

/* Make sure we keep the same behaviour */
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	struct dma_map_ops *ops = get_dma_ops(dev);
	debug_dma_mapping_error(dev, dma_addr);
	if (ops->mapping_error)
		return ops->mapping_error(dev, dma_addr);

	return (dma_addr == DMA_ERROR_CODE);
}

#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)

extern int dma_supported(struct device *hwdev, u64 mask);
extern int dma_set_mask(struct device *dev, u64 mask);

extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
					dma_addr_t *dma_addr, gfp_t flag,
					struct dma_attrs *attrs);

extern void dma_generic_free_coherent(struct device *dev, size_t size,
				      void *vaddr, dma_addr_t dma_addr,
				      struct dma_attrs *attrs);

#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */
extern bool dma_capable(struct device *dev, dma_addr_t addr, size_t size);
extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
#else

static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
	if (!dev->dma_mask)
		return 0;

	return addr + size - 1 <= *dev->dma_mask;
}

static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	return paddr;
}

static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
{
	return daddr;
}
#endif /* CONFIG_X86_DMA_REMAP */

static inline void
dma_cache_sync(struct device *dev, void *vaddr, size_t size,
	enum dma_data_direction dir)
{
	flush_write_buffers();
}

static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
						    gfp_t gfp)
{
	unsigned long dma_mask = 0;

	dma_mask = dev->coherent_dma_mask;
	if (!dma_mask)
		dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);

	return dma_mask;
}

static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
{
	unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);

	if (dma_mask <= DMA_BIT_MASK(24))
		gfp |= GFP_DMA;
#ifdef CONFIG_X86_64
	if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
		gfp |= GFP_DMA32;
#endif
       return gfp;
}

#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)

void *
dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
		gfp_t gfp, struct dma_attrs *attrs);

#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)

void dma_free_attrs(struct device *dev, size_t size,
		    void *vaddr, dma_addr_t bus,
		    struct dma_attrs *attrs);

#endif
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_DMA_MAPPING_H
1965aae3 PA	2	#define _ASM_X86_DMA_MAPPING_H
6f536635 GC	3
6f536635 GC	4	/*
395cf969	5	* IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
5872fb94	6	* Documentation/DMA-API.txt for documentation.
6f536635 GC	7	*/
6f536635 GC	8
d7002857	9	#include <linux/kmemcheck.h>
6f536635	10	#include <linux/scatterlist.h>
2118d0c5	11	#include <linux/dma-debug.h>
abe6602b	12	#include <linux/dma-attrs.h>
6f536635 GC	13	#include <asm/io.h>
6f536635 GC	14	#include <asm/swiotlb.h>
6c505ce3	15	#include <asm-generic/dma-coherent.h>
0a2b9a6e	16	#include <linux/dma-contiguous.h>
6f536635	17
eb647138 JB	18	#ifdef CONFIG_ISA
	19	# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
	20	#else
	21	# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
	22	#endif
	23
8fd524b3 FT	24	#define DMA_ERROR_CODE 0
8fd524b3 FT	25
b7107a3d	26	extern int iommu_merge;
6c505ce3	27	extern struct device x86_dma_fallback_dev;
b7107a3d	28	extern int panic_on_overflow;
7c183416	29
160c1d8e FT	30	extern struct dma_map_ops *dma_ops;
	31
	32	static inline struct dma_map_ops get_dma_ops(struct device dev)
c786df08	33	{
4692d77f	34	#ifndef CONFIG_X86_DEV_DMA_OPS
8d8bb39b FT	35	return dma_ops;
	36	#else
	37	if (unlikely(!dev) \|\| !dev->archdata.dma_ops)
	38	return dma_ops;
	39	else
	40	return dev->archdata.dma_ops;
cfb80c9e	41	#endif
8d8bb39b FT	42	}
8d8bb39b FT	43
7c095e46 FT	44	#include <asm-generic/dma-mapping-common.h>
7c095e46 FT	45
8d8bb39b FT	46	/* Make sure we keep the same behaviour */
	47	static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
	48	{
160c1d8e	49	struct dma_map_ops *ops = get_dma_ops(dev);
6c9c6d63	50	debug_dma_mapping_error(dev, dma_addr);
8d8bb39b FT	51	if (ops->mapping_error)
8d8bb39b FT	52	return ops->mapping_error(dev, dma_addr);
c786df08	53
8fd524b3	54	return (dma_addr == DMA_ERROR_CODE);
c786df08 GC	55	}
c786df08 GC	56
8d396ded GC	57	#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
8d396ded GC	58	#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
8d396ded	59
802c1f66 GC	60	extern int dma_supported(struct device *hwdev, u64 mask);
	61	extern int dma_set_mask(struct device *dev, u64 mask);
	62
9f6ac577	63	extern void dma_generic_alloc_coherent(struct device dev, size_t size,
baa676fc AP	64	dma_addr_t *dma_addr, gfp_t flag,
baa676fc AP	65	struct dma_attrs *attrs);
9f6ac577	66
0a2b9a6e MS	67	extern void dma_generic_free_coherent(struct device *dev, size_t size,
	68	void *vaddr, dma_addr_t dma_addr,
	69	struct dma_attrs *attrs);
	70
f7219a53 AR	71	#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */
	72	extern bool dma_capable(struct device *dev, dma_addr_t addr, size_t size);
	73	extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
	74	extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
	75	#else
	76
99becaca FT	77	static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
	78	{
	79	if (!dev->dma_mask)
	80	return 0;
	81
ac2b3e67	82	return addr + size - 1 <= *dev->dma_mask;
99becaca FT	83	}
99becaca FT	84
8d4f5339 FT	85	static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
	86	{
	87	return paddr;
	88	}
	89
	90	static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
	91	{
	92	return daddr;
	93	}
f7219a53	94	#endif /* CONFIG_X86_DMA_REMAP */
8d4f5339	95
3cb6a917 GC	96	static inline void
	97	dma_cache_sync(struct device dev, void vaddr, size_t size,
	98	enum dma_data_direction dir)
	99	{
	100	flush_write_buffers();
	101	}
ae17a63b	102
823e7e8c FT	103	static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
	104	gfp_t gfp)
	105	{
	106	unsigned long dma_mask = 0;
b7107a3d	107
823e7e8c FT	108	dma_mask = dev->coherent_dma_mask;
823e7e8c FT	109	if (!dma_mask)
2f4f27d4	110	dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
823e7e8c FT	111
	112	return dma_mask;
	113	}
	114
	115	static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
	116	{
	117	unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
	118
2f4f27d4	119	if (dma_mask <= DMA_BIT_MASK(24))
75bebb7f FT	120	gfp \|= GFP_DMA;
75bebb7f FT	121	#ifdef CONFIG_X86_64
284901a9	122	if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
823e7e8c FT	123	gfp \|= GFP_DMA32;
	124	#endif
	125	return gfp;
	126	}
	127
baa676fc AP	128	#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
baa676fc AP	129
0c7965ff	130	void *
baa676fc	131	dma_alloc_attrs(struct device dev, size_t size, dma_addr_t dma_handle,
0c7965ff	132	gfp_t gfp, struct dma_attrs *attrs);
6c505ce3	133
baa676fc AP	134	#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
baa676fc AP	135
f1dc154f DV	136	void dma_free_attrs(struct device *dev, size_t size,
	137	void *vaddr, dma_addr_t bus,
	138	struct dma_attrs *attrs);
b7107a3d	139
6f536635	140	#endif