Commit | Line | Data |
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af2730f6 | 1 | /* |
05454c26 | 2 | * intel-mid.h: Intel MID specific setup code |
af2730f6 JP |
3 | * |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; version 2 | |
9 | * of the License. | |
10 | */ | |
05454c26 KS |
11 | #ifndef _ASM_X86_INTEL_MID_H |
12 | #define _ASM_X86_INTEL_MID_H | |
c20b5c33 FT |
13 | |
14 | #include <linux/sfi.h> | |
40a96d54 | 15 | #include <linux/platform_device.h> |
c20b5c33 | 16 | |
712b6aa8 | 17 | extern int intel_mid_pci_init(void); |
40a96d54 DC |
18 | extern int get_gpio_by_name(const char *name); |
19 | extern void intel_scu_device_register(struct platform_device *pdev); | |
7309282c | 20 | extern int __init sfi_parse_mrtc(struct sfi_table_header *table); |
aeedb370 | 21 | extern int __init sfi_parse_mtmr(struct sfi_table_header *table); |
7309282c FT |
22 | extern int sfi_mrtc_num; |
23 | extern struct sfi_rtc_table_entry sfi_mrtc_array[]; | |
af2730f6 | 24 | |
49c72a0a KS |
25 | /* |
26 | * Here defines the array of devices platform data that IAFW would export | |
27 | * through SFI "DEVS" table, we use name and type to match the device and | |
28 | * its platform data. | |
29 | */ | |
30 | struct devs_id { | |
31 | char name[SFI_NAME_LEN + 1]; | |
32 | u8 type; | |
33 | u8 delay; | |
34 | void *(*get_platform_data)(void *info); | |
35 | /* Custom handler for devices */ | |
36 | void (*device_handler)(struct sfi_device_table_entry *pentry, | |
37 | struct devs_id *dev); | |
38 | }; | |
39 | ||
40a96d54 DC |
40 | #define sfi_device(i) \ |
41 | static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ | |
42 | __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i | |
43 | ||
a0c173bd JP |
44 | /* |
45 | * Medfield is the follow-up of Moorestown, it combines two chip solution into | |
46 | * one. Other than that it also added always-on and constant tsc and lapic | |
47 | * timers. Medfield is the platform name, and the chip name is called Penwell | |
48 | * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be | |
49 | * identified via MSRs. | |
50 | */ | |
712b6aa8 | 51 | enum intel_mid_cpu_type { |
1a8359e4 | 52 | /* 1 was Moorestown */ |
712b6aa8 | 53 | INTEL_MID_CPU_CHIP_PENWELL = 2, |
85611e3f | 54 | INTEL_MID_CPU_CHIP_CLOVERVIEW, |
bc20aa48 | 55 | INTEL_MID_CPU_CHIP_TANGIER, |
a0c173bd JP |
56 | }; |
57 | ||
712b6aa8 | 58 | extern enum intel_mid_cpu_type __intel_mid_cpu_chip; |
35d47699 | 59 | |
85611e3f KS |
60 | /** |
61 | * struct intel_mid_ops - Interface between intel-mid & sub archs | |
62 | * @arch_setup: arch_setup function to re-initialize platform | |
63 | * structures (x86_init, x86_platform_init) | |
64 | * | |
65 | * This structure can be extended if any new interface is required | |
66 | * between intel-mid & its sub arch files. | |
67 | */ | |
68 | struct intel_mid_ops { | |
69 | void (*arch_setup)(void); | |
70 | }; | |
71 | ||
72 | /* Helper API's for INTEL_MID_OPS_INIT */ | |
73 | #define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ | |
74 | [cpuid] = get_##cpuname##_ops | |
75 | ||
76 | /* Maximum number of CPU ops */ | |
77 | #define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) | |
78 | ||
79 | /* | |
80 | * For every new cpu addition, a weak get_<cpuname>_ops() function needs be | |
81 | * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. | |
82 | */ | |
83 | #define INTEL_MID_OPS_INIT {\ | |
84 | DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ | |
85 | DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ | |
bc20aa48 | 86 | DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ |
85611e3f KS |
87 | }; |
88 | ||
35d47699 MN |
89 | #ifdef CONFIG_X86_INTEL_MID |
90 | ||
712b6aa8 | 91 | static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) |
a75af580 | 92 | { |
712b6aa8 | 93 | return __intel_mid_cpu_chip; |
a75af580 PA |
94 | } |
95 | ||
40a96d54 DC |
96 | static inline bool intel_mid_has_msic(void) |
97 | { | |
98 | return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); | |
99 | } | |
100 | ||
35d47699 MN |
101 | #else /* !CONFIG_X86_INTEL_MID */ |
102 | ||
712b6aa8 | 103 | #define intel_mid_identify_cpu() (0) |
40a96d54 | 104 | #define intel_mid_has_msic() (0) |
35d47699 MN |
105 | |
106 | #endif /* !CONFIG_X86_INTEL_MID */ | |
107 | ||
712b6aa8 KS |
108 | enum intel_mid_timer_options { |
109 | INTEL_MID_TIMER_DEFAULT, | |
110 | INTEL_MID_TIMER_APBT_ONLY, | |
111 | INTEL_MID_TIMER_LAPIC_APBT, | |
a0c173bd JP |
112 | }; |
113 | ||
712b6aa8 | 114 | extern enum intel_mid_timer_options intel_mid_timer_options; |
14671386 | 115 | |
0a915326 DB |
116 | /* |
117 | * Penwell uses spread spectrum clock, so the freq number is not exactly | |
118 | * the same as reported by MSR based on SDM. | |
119 | */ | |
85611e3f KS |
120 | #define FSB_FREQ_83SKU 83200 |
121 | #define FSB_FREQ_100SKU 99840 | |
122 | #define FSB_FREQ_133SKU 133000 | |
123 | ||
124 | #define FSB_FREQ_167SKU 167000 | |
125 | #define FSB_FREQ_200SKU 200000 | |
126 | #define FSB_FREQ_267SKU 267000 | |
127 | #define FSB_FREQ_333SKU 333000 | |
128 | #define FSB_FREQ_400SKU 400000 | |
129 | ||
130 | /* Bus Select SoC Fuse value */ | |
131 | #define BSEL_SOC_FUSE_MASK 0x7 | |
132 | #define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ | |
133 | #define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ | |
134 | #define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ | |
0a915326 | 135 | |
16ab5395 | 136 | #define SFI_MTMR_MAX_NUM 8 |
cf089455 | 137 | #define SFI_MRTC_MAX 8 |
16ab5395 | 138 | |
1da4b1c6 FT |
139 | extern void intel_scu_devices_create(void); |
140 | extern void intel_scu_devices_destroy(void); | |
141 | ||
7309282c FT |
142 | /* VRTC timer */ |
143 | #define MRST_VRTC_MAP_SZ (1024) | |
144 | /*#define MRST_VRTC_PGOFFSET (0xc00) */ | |
145 | ||
712b6aa8 | 146 | extern void intel_mid_rtc_init(void); |
7309282c | 147 | |
40a96d54 DC |
148 | /* the offset for the mapping of global gpio pin to irq */ |
149 | #define INTEL_MID_IRQ_OFFSET 0x100 | |
150 | ||
05454c26 | 151 | #endif /* _ASM_X86_INTEL_MID_H */ |