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1 | #ifndef _ASM_X86_INTEL_PMC_IPC_H_ |
2 | #define _ASM_X86_INTEL_PMC_IPC_H_ |
3 | |
4 | /* Commands */ |
5 | #define PMC_IPC_PMIC_ACCESS 0xFF |
6 | #define PMC_IPC_PMIC_ACCESS_READ 0x0 |
7 | #define PMC_IPC_PMIC_ACCESS_WRITE 0x1 |
8 | #define PMC_IPC_USB_PWR_CTRL 0xF0 |
9 | #define PMC_IPC_PMIC_BLACKLIST_SEL 0xEF |
10 | #define PMC_IPC_PHY_CONFIG 0xEE |
11 | #define PMC_IPC_NORTHPEAK_CTRL 0xED |
12 | #define PMC_IPC_PM_DEBUG 0xEC |
13 | #define PMC_IPC_PMC_TELEMTRY 0xEB |
14 | #define PMC_IPC_PMC_FW_MSG_CTRL 0xEA |
15 | |
16 | /* IPC return code */ |
17 | #define IPC_ERR_NONE 0 |
18 | #define IPC_ERR_CMD_NOT_SUPPORTED 1 |
19 | #define IPC_ERR_CMD_NOT_SERVICED 2 |
20 | #define IPC_ERR_UNABLE_TO_SERVICE 3 |
21 | #define IPC_ERR_CMD_INVALID 4 |
22 | #define IPC_ERR_CMD_FAILED 5 |
23 | #define IPC_ERR_EMSECURITY 6 |
24 | #define IPC_ERR_UNSIGNEDKERNEL 7 |
25 | |
26 | #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) |
27 | |
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28 | int intel_pmc_ipc_simple_command(int cmd, int sub); |
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29 | int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, |
30 | u32 *out, u32 outlen, u32 dptr, u32 sptr); |
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31 | int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, |
32 | u32 *out, u32 outlen); |
33 | |
34 | #else |
35 | |
36 | static inline int intel_pmc_ipc_simple_command(int cmd, int sub) |
37 | { |
38 | return -EINVAL; |
39 | } |
40 | |
41 | static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, |
42 | u32 *out, u32 outlen, u32 dptr, u32 sptr) |
43 | { |
44 | return -EINVAL; |
45 | } |
46 | |
47 | static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, |
48 | u32 *out, u32 outlen) |
49 | { |
50 | return -EINVAL; |
51 | } |
52 | |
53 | #endif /*CONFIG_INTEL_PMC_IPC*/ |
54 | |
55 | #endif |