[deliverable/linux.git] / arch / x86 / include / asm / io_apic.h

#ifndef _ASM_X86_IO_APIC_H
#define _ASM_X86_IO_APIC_H

#include <linux/types.h>
#include <asm/mpspec.h>
#include <asm/apicdef.h>
#include <asm/irq_vectors.h>
#include <asm/x86_init.h>
/*
 * Intel IO-APIC support for SMP and UP systems.
 *
 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
 */

/* I/O Unit Redirection Table */
#define IO_APIC_REDIR_VECTOR_MASK	0x000FF
#define IO_APIC_REDIR_DEST_LOGICAL	0x00800
#define IO_APIC_REDIR_DEST_PHYSICAL	0x00000
#define IO_APIC_REDIR_SEND_PENDING	(1 << 12)
#define IO_APIC_REDIR_REMOTE_IRR	(1 << 14)
#define IO_APIC_REDIR_LEVEL_TRIGGER	(1 << 15)
#define IO_APIC_REDIR_MASKED		(1 << 16)

/*
 * The structure of the IO-APIC:
 */
union IO_APIC_reg_00 {
	u32	raw;
	struct {
		u32	__reserved_2	: 14,
			LTS		:  1,
			delivery_type	:  1,
			__reserved_1	:  8,
			ID		:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_01 {
	u32	raw;
	struct {
		u32	version		:  8,
			__reserved_2	:  7,
			PRQ		:  1,
			entries		:  8,
			__reserved_1	:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_02 {
	u32	raw;
	struct {
		u32	__reserved_2	: 24,
			arbitration	:  4,
			__reserved_1	:  4;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_03 {
	u32	raw;
	struct {
		u32	boot_DT		:  1,
			__reserved_1	: 31;
	} __attribute__ ((packed)) bits;
};

struct IO_APIC_route_entry {
	__u32	vector		:  8,
		delivery_mode	:  3,	/* 000: FIXED
					 * 001: lowest prio
					 * 111: ExtINT
					 */
		dest_mode	:  1,	/* 0: physical, 1: logical */
		delivery_status	:  1,
		polarity	:  1,
		irr		:  1,
		trigger		:  1,	/* 0: edge, 1: level */
		mask		:  1,	/* 0: enabled, 1: disabled */
		__reserved_2	: 15;

	__u32	__reserved_3	: 24,
		dest		:  8;
} __attribute__ ((packed));

struct IR_IO_APIC_route_entry {
	__u64	vector		: 8,
		zero		: 3,
		index2		: 1,
		delivery_status : 1,
		polarity	: 1,
		irr		: 1,
		trigger		: 1,
		mask		: 1,
		reserved	: 31,
		format		: 1,
		index		: 15;
} __attribute__ ((packed));

struct irq_alloc_info;
struct ioapic_domain_cfg;

#define IOAPIC_AUTO			-1
#define IOAPIC_EDGE			0
#define IOAPIC_LEVEL			1

#define IOAPIC_MASKED			1
#define IOAPIC_UNMASKED			0

#define IOAPIC_POL_HIGH			0
#define IOAPIC_POL_LOW			1

#define IOAPIC_DEST_MODE_PHYSICAL	0
#define IOAPIC_DEST_MODE_LOGICAL	1

#define	IOAPIC_MAP_ALLOC		0x1
#define	IOAPIC_MAP_CHECK		0x2

#ifdef CONFIG_X86_IO_APIC

/*
 * # of IO-APICs and # of IRQ routing registers
 */
extern int nr_ioapics;

extern int mpc_ioapic_id(int ioapic);
extern unsigned int mpc_ioapic_addr(int ioapic);

/* # of MP IRQ source entries */
extern int mp_irq_entries;

/* MP IRQ source entries */
extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* 1 if "noapic" boot option passed */
extern int skip_ioapic_setup;

/* 1 if "noapic" boot option passed */
extern int noioapicquirk;

/* -1 if "noapic" boot option passed */
extern int noioapicreroute;

extern u32 gsi_top;

extern unsigned long io_apic_irqs;

#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))

/*
 * If we use the IO-APIC for IRQ routing, disable automatic
 * assignment of PCI IRQ's.
 */
#define io_apic_assign_pci_irqs \
	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)

struct irq_cfg;
extern void ioapic_insert_resources(void);
extern int arch_early_ioapic_init(void);

extern int save_ioapic_entries(void);
extern void mask_ioapic_entries(void);
extern int restore_ioapic_entries(void);

extern void setup_ioapic_ids_from_mpc(void);
extern void setup_ioapic_ids_from_mpc_nocheck(void);

extern int mp_find_ioapic(u32 gsi);
extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
			     struct irq_alloc_info *info);
extern void mp_unmap_irq(int irq);
extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
			      struct ioapic_domain_cfg *cfg);
extern int mp_unregister_ioapic(u32 gsi_base);
extern int mp_ioapic_registered(u32 gsi_base);

extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
				  int node, int trigger, int polarity);

extern void mp_save_irq(struct mpc_intsrc *m);

extern void disable_ioapic_support(void);

extern void __init io_apic_init_mappings(void);
extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
extern void native_disable_io_apic(void);

static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
	return x86_io_apic_ops.read(apic, reg);
}

extern void setup_IO_APIC(void);
extern void enable_IO_APIC(void);
extern void disable_IO_APIC(void);
extern void setup_ioapic_dest(void);
extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
extern void print_IO_APICs(void);
#else  /* !CONFIG_X86_IO_APIC */

#define IO_APIC_IRQ(x)		0
#define io_apic_assign_pci_irqs 0
#define setup_ioapic_ids_from_mpc x86_init_noop
static inline void ioapic_insert_resources(void) { }
static inline int arch_early_ioapic_init(void) { return 0; }
static inline void print_IO_APICs(void) {}
#define gsi_top (NR_IRQS_LEGACY)
static inline int mp_find_ioapic(u32 gsi) { return 0; }
static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
				    struct irq_alloc_info *info)
{
	return gsi;
}

static inline void mp_unmap_irq(int irq) { }

static inline int save_ioapic_entries(void)
{
	return -ENOMEM;
}

static inline void mask_ioapic_entries(void) { }
static inline int restore_ioapic_entries(void)
{
	return -ENOMEM;
}

static inline void mp_save_irq(struct mpc_intsrc *m) { }
static inline void disable_ioapic_support(void) { }
static inline void io_apic_init_mappings(void) { }
#define native_io_apic_read		NULL
#define native_disable_io_apic		NULL

static inline void setup_IO_APIC(void) { }
static inline void enable_IO_APIC(void) { }
static inline void setup_ioapic_dest(void) { }

#endif

#endif /* _ASM_X86_IO_APIC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_IO_APIC_H
1965aae3 PA	2	#define _ASM_X86_IO_APIC_H
e1d91978	3
a1a33fa3	4	#include <linux/types.h>
e1d91978 TG	5	#include <asm/mpspec.h>
e1d91978 TG	6	#include <asm/apicdef.h>
9d6a4d08	7	#include <asm/irq_vectors.h>
4a8e2a31	8	#include <asm/x86_init.h>
e1d91978 TG	9	/*
	10	* Intel IO-APIC support for SMP and UP systems.
	11	*
	12	* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
	13	*/
	14
d3f020d2 CG	15	/* I/O Unit Redirection Table */
	16	#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
	17	#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
	18	#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
	19	#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
	20	#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
	21	#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
	22	#define IO_APIC_REDIR_MASKED (1 << 16)
	23
e1d91978 TG	24	/*
	25	* The structure of the IO-APIC:
	26	*/
	27	union IO_APIC_reg_00 {
	28	u32 raw;
	29	struct {
	30	u32 __reserved_2 : 14,
	31	LTS : 1,
	32	delivery_type : 1,
	33	__reserved_1 : 8,
	34	ID : 8;
	35	} __attribute__ ((packed)) bits;
	36	};
	37
	38	union IO_APIC_reg_01 {
	39	u32 raw;
	40	struct {
	41	u32 version : 8,
	42	__reserved_2 : 7,
	43	PRQ : 1,
	44	entries : 8,
	45	__reserved_1 : 8;
	46	} __attribute__ ((packed)) bits;
	47	};
	48
	49	union IO_APIC_reg_02 {
	50	u32 raw;
	51	struct {
	52	u32 __reserved_2 : 24,
	53	arbitration : 4,
	54	__reserved_1 : 4;
	55	} __attribute__ ((packed)) bits;
	56	};
	57
	58	union IO_APIC_reg_03 {
	59	u32 raw;
	60	struct {
	61	u32 boot_DT : 1,
	62	__reserved_1 : 31;
	63	} __attribute__ ((packed)) bits;
	64	};
	65
e1d91978 TG	66	struct IO_APIC_route_entry {
	67	__u32 vector : 8,
	68	delivery_mode : 3, /* 000: FIXED
	69	* 001: lowest prio
	70	* 111: ExtINT
	71	*/
	72	dest_mode : 1, /* 0: physical, 1: logical */
	73	delivery_status : 1,
	74	polarity : 1,
	75	irr : 1,
	76	trigger : 1, /* 0: edge, 1: level */
	77	mask : 1, /* 0: enabled, 1: disabled */
	78	__reserved_2 : 15;
	79
e1d91978 TG	80	__u32 __reserved_3 : 24,
e1d91978 TG	81	dest : 8;
e1d91978	82	} __attribute__ ((packed));
e1d91978	83
89027d35 SS	84	struct IR_IO_APIC_route_entry {
	85	__u64 vector : 8,
	86	zero : 3,
	87	index2 : 1,
	88	delivery_status : 1,
	89	polarity : 1,
	90	irr : 1,
	91	trigger : 1,
	92	mask : 1,
	93	reserved : 31,
	94	format : 1,
	95	index : 15;
e1d91978 TG	96	} __attribute__ ((packed));
e1d91978 TG	97
c4d05a2c	98	struct irq_alloc_info;
f7a0c786	99	struct ioapic_domain_cfg;
c4d05a2c	100
335efdf5 TG	101	#define IOAPIC_AUTO -1
	102	#define IOAPIC_EDGE 0
	103	#define IOAPIC_LEVEL 1
	104
	105	#define IOAPIC_MASKED 1
	106	#define IOAPIC_UNMASKED 0
	107
	108	#define IOAPIC_POL_HIGH 0
	109	#define IOAPIC_POL_LOW 1
	110
	111	#define IOAPIC_DEST_MODE_PHYSICAL 0
	112	#define IOAPIC_DEST_MODE_LOGICAL 1
	113
d7f3d478 JL	114	#define IOAPIC_MAP_ALLOC 0x1
d7f3d478 JL	115	#define IOAPIC_MAP_CHECK 0x2
abb00522	116
e1d91978 TG	117	#ifdef CONFIG_X86_IO_APIC
	118
	119	/*
	120	* # of IO-APICs and # of IRQ routing registers
	121	*/
	122	extern int nr_ioapics;
e1d91978	123
d5371430 SS	124	extern int mpc_ioapic_id(int ioapic);
d5371430 SS	125	extern unsigned int mpc_ioapic_addr(int ioapic);
e1d91978 TG	126
	127	/* # of MP IRQ source entries */
	128	extern int mp_irq_entries;
	129
	130	/* MP IRQ source entries */
c2c21745	131	extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
e1d91978	132
e1d91978 TG	133	/* 1 if "noapic" boot option passed */
	134	extern int skip_ioapic_setup;
	135
a9322f64 SA	136	/* 1 if "noapic" boot option passed */
	137	extern int noioapicquirk;
	138
9197979b SA	139	/* -1 if "noapic" boot option passed */
	140	extern int noioapicreroute;
	141
154d9e50 JL	142	extern u32 gsi_top;
154d9e50 JL	143
8643e28d JL	144	extern unsigned long io_apic_irqs;
	145
	146	#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) \|\| ((1 << (x)) & io_apic_irqs))
	147
e1d91978 TG	148	/*
	149	* If we use the IO-APIC for IRQ routing, disable automatic
	150	* assignment of PCI IRQ's.
	151	*/
	152	#define io_apic_assign_pci_irqs \
	153	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
	154
9b1b0e42	155	struct irq_cfg;
857fdc53	156	extern void ioapic_insert_resources(void);
11d686e9	157	extern int arch_early_ioapic_init(void);
e1d91978	158
31dce14a SS	159	extern int save_ioapic_entries(void);
	160	extern void mask_ioapic_entries(void);
	161	extern int restore_ioapic_entries(void);
4dc2f96c	162
de934103	163	extern void setup_ioapic_ids_from_mpc(void);
a38c5380	164	extern void setup_ioapic_ids_from_mpc_nocheck(void);
2a4ab640	165
3eb2be5f JL	166	extern int mp_find_ioapic(u32 gsi);
3eb2be5f JL	167	extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
c4d05a2c JL	168	extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
c4d05a2c JL	169	struct irq_alloc_info *info);
df334bea	170	extern void mp_unmap_irq(int irq);
35ef9c94 JL	171	extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
35ef9c94 JL	172	struct ioapic_domain_cfg *cfg);
15516a3b	173	extern int mp_unregister_ioapic(u32 gsi_base);
e89900c9	174	extern int mp_ioapic_registered(u32 gsi_base);
f7a0c786	175
c4d05a2c JL	176	extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
c4d05a2c JL	177	int node, int trigger, int polarity);
2a4ab640	178
2d8009ba FT	179	extern void mp_save_irq(struct mpc_intsrc *m);
2d8009ba FT	180
7167d08e HK	181	extern void disable_ioapic_support(void);
7167d08e HK	182
ca1b8862	183	extern void __init io_apic_init_mappings(void);
4a8e2a31	184	extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
1c4248ca	185	extern void native_disable_io_apic(void);
4a8e2a31 KRW	186
	187	static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
	188	{
	189	return x86_io_apic_ops.read(apic, reg);
	190	}
	191
8643e28d JL	192	extern void setup_IO_APIC(void);
	193	extern void enable_IO_APIC(void);
	194	extern void disable_IO_APIC(void);
	195	extern void setup_ioapic_dest(void);
	196	extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
	197	extern void print_IO_APICs(void);
e1d91978	198	#else /* !CONFIG_X86_IO_APIC */
78f28b7c	199
8643e28d	200	#define IO_APIC_IRQ(x) 0
e1d91978	201	#define io_apic_assign_pci_irqs 0
de934103	202	#define setup_ioapic_ids_from_mpc x86_init_noop
857fdc53	203	static inline void ioapic_insert_resources(void) { }
11d686e9	204	static inline int arch_early_ioapic_init(void) { return 0; }
8643e28d	205	static inline void print_IO_APICs(void) {}
a4384df3	206	#define gsi_top (NR_IRQS_LEGACY)
eddb0c55	207	static inline int mp_find_ioapic(u32 gsi) { return 0; }
c4d05a2c JL	208	static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
	209	struct irq_alloc_info *info)
	210	{
	211	return gsi;
	212	}
	213
df334bea	214	static inline void mp_unmap_irq(int irq) { }
78f28b7c	215
31dce14a	216	static inline int save_ioapic_entries(void)
7d0f1926 HK	217	{
	218	return -ENOMEM;
	219	}
	220
31dce14a SS	221	static inline void mask_ioapic_entries(void) { }
31dce14a SS	222	static inline int restore_ioapic_entries(void)
7d0f1926 HK	223	{
	224	return -ENOMEM;
	225	}
	226
ca1b8862	227	static inline void mp_save_irq(struct mpc_intsrc *m) { }
7167d08e	228	static inline void disable_ioapic_support(void) { }
ca1b8862	229	static inline void io_apic_init_mappings(void) { }
4a8e2a31	230	#define native_io_apic_read NULL
1c4248ca	231	#define native_disable_io_apic NULL
86866083 TG	232
	233	static inline void setup_IO_APIC(void) { }
	234	static inline void enable_IO_APIC(void) { }
	235	static inline void setup_ioapic_dest(void) { }
	236
96a388de	237	#endif
e1d91978	238
1965aae3	239	#endif /* _ASM_X86_IO_APIC_H */