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1965aae3 PA |
1 | #ifndef _ASM_X86_IO_APIC_H |
2 | #define _ASM_X86_IO_APIC_H | |
e1d91978 | 3 | |
a1a33fa3 | 4 | #include <linux/types.h> |
e1d91978 TG |
5 | #include <asm/mpspec.h> |
6 | #include <asm/apicdef.h> | |
9d6a4d08 | 7 | #include <asm/irq_vectors.h> |
4a8e2a31 | 8 | #include <asm/x86_init.h> |
e1d91978 TG |
9 | /* |
10 | * Intel IO-APIC support for SMP and UP systems. | |
11 | * | |
12 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar | |
13 | */ | |
14 | ||
d3f020d2 CG |
15 | /* I/O Unit Redirection Table */ |
16 | #define IO_APIC_REDIR_VECTOR_MASK 0x000FF | |
17 | #define IO_APIC_REDIR_DEST_LOGICAL 0x00800 | |
18 | #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 | |
19 | #define IO_APIC_REDIR_SEND_PENDING (1 << 12) | |
20 | #define IO_APIC_REDIR_REMOTE_IRR (1 << 14) | |
21 | #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) | |
22 | #define IO_APIC_REDIR_MASKED (1 << 16) | |
23 | ||
e1d91978 TG |
24 | /* |
25 | * The structure of the IO-APIC: | |
26 | */ | |
27 | union IO_APIC_reg_00 { | |
28 | u32 raw; | |
29 | struct { | |
30 | u32 __reserved_2 : 14, | |
31 | LTS : 1, | |
32 | delivery_type : 1, | |
33 | __reserved_1 : 8, | |
34 | ID : 8; | |
35 | } __attribute__ ((packed)) bits; | |
36 | }; | |
37 | ||
38 | union IO_APIC_reg_01 { | |
39 | u32 raw; | |
40 | struct { | |
41 | u32 version : 8, | |
42 | __reserved_2 : 7, | |
43 | PRQ : 1, | |
44 | entries : 8, | |
45 | __reserved_1 : 8; | |
46 | } __attribute__ ((packed)) bits; | |
47 | }; | |
48 | ||
49 | union IO_APIC_reg_02 { | |
50 | u32 raw; | |
51 | struct { | |
52 | u32 __reserved_2 : 24, | |
53 | arbitration : 4, | |
54 | __reserved_1 : 4; | |
55 | } __attribute__ ((packed)) bits; | |
56 | }; | |
57 | ||
58 | union IO_APIC_reg_03 { | |
59 | u32 raw; | |
60 | struct { | |
61 | u32 boot_DT : 1, | |
62 | __reserved_1 : 31; | |
63 | } __attribute__ ((packed)) bits; | |
64 | }; | |
65 | ||
e1d91978 TG |
66 | struct IO_APIC_route_entry { |
67 | __u32 vector : 8, | |
68 | delivery_mode : 3, /* 000: FIXED | |
69 | * 001: lowest prio | |
70 | * 111: ExtINT | |
71 | */ | |
72 | dest_mode : 1, /* 0: physical, 1: logical */ | |
73 | delivery_status : 1, | |
74 | polarity : 1, | |
75 | irr : 1, | |
76 | trigger : 1, /* 0: edge, 1: level */ | |
77 | mask : 1, /* 0: enabled, 1: disabled */ | |
78 | __reserved_2 : 15; | |
79 | ||
e1d91978 TG |
80 | __u32 __reserved_3 : 24, |
81 | dest : 8; | |
e1d91978 | 82 | } __attribute__ ((packed)); |
e1d91978 | 83 | |
89027d35 SS |
84 | struct IR_IO_APIC_route_entry { |
85 | __u64 vector : 8, | |
86 | zero : 3, | |
87 | index2 : 1, | |
88 | delivery_status : 1, | |
89 | polarity : 1, | |
90 | irr : 1, | |
91 | trigger : 1, | |
92 | mask : 1, | |
93 | reserved : 31, | |
94 | format : 1, | |
95 | index : 15; | |
e1d91978 TG |
96 | } __attribute__ ((packed)); |
97 | ||
abb00522 TG |
98 | #define IOAPIC_AUTO -1 |
99 | #define IOAPIC_EDGE 0 | |
100 | #define IOAPIC_LEVEL 1 | |
101 | ||
e1d91978 TG |
102 | #ifdef CONFIG_X86_IO_APIC |
103 | ||
104 | /* | |
105 | * # of IO-APICs and # of IRQ routing registers | |
106 | */ | |
107 | extern int nr_ioapics; | |
e1d91978 | 108 | |
d5371430 SS |
109 | extern int mpc_ioapic_id(int ioapic); |
110 | extern unsigned int mpc_ioapic_addr(int ioapic); | |
c040aaeb | 111 | extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic); |
a1a33fa3 | 112 | |
d5371430 | 113 | #define MP_MAX_IOAPIC_PIN 127 |
e1d91978 TG |
114 | |
115 | /* # of MP IRQ source entries */ | |
116 | extern int mp_irq_entries; | |
117 | ||
118 | /* MP IRQ source entries */ | |
c2c21745 | 119 | extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
e1d91978 | 120 | |
e1d91978 TG |
121 | /* Older SiS APIC requires we rewrite the index register */ |
122 | extern int sis_apic_bug; | |
123 | ||
124 | /* 1 if "noapic" boot option passed */ | |
125 | extern int skip_ioapic_setup; | |
126 | ||
a9322f64 SA |
127 | /* 1 if "noapic" boot option passed */ |
128 | extern int noioapicquirk; | |
129 | ||
9197979b SA |
130 | /* -1 if "noapic" boot option passed */ |
131 | extern int noioapicreroute; | |
132 | ||
e1d91978 TG |
133 | /* |
134 | * If we use the IO-APIC for IRQ routing, disable automatic | |
135 | * assignment of PCI IRQ's. | |
136 | */ | |
137 | #define io_apic_assign_pci_irqs \ | |
138 | (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) | |
139 | ||
e5198075 | 140 | struct io_apic_irq_attr; |
9b1b0e42 | 141 | struct irq_cfg; |
e5198075 YL |
142 | extern int io_apic_set_pci_routing(struct device *dev, int irq, |
143 | struct io_apic_irq_attr *irq_attr); | |
3eb2be5f | 144 | extern void setup_IO_APIC_irq_extra(u32 gsi); |
857fdc53 | 145 | extern void ioapic_insert_resources(void); |
e1d91978 | 146 | |
9b1b0e42 JR |
147 | extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *, |
148 | unsigned int, int, | |
149 | struct io_apic_irq_attr *); | |
150 | extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); | |
a6a25dd3 | 151 | |
7601384f JR |
152 | extern void native_compose_msi_msg(struct pci_dev *pdev, |
153 | unsigned int irq, unsigned int dest, | |
154 | struct msi_msg *msg, u8 hpet_id); | |
da165322 | 155 | extern void native_eoi_ioapic_pin(int apic, int pin, int vector); |
3eb2be5f JL |
156 | extern int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
157 | struct io_apic_irq_attr *attr); | |
ff973d04 | 158 | |
31dce14a SS |
159 | extern int save_ioapic_entries(void); |
160 | extern void mask_ioapic_entries(void); | |
161 | extern int restore_ioapic_entries(void); | |
4dc2f96c | 162 | |
de934103 | 163 | extern void setup_ioapic_ids_from_mpc(void); |
a38c5380 | 164 | extern void setup_ioapic_ids_from_mpc_nocheck(void); |
2a4ab640 FT |
165 | |
166 | struct mp_ioapic_gsi{ | |
eddb0c55 EB |
167 | u32 gsi_base; |
168 | u32 gsi_end; | |
2a4ab640 | 169 | }; |
a4384df3 | 170 | extern u32 gsi_top; |
3eb2be5f JL |
171 | |
172 | extern int mp_find_ioapic(u32 gsi); | |
173 | extern int mp_find_ioapic_pin(int ioapic, u32 gsi); | |
18e48551 | 174 | extern u32 mp_pin_to_gsi(int ioapic, int pin); |
6b9fb708 | 175 | extern int mp_map_gsi_to_irq(u32 gsi); |
3eb2be5f | 176 | extern void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); |
05ddafb1 | 177 | extern void __init pre_init_apic_IRQ0(void); |
2a4ab640 | 178 | |
2d8009ba FT |
179 | extern void mp_save_irq(struct mpc_intsrc *m); |
180 | ||
7167d08e HK |
181 | extern void disable_ioapic_support(void); |
182 | ||
4a8e2a31 KRW |
183 | extern void __init native_io_apic_init_mappings(void); |
184 | extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); | |
185 | extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val); | |
186 | extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val); | |
1c4248ca | 187 | extern void native_disable_io_apic(void); |
afcc8a40 JR |
188 | extern void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries); |
189 | extern void intel_ir_io_apic_print_entries(unsigned int apic, unsigned int nr_entries); | |
373dd7a2 JR |
190 | extern int native_ioapic_set_affinity(struct irq_data *, |
191 | const struct cpumask *, | |
192 | bool); | |
4a8e2a31 KRW |
193 | |
194 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
195 | { | |
196 | return x86_io_apic_ops.read(apic, reg); | |
197 | } | |
198 | ||
199 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
200 | { | |
201 | x86_io_apic_ops.write(apic, reg, value); | |
202 | } | |
203 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
204 | { | |
205 | x86_io_apic_ops.modify(apic, reg, value); | |
206 | } | |
da165322 JR |
207 | |
208 | extern void io_apic_eoi(unsigned int apic, unsigned int vector); | |
209 | ||
e1d91978 | 210 | #else /* !CONFIG_X86_IO_APIC */ |
78f28b7c | 211 | |
e1d91978 | 212 | #define io_apic_assign_pci_irqs 0 |
de934103 | 213 | #define setup_ioapic_ids_from_mpc x86_init_noop |
857fdc53 | 214 | static inline void ioapic_insert_resources(void) { } |
a4384df3 | 215 | #define gsi_top (NR_IRQS_LEGACY) |
eddb0c55 | 216 | static inline int mp_find_ioapic(u32 gsi) { return 0; } |
18e48551 | 217 | static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; } |
6b9fb708 | 218 | static inline int mp_map_gsi_to_irq(u32 gsi) { return gsi; } |
78f28b7c | 219 | |
4966e1af JP |
220 | struct io_apic_irq_attr; |
221 | static inline int io_apic_set_pci_routing(struct device *dev, int irq, | |
222 | struct io_apic_irq_attr *irq_attr) { return 0; } | |
7d0f1926 | 223 | |
31dce14a | 224 | static inline int save_ioapic_entries(void) |
7d0f1926 HK |
225 | { |
226 | return -ENOMEM; | |
227 | } | |
228 | ||
31dce14a SS |
229 | static inline void mask_ioapic_entries(void) { } |
230 | static inline int restore_ioapic_entries(void) | |
7d0f1926 HK |
231 | { |
232 | return -ENOMEM; | |
233 | } | |
234 | ||
b6a1432d | 235 | static inline void mp_save_irq(struct mpc_intsrc *m) { }; |
7167d08e | 236 | static inline void disable_ioapic_support(void) { } |
4a8e2a31 KRW |
237 | #define native_io_apic_init_mappings NULL |
238 | #define native_io_apic_read NULL | |
239 | #define native_io_apic_write NULL | |
240 | #define native_io_apic_modify NULL | |
1c4248ca | 241 | #define native_disable_io_apic NULL |
afcc8a40 | 242 | #define native_io_apic_print_entries NULL |
373dd7a2 | 243 | #define native_ioapic_set_affinity NULL |
a6a25dd3 | 244 | #define native_setup_ioapic_entry NULL |
7601384f | 245 | #define native_compose_msi_msg NULL |
da165322 | 246 | #define native_eoi_ioapic_pin NULL |
96a388de | 247 | #endif |
e1d91978 | 248 | |
1965aae3 | 249 | #endif /* _ASM_X86_IO_APIC_H */ |