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1965aae3 PA |
1 | #ifndef _ASM_X86_IRQ_VECTORS_H |
2 | #define _ASM_X86_IRQ_VECTORS_H | |
9b7dc567 TG |
3 | |
4 | #include <linux/threads.h> | |
5 | ||
6 | #define NMI_VECTOR 0x02 | |
7 | ||
8 | /* | |
9 | * IDT vectors usable for external interrupt sources start | |
10 | * at 0x20: | |
11 | */ | |
12 | #define FIRST_EXTERNAL_VECTOR 0x20 | |
13 | ||
14 | #ifdef CONFIG_X86_32 | |
15 | # define SYSCALL_VECTOR 0x80 | |
16 | #else | |
17 | # define IA32_SYSCALL_VECTOR 0x80 | |
18 | #endif | |
19 | ||
20 | /* | |
9b7dc567 | 21 | * Reserve the lowest usable priority level 0x20 - 0x2f for triggering |
497c9a19 | 22 | * cleanup after irq migration. |
9b7dc567 TG |
23 | */ |
24 | #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR | |
25 | ||
26 | /* | |
497c9a19 | 27 | * Vectors 0x30-0x3f are used for ISA interrupts. |
9b7dc567 TG |
28 | */ |
29 | #define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10) | |
30 | #define IRQ1_VECTOR (IRQ0_VECTOR + 1) | |
31 | #define IRQ2_VECTOR (IRQ0_VECTOR + 2) | |
32 | #define IRQ3_VECTOR (IRQ0_VECTOR + 3) | |
33 | #define IRQ4_VECTOR (IRQ0_VECTOR + 4) | |
34 | #define IRQ5_VECTOR (IRQ0_VECTOR + 5) | |
35 | #define IRQ6_VECTOR (IRQ0_VECTOR + 6) | |
36 | #define IRQ7_VECTOR (IRQ0_VECTOR + 7) | |
37 | #define IRQ8_VECTOR (IRQ0_VECTOR + 8) | |
38 | #define IRQ9_VECTOR (IRQ0_VECTOR + 9) | |
39 | #define IRQ10_VECTOR (IRQ0_VECTOR + 10) | |
40 | #define IRQ11_VECTOR (IRQ0_VECTOR + 11) | |
41 | #define IRQ12_VECTOR (IRQ0_VECTOR + 12) | |
42 | #define IRQ13_VECTOR (IRQ0_VECTOR + 13) | |
43 | #define IRQ14_VECTOR (IRQ0_VECTOR + 14) | |
44 | #define IRQ15_VECTOR (IRQ0_VECTOR + 15) | |
45 | ||
46 | /* | |
47 | * Special IRQ vectors used by the SMP architecture, 0xf0-0xff | |
48 | * | |
49 | * some of the following vectors are 'rare', they are merged | |
50 | * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. | |
51 | * TLB, reschedule and local APIC vectors are performance-critical. | |
52 | * | |
53 | * Vectors 0xf0-0xfa are free (reserved for future Linux use). | |
54 | */ | |
55 | #ifdef CONFIG_X86_32 | |
56 | ||
57 | # define SPURIOUS_APIC_VECTOR 0xff | |
58 | # define ERROR_APIC_VECTOR 0xfe | |
59 | # define INVALIDATE_TLB_VECTOR 0xfd | |
60 | # define RESCHEDULE_VECTOR 0xfc | |
61 | # define CALL_FUNCTION_VECTOR 0xfb | |
1a781a77 | 62 | # define CALL_FUNCTION_SINGLE_VECTOR 0xfa |
9b7dc567 TG |
63 | # define THERMAL_APIC_VECTOR 0xf0 |
64 | ||
65 | #else | |
66 | ||
67 | #define SPURIOUS_APIC_VECTOR 0xff | |
68 | #define ERROR_APIC_VECTOR 0xfe | |
69 | #define RESCHEDULE_VECTOR 0xfd | |
70 | #define CALL_FUNCTION_VECTOR 0xfc | |
1a781a77 | 71 | #define CALL_FUNCTION_SINGLE_VECTOR 0xfb |
9b7dc567 TG |
72 | #define THERMAL_APIC_VECTOR 0xfa |
73 | #define THRESHOLD_APIC_VECTOR 0xf9 | |
99dd8713 | 74 | #define UV_BAU_MESSAGE 0xf8 |
9b7dc567 TG |
75 | #define INVALIDATE_TLB_VECTOR_END 0xf7 |
76 | #define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */ | |
77 | ||
78 | #define NUM_INVALIDATE_TLB_VECTORS 8 | |
79 | ||
80 | #endif | |
81 | ||
82 | /* | |
83 | * Local APIC timer IRQ vector is on a different priority level, | |
84 | * to work around the 'lost local interrupt if more than 2 IRQ | |
85 | * sources per level' errata. | |
86 | */ | |
87 | #define LOCAL_TIMER_VECTOR 0xef | |
88 | ||
89 | /* | |
90 | * First APIC vector available to drivers: (vectors 0x30-0xee) we | |
91 | * start at 0x31(0x41) to spread out vectors evenly between priority | |
92 | * levels. (0x80 is the syscall vector) | |
93 | */ | |
497c9a19 | 94 | #define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2) |
9b7dc567 | 95 | |
9b7dc567 TG |
96 | #define NR_VECTORS 256 |
97 | ||
98 | #define FPU_IRQ 13 | |
99 | ||
100 | #define FIRST_VM86_IRQ 3 | |
101 | #define LAST_VM86_IRQ 15 | |
102 | #define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) | |
103 | ||
3c7569b2 EB |
104 | #ifdef CONFIG_X86_64 |
105 | # if NR_CPUS < MAX_IO_APICS | |
106 | # define NR_IRQS (NR_VECTORS + (32 * NR_CPUS)) | |
107 | # else | |
108 | # define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS)) | |
109 | # endif | |
3c7569b2 EB |
110 | |
111 | #elif !defined(CONFIG_X86_VOYAGER) | |
9b7dc567 | 112 | |
8bfaba87 | 113 | # if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS) |
9b7dc567 TG |
114 | |
115 | # define NR_IRQS 224 | |
116 | ||
9b7dc567 TG |
117 | # else /* IO_APIC || PARAVIRT */ |
118 | ||
119 | # define NR_IRQS 16 | |
9b7dc567 TG |
120 | |
121 | # endif | |
122 | ||
123 | #else /* !VISWS && !VOYAGER */ | |
124 | ||
125 | # define NR_IRQS 224 | |
9b7dc567 TG |
126 | |
127 | #endif /* VISWS */ | |
128 | ||
129 | /* Voyager specific defines */ | |
130 | /* These define the CPIs we use in linux */ | |
131 | #define VIC_CPI_LEVEL0 0 | |
132 | #define VIC_CPI_LEVEL1 1 | |
133 | /* now the fake CPIs */ | |
134 | #define VIC_TIMER_CPI 2 | |
135 | #define VIC_INVALIDATE_CPI 3 | |
136 | #define VIC_RESCHEDULE_CPI 4 | |
137 | #define VIC_ENABLE_IRQ_CPI 5 | |
138 | #define VIC_CALL_FUNCTION_CPI 6 | |
1a781a77 | 139 | #define VIC_CALL_FUNCTION_SINGLE_CPI 7 |
9b7dc567 TG |
140 | |
141 | /* Now the QIC CPIs: Since we don't need the two initial levels, | |
142 | * these are 2 less than the VIC CPIs */ | |
143 | #define QIC_CPI_OFFSET 1 | |
144 | #define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET) | |
145 | #define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET) | |
146 | #define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET) | |
147 | #define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET) | |
148 | #define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET) | |
1a781a77 | 149 | #define QIC_CALL_FUNCTION_SINGLE_CPI (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET) |
9b7dc567 TG |
150 | |
151 | #define VIC_START_FAKE_CPI VIC_TIMER_CPI | |
1a781a77 | 152 | #define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_SINGLE_CPI |
9b7dc567 TG |
153 | |
154 | /* this is the SYS_INT CPI. */ | |
155 | #define VIC_SYS_INT 8 | |
156 | #define VIC_CMN_INT 15 | |
157 | ||
158 | /* This is the boot CPI for alternate processors. It gets overwritten | |
159 | * by the above once the system has activated all available processors */ | |
160 | #define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0 | |
161 | #define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8) | |
162 | ||
163 | ||
1965aae3 | 164 | #endif /* _ASM_X86_IRQ_VECTORS_H */ |