Commit | Line | Data |
---|---|---|
a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
d828199e MT |
25 | #include <linux/pvclock_gtod.h> |
26 | #include <linux/clocksource.h> | |
34c16eec | 27 | |
50d0a0f9 | 28 | #include <asm/pvclock-abi.h> |
e01a1b57 | 29 | #include <asm/desc.h> |
0bed3b56 | 30 | #include <asm/mtrr.h> |
9962d032 | 31 | #include <asm/msr-index.h> |
3ee89722 | 32 | #include <asm/asm.h> |
e01a1b57 | 33 | |
cbf64358 | 34 | #define KVM_MAX_VCPUS 255 |
a59cb29e | 35 | #define KVM_SOFT_MAX_VCPUS 160 |
1d4e7e3c | 36 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
37 | /* memory slots that are not exposed to userspace */ |
38 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 39 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 40 | |
69a9f69b | 41 | #define KVM_PIO_PAGE_OFFSET 1 |
542472b5 | 42 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
69a9f69b | 43 | |
8175e5b7 AG |
44 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
45 | ||
cfec82cb JR |
46 | #define CR0_RESERVED_BITS \ |
47 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
48 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
49 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
50 | ||
346874c9 | 51 | #define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL |
cfaa790a | 52 | #define CR3_PCID_INVD BIT_64(63) |
cfec82cb JR |
53 | #define CR4_RESERVED_BITS \ |
54 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
55 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 56 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 57 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
56d6efc2 | 58 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP)) |
cfec82cb JR |
59 | |
60 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
61 | ||
62 | ||
cd6e8f87 | 63 | |
cd6e8f87 | 64 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
65 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
66 | ||
cd6e8f87 ZX |
67 | #define UNMAPPED_GVA (~(gpa_t)0) |
68 | ||
ec04b260 | 69 | /* KVM Hugepage definitions for x86 */ |
04326caa | 70 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
71 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
72 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
73 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
74 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
75 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 76 | |
6d9d41e5 CD |
77 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
78 | { | |
79 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
80 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
81 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
82 | } | |
83 | ||
d657a98e ZX |
84 | #define KVM_PERMILLE_MMU_PAGES 20 |
85 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
86 | #define KVM_MMU_HASH_SHIFT 10 |
87 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
88 | #define KVM_MIN_FREE_MMU_PAGES 5 |
89 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 90 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 91 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 92 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 93 | |
af585b92 GN |
94 | #define ASYNC_PF_PER_VCPU 64 |
95 | ||
5fdbf976 | 96 | enum kvm_reg { |
2b3ccfa0 ZX |
97 | VCPU_REGS_RAX = 0, |
98 | VCPU_REGS_RCX = 1, | |
99 | VCPU_REGS_RDX = 2, | |
100 | VCPU_REGS_RBX = 3, | |
101 | VCPU_REGS_RSP = 4, | |
102 | VCPU_REGS_RBP = 5, | |
103 | VCPU_REGS_RSI = 6, | |
104 | VCPU_REGS_RDI = 7, | |
105 | #ifdef CONFIG_X86_64 | |
106 | VCPU_REGS_R8 = 8, | |
107 | VCPU_REGS_R9 = 9, | |
108 | VCPU_REGS_R10 = 10, | |
109 | VCPU_REGS_R11 = 11, | |
110 | VCPU_REGS_R12 = 12, | |
111 | VCPU_REGS_R13 = 13, | |
112 | VCPU_REGS_R14 = 14, | |
113 | VCPU_REGS_R15 = 15, | |
114 | #endif | |
5fdbf976 | 115 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
116 | NR_VCPU_REGS |
117 | }; | |
118 | ||
6de4f3ad AK |
119 | enum kvm_reg_ex { |
120 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 121 | VCPU_EXREG_CR3, |
6de12732 | 122 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 123 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
124 | }; |
125 | ||
2b3ccfa0 | 126 | enum { |
81609e3e | 127 | VCPU_SREG_ES, |
2b3ccfa0 | 128 | VCPU_SREG_CS, |
81609e3e | 129 | VCPU_SREG_SS, |
2b3ccfa0 | 130 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
131 | VCPU_SREG_FS, |
132 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
133 | VCPU_SREG_TR, |
134 | VCPU_SREG_LDTR, | |
135 | }; | |
136 | ||
56e82318 | 137 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 138 | |
d657a98e ZX |
139 | #define KVM_NR_MEM_OBJS 40 |
140 | ||
42dbaa5a JK |
141 | #define KVM_NR_DB_REGS 4 |
142 | ||
143 | #define DR6_BD (1 << 13) | |
144 | #define DR6_BS (1 << 14) | |
6f43ed01 NA |
145 | #define DR6_RTM (1 << 16) |
146 | #define DR6_FIXED_1 0xfffe0ff0 | |
147 | #define DR6_INIT 0xffff0ff0 | |
148 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
149 | |
150 | #define DR7_BP_EN_MASK 0x000000ff | |
151 | #define DR7_GE (1 << 9) | |
152 | #define DR7_GD (1 << 13) | |
153 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 154 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 155 | |
c205fb7d NA |
156 | #define PFERR_PRESENT_BIT 0 |
157 | #define PFERR_WRITE_BIT 1 | |
158 | #define PFERR_USER_BIT 2 | |
159 | #define PFERR_RSVD_BIT 3 | |
160 | #define PFERR_FETCH_BIT 4 | |
161 | ||
162 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
163 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
164 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
165 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
166 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
167 | ||
41383771 GN |
168 | /* apic attention bits */ |
169 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
170 | /* |
171 | * The following bit is set with PV-EOI, unset on EOI. | |
172 | * We detect PV-EOI changes by guest by comparing | |
173 | * this bit with PV-EOI in guest memory. | |
174 | * See the implementation in apic_update_pv_eoi. | |
175 | */ | |
176 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 177 | |
d657a98e ZX |
178 | /* |
179 | * We don't want allocation failures within the mmu code, so we preallocate | |
180 | * enough memory for a single page fault in a cache. | |
181 | */ | |
182 | struct kvm_mmu_memory_cache { | |
183 | int nobjs; | |
184 | void *objects[KVM_NR_MEM_OBJS]; | |
185 | }; | |
186 | ||
d657a98e ZX |
187 | union kvm_mmu_page_role { |
188 | unsigned word; | |
189 | struct { | |
7d76b4d3 | 190 | unsigned level:4; |
5b7e0102 | 191 | unsigned cr4_pae:1; |
7d76b4d3 | 192 | unsigned quadrant:2; |
f6e2c02b | 193 | unsigned direct:1; |
7d76b4d3 | 194 | unsigned access:3; |
2e53d63a | 195 | unsigned invalid:1; |
9645bb56 | 196 | unsigned nxe:1; |
3dbe1415 | 197 | unsigned cr0_wp:1; |
411c588d | 198 | unsigned smep_andnot_wp:1; |
0be0226f | 199 | unsigned smap_andnot_wp:1; |
699023e2 PB |
200 | unsigned :8; |
201 | ||
202 | /* | |
203 | * This is left at the top of the word so that | |
204 | * kvm_memslots_for_spte_role can extract it with a | |
205 | * simple shift. While there is room, give it a whole | |
206 | * byte so it is also faster to load it from memory. | |
207 | */ | |
208 | unsigned smm:8; | |
d657a98e ZX |
209 | }; |
210 | }; | |
211 | ||
212 | struct kvm_mmu_page { | |
213 | struct list_head link; | |
214 | struct hlist_node hash_link; | |
215 | ||
216 | /* | |
217 | * The following two entries are used to key the shadow page in the | |
218 | * hash table. | |
219 | */ | |
220 | gfn_t gfn; | |
221 | union kvm_mmu_page_role role; | |
222 | ||
223 | u64 *spt; | |
224 | /* hold the gfn of each spte inside spt */ | |
225 | gfn_t *gfns; | |
4731d4c7 | 226 | bool unsync; |
0571d366 | 227 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 228 | unsigned int unsync_children; |
67052b35 | 229 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
f6f8adee XG |
230 | |
231 | /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ | |
5304b8d3 | 232 | unsigned long mmu_valid_gen; |
f6f8adee | 233 | |
0074ff63 | 234 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
235 | |
236 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
237 | /* |
238 | * Used out of the mmu-lock to avoid reading spte values while an | |
239 | * update is in progress; see the comments in __get_spte_lockless(). | |
240 | */ | |
c2a2ac2b XG |
241 | int clear_spte_count; |
242 | #endif | |
243 | ||
0cbf8e43 | 244 | /* Number of writes since the last time traversal visited this page. */ |
a30f47cb | 245 | int write_flooding_count; |
d657a98e ZX |
246 | }; |
247 | ||
1c08364c AK |
248 | struct kvm_pio_request { |
249 | unsigned long count; | |
1c08364c AK |
250 | int in; |
251 | int port; | |
252 | int size; | |
1c08364c AK |
253 | }; |
254 | ||
a0a64f50 XG |
255 | struct rsvd_bits_validate { |
256 | u64 rsvd_bits_mask[2][4]; | |
257 | u64 bad_mt_xwr; | |
258 | }; | |
259 | ||
d657a98e ZX |
260 | /* |
261 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
262 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
263 | * mode. | |
264 | */ | |
265 | struct kvm_mmu { | |
f43addd4 | 266 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 267 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 268 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
269 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
270 | bool prefault); | |
6389ee94 AK |
271 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
272 | struct x86_exception *fault); | |
1871c602 | 273 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 274 | struct x86_exception *exception); |
54987b7a PB |
275 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
276 | struct x86_exception *exception); | |
e8bc217a | 277 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 278 | struct kvm_mmu_page *sp); |
a7052897 | 279 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 280 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 281 | u64 *spte, const void *pte); |
d657a98e ZX |
282 | hpa_t root_hpa; |
283 | int root_level; | |
284 | int shadow_root_level; | |
a770f6f2 | 285 | union kvm_mmu_page_role base_role; |
c5a78f2b | 286 | bool direct_map; |
d657a98e | 287 | |
97d64b78 AK |
288 | /* |
289 | * Bitmap; bit set = permission fault | |
290 | * Byte index: page fault error code [4:1] | |
291 | * Bit index: pte permissions in ACC_* format | |
292 | */ | |
293 | u8 permissions[16]; | |
294 | ||
d657a98e | 295 | u64 *pae_root; |
81407ca5 | 296 | u64 *lm_root; |
c258b62b XG |
297 | |
298 | /* | |
299 | * check zero bits on shadow page table entries, these | |
300 | * bits include not only hardware reserved bits but also | |
301 | * the bits spte never used. | |
302 | */ | |
303 | struct rsvd_bits_validate shadow_zero_check; | |
304 | ||
a0a64f50 | 305 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 306 | |
6fd01b71 AK |
307 | /* |
308 | * Bitmap: bit set = last pte in walk | |
309 | * index[0:1]: level (zero-based) | |
310 | * index[2]: pte.ps | |
311 | */ | |
312 | u8 last_pte_bitmap; | |
313 | ||
2d48a985 JR |
314 | bool nx; |
315 | ||
ff03a073 | 316 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
317 | }; |
318 | ||
f5132b01 GN |
319 | enum pmc_type { |
320 | KVM_PMC_GP = 0, | |
321 | KVM_PMC_FIXED, | |
322 | }; | |
323 | ||
324 | struct kvm_pmc { | |
325 | enum pmc_type type; | |
326 | u8 idx; | |
327 | u64 counter; | |
328 | u64 eventsel; | |
329 | struct perf_event *perf_event; | |
330 | struct kvm_vcpu *vcpu; | |
331 | }; | |
332 | ||
333 | struct kvm_pmu { | |
334 | unsigned nr_arch_gp_counters; | |
335 | unsigned nr_arch_fixed_counters; | |
336 | unsigned available_event_types; | |
337 | u64 fixed_ctr_ctrl; | |
338 | u64 global_ctrl; | |
339 | u64 global_status; | |
340 | u64 global_ovf_ctrl; | |
341 | u64 counter_bitmask[2]; | |
342 | u64 global_ctrl_mask; | |
103af0a9 | 343 | u64 reserved_bits; |
f5132b01 | 344 | u8 version; |
15c7ad51 RR |
345 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
346 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
347 | struct irq_work irq_work; |
348 | u64 reprogram_pmi; | |
349 | }; | |
350 | ||
25462f7f WH |
351 | struct kvm_pmu_ops; |
352 | ||
360b948d PB |
353 | enum { |
354 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 355 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 356 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
357 | }; |
358 | ||
86fd5270 XG |
359 | struct kvm_mtrr_range { |
360 | u64 base; | |
361 | u64 mask; | |
19efffa2 | 362 | struct list_head node; |
86fd5270 XG |
363 | }; |
364 | ||
70109e7d | 365 | struct kvm_mtrr { |
86fd5270 | 366 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 367 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 368 | u64 deftype; |
19efffa2 XG |
369 | |
370 | struct list_head head; | |
70109e7d XG |
371 | }; |
372 | ||
e83d5887 AS |
373 | /* Hyper-V per vcpu emulation context */ |
374 | struct kvm_vcpu_hv { | |
375 | u64 hv_vapic; | |
376 | }; | |
377 | ||
ad312c7c | 378 | struct kvm_vcpu_arch { |
5fdbf976 MT |
379 | /* |
380 | * rip and regs accesses must go through | |
381 | * kvm_{register,rip}_{read,write} functions. | |
382 | */ | |
383 | unsigned long regs[NR_VCPU_REGS]; | |
384 | u32 regs_avail; | |
385 | u32 regs_dirty; | |
34c16eec ZX |
386 | |
387 | unsigned long cr0; | |
e8467fda | 388 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
389 | unsigned long cr2; |
390 | unsigned long cr3; | |
391 | unsigned long cr4; | |
fc78f519 | 392 | unsigned long cr4_guest_owned_bits; |
34c16eec | 393 | unsigned long cr8; |
1371d904 | 394 | u32 hflags; |
f6801dff | 395 | u64 efer; |
34c16eec ZX |
396 | u64 apic_base; |
397 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
41383771 | 398 | unsigned long apic_attention; |
e1035715 | 399 | int32_t apic_arb_prio; |
34c16eec | 400 | int mp_state; |
34c16eec | 401 | u64 ia32_misc_enable_msr; |
64d60670 | 402 | u64 smbase; |
b209749f | 403 | bool tpr_access_reporting; |
20300099 | 404 | u64 ia32_xss; |
34c16eec | 405 | |
14dfe855 JR |
406 | /* |
407 | * Paging state of the vcpu | |
408 | * | |
409 | * If the vcpu runs in guest mode with two level paging this still saves | |
410 | * the paging mode of the l1 guest. This context is always used to | |
411 | * handle faults. | |
412 | */ | |
34c16eec | 413 | struct kvm_mmu mmu; |
8df25a32 | 414 | |
6539e738 JR |
415 | /* |
416 | * Paging state of an L2 guest (used for nested npt) | |
417 | * | |
418 | * This context will save all necessary information to walk page tables | |
419 | * of the an L2 guest. This context is only initialized for page table | |
420 | * walking and not for faulting since we never handle l2 page faults on | |
421 | * the host. | |
422 | */ | |
423 | struct kvm_mmu nested_mmu; | |
424 | ||
14dfe855 JR |
425 | /* |
426 | * Pointer to the mmu context currently used for | |
427 | * gva_to_gpa translations. | |
428 | */ | |
429 | struct kvm_mmu *walk_mmu; | |
430 | ||
53c07b18 | 431 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
432 | struct kvm_mmu_memory_cache mmu_page_cache; |
433 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
434 | ||
98918833 | 435 | struct fpu guest_fpu; |
c447e76b | 436 | bool eager_fpu; |
2acf923e | 437 | u64 xcr0; |
d7876f1b | 438 | u64 guest_supported_xcr0; |
4344ee98 | 439 | u32 guest_xstate_size; |
34c16eec | 440 | |
34c16eec ZX |
441 | struct kvm_pio_request pio; |
442 | void *pio_data; | |
443 | ||
66fd3f7f GN |
444 | u8 event_exit_inst_len; |
445 | ||
298101da AK |
446 | struct kvm_queued_exception { |
447 | bool pending; | |
448 | bool has_error_code; | |
ce7ddec4 | 449 | bool reinject; |
298101da AK |
450 | u8 nr; |
451 | u32 error_code; | |
452 | } exception; | |
453 | ||
937a7eae AK |
454 | struct kvm_queued_interrupt { |
455 | bool pending; | |
66fd3f7f | 456 | bool soft; |
937a7eae AK |
457 | u8 nr; |
458 | } interrupt; | |
459 | ||
34c16eec ZX |
460 | int halt_request; /* real mode on Intel only */ |
461 | ||
462 | int cpuid_nent; | |
07716717 | 463 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
464 | |
465 | int maxphyaddr; | |
466 | ||
34c16eec ZX |
467 | /* emulate context */ |
468 | ||
469 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
470 | bool emulate_regs_need_sync_to_vcpu; |
471 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 472 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
473 | |
474 | gpa_t time; | |
50d0a0f9 | 475 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 476 | unsigned int hw_tsc_khz; |
0b79459b AH |
477 | struct gfn_to_hva_cache pv_time; |
478 | bool pv_time_enabled; | |
51d59c6b MT |
479 | /* set guest stopped flag in pvclock flags field */ |
480 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
481 | |
482 | struct { | |
483 | u64 msr_val; | |
484 | u64 last_steal; | |
485 | u64 accum_steal; | |
486 | struct gfn_to_hva_cache stime; | |
487 | struct kvm_steal_time steal; | |
488 | } st; | |
489 | ||
1d5f066e | 490 | u64 last_guest_tsc; |
6f526ec5 | 491 | u64 last_host_tsc; |
0dd6a6ed | 492 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
493 | u64 this_tsc_nsec; |
494 | u64 this_tsc_write; | |
0d3da0d2 | 495 | u64 this_tsc_generation; |
c285545f | 496 | bool tsc_catchup; |
cc578287 ZA |
497 | bool tsc_always_catchup; |
498 | s8 virtual_tsc_shift; | |
499 | u32 virtual_tsc_mult; | |
500 | u32 virtual_tsc_khz; | |
ba904635 | 501 | s64 ia32_tsc_adjust_msr; |
3419ffc8 | 502 | |
7460fb4a AK |
503 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
504 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
505 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 506 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 507 | |
70109e7d | 508 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 509 | u64 pat; |
42dbaa5a | 510 | |
360b948d | 511 | unsigned switch_db_regs; |
42dbaa5a JK |
512 | unsigned long db[KVM_NR_DB_REGS]; |
513 | unsigned long dr6; | |
514 | unsigned long dr7; | |
515 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 516 | unsigned long guest_debug_dr7; |
890ca9ae HY |
517 | |
518 | u64 mcg_cap; | |
519 | u64 mcg_status; | |
520 | u64 mcg_ctl; | |
521 | u64 *mce_banks; | |
94fe45da | 522 | |
bebb106a XG |
523 | /* Cache MMIO info */ |
524 | u64 mmio_gva; | |
525 | unsigned access; | |
526 | gfn_t mmio_gfn; | |
56f17dd3 | 527 | u64 mmio_gen; |
bebb106a | 528 | |
f5132b01 GN |
529 | struct kvm_pmu pmu; |
530 | ||
94fe45da | 531 | /* used for guest single stepping over the given code position */ |
94fe45da | 532 | unsigned long singlestep_rip; |
f92653ee | 533 | |
e83d5887 | 534 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
535 | |
536 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 537 | |
1cb3f3ae XG |
538 | unsigned long last_retry_eip; |
539 | unsigned long last_retry_addr; | |
540 | ||
af585b92 GN |
541 | struct { |
542 | bool halted; | |
543 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
544 | struct gfn_to_hva_cache data; |
545 | u64 msr_val; | |
7c90705b | 546 | u32 id; |
6adba527 | 547 | bool send_user_only; |
af585b92 | 548 | } apf; |
2b036c6b BO |
549 | |
550 | /* OSVW MSRs (AMD only) */ | |
551 | struct { | |
552 | u64 length; | |
553 | u64 status; | |
554 | } osvw; | |
ae7a2a3f MT |
555 | |
556 | struct { | |
557 | u64 msr_val; | |
558 | struct gfn_to_hva_cache data; | |
559 | } pv_eoi; | |
93c05d3e XG |
560 | |
561 | /* | |
562 | * Indicate whether the access faults on its page table in guest | |
563 | * which is set when fix page fault and used to detect unhandeable | |
564 | * instruction. | |
565 | */ | |
566 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
567 | |
568 | /* set at EPT violation at this point */ | |
569 | unsigned long exit_qualification; | |
6aef266c SV |
570 | |
571 | /* pv related host specific info */ | |
572 | struct { | |
573 | bool pv_unhalted; | |
574 | } pv; | |
34c16eec ZX |
575 | }; |
576 | ||
db3fe4eb | 577 | struct kvm_lpage_info { |
db3fe4eb TY |
578 | int write_count; |
579 | }; | |
580 | ||
581 | struct kvm_arch_memory_slot { | |
d89cc617 | 582 | unsigned long *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb TY |
583 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
584 | }; | |
585 | ||
3548a259 RK |
586 | /* |
587 | * We use as the mode the number of bits allocated in the LDR for the | |
588 | * logical processor ID. It happens that these are all powers of two. | |
589 | * This makes it is very easy to detect cases where the APICs are | |
590 | * configured for multiple modes; in that case, we cannot use the map and | |
591 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
592 | */ | |
593 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
594 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
595 | #define KVM_APIC_MODE_X2APIC 16 | |
596 | ||
1e08ec4a GN |
597 | struct kvm_apic_map { |
598 | struct rcu_head rcu; | |
3548a259 | 599 | u8 mode; |
1e08ec4a GN |
600 | struct kvm_lapic *phys_map[256]; |
601 | /* first index is cluster id second is cpu id in a cluster */ | |
602 | struct kvm_lapic *logical_map[16][16]; | |
603 | }; | |
604 | ||
e83d5887 AS |
605 | /* Hyper-V emulation context */ |
606 | struct kvm_hv { | |
607 | u64 hv_guest_os_id; | |
608 | u64 hv_hypercall; | |
609 | u64 hv_tsc_page; | |
e7d9513b AS |
610 | |
611 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
612 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
613 | u64 hv_crash_ctl; | |
e83d5887 AS |
614 | }; |
615 | ||
fef9cce0 | 616 | struct kvm_arch { |
49d5ca26 | 617 | unsigned int n_used_mmu_pages; |
f05e70ac | 618 | unsigned int n_requested_mmu_pages; |
39de71ec | 619 | unsigned int n_max_mmu_pages; |
332b207d | 620 | unsigned int indirect_shadow_pages; |
5304b8d3 | 621 | unsigned long mmu_valid_gen; |
f05e70ac ZX |
622 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
623 | /* | |
624 | * Hash table of struct kvm_mmu_page. | |
625 | */ | |
626 | struct list_head active_mmu_pages; | |
365c8868 XG |
627 | struct list_head zapped_obsolete_pages; |
628 | ||
4d5c5d0f | 629 | struct list_head assigned_dev_head; |
19de40a8 | 630 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 631 | bool iommu_noncoherent; |
e0f0bbc5 AW |
632 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
633 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
634 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
635 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
636 | struct kvm_pic *vpic; |
637 | struct kvm_ioapic *vioapic; | |
7837699f | 638 | struct kvm_pit *vpit; |
42720138 | 639 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
640 | struct mutex apic_map_lock; |
641 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 642 | |
bfc6d222 | 643 | unsigned int tss_addr; |
c24ae0dc | 644 | bool apic_access_page_done; |
18068523 GOC |
645 | |
646 | gpa_t wall_clock; | |
b7ebfb05 | 647 | |
b7ebfb05 | 648 | bool ept_identity_pagetable_done; |
b927a3ce | 649 | gpa_t ept_identity_map_addr; |
5550af4d SY |
650 | |
651 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 652 | s64 kvmclock_offset; |
038f8c11 | 653 | raw_spinlock_t tsc_write_lock; |
f38e098f | 654 | u64 last_tsc_nsec; |
f38e098f | 655 | u64 last_tsc_write; |
5d3cb0f6 | 656 | u32 last_tsc_khz; |
e26101b1 ZA |
657 | u64 cur_tsc_nsec; |
658 | u64 cur_tsc_write; | |
659 | u64 cur_tsc_offset; | |
0d3da0d2 | 660 | u64 cur_tsc_generation; |
b48aa97e | 661 | int nr_vcpus_matched_tsc; |
ffde22ac | 662 | |
d828199e MT |
663 | spinlock_t pvclock_gtod_sync_lock; |
664 | bool use_master_clock; | |
665 | u64 master_kernel_ns; | |
666 | cycle_t master_cycle_now; | |
7e44e449 | 667 | struct delayed_work kvmclock_update_work; |
332967a3 | 668 | struct delayed_work kvmclock_sync_work; |
d828199e | 669 | |
ffde22ac | 670 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 671 | |
6ef768fa PB |
672 | /* reads protected by irq_srcu, writes by irq_lock */ |
673 | struct hlist_head mask_notifier_list; | |
674 | ||
e83d5887 | 675 | struct kvm_hv hyperv; |
b034cf01 XG |
676 | |
677 | #ifdef CONFIG_KVM_MMU_AUDIT | |
678 | int audit_point; | |
679 | #endif | |
54750f2c MT |
680 | |
681 | bool boot_vcpu_runs_old_kvmclock; | |
d71ba788 | 682 | u32 bsp_vcpu_id; |
90de4a18 NA |
683 | |
684 | u64 disabled_quirks; | |
d69fb81f ZX |
685 | }; |
686 | ||
0711456c ZX |
687 | struct kvm_vm_stat { |
688 | u32 mmu_shadow_zapped; | |
689 | u32 mmu_pte_write; | |
690 | u32 mmu_pte_updated; | |
691 | u32 mmu_pde_zapped; | |
692 | u32 mmu_flooded; | |
693 | u32 mmu_recycled; | |
dfc5aa00 | 694 | u32 mmu_cache_miss; |
4731d4c7 | 695 | u32 mmu_unsync; |
0711456c | 696 | u32 remote_tlb_flush; |
05da4558 | 697 | u32 lpages; |
0711456c ZX |
698 | }; |
699 | ||
77b4c255 ZX |
700 | struct kvm_vcpu_stat { |
701 | u32 pf_fixed; | |
702 | u32 pf_guest; | |
703 | u32 tlb_flush; | |
704 | u32 invlpg; | |
705 | ||
706 | u32 exits; | |
707 | u32 io_exits; | |
708 | u32 mmio_exits; | |
709 | u32 signal_exits; | |
710 | u32 irq_window_exits; | |
f08864b4 | 711 | u32 nmi_window_exits; |
77b4c255 | 712 | u32 halt_exits; |
f7819512 | 713 | u32 halt_successful_poll; |
77b4c255 ZX |
714 | u32 halt_wakeup; |
715 | u32 request_irq_exits; | |
716 | u32 irq_exits; | |
717 | u32 host_state_reload; | |
718 | u32 efer_reload; | |
719 | u32 fpu_reload; | |
720 | u32 insn_emulation; | |
721 | u32 insn_emulation_fail; | |
f11c3a8d | 722 | u32 hypercalls; |
fa89a817 | 723 | u32 irq_injections; |
c4abb7c9 | 724 | u32 nmi_injections; |
77b4c255 | 725 | }; |
ad312c7c | 726 | |
8a76d7f2 JR |
727 | struct x86_instruction_info; |
728 | ||
8fe8ab46 WA |
729 | struct msr_data { |
730 | bool host_initiated; | |
731 | u32 index; | |
732 | u64 data; | |
733 | }; | |
734 | ||
cb5281a5 PB |
735 | struct kvm_lapic_irq { |
736 | u32 vector; | |
b7cb2231 PB |
737 | u16 delivery_mode; |
738 | u16 dest_mode; | |
739 | bool level; | |
740 | u16 trig_mode; | |
cb5281a5 PB |
741 | u32 shorthand; |
742 | u32 dest_id; | |
93bbf0b8 | 743 | bool msi_redir_hint; |
cb5281a5 PB |
744 | }; |
745 | ||
ea4a5ff8 ZX |
746 | struct kvm_x86_ops { |
747 | int (*cpu_has_kvm_support)(void); /* __init */ | |
748 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
749 | int (*hardware_enable)(void); |
750 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
751 | void (*check_processor_compatibility)(void *rtn); |
752 | int (*hardware_setup)(void); /* __init */ | |
753 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 754 | bool (*cpu_has_accelerated_tpr)(void); |
6d396b55 | 755 | bool (*cpu_has_high_real_mode_segbase)(void); |
0e851880 | 756 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
757 | |
758 | /* Create, but do not attach this VCPU */ | |
759 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
760 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 761 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
762 | |
763 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
764 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
765 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 766 | |
c8639010 | 767 | void (*update_db_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 768 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 769 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
770 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
771 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
772 | struct kvm_segment *var, int seg); | |
2e4d2653 | 773 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
774 | void (*set_segment)(struct kvm_vcpu *vcpu, |
775 | struct kvm_segment *var, int seg); | |
776 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 777 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 778 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
779 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
780 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
781 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 782 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 783 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
784 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
785 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
786 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
787 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
788 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
789 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 790 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 791 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 792 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
793 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
794 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
0fdd74f7 | 795 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 796 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
797 | |
798 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 799 | |
851ba692 AK |
800 | void (*run)(struct kvm_vcpu *vcpu); |
801 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 802 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 803 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 804 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
805 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
806 | unsigned char *hypercall_addr); | |
66fd3f7f | 807 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 808 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 809 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
810 | bool has_error_code, u32 error_code, |
811 | bool reinject); | |
b463a6f7 | 812 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 813 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 814 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
815 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
816 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
817 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
818 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 819 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
c7c9c56c YZ |
820 | int (*vm_has_apicv)(struct kvm *kvm); |
821 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); | |
822 | void (*hwapic_isr_update)(struct kvm *kvm, int isr); | |
823 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); | |
8d14695f | 824 | void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); |
4256f43f | 825 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d YZ |
826 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
827 | void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 828 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 829 | int (*get_tdp_level)(void); |
4b12f0de | 830 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 831 | int (*get_lpage_level)(void); |
4e47c7a6 | 832 | bool (*rdtscp_supported)(void); |
ad756a16 | 833 | bool (*invpcid_supported)(void); |
f1e2b260 | 834 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 835 | |
1c97f0a0 JR |
836 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
837 | ||
d4330ef2 JR |
838 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
839 | ||
f5f48ee1 SY |
840 | bool (*has_wbinvd_exit)(void); |
841 | ||
cc578287 | 842 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
ba904635 | 843 | u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu); |
99e3e30a ZA |
844 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
845 | ||
857e4099 | 846 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
886b470c | 847 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc); |
857e4099 | 848 | |
586f9607 | 849 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
850 | |
851 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
852 | struct x86_instruction_info *info, | |
853 | enum x86_intercept_stage stage); | |
a547c6db | 854 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 855 | bool (*mpx_supported)(void); |
55412b2e | 856 | bool (*xsaves_supported)(void); |
b6b8a145 JK |
857 | |
858 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
ae97a3b8 RK |
859 | |
860 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
861 | |
862 | /* | |
863 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
864 | * be valid if the specific arch has hardware-accelerated dirty logging | |
865 | * mechanism. Currently only for PML on VMX. | |
866 | * | |
867 | * - slot_enable_log_dirty: | |
868 | * called when enabling log dirty mode for the slot. | |
869 | * - slot_disable_log_dirty: | |
870 | * called when disabling log dirty mode for the slot. | |
871 | * also called when slot is created with log dirty disabled. | |
872 | * - flush_log_dirty: | |
873 | * called before reporting dirty_bitmap to userspace. | |
874 | * - enable_log_dirty_pt_masked: | |
875 | * called when reenabling log dirty for the GFNs in the mask after | |
876 | * corresponding bits are cleared in slot->dirty_bitmap. | |
877 | */ | |
878 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
879 | struct kvm_memory_slot *slot); | |
880 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
881 | struct kvm_memory_slot *slot); | |
882 | void (*flush_log_dirty)(struct kvm *kvm); | |
883 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
884 | struct kvm_memory_slot *slot, | |
885 | gfn_t offset, unsigned long mask); | |
25462f7f WH |
886 | /* pmu operations of sub-arch */ |
887 | const struct kvm_pmu_ops *pmu_ops; | |
ea4a5ff8 ZX |
888 | }; |
889 | ||
af585b92 | 890 | struct kvm_arch_async_pf { |
7c90705b | 891 | u32 token; |
af585b92 | 892 | gfn_t gfn; |
fb67e14f | 893 | unsigned long cr3; |
c4806acd | 894 | bool direct_map; |
af585b92 GN |
895 | }; |
896 | ||
97896d04 ZX |
897 | extern struct kvm_x86_ops *kvm_x86_ops; |
898 | ||
f1e2b260 MT |
899 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
900 | s64 adjustment) | |
901 | { | |
902 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
903 | } | |
904 | ||
905 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
906 | { | |
907 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
908 | } | |
909 | ||
54f1585a ZX |
910 | int kvm_mmu_module_init(void); |
911 | void kvm_mmu_module_exit(void); | |
912 | ||
913 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
914 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
8a3c1a33 | 915 | void kvm_mmu_setup(struct kvm_vcpu *vcpu); |
7b52345e | 916 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 917 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a | 918 | |
8a3c1a33 | 919 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
920 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
921 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 922 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 923 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
924 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
925 | struct kvm_memory_slot *memslot); | |
926 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
927 | struct kvm_memory_slot *memslot); | |
928 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
929 | struct kvm_memory_slot *memslot); | |
930 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
931 | struct kvm_memory_slot *slot, | |
932 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 933 | void kvm_mmu_zap_all(struct kvm *kvm); |
54bf36aa | 934 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); |
3ad82a7e | 935 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
936 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
937 | ||
ff03a073 | 938 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 939 | |
3200f405 | 940 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 941 | const void *val, int bytes); |
2f333bcb | 942 | |
6ef768fa PB |
943 | struct kvm_irq_mask_notifier { |
944 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
945 | int irq; | |
946 | struct hlist_node link; | |
947 | }; | |
948 | ||
949 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
950 | struct kvm_irq_mask_notifier *kimn); | |
951 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
952 | struct kvm_irq_mask_notifier *kimn); | |
953 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
954 | bool mask); | |
955 | ||
2f333bcb | 956 | extern bool tdp_enabled; |
9f811285 | 957 | |
a3e06bbe LJ |
958 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
959 | ||
92a1f12d JR |
960 | /* control of guest tsc rate supported? */ |
961 | extern bool kvm_has_tsc_control; | |
962 | /* minimum supported tsc_khz for guests */ | |
963 | extern u32 kvm_min_guest_tsc_khz; | |
964 | /* maximum supported tsc_khz for guests */ | |
965 | extern u32 kvm_max_guest_tsc_khz; | |
966 | ||
54f1585a | 967 | enum emulation_result { |
ac0a48c3 PB |
968 | EMULATE_DONE, /* no further processing */ |
969 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
970 | EMULATE_FAIL, /* can't emulate this instruction */ |
971 | }; | |
972 | ||
571008da SY |
973 | #define EMULTYPE_NO_DECODE (1 << 0) |
974 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 975 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 976 | #define EMULTYPE_RETRY (1 << 3) |
991eebf9 | 977 | #define EMULTYPE_NO_REEXECUTE (1 << 4) |
dc25e89e AP |
978 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
979 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
980 | |
981 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
982 | int emulation_type) | |
983 | { | |
dc25e89e | 984 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
985 | } |
986 | ||
f2b4b7dd | 987 | void kvm_enable_efer_bits(u64); |
384bb783 | 988 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 989 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 990 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
991 | |
992 | struct x86_emulate_ctxt; | |
993 | ||
cf8f70bf | 994 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
995 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
996 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
5cb56059 | 997 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 998 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 999 | |
3e6e0aab | 1000 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1001 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1002 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1003 | |
7f3d35fd KW |
1004 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1005 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1006 | |
49a9b07e | 1007 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1008 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1009 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1010 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1011 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1012 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1013 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1014 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1015 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1016 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1017 | |
609e36d3 | 1018 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1019 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1020 | |
91586a3b JK |
1021 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1022 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1023 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1024 | |
298101da AK |
1025 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1026 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1027 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1028 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1029 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1030 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1031 | gfn_t gfn, void *data, int offset, int len, | |
1032 | u32 access); | |
0a79b009 | 1033 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1034 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1035 | |
1a577b72 MT |
1036 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1037 | int irq_source_id, int level) | |
1038 | { | |
1039 | /* Logical OR for level trig interrupt */ | |
1040 | if (level) | |
1041 | __set_bit(irq_source_id, irq_state); | |
1042 | else | |
1043 | __clear_bit(irq_source_id, irq_state); | |
1044 | ||
1045 | return !!(*irq_state); | |
1046 | } | |
1047 | ||
1048 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); | |
1049 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1050 | |
3419ffc8 SY |
1051 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1052 | ||
54f1585a | 1053 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 1054 | const u8 *new, int bytes); |
1cb3f3ae | 1055 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1056 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1057 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1058 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1059 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1060 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
54987b7a PB |
1061 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1062 | struct x86_exception *exception); | |
ab9ae313 AK |
1063 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1064 | struct x86_exception *exception); | |
1065 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1066 | struct x86_exception *exception); | |
1067 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1068 | struct x86_exception *exception); | |
1069 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1070 | struct x86_exception *exception); | |
54f1585a ZX |
1071 | |
1072 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
1073 | ||
dc25e89e AP |
1074 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
1075 | void *insn, int insn_len); | |
a7052897 | 1076 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
d8d173da | 1077 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); |
34c16eec | 1078 | |
18552672 | 1079 | void kvm_enable_tdp(void); |
5f4cb662 | 1080 | void kvm_disable_tdp(void); |
18552672 | 1081 | |
54987b7a PB |
1082 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1083 | struct x86_exception *exception) | |
e459e322 XG |
1084 | { |
1085 | return gpa; | |
1086 | } | |
1087 | ||
ec6d273d ZX |
1088 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1089 | { | |
1090 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1091 | ||
1092 | return (struct kvm_mmu_page *)page_private(page); | |
1093 | } | |
1094 | ||
d6e88aec | 1095 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1096 | { |
1097 | u16 ldt; | |
1098 | asm("sldt %0" : "=g"(ldt)); | |
1099 | return ldt; | |
1100 | } | |
1101 | ||
d6e88aec | 1102 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1103 | { |
1104 | asm("lldt %0" : : "rm"(sel)); | |
1105 | } | |
ec6d273d | 1106 | |
ec6d273d ZX |
1107 | #ifdef CONFIG_X86_64 |
1108 | static inline unsigned long read_msr(unsigned long msr) | |
1109 | { | |
1110 | u64 value; | |
1111 | ||
1112 | rdmsrl(msr, value); | |
1113 | return value; | |
1114 | } | |
1115 | #endif | |
1116 | ||
ec6d273d ZX |
1117 | static inline u32 get_rdx_init_val(void) |
1118 | { | |
1119 | return 0x600; /* P6 family */ | |
1120 | } | |
1121 | ||
c1a5d4f9 AK |
1122 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1123 | { | |
1124 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1125 | } | |
1126 | ||
854e8bb1 NA |
1127 | static inline u64 get_canonical(u64 la) |
1128 | { | |
1129 | return ((int64_t)la << 16) >> 16; | |
1130 | } | |
1131 | ||
1132 | static inline bool is_noncanonical_address(u64 la) | |
1133 | { | |
1134 | #ifdef CONFIG_X86_64 | |
1135 | return get_canonical(la) != la; | |
1136 | #else | |
1137 | return false; | |
1138 | #endif | |
1139 | } | |
1140 | ||
ec6d273d ZX |
1141 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1142 | #define TSS_BASE_SIZE 0x68 | |
1143 | #define TSS_IOPB_SIZE (65536 / 8) | |
1144 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1145 | #define RMODE_TSS_SIZE \ |
1146 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1147 | |
37817f29 IE |
1148 | enum { |
1149 | TASK_SWITCH_CALL = 0, | |
1150 | TASK_SWITCH_IRET = 1, | |
1151 | TASK_SWITCH_JMP = 2, | |
1152 | TASK_SWITCH_GATE = 3, | |
1153 | }; | |
1154 | ||
1371d904 | 1155 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1156 | #define HF_HIF_MASK (1 << 1) |
1157 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1158 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1159 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1160 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1161 | #define HF_SMM_MASK (1 << 6) |
1162 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1163 | |
699023e2 PB |
1164 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1165 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1166 | ||
1167 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1168 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1169 | |
4ecac3fd AK |
1170 | /* |
1171 | * Hardware virtualization extension instructions may fault if a | |
1172 | * reboot turns off virtualization while processes are running. | |
1173 | * Trap the fault and ignore the instruction if that happens. | |
1174 | */ | |
b7c4145b | 1175 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1176 | |
5e520e62 | 1177 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1178 | "666: " insn "\n\t" \ |
b7c4145b | 1179 | "668: \n\t" \ |
18b13e54 | 1180 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1181 | "667: \n\t" \ |
5e520e62 | 1182 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1183 | "cmpb $0, kvm_rebooting \n\t" \ |
1184 | "jne 668b \n\t" \ | |
8ceed347 | 1185 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 1186 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 1187 | ".popsection \n\t" \ |
3ee89722 | 1188 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1189 | |
5e520e62 AK |
1190 | #define __kvm_handle_fault_on_reboot(insn) \ |
1191 | ____kvm_handle_fault_on_reboot(insn, "") | |
1192 | ||
e930bffe AA |
1193 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
1194 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
b3ae2096 | 1195 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1196 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1197 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 1198 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1199 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1200 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1201 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1202 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1203 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1204 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
fe71557a TC |
1205 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
1206 | unsigned long address); | |
e930bffe | 1207 | |
18863bdd | 1208 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1209 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1210 | |
82b32774 | 1211 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1212 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1213 | ||
af585b92 GN |
1214 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1215 | struct kvm_async_pf *work); | |
1216 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1217 | struct kvm_async_pf *work); | |
56028d08 GN |
1218 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1219 | struct kvm_async_pf *work); | |
7c90705b | 1220 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1221 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1222 | ||
db8fcefa AP |
1223 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
1224 | ||
f5132b01 GN |
1225 | int kvm_is_in_guest(void); |
1226 | ||
9da0e4d5 PB |
1227 | int __x86_set_memory_region(struct kvm *kvm, |
1228 | const struct kvm_userspace_memory_region *mem); | |
1229 | int x86_set_memory_region(struct kvm *kvm, | |
1230 | const struct kvm_userspace_memory_region *mem); | |
d71ba788 PB |
1231 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1232 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1233 | |
1965aae3 | 1234 | #endif /* _ASM_X86_KVM_HOST_H */ |