Commit | Line | Data |
---|---|---|
1965aae3 PA |
1 | #ifndef _ASM_X86_MCE_H |
2 | #define _ASM_X86_MCE_H | |
e2f43029 | 3 | |
af170c50 | 4 | #include <uapi/asm/mce.h> |
e2f43029 | 5 | |
f51bde6f BP |
6 | /* |
7 | * Machine Check support for x86 | |
8 | */ | |
9 | ||
10 | /* MCG_CAP register defines */ | |
11 | #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ | |
12 | #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ | |
13 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ | |
14 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ | |
15 | #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ | |
16 | #define MCG_EXT_CNT_SHIFT 16 | |
17 | #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) | |
18 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
19 | ||
20 | /* MCG_STATUS register defines */ | |
21 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ | |
22 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
23 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
24 | ||
25 | /* MCi_STATUS register defines */ | |
26 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ | |
27 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
28 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
29 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
30 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
31 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
32 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
33 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
34 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
35 | #define MCACOD 0xffff /* MCA Error Code */ | |
36 | ||
37 | /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ | |
38 | #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ | |
39 | #define MCACOD_SCRUBMSK 0xfff0 | |
40 | #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ | |
41 | #define MCACOD_DATA 0x0134 /* Data Load */ | |
42 | #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ | |
43 | ||
44 | /* MCi_MISC register defines */ | |
45 | #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) | |
46 | #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) | |
47 | #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ | |
48 | #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ | |
49 | #define MCI_MISC_ADDR_PHYS 2 /* physical address */ | |
50 | #define MCI_MISC_ADDR_MEM 3 /* memory address */ | |
51 | #define MCI_MISC_ADDR_GENERIC 7 /* generic */ | |
52 | ||
53 | /* CTL2 register defines */ | |
54 | #define MCI_CTL2_CMCI_EN (1ULL << 30) | |
55 | #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL | |
56 | ||
57 | #define MCJ_CTX_MASK 3 | |
58 | #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) | |
59 | #define MCJ_CTX_RANDOM 0 /* inject context: random */ | |
60 | #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ | |
61 | #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ | |
62 | #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ | |
63 | #define MCJ_EXCEPTION 0x8 /* raise as exception */ | |
a9093684 | 64 | #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ |
f51bde6f BP |
65 | |
66 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ | |
67 | ||
68 | /* Software defined banks */ | |
69 | #define MCE_EXTENDED_BANK 128 | |
70 | #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) | |
71 | #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) | |
72 | ||
73 | #define MCE_LOG_LEN 32 | |
74 | #define MCE_LOG_SIGNATURE "MACHINECHECK" | |
75 | ||
76 | /* | |
77 | * This structure contains all data related to the MCE log. Also | |
78 | * carries a signature to make it easier to find from external | |
79 | * debugging tools. Each entry is only valid when its finished flag | |
80 | * is set. | |
81 | */ | |
82 | struct mce_log { | |
83 | char signature[12]; /* "MACHINECHECK" */ | |
84 | unsigned len; /* = MCE_LOG_LEN */ | |
85 | unsigned next; | |
86 | unsigned flags; | |
87 | unsigned recordlen; /* length of struct mce */ | |
88 | struct mce entry[MCE_LOG_LEN]; | |
89 | }; | |
d203f0b8 BP |
90 | |
91 | struct mca_config { | |
92 | bool dont_log_ce; | |
7af19e4a BP |
93 | bool cmci_disabled; |
94 | bool ignore_ce; | |
1462594b BP |
95 | bool disabled; |
96 | bool ser; | |
97 | bool bios_cmci_threshold; | |
d203f0b8 | 98 | u8 banks; |
84c2559d | 99 | s8 bootlog; |
d203f0b8 | 100 | int tolerant; |
84c2559d | 101 | int monarch_timeout; |
7af19e4a | 102 | int panic_timeout; |
84c2559d | 103 | u32 rip_msr; |
d203f0b8 BP |
104 | }; |
105 | ||
7af19e4a | 106 | extern struct mca_config mca_cfg; |
3653ada5 BP |
107 | extern void mce_register_decode_chain(struct notifier_block *nb); |
108 | extern void mce_unregister_decode_chain(struct notifier_block *nb); | |
df39a2e4 | 109 | |
9e55e44e HS |
110 | #include <linux/percpu.h> |
111 | #include <linux/init.h> | |
60063497 | 112 | #include <linux/atomic.h> |
9e55e44e | 113 | |
c6978369 | 114 | extern int mce_p5_enabled; |
e2f43029 | 115 | |
58995d2d | 116 | #ifdef CONFIG_X86_MCE |
a2202aa2 | 117 | int mcheck_init(void); |
5e09954a | 118 | void mcheck_cpu_init(struct cpuinfo_x86 *c); |
58995d2d | 119 | #else |
a2202aa2 | 120 | static inline int mcheck_init(void) { return 0; } |
5e09954a | 121 | static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} |
58995d2d HS |
122 | #endif |
123 | ||
9e55e44e HS |
124 | #ifdef CONFIG_X86_ANCIENT_MCE |
125 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c); | |
126 | void winchip_mcheck_init(struct cpuinfo_x86 *c); | |
c6978369 | 127 | static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } |
9e55e44e HS |
128 | #else |
129 | static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} | |
130 | static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} | |
c6978369 | 131 | static inline void enable_p5_mce(void) {} |
9e55e44e HS |
132 | #endif |
133 | ||
b5f2fa4e | 134 | void mce_setup(struct mce *m); |
e2f43029 | 135 | void mce_log(struct mce *m); |
d6126ef5 | 136 | DECLARE_PER_CPU(struct device *, mce_device); |
e2f43029 | 137 | |
41fdff32 | 138 | /* |
3ccdccfa AK |
139 | * Maximum banks number. |
140 | * This is the limit of the current register layout on | |
141 | * Intel CPUs. | |
41fdff32 | 142 | */ |
3ccdccfa | 143 | #define MAX_NR_BANKS 32 |
41fdff32 | 144 | |
e2f43029 TG |
145 | #ifdef CONFIG_X86_MCE_INTEL |
146 | void mce_intel_feature_init(struct cpuinfo_x86 *c); | |
88ccbedd AK |
147 | void cmci_clear(void); |
148 | void cmci_reenable(void); | |
7a0c819d | 149 | void cmci_rediscover(void); |
88ccbedd | 150 | void cmci_recheck(void); |
e2f43029 TG |
151 | #else |
152 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } | |
88ccbedd AK |
153 | static inline void cmci_clear(void) {} |
154 | static inline void cmci_reenable(void) {} | |
7a0c819d | 155 | static inline void cmci_rediscover(void) {} |
88ccbedd | 156 | static inline void cmci_recheck(void) {} |
e2f43029 TG |
157 | #endif |
158 | ||
159 | #ifdef CONFIG_X86_MCE_AMD | |
160 | void mce_amd_feature_init(struct cpuinfo_x86 *c); | |
161 | #else | |
162 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } | |
163 | #endif | |
164 | ||
38736072 | 165 | int mce_available(struct cpuinfo_x86 *c); |
88ccbedd | 166 | |
01ca79f1 | 167 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
ca84f696 | 168 | DECLARE_PER_CPU(unsigned, mce_poll_count); |
01ca79f1 | 169 | |
e2f43029 TG |
170 | extern atomic_t mce_entry; |
171 | ||
ee031c31 AK |
172 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
173 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); | |
174 | ||
b79109c3 AK |
175 | enum mcp_flags { |
176 | MCP_TIMESTAMP = (1 << 0), /* log time stamp */ | |
177 | MCP_UC = (1 << 1), /* log uncorrected errors */ | |
5679af4c | 178 | MCP_DONTLOG = (1 << 2), /* only clear, don't log */ |
b79109c3 | 179 | }; |
38736072 | 180 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
b79109c3 | 181 | |
9ff36ee9 | 182 | int mce_notify_irq(void); |
9b1beaf2 | 183 | void mce_notify_process(void); |
e2f43029 | 184 | |
ea149b36 | 185 | DECLARE_PER_CPU(struct mce, injectm); |
66f5ddf3 LT |
186 | |
187 | extern void register_mce_write_callback(ssize_t (*)(struct file *filp, | |
188 | const char __user *ubuf, | |
189 | size_t usize, loff_t *off)); | |
ea149b36 | 190 | |
58995d2d HS |
191 | /* |
192 | * Exception handler | |
193 | */ | |
194 | ||
195 | /* Call the installed machine check handler for this CPU setup. */ | |
196 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); | |
197 | void do_machine_check(struct pt_regs *, long); | |
198 | ||
199 | /* | |
200 | * Threshold handler | |
201 | */ | |
e2f43029 | 202 | |
b2762686 | 203 | extern void (*mce_threshold_vector)(void); |
58995d2d | 204 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
b2762686 | 205 | |
e8ce2c5e HS |
206 | /* |
207 | * Thermal handler | |
208 | */ | |
209 | ||
e8ce2c5e HS |
210 | void intel_init_thermal(struct cpuinfo_x86 *c); |
211 | ||
e8ce2c5e | 212 | void mce_log_therm_throt_event(__u64 status); |
a2202aa2 | 213 | |
9e76a97e D |
214 | /* Interrupt Handler for core thermal thresholds */ |
215 | extern int (*platform_thermal_notify)(__u64 msr_val); | |
216 | ||
a2202aa2 YW |
217 | #ifdef CONFIG_X86_THERMAL_VECTOR |
218 | extern void mcheck_intel_therm_init(void); | |
219 | #else | |
220 | static inline void mcheck_intel_therm_init(void) { } | |
221 | #endif | |
222 | ||
d334a491 HY |
223 | /* |
224 | * Used by APEI to report memory error via /dev/mcelog | |
225 | */ | |
226 | ||
227 | struct cper_sec_mem_err; | |
228 | extern void apei_mce_report_mem_error(int corrected, | |
229 | struct cper_sec_mem_err *mem_err); | |
230 | ||
1965aae3 | 231 | #endif /* _ASM_X86_MCE_H */ |