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1965aae3 PA |
1 | #ifndef _ASM_X86_MPSPEC_H |
2 | #define _ASM_X86_MPSPEC_H | |
c2805aa1 | 3 | |
86c9835b IM |
4 | #include <linux/init.h> |
5 | ||
c2805aa1 | 6 | #include <asm/mpspec_def.h> |
b3f1b617 | 7 | #include <asm/x86_init.h> |
c2805aa1 | 8 | |
11494547 | 9 | extern int apic_version[MAX_APICS]; |
a1ae299d | 10 | extern int pic_mode; |
11494547 | 11 | |
96a388de | 12 | #ifdef CONFIG_X86_32 |
b2af018f IM |
13 | |
14 | /* | |
15 | * Summit or generic (i.e. installer) kernels need lots of bus entries. | |
16 | * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. | |
17 | */ | |
18 | #if CONFIG_BASE_SMALL == 0 | |
19 | # define MAX_MP_BUSSES 260 | |
20 | #else | |
21 | # define MAX_MP_BUSSES 32 | |
22 | #endif | |
23 | ||
24 | #define MAX_IRQ_SOURCES 256 | |
c2805aa1 | 25 | |
c2805aa1 | 26 | extern unsigned int def_to_bigsmp; |
ae9d983b | 27 | extern u8 apicid_2_node[]; |
c2805aa1 | 28 | |
d49c4288 YL |
29 | #ifdef CONFIG_X86_NUMAQ |
30 | extern int mp_bus_id_to_node[MAX_MP_BUSSES]; | |
31 | extern int mp_bus_id_to_local[MAX_MP_BUSSES]; | |
32 | extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; | |
33 | #endif | |
34 | ||
b2af018f | 35 | #define MAX_APICID 256 |
ae9d983b | 36 | |
b2af018f | 37 | #else /* CONFIG_X86_64: */ |
c2805aa1 | 38 | |
b2af018f | 39 | #define MAX_MP_BUSSES 256 |
c2805aa1 | 40 | /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ |
b2af018f | 41 | #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) |
c2805aa1 | 42 | |
b2af018f | 43 | #endif /* CONFIG_X86_64 */ |
ab530e1f | 44 | |
c0a282c2 AS |
45 | #if defined(CONFIG_MCA) || defined(CONFIG_EISA) |
46 | extern int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
47 | #endif | |
48 | ||
a6333c3c | 49 | extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
c0a282c2 | 50 | |
c2805aa1 | 51 | extern unsigned int boot_cpu_physical_apicid; |
e0da3364 | 52 | extern unsigned int max_physical_apicid; |
c2805aa1 TG |
53 | extern int mpc_default_type; |
54 | extern unsigned long mp_lapic_addr; | |
55 | ||
b3f1b617 TG |
56 | #ifdef CONFIG_X86_LOCAL_APIC |
57 | extern int smp_found_config; | |
58 | #else | |
59 | # define smp_found_config 0 | |
60 | #endif | |
61 | ||
62 | static inline void get_smp_config(void) | |
63 | { | |
64 | x86_init.mpparse.get_smp_config(0); | |
65 | } | |
66 | ||
67 | static inline void early_get_smp_config(void) | |
68 | { | |
69 | x86_init.mpparse.get_smp_config(1); | |
70 | } | |
71 | ||
72 | static inline void find_smp_config(void) | |
73 | { | |
b24c2a92 | 74 | x86_init.mpparse.find_smp_config(); |
b3f1b617 | 75 | } |
550fe4f1 | 76 | |
af1cf204 | 77 | #ifdef CONFIG_X86_MPPARSE |
2944e16b | 78 | extern void early_reserve_e820_mpc_new(void); |
abfe0af9 | 79 | extern int enable_update_mptable; |
fd6c6661 | 80 | extern int default_mpc_apic_id(struct mpc_cpu *m); |
72302142 | 81 | extern void default_smp_read_mpc_oem(struct mpc_table *mpc); |
90e1c696 TG |
82 | # ifdef CONFIG_X86_IO_APIC |
83 | extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str); | |
84 | # else | |
85 | # define default_mpc_oem_bus_info NULL | |
86 | # endif | |
b24c2a92 | 87 | extern void default_find_smp_config(void); |
b3f1b617 | 88 | extern void default_get_smp_config(unsigned int early); |
af1cf204 IM |
89 | #else |
90 | static inline void early_reserve_e820_mpc_new(void) { } | |
abfe0af9 | 91 | #define enable_update_mptable 0 |
fd6c6661 | 92 | #define default_mpc_apic_id NULL |
72302142 | 93 | #define default_smp_read_mpc_oem NULL |
90e1c696 | 94 | #define default_mpc_oem_bus_info NULL |
b24c2a92 | 95 | #define default_find_smp_config x86_init_noop |
b3f1b617 | 96 | #define default_get_smp_config x86_init_uint_noop |
af1cf204 | 97 | #endif |
c2805aa1 | 98 | |
903dcb5a | 99 | void __cpuinit generic_processor_info(int apicid, int version); |
c2805aa1 | 100 | #ifdef CONFIG_ACPI |
a65d1d64 | 101 | extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); |
c2805aa1 TG |
102 | extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, |
103 | u32 gsi); | |
104 | extern void mp_config_acpi_legacy_irqs(void); | |
a2f809b0 YL |
105 | struct device; |
106 | extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level, | |
107 | int active_high_low); | |
c2805aa1 TG |
108 | #endif /* CONFIG_ACPI */ |
109 | ||
110 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
111 | ||
30971e17 | 112 | struct physid_mask { |
c2805aa1 TG |
113 | unsigned long mask[PHYSID_ARRAY_SIZE]; |
114 | }; | |
115 | ||
116 | typedef struct physid_mask physid_mask_t; | |
117 | ||
118 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
119 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
120 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
30971e17 | 121 | #define physid_test_and_set(physid, map) \ |
c2805aa1 TG |
122 | test_and_set_bit(physid, (map).mask) |
123 | ||
30971e17 | 124 | #define physids_and(dst, src1, src2) \ |
c2805aa1 TG |
125 | bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
126 | ||
30971e17 | 127 | #define physids_or(dst, src1, src2) \ |
c2805aa1 TG |
128 | bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
129 | ||
30971e17 | 130 | #define physids_clear(map) \ |
c2805aa1 TG |
131 | bitmap_zero((map).mask, MAX_APICS) |
132 | ||
30971e17 | 133 | #define physids_complement(dst, src) \ |
c2805aa1 TG |
134 | bitmap_complement((dst).mask, (src).mask, MAX_APICS) |
135 | ||
30971e17 | 136 | #define physids_empty(map) \ |
c2805aa1 TG |
137 | bitmap_empty((map).mask, MAX_APICS) |
138 | ||
30971e17 | 139 | #define physids_equal(map1, map2) \ |
c2805aa1 TG |
140 | bitmap_equal((map1).mask, (map2).mask, MAX_APICS) |
141 | ||
30971e17 | 142 | #define physids_weight(map) \ |
c2805aa1 TG |
143 | bitmap_weight((map).mask, MAX_APICS) |
144 | ||
30971e17 | 145 | #define physids_shift_right(d, s, n) \ |
c2805aa1 TG |
146 | bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) |
147 | ||
30971e17 | 148 | #define physids_shift_left(d, s, n) \ |
c2805aa1 TG |
149 | bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) |
150 | ||
7abc0753 CG |
151 | static inline unsigned long physids_coerce(physid_mask_t *map) |
152 | { | |
153 | return map->mask[0]; | |
154 | } | |
c2805aa1 | 155 | |
7abc0753 CG |
156 | static inline void physids_promote(unsigned long physids, physid_mask_t *map) |
157 | { | |
158 | physids_clear(*map); | |
159 | map->mask[0] = physids; | |
160 | } | |
c2805aa1 | 161 | |
b6df1b8b | 162 | /* Note: will create very large stack frames if physid_mask_t is big */ |
c2805aa1 TG |
163 | #define physid_mask_of_physid(physid) \ |
164 | ({ \ | |
165 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
166 | physid_set(physid, __physid_mask); \ | |
167 | __physid_mask; \ | |
168 | }) | |
169 | ||
b6df1b8b JS |
170 | static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map) |
171 | { | |
172 | physids_clear(*map); | |
173 | physid_set(physid, *map); | |
174 | } | |
175 | ||
c2805aa1 TG |
176 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } |
177 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
178 | ||
179 | extern physid_mask_t phys_cpu_present_map; | |
180 | ||
fb5b33c9 IM |
181 | extern int generic_mps_oem_check(struct mpc_table *, char *, char *); |
182 | ||
183 | extern int default_acpi_madt_oem_check(char *, char *); | |
184 | ||
1965aae3 | 185 | #endif /* _ASM_X86_MPSPEC_H */ |