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1965aae3 PA |
1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H | |
be7baf80 | 3 | |
b72e7464 | 4 | #include "msr-index.h" |
be7baf80 | 5 | |
8f12dea6 | 6 | #ifndef __ASSEMBLY__ |
c210d249 GOC |
7 | |
8 | #include <asm/asm.h> | |
9 | #include <asm/errno.h> | |
6bc1096d | 10 | #include <asm/cpumask.h> |
b72e7464 | 11 | #include <uapi/asm/msr.h> |
6bc1096d BP |
12 | |
13 | struct msr { | |
14 | union { | |
15 | struct { | |
16 | u32 l; | |
17 | u32 h; | |
18 | }; | |
19 | u64 q; | |
20 | }; | |
21 | }; | |
c210d249 | 22 | |
6ede31e0 BP |
23 | struct msr_info { |
24 | u32 msr_no; | |
25 | struct msr reg; | |
26 | struct msr *msrs; | |
27 | int err; | |
28 | }; | |
29 | ||
30 | struct msr_regs_info { | |
31 | u32 *regs; | |
32 | int err; | |
33 | }; | |
34 | ||
1e160cc3 | 35 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
8f12dea6 GOC |
36 | { |
37 | unsigned long low, high; | |
abb0ade0 JP |
38 | asm volatile(".byte 0x0f,0x01,0xf9" |
39 | : "=a" (low), "=d" (high), "=c" (*aux)); | |
41aefdcc | 40 | return low | ((u64)high << 32); |
8f12dea6 GOC |
41 | } |
42 | ||
c210d249 | 43 | /* |
d4f1b103 JS |
44 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
45 | * constraint has different meanings. For i386, "A" means exactly | |
46 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, | |
47 | * it means rax *or* rdx. | |
c210d249 GOC |
48 | */ |
49 | #ifdef CONFIG_X86_64 | |
5a33fcb8 GS |
50 | /* Using 64-bit values saves one instruction clearing the high half of low */ |
51 | #define DECLARE_ARGS(val, low, high) unsigned long low, high | |
52 | #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) | |
c210d249 GOC |
53 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
54 | #else | |
55 | #define DECLARE_ARGS(val, low, high) unsigned long long val | |
56 | #define EAX_EDX_VAL(val, low, high) (val) | |
c210d249 | 57 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
8f12dea6 GOC |
58 | #endif |
59 | ||
be7baf80 TG |
60 | static inline unsigned long long native_read_msr(unsigned int msr) |
61 | { | |
c210d249 | 62 | DECLARE_ARGS(val, low, high); |
be7baf80 | 63 | |
c210d249 GOC |
64 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
65 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
66 | } |
67 | ||
68 | static inline unsigned long long native_read_msr_safe(unsigned int msr, | |
69 | int *err) | |
70 | { | |
c210d249 | 71 | DECLARE_ARGS(val, low, high); |
be7baf80 | 72 | |
08970fc4 | 73 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
74 | "1:\n\t" |
75 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 76 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 77 | ".previous\n\t" |
abb0ade0 | 78 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 79 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
0cc0213e | 80 | : "c" (msr), [fault] "i" (-EIO)); |
c210d249 | 81 | return EAX_EDX_VAL(val, low, high); |
be7baf80 TG |
82 | } |
83 | ||
c9dcda5c GOC |
84 | static inline void native_write_msr(unsigned int msr, |
85 | unsigned low, unsigned high) | |
be7baf80 | 86 | { |
af2b1c60 | 87 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
be7baf80 TG |
88 | } |
89 | ||
0ca59dd9 FW |
90 | /* Can be uninlined because referenced by paravirt */ |
91 | notrace static inline int native_write_msr_safe(unsigned int msr, | |
c9dcda5c | 92 | unsigned low, unsigned high) |
be7baf80 TG |
93 | { |
94 | int err; | |
08970fc4 | 95 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
96 | "1:\n\t" |
97 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 98 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 99 | ".previous\n\t" |
abb0ade0 | 100 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 101 | : [err] "=a" (err) |
c9dcda5c | 102 | : "c" (msr), "0" (low), "d" (high), |
0cc0213e | 103 | [fault] "i" (-EIO) |
af2b1c60 | 104 | : "memory"); |
be7baf80 TG |
105 | return err; |
106 | } | |
107 | ||
1f975f78 AP |
108 | extern int rdmsr_safe_regs(u32 regs[8]); |
109 | extern int wrmsr_safe_regs(u32 regs[8]); | |
132ec92f | 110 | |
4ea1636b AL |
111 | /** |
112 | * rdtsc() - returns the current TSC without ordering constraints | |
113 | * | |
114 | * rdtsc() returns the result of RDTSC as a 64-bit integer. The | |
115 | * only ordering constraint it supplies is the ordering implied by | |
116 | * "asm volatile": it will put the RDTSC in the place you expect. The | |
117 | * CPU can and will speculatively execute that RDTSC, though, so the | |
118 | * results can be non-monotonic if compared on different CPUs. | |
119 | */ | |
120 | static __always_inline unsigned long long rdtsc(void) | |
92767af0 IM |
121 | { |
122 | DECLARE_ARGS(val, low, high); | |
123 | ||
92767af0 | 124 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
92767af0 IM |
125 | |
126 | return EAX_EDX_VAL(val, low, high); | |
127 | } | |
128 | ||
03b9730b AL |
129 | /** |
130 | * rdtsc_ordered() - read the current TSC in program order | |
131 | * | |
132 | * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. | |
133 | * It is ordered like a load to a global in-memory counter. It should | |
134 | * be impossible to observe non-monotonic rdtsc_unordered() behavior | |
135 | * across multiple CPUs as long as the TSC is synced. | |
136 | */ | |
137 | static __always_inline unsigned long long rdtsc_ordered(void) | |
138 | { | |
139 | /* | |
140 | * The RDTSC instruction is not ordered relative to memory | |
141 | * access. The Intel SDM and the AMD APM are both vague on this | |
142 | * point, but empirically an RDTSC instruction can be | |
143 | * speculatively executed before prior loads. An RDTSC | |
144 | * immediately after an appropriate barrier appears to be | |
145 | * ordered as a normal load, that is, it provides the same | |
146 | * ordering guarantees as reading from a global memory location | |
147 | * that some other imaginary CPU is updating continuously with a | |
148 | * time stamp. | |
149 | */ | |
150 | alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, | |
151 | "lfence", X86_FEATURE_LFENCE_RDTSC); | |
152 | return rdtsc(); | |
153 | } | |
154 | ||
99770737 IM |
155 | /* Deprecated, keep it for a cycle for easier merging: */ |
156 | #define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0) | |
157 | ||
b8d1fae7 | 158 | static inline unsigned long long native_read_pmc(int counter) |
be7baf80 | 159 | { |
c210d249 GOC |
160 | DECLARE_ARGS(val, low, high); |
161 | ||
162 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); | |
163 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
164 | } |
165 | ||
166 | #ifdef CONFIG_PARAVIRT | |
167 | #include <asm/paravirt.h> | |
96a388de | 168 | #else |
be7baf80 TG |
169 | #include <linux/errno.h> |
170 | /* | |
171 | * Access to machine-specific registers (available on 586 and better only) | |
172 | * Note: the rd* operations modify the parameters directly (without using | |
173 | * pointer indirection), this allows gcc to optimize better | |
174 | */ | |
175 | ||
1423bed2 | 176 | #define rdmsr(msr, low, high) \ |
abb0ade0 JP |
177 | do { \ |
178 | u64 __val = native_read_msr((msr)); \ | |
1423bed2 BP |
179 | (void)((low) = (u32)__val); \ |
180 | (void)((high) = (u32)(__val >> 32)); \ | |
abb0ade0 | 181 | } while (0) |
be7baf80 | 182 | |
c9dcda5c | 183 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 184 | { |
c9dcda5c | 185 | native_write_msr(msr, low, high); |
be7baf80 TG |
186 | } |
187 | ||
abb0ade0 JP |
188 | #define rdmsrl(msr, val) \ |
189 | ((val) = native_read_msr((msr))) | |
be7baf80 | 190 | |
47edb651 AL |
191 | static inline void wrmsrl(unsigned msr, u64 val) |
192 | { | |
193 | native_write_msr(msr, (u32)val, (u32)(val >> 32)); | |
194 | } | |
be7baf80 TG |
195 | |
196 | /* wrmsr with exception handling */ | |
c9dcda5c | 197 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 198 | { |
c9dcda5c | 199 | return native_write_msr_safe(msr, low, high); |
be7baf80 TG |
200 | } |
201 | ||
060feb65 | 202 | /* rdmsr with exception handling */ |
1423bed2 | 203 | #define rdmsr_safe(msr, low, high) \ |
abb0ade0 JP |
204 | ({ \ |
205 | int __err; \ | |
206 | u64 __val = native_read_msr_safe((msr), &__err); \ | |
1423bed2 BP |
207 | (*low) = (u32)__val; \ |
208 | (*high) = (u32)(__val >> 32); \ | |
abb0ade0 JP |
209 | __err; \ |
210 | }) | |
be7baf80 | 211 | |
1de87bd4 AK |
212 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
213 | { | |
214 | int err; | |
215 | ||
216 | *p = native_read_msr_safe(msr, &err); | |
217 | return err; | |
218 | } | |
177fed1e | 219 | |
abb0ade0 JP |
220 | #define rdpmc(counter, low, high) \ |
221 | do { \ | |
222 | u64 _l = native_read_pmc((counter)); \ | |
223 | (low) = (u32)_l; \ | |
224 | (high) = (u32)(_l >> 32); \ | |
225 | } while (0) | |
be7baf80 | 226 | |
1ff4d58a AK |
227 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
228 | ||
9261e050 AL |
229 | #endif /* !CONFIG_PARAVIRT */ |
230 | ||
cf991de2 AL |
231 | /* |
232 | * 64-bit version of wrmsr_safe(): | |
233 | */ | |
234 | static inline int wrmsrl_safe(u32 msr, u64 val) | |
235 | { | |
236 | return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); | |
237 | } | |
be7baf80 | 238 | |
1423bed2 | 239 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
be7baf80 | 240 | |
5df97400 | 241 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
be7baf80 | 242 | |
50542251 BP |
243 | struct msr *msrs_alloc(void); |
244 | void msrs_free(struct msr *msrs); | |
22085a66 BP |
245 | int msr_set_bit(u32 msr, u8 bit); |
246 | int msr_clear_bit(u32 msr, u8 bit); | |
50542251 | 247 | |
be7baf80 | 248 | #ifdef CONFIG_SMP |
c6f31932 PA |
249 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
250 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
1a6b991a JP |
251 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
252 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); | |
b8a47541 BP |
253 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
254 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); | |
be7baf80 TG |
255 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
256 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
1a6b991a JP |
257 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
258 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); | |
8b956bf1 PA |
259 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
260 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); | |
be7baf80 | 261 | #else /* CONFIG_SMP */ |
c6f31932 | 262 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
be7baf80 TG |
263 | { |
264 | rdmsr(msr_no, *l, *h); | |
c6f31932 | 265 | return 0; |
be7baf80 | 266 | } |
c6f31932 | 267 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
be7baf80 TG |
268 | { |
269 | wrmsr(msr_no, l, h); | |
c6f31932 | 270 | return 0; |
be7baf80 | 271 | } |
1a6b991a JP |
272 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
273 | { | |
274 | rdmsrl(msr_no, *q); | |
275 | return 0; | |
276 | } | |
277 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) | |
278 | { | |
279 | wrmsrl(msr_no, q); | |
280 | return 0; | |
281 | } | |
0d0fbbdd | 282 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
283 | struct msr *msrs) |
284 | { | |
285 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); | |
286 | } | |
0d0fbbdd | 287 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
288 | struct msr *msrs) |
289 | { | |
290 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); | |
291 | } | |
abb0ade0 JP |
292 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
293 | u32 *l, u32 *h) | |
be7baf80 TG |
294 | { |
295 | return rdmsr_safe(msr_no, l, h); | |
296 | } | |
297 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |
298 | { | |
299 | return wrmsr_safe(msr_no, l, h); | |
300 | } | |
1a6b991a JP |
301 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
302 | { | |
303 | return rdmsrl_safe(msr_no, q); | |
304 | } | |
305 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) | |
306 | { | |
307 | return wrmsrl_safe(msr_no, q); | |
308 | } | |
8b956bf1 PA |
309 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
310 | { | |
311 | return rdmsr_safe_regs(regs); | |
312 | } | |
313 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) | |
314 | { | |
315 | return wrmsr_safe_regs(regs); | |
316 | } | |
be7baf80 | 317 | #endif /* CONFIG_SMP */ |
ff55df53 | 318 | #endif /* __ASSEMBLY__ */ |
1965aae3 | 319 | #endif /* _ASM_X86_MSR_H */ |