[deliverable/linux.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define X86_PMC_MAX_GENERIC				       32
#define X86_PMC_MAX_FIXED					3

#define X86_PMC_IDX_GENERIC				        0
#define X86_PMC_IDX_FIXED				       32
#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define AMD_PERFMON_EVENTSEL_GUESTONLY			(1ULL << 40)
#define AMD_PERFMON_EVENTSEL_HOSTONLY			(1ULL << 41)

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		      0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX			 0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED			 6

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:5;
		unsigned int bit_width_fixed:8;
		unsigned int reserved:19;
	} split;
	unsigned int full;
};


/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL			0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0			0x309
#define X86_PMC_IDX_FIXED_INSTRUCTIONS			(X86_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1			0x30a
#define X86_PMC_IDX_FIXED_CPU_CYCLES			(X86_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2			0x30b
#define X86_PMC_IDX_FIXED_BUS_CYCLES			(X86_PMC_IDX_FIXED + 2)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)

/* IbsFetchCtl bits/masks */
#define IBS_FETCH_RAND_EN	(1ULL<<57)
#define IBS_FETCH_VAL		(1ULL<<49)
#define IBS_FETCH_ENABLE	(1ULL<<48)
#define IBS_FETCH_CNT		0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT	0x0000FFFFULL

/* IbsOpCtl bits */
#define IBS_OP_CNT_CTL		(1ULL<<19)
#define IBS_OP_VAL		(1ULL<<18)
#define IBS_OP_ENABLE		(1ULL<<17)
#define IBS_OP_MAX_CNT		0x0000FFFFULL
#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */

#ifdef CONFIG_PERF_EVENTS
extern void perf_events_lapic_init(void);

#define PERF_EVENT_INDEX_OFFSET			0

/*
 * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
 * This flag is otherwise unused and ABI specified to be 0, so nobody should
 * care what we do with it.
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)

struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#include <asm/stacktrace.h>

/*
 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 * and the comment with PERF_EFLAGS_EXACT.
 */
#define perf_arch_fetch_caller_regs(regs, __ip)		{	\
	(regs)->ip = (__ip);					\
	(regs)->bp = caller_frame_pointer();			\
	(regs)->cs = __KERNEL_CS;				\
	regs->flags = 0;					\
	asm volatile(						\
		_ASM_MOV "%%"_ASM_SP ", %0\n"			\
		: "=m" ((regs)->sp)				\
		:: "memory"					\
	);							\
}

#else
static inline void perf_events_lapic_init(void)	{ }
#endif

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
eb2b8618 IM	7
a072738e	8	#define X86_PMC_MAX_GENERIC 32
eb2b8618 IM	9	#define X86_PMC_MAX_FIXED 3
eb2b8618 IM	10
862a1a5f IM	11	#define X86_PMC_IDX_GENERIC 0
	12	#define X86_PMC_IDX_FIXED 32
	13	#define X86_PMC_IDX_MAX 64
	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
a098f448 RR	21	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	22	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	23	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	24	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	25	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
	26	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	27	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	28	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	29	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	30	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	31
011af857 JR	32	#define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40)
	33	#define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41)
	34
a098f448 RR	35	#define AMD64_EVENTSEL_EVENT \
	36	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	37	#define INTEL_ARCH_EVENT_MASK \
	38	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	39
	40	#define X86_RAW_EVENT_MASK \
	41	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	42	ARCH_PERFMON_EVENTSEL_UMASK \| \
	43	ARCH_PERFMON_EVENTSEL_EDGE \| \
	44	ARCH_PERFMON_EVENTSEL_INV \| \
	45	ARCH_PERFMON_EVENTSEL_CMASK)
	46	#define AMD64_RAW_EVENT_MASK \
	47	(X86_RAW_EVENT_MASK \| \
	48	AMD64_EVENTSEL_EVENT)
04a705df	49
241771ef IM	50	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef IM	51	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
04a705df	52	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	53	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	54	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
	55
	56	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
003a46cf	57
eb2b8618 IM	58	/*
	59	* Intel "Architectural Performance Monitoring" CPUID
	60	* detection/enumeration details:
	61	*/
003a46cf TG	62	union cpuid10_eax {
	63	struct {
	64	unsigned int version_id:8;
948b1bb8	65	unsigned int num_counters:8;
003a46cf TG	66	unsigned int bit_width:8;
	67	unsigned int mask_length:8;
	68	} split;
	69	unsigned int full;
	70	};
	71
703e937c IM	72	union cpuid10_edx {
703e937c IM	73	struct {
e768aee8 LS	74	unsigned int num_counters_fixed:5;
	75	unsigned int bit_width_fixed:8;
	76	unsigned int reserved:19;
703e937c IM	77	} split;
	78	unsigned int full;
	79	};
	80
	81
	82	/*
cdd6c482	83	* Fixed-purpose performance events:
703e937c IM	84	*/
703e937c IM	85
862a1a5f IM	86	/*
	87	* All 3 fixed-mode PMCs are configured via this single MSR:
	88	*/
	89	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
	90
	91	/*
	92	* The counts are available in three separate MSRs:
	93	*/
	94
703e937c IM	95	/* Instr_Retired.Any: */
703e937c IM	96	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
2f18d1e8	97	#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
703e937c IM	98
	99	/* CPU_CLK_Unhalted.Core: */
	100	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
2f18d1e8	101	#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
703e937c IM	102
	103	/* CPU_CLK_Unhalted.Ref: */
	104	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
2f18d1e8	105	#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
703e937c	106
30dd568c MM	107	/*
	108	* We model BTS tracing as another fixed-mode PMC.
	109	*
cdd6c482 IM	110	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	111	* values are used by actual fixed events and higher values are used
30dd568c MM	112	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
	113	*/
	114	#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
	115
1d6040f1	116	/* IbsFetchCtl bits/masks */
b47fad3b RR	117	#define IBS_FETCH_RAND_EN (1ULL<<57)
	118	#define IBS_FETCH_VAL (1ULL<<49)
	119	#define IBS_FETCH_ENABLE (1ULL<<48)
	120	#define IBS_FETCH_CNT 0xFFFF0000ULL
	121	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1 RR	122
1d6040f1 RR	123	/* IbsOpCtl bits */
b47fad3b RR	124	#define IBS_OP_CNT_CTL (1ULL<<19)
	125	#define IBS_OP_VAL (1ULL<<18)
	126	#define IBS_OP_ENABLE (1ULL<<17)
	127	#define IBS_OP_MAX_CNT 0x0000FFFFULL
	128	#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
30dd568c	129
cdd6c482	130	#ifdef CONFIG_PERF_EVENTS
cdd6c482	131	extern void perf_events_lapic_init(void);
194002b2	132
cdd6c482	133	#define PERF_EVENT_INDEX_OFFSET 0
194002b2	134
ef21f683 PZ	135	/*
	136	* Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
	137	* This flag is otherwise unused and ABI specified to be 0, so nobody should
	138	* care what we do with it.
	139	*/
	140	#define PERF_EFLAGS_EXACT (1UL << 3)
	141
39447b38 ZY	142	struct pt_regs;
	143	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	144	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	145	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	146
b0f82b81 FW	147	#include <asm/stacktrace.h>
	148
	149	/*
	150	* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
	151	* and the comment with PERF_EFLAGS_EXACT.
	152	*/
	153	#define perf_arch_fetch_caller_regs(regs, __ip) { \
	154	(regs)->ip = (__ip); \
	155	(regs)->bp = caller_frame_pointer(); \
	156	(regs)->cs = __KERNEL_CS; \
	157	regs->flags = 0; \
9e46294d FW	158	asm volatile( \
	159	_ASM_MOV "%%"_ASM_SP ", %0\n" \
	160	: "=m" ((regs)->sp) \
	161	:: "memory" \
	162	); \
b0f82b81 FW	163	}
b0f82b81 FW	164
241771ef	165	#else
cdd6c482	166	static inline void perf_events_lapic_init(void) { }
241771ef IM	167	#endif
241771ef IM	168
cdd6c482	169	#endif /* _ASM_X86_PERF_EVENT_H */