[deliverable/linux.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define X86_PMC_MAX_GENERIC				       32
#define X86_PMC_MAX_FIXED					3

#define X86_PMC_IDX_GENERIC				        0
#define X86_PMC_IDX_FIXED				       32
#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL		(1ULL << 19)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define AMD_PERFMON_EVENTSEL_GUESTONLY			(1ULL << 40)
#define AMD_PERFMON_EVENTSEL_HOSTONLY			(1ULL << 41)

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)
#define AMD64_NUM_COUNTERS				4
#define AMD64_NUM_COUNTERS_F15H				6
#define AMD64_NUM_COUNTERS_MAX				AMD64_NUM_COUNTERS_F15H

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX		0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
#define ARCH_PERFMON_EVENTS_COUNT			7

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_ebx {
	struct {
		unsigned int no_unhalted_core_cycles:1;
		unsigned int no_instructions_retired:1;
		unsigned int no_unhalted_reference_cycles:1;
		unsigned int no_llc_reference:1;
		unsigned int no_llc_misses:1;
		unsigned int no_branch_instruction_retired:1;
		unsigned int no_branch_misses_retired:1;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:5;
		unsigned int bit_width_fixed:8;
		unsigned int reserved:19;
	} split;
	unsigned int full;
};

struct x86_pmu_capability {
	int		version;
	int		num_counters_gp;
	int		num_counters_fixed;
	int		bit_width_gp;
	int		bit_width_fixed;
	unsigned int	events_mask;
	int		events_mask_len;
};

/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
#define X86_PMC_IDX_FIXED_INSTRUCTIONS	(X86_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
#define X86_PMC_IDX_FIXED_CPU_CYCLES	(X86_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
#define X86_PMC_IDX_FIXED_REF_CYCLES	(X86_PMC_IDX_FIXED + 2)
#define X86_PMC_MSK_FIXED_REF_CYCLES	(1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)

/*
 * IBS cpuid feature detection
 */

#define IBS_CPUID_FEATURES		0x8000001b

/*
 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
 * bit 0 is used to indicate the existence of IBS.
 */
#define IBS_CAPS_AVAIL			(1U<<0)
#define IBS_CAPS_FETCHSAM		(1U<<1)
#define IBS_CAPS_OPSAM			(1U<<2)
#define IBS_CAPS_RDWROPCNT		(1U<<3)
#define IBS_CAPS_OPCNT			(1U<<4)
#define IBS_CAPS_BRNTRGT		(1U<<5)
#define IBS_CAPS_OPCNTEXT		(1U<<6)

#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
					 | IBS_CAPS_FETCHSAM	\
					 | IBS_CAPS_OPSAM)

/*
 * IBS APIC setup
 */
#define IBSCTL				0x1cc
#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)
#define IBSCTL_LVT_OFFSET_MASK		0x0F

/* IbsFetchCtl bits/masks */
#define IBS_FETCH_RAND_EN	(1ULL<<57)
#define IBS_FETCH_VAL		(1ULL<<49)
#define IBS_FETCH_ENABLE	(1ULL<<48)
#define IBS_FETCH_CNT		0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT	0x0000FFFFULL

/* IbsOpCtl bits */
/* lower 4 bits of the current count are ignored: */
#define IBS_OP_CUR_CNT		(0xFFFF0ULL<<32)
#define IBS_OP_CNT_CTL		(1ULL<<19)
#define IBS_OP_VAL		(1ULL<<18)
#define IBS_OP_ENABLE		(1ULL<<17)
#define IBS_OP_MAX_CNT		0x0000FFFFULL
#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */

extern u32 get_ibs_caps(void);

#ifdef CONFIG_PERF_EVENTS
extern void perf_events_lapic_init(void);

/*
 * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
 * This flag is otherwise unused and ABI specified to be 0, so nobody should
 * care what we do with it.
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)

struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#include <asm/stacktrace.h>

/*
 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 * and the comment with PERF_EFLAGS_EXACT.
 */
#define perf_arch_fetch_caller_regs(regs, __ip)		{	\
	(regs)->ip = (__ip);					\
	(regs)->bp = caller_frame_pointer();			\
	(regs)->cs = __KERNEL_CS;				\
	regs->flags = 0;					\
	asm volatile(						\
		_ASM_MOV "%%"_ASM_SP ", %0\n"			\
		: "=m" ((regs)->sp)				\
		:: "memory"					\
	);							\
}

struct perf_guest_switch_msr {
	unsigned msr;
	u64 host, guest;
};

extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
#else
static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
{
	*nr = 0;
	return NULL;
}

static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	memset(cap, 0, sizeof(*cap));
}

static inline void perf_events_lapic_init(void)	{ }
#endif

#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 extern void amd_pmu_enable_virt(void);
 extern void amd_pmu_disable_virt(void);
#else
 static inline void amd_pmu_enable_virt(void) { }
 static inline void amd_pmu_disable_virt(void) { }
#endif

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
eb2b8618 IM	7
a072738e	8	#define X86_PMC_MAX_GENERIC 32
eb2b8618 IM	9	#define X86_PMC_MAX_FIXED 3
eb2b8618 IM	10
862a1a5f IM	11	#define X86_PMC_IDX_GENERIC 0
	12	#define X86_PMC_IDX_FIXED 32
	13	#define X86_PMC_IDX_MAX 64
	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
a098f448 RR	21	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	22	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	23	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	24	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	25	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
a7b9d2cc	26	#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
a098f448 RR	27	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	28	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	29	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	30	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	31	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	32
011af857 JR	33	#define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40)
	34	#define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41)
	35
a098f448 RR	36	#define AMD64_EVENTSEL_EVENT \
	37	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	38	#define INTEL_ARCH_EVENT_MASK \
	39	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	40
	41	#define X86_RAW_EVENT_MASK \
	42	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	43	ARCH_PERFMON_EVENTSEL_UMASK \| \
	44	ARCH_PERFMON_EVENTSEL_EDGE \| \
	45	ARCH_PERFMON_EVENTSEL_INV \| \
	46	ARCH_PERFMON_EVENTSEL_CMASK)
	47	#define AMD64_RAW_EVENT_MASK \
	48	(X86_RAW_EVENT_MASK \| \
	49	AMD64_EVENTSEL_EVENT)
ee5789db RR	50	#define AMD64_NUM_COUNTERS 4
	51	#define AMD64_NUM_COUNTERS_F15H 6
	52	#define AMD64_NUM_COUNTERS_MAX AMD64_NUM_COUNTERS_F15H
04a705df	53
ee5789db	54	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef	55	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
ee5789db	56	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	57	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	58	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
241771ef IM	59
ee5789db	60	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
ffb871bc	61	#define ARCH_PERFMON_EVENTS_COUNT 7
003a46cf	62
eb2b8618 IM	63	/*
	64	* Intel "Architectural Performance Monitoring" CPUID
	65	* detection/enumeration details:
	66	*/
003a46cf TG	67	union cpuid10_eax {
	68	struct {
	69	unsigned int version_id:8;
948b1bb8	70	unsigned int num_counters:8;
003a46cf TG	71	unsigned int bit_width:8;
	72	unsigned int mask_length:8;
	73	} split;
	74	unsigned int full;
	75	};
	76
ffb871bc GN	77	union cpuid10_ebx {
	78	struct {
	79	unsigned int no_unhalted_core_cycles:1;
	80	unsigned int no_instructions_retired:1;
	81	unsigned int no_unhalted_reference_cycles:1;
	82	unsigned int no_llc_reference:1;
	83	unsigned int no_llc_misses:1;
	84	unsigned int no_branch_instruction_retired:1;
	85	unsigned int no_branch_misses_retired:1;
	86	} split;
	87	unsigned int full;
	88	};
	89
703e937c IM	90	union cpuid10_edx {
703e937c IM	91	struct {
e768aee8 LS	92	unsigned int num_counters_fixed:5;
	93	unsigned int bit_width_fixed:8;
	94	unsigned int reserved:19;
703e937c IM	95	} split;
	96	unsigned int full;
	97	};
	98
b3d9468a GN	99	struct x86_pmu_capability {
	100	int version;
	101	int num_counters_gp;
	102	int num_counters_fixed;
	103	int bit_width_gp;
	104	int bit_width_fixed;
	105	unsigned int events_mask;
	106	int events_mask_len;
	107	};
703e937c IM	108
703e937c IM	109	/*
cdd6c482	110	* Fixed-purpose performance events:
703e937c IM	111	*/
703e937c IM	112
862a1a5f IM	113	/*
	114	* All 3 fixed-mode PMCs are configured via this single MSR:
	115	*/
cd09c0c4	116	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
862a1a5f IM	117
	118	/*
	119	* The counts are available in three separate MSRs:
	120	*/
	121
703e937c	122	/* Instr_Retired.Any: */
cd09c0c4 SE	123	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
cd09c0c4 SE	124	#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
703e937c IM	125
703e937c IM	126	/* CPU_CLK_Unhalted.Core: */
cd09c0c4 SE	127	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
cd09c0c4 SE	128	#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
703e937c IM	129
703e937c IM	130	/* CPU_CLK_Unhalted.Ref: */
cd09c0c4 SE	131	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
	132	#define X86_PMC_IDX_FIXED_REF_CYCLES (X86_PMC_IDX_FIXED + 2)
	133	#define X86_PMC_MSK_FIXED_REF_CYCLES (1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)
703e937c	134
30dd568c MM	135	/*
	136	* We model BTS tracing as another fixed-mode PMC.
	137	*
cdd6c482 IM	138	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	139	* values are used by actual fixed events and higher values are used
30dd568c MM	140	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
	141	*/
	142	#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
	143
ee5789db RR	144	/*
	145	* IBS cpuid feature detection
	146	*/
	147
	148	#define IBS_CPUID_FEATURES 0x8000001b
	149
	150	/*
	151	* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
	152	* bit 0 is used to indicate the existence of IBS.
	153	*/
	154	#define IBS_CAPS_AVAIL (1U<<0)
	155	#define IBS_CAPS_FETCHSAM (1U<<1)
	156	#define IBS_CAPS_OPSAM (1U<<2)
	157	#define IBS_CAPS_RDWROPCNT (1U<<3)
	158	#define IBS_CAPS_OPCNT (1U<<4)
	159	#define IBS_CAPS_BRNTRGT (1U<<5)
	160	#define IBS_CAPS_OPCNTEXT (1U<<6)
	161
	162	#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
	163	\| IBS_CAPS_FETCHSAM \
	164	\| IBS_CAPS_OPSAM)
	165
	166	/*
	167	* IBS APIC setup
	168	*/
	169	#define IBSCTL 0x1cc
	170	#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
	171	#define IBSCTL_LVT_OFFSET_MASK 0x0F
	172
1d6040f1	173	/* IbsFetchCtl bits/masks */
b47fad3b RR	174	#define IBS_FETCH_RAND_EN (1ULL<<57)
	175	#define IBS_FETCH_VAL (1ULL<<49)
	176	#define IBS_FETCH_ENABLE (1ULL<<48)
	177	#define IBS_FETCH_CNT 0xFFFF0000ULL
	178	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1 RR	179
1d6040f1 RR	180	/* IbsOpCtl bits */
db98c5fa RR	181	/* lower 4 bits of the current count are ignored: */
db98c5fa RR	182	#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
b47fad3b RR	183	#define IBS_OP_CNT_CTL (1ULL<<19)
	184	#define IBS_OP_VAL (1ULL<<18)
	185	#define IBS_OP_ENABLE (1ULL<<17)
	186	#define IBS_OP_MAX_CNT 0x0000FFFFULL
	187	#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
30dd568c	188
b7169166 RR	189	extern u32 get_ibs_caps(void);
b7169166 RR	190
cdd6c482	191	#ifdef CONFIG_PERF_EVENTS
cdd6c482	192	extern void perf_events_lapic_init(void);
194002b2	193
ef21f683 PZ	194	/*
	195	* Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
	196	* This flag is otherwise unused and ABI specified to be 0, so nobody should
	197	* care what we do with it.
	198	*/
	199	#define PERF_EFLAGS_EXACT (1UL << 3)
	200
39447b38 ZY	201	struct pt_regs;
	202	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	203	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	204	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	205
b0f82b81 FW	206	#include <asm/stacktrace.h>
	207
	208	/*
	209	* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
	210	* and the comment with PERF_EFLAGS_EXACT.
	211	*/
	212	#define perf_arch_fetch_caller_regs(regs, __ip) { \
	213	(regs)->ip = (__ip); \
	214	(regs)->bp = caller_frame_pointer(); \
	215	(regs)->cs = __KERNEL_CS; \
	216	regs->flags = 0; \
9e46294d FW	217	asm volatile( \
	218	_ASM_MOV "%%"_ASM_SP ", %0\n" \
	219	: "=m" ((regs)->sp) \
	220	:: "memory" \
	221	); \
b0f82b81 FW	222	}
b0f82b81 FW	223
144d31e6 GN	224	struct perf_guest_switch_msr {
	225	unsigned msr;
	226	u64 host, guest;
	227	};
	228
	229	extern struct perf_guest_switch_msr perf_guest_get_msrs(int nr);
b3d9468a	230	extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
241771ef	231	#else
144d31e6 GN	232	static inline perf_guest_switch_msr perf_guest_get_msrs(int nr)
	233	{
	234	*nr = 0;
	235	return NULL;
	236	}
	237
b3d9468a GN	238	static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
	239	{
	240	memset(cap, 0, sizeof(*cap));
	241	}
	242
cdd6c482	243	static inline void perf_events_lapic_init(void) { }
241771ef IM	244	#endif
241771ef IM	245
1018faa6 JR	246	#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
	247	extern void amd_pmu_enable_virt(void);
	248	extern void amd_pmu_disable_virt(void);
	249	#else
	250	static inline void amd_pmu_enable_virt(void) { }
	251	static inline void amd_pmu_disable_virt(void) { }
	252	#endif
	253
cdd6c482	254	#endif /* _ASM_X86_PERF_EVENT_H */