Commit | Line | Data |
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cdd6c482 IM |
1 | #ifndef _ASM_X86_PERF_EVENT_H |
2 | #define _ASM_X86_PERF_EVENT_H | |
003a46cf | 3 | |
eb2b8618 | 4 | /* |
cdd6c482 | 5 | * Performance event hw details: |
eb2b8618 IM |
6 | */ |
7 | ||
a072738e | 8 | #define X86_PMC_MAX_GENERIC 32 |
eb2b8618 IM |
9 | #define X86_PMC_MAX_FIXED 3 |
10 | ||
862a1a5f IM |
11 | #define X86_PMC_IDX_GENERIC 0 |
12 | #define X86_PMC_IDX_FIXED 32 | |
13 | #define X86_PMC_IDX_MAX 64 | |
14 | ||
241771ef IM |
15 | #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 |
16 | #define MSR_ARCH_PERFMON_PERFCTR1 0xc2 | |
003a46cf | 17 | |
241771ef IM |
18 | #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 |
19 | #define MSR_ARCH_PERFMON_EVENTSEL1 0x187 | |
003a46cf | 20 | |
a098f448 RR |
21 | #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL |
22 | #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL | |
23 | #define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16) | |
24 | #define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) | |
25 | #define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18) | |
26 | #define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20) | |
27 | #define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21) | |
28 | #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) | |
29 | #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) | |
30 | #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL | |
31 | ||
011af857 JR |
32 | #define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40) |
33 | #define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41) | |
34 | ||
a098f448 RR |
35 | #define AMD64_EVENTSEL_EVENT \ |
36 | (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32)) | |
37 | #define INTEL_ARCH_EVENT_MASK \ | |
38 | (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT) | |
39 | ||
40 | #define X86_RAW_EVENT_MASK \ | |
41 | (ARCH_PERFMON_EVENTSEL_EVENT | \ | |
42 | ARCH_PERFMON_EVENTSEL_UMASK | \ | |
43 | ARCH_PERFMON_EVENTSEL_EDGE | \ | |
44 | ARCH_PERFMON_EVENTSEL_INV | \ | |
45 | ARCH_PERFMON_EVENTSEL_CMASK) | |
46 | #define AMD64_RAW_EVENT_MASK \ | |
47 | (X86_RAW_EVENT_MASK | \ | |
48 | AMD64_EVENTSEL_EVENT) | |
ee5789db RR |
49 | #define AMD64_NUM_COUNTERS 4 |
50 | #define AMD64_NUM_COUNTERS_F15H 6 | |
51 | #define AMD64_NUM_COUNTERS_MAX AMD64_NUM_COUNTERS_F15H | |
04a705df | 52 | |
ee5789db | 53 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
241771ef | 54 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) |
ee5789db | 55 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 |
003a46cf | 56 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ |
241771ef IM |
57 | (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) |
58 | ||
ee5789db | 59 | #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 |
003a46cf | 60 | |
eb2b8618 IM |
61 | /* |
62 | * Intel "Architectural Performance Monitoring" CPUID | |
63 | * detection/enumeration details: | |
64 | */ | |
003a46cf TG |
65 | union cpuid10_eax { |
66 | struct { | |
67 | unsigned int version_id:8; | |
948b1bb8 | 68 | unsigned int num_counters:8; |
003a46cf TG |
69 | unsigned int bit_width:8; |
70 | unsigned int mask_length:8; | |
71 | } split; | |
72 | unsigned int full; | |
73 | }; | |
74 | ||
703e937c IM |
75 | union cpuid10_edx { |
76 | struct { | |
e768aee8 LS |
77 | unsigned int num_counters_fixed:5; |
78 | unsigned int bit_width_fixed:8; | |
79 | unsigned int reserved:19; | |
703e937c IM |
80 | } split; |
81 | unsigned int full; | |
82 | }; | |
83 | ||
84 | ||
85 | /* | |
cdd6c482 | 86 | * Fixed-purpose performance events: |
703e937c IM |
87 | */ |
88 | ||
862a1a5f IM |
89 | /* |
90 | * All 3 fixed-mode PMCs are configured via this single MSR: | |
91 | */ | |
92 | #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d | |
93 | ||
94 | /* | |
95 | * The counts are available in three separate MSRs: | |
96 | */ | |
97 | ||
703e937c IM |
98 | /* Instr_Retired.Any: */ |
99 | #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 | |
2f18d1e8 | 100 | #define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0) |
703e937c IM |
101 | |
102 | /* CPU_CLK_Unhalted.Core: */ | |
103 | #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a | |
2f18d1e8 | 104 | #define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1) |
703e937c IM |
105 | |
106 | /* CPU_CLK_Unhalted.Ref: */ | |
107 | #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b | |
2f18d1e8 | 108 | #define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2) |
703e937c | 109 | |
30dd568c MM |
110 | /* |
111 | * We model BTS tracing as another fixed-mode PMC. | |
112 | * | |
cdd6c482 IM |
113 | * We choose a value in the middle of the fixed event range, since lower |
114 | * values are used by actual fixed events and higher values are used | |
30dd568c MM |
115 | * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. |
116 | */ | |
117 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) | |
118 | ||
ee5789db RR |
119 | /* |
120 | * IBS cpuid feature detection | |
121 | */ | |
122 | ||
123 | #define IBS_CPUID_FEATURES 0x8000001b | |
124 | ||
125 | /* | |
126 | * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but | |
127 | * bit 0 is used to indicate the existence of IBS. | |
128 | */ | |
129 | #define IBS_CAPS_AVAIL (1U<<0) | |
130 | #define IBS_CAPS_FETCHSAM (1U<<1) | |
131 | #define IBS_CAPS_OPSAM (1U<<2) | |
132 | #define IBS_CAPS_RDWROPCNT (1U<<3) | |
133 | #define IBS_CAPS_OPCNT (1U<<4) | |
134 | #define IBS_CAPS_BRNTRGT (1U<<5) | |
135 | #define IBS_CAPS_OPCNTEXT (1U<<6) | |
136 | ||
137 | #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ | |
138 | | IBS_CAPS_FETCHSAM \ | |
139 | | IBS_CAPS_OPSAM) | |
140 | ||
141 | /* | |
142 | * IBS APIC setup | |
143 | */ | |
144 | #define IBSCTL 0x1cc | |
145 | #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) | |
146 | #define IBSCTL_LVT_OFFSET_MASK 0x0F | |
147 | ||
1d6040f1 | 148 | /* IbsFetchCtl bits/masks */ |
b47fad3b RR |
149 | #define IBS_FETCH_RAND_EN (1ULL<<57) |
150 | #define IBS_FETCH_VAL (1ULL<<49) | |
151 | #define IBS_FETCH_ENABLE (1ULL<<48) | |
152 | #define IBS_FETCH_CNT 0xFFFF0000ULL | |
153 | #define IBS_FETCH_MAX_CNT 0x0000FFFFULL | |
1d6040f1 RR |
154 | |
155 | /* IbsOpCtl bits */ | |
b47fad3b RR |
156 | #define IBS_OP_CNT_CTL (1ULL<<19) |
157 | #define IBS_OP_VAL (1ULL<<18) | |
158 | #define IBS_OP_ENABLE (1ULL<<17) | |
159 | #define IBS_OP_MAX_CNT 0x0000FFFFULL | |
160 | #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ | |
30dd568c | 161 | |
b7169166 RR |
162 | extern u32 get_ibs_caps(void); |
163 | ||
cdd6c482 | 164 | #ifdef CONFIG_PERF_EVENTS |
cdd6c482 | 165 | extern void perf_events_lapic_init(void); |
194002b2 | 166 | |
cdd6c482 | 167 | #define PERF_EVENT_INDEX_OFFSET 0 |
194002b2 | 168 | |
ef21f683 PZ |
169 | /* |
170 | * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups. | |
171 | * This flag is otherwise unused and ABI specified to be 0, so nobody should | |
172 | * care what we do with it. | |
173 | */ | |
174 | #define PERF_EFLAGS_EXACT (1UL << 3) | |
175 | ||
39447b38 ZY |
176 | struct pt_regs; |
177 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); | |
178 | extern unsigned long perf_misc_flags(struct pt_regs *regs); | |
179 | #define perf_misc_flags(regs) perf_misc_flags(regs) | |
ef21f683 | 180 | |
b0f82b81 FW |
181 | #include <asm/stacktrace.h> |
182 | ||
183 | /* | |
184 | * We abuse bit 3 from flags to pass exact information, see perf_misc_flags | |
185 | * and the comment with PERF_EFLAGS_EXACT. | |
186 | */ | |
187 | #define perf_arch_fetch_caller_regs(regs, __ip) { \ | |
188 | (regs)->ip = (__ip); \ | |
189 | (regs)->bp = caller_frame_pointer(); \ | |
190 | (regs)->cs = __KERNEL_CS; \ | |
191 | regs->flags = 0; \ | |
9e46294d FW |
192 | asm volatile( \ |
193 | _ASM_MOV "%%"_ASM_SP ", %0\n" \ | |
194 | : "=m" ((regs)->sp) \ | |
195 | :: "memory" \ | |
196 | ); \ | |
b0f82b81 FW |
197 | } |
198 | ||
144d31e6 GN |
199 | struct perf_guest_switch_msr { |
200 | unsigned msr; | |
201 | u64 host, guest; | |
202 | }; | |
203 | ||
204 | extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); | |
241771ef | 205 | #else |
144d31e6 GN |
206 | static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr) |
207 | { | |
208 | *nr = 0; | |
209 | return NULL; | |
210 | } | |
211 | ||
cdd6c482 | 212 | static inline void perf_events_lapic_init(void) { } |
241771ef IM |
213 | #endif |
214 | ||
cdd6c482 | 215 | #endif /* _ASM_X86_PERF_EVENT_H */ |