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Merge commit 'v2.6.35-rc4' into perf/core
[deliverable/linux.git] / arch / x86 / include / asm / perf_event_p4.h
CommitLineData
a072738e
CG		 1/*
2 * Netburst Perfomance Events (P4, old Xeon)
3 */
4
5#ifndef PERF_EVENT_P4_H
6#define PERF_EVENT_P4_H
7
8#include <linux/cpu.h>
9#include <linux/bitops.h>
10
11/*
12 * NetBurst has perfomance MSRs shared between
13 * threads if HT is turned on, ie for both logical
14 * processors (mem: in turn in Atom with HT support
15 * perf-MSRs are not shared and every thread has its
16 * own perf-MSRs set)
17 */
d814f301
CG		 18#define ARCH_P4_TOTAL_ESCR (46)
19#define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */
20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
21#define ARCH_P4_MAX_CCCR (18)
22#define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2)
23
24#define P4_ESCR_EVENT_MASK 0x7e000000U
25#define P4_ESCR_EVENT_SHIFT 25
26#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U
27#define P4_ESCR_EVENTMASK_SHIFT 9
28#define P4_ESCR_TAG_MASK 0x000001e0U
29#define P4_ESCR_TAG_SHIFT 5
30#define P4_ESCR_TAG_ENABLE 0x00000010U
31#define P4_ESCR_T0_OS 0x00000008U
32#define P4_ESCR_T0_USR 0x00000004U
33#define P4_ESCR_T1_OS 0x00000002U
34#define P4_ESCR_T1_USR 0x00000001U
35
36#define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)
37#define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)
38#define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)
a072738e
CG		 39
40/* Non HT mask */
d814f301
CG		 41#define P4_ESCR_MASK \
42 (P4_ESCR_EVENT_MASK | \
43 P4_ESCR_EVENTMASK_MASK | \
44 P4_ESCR_TAG_MASK | \
45 P4_ESCR_TAG_ENABLE | \
46 P4_ESCR_T0_OS | \
47 P4_ESCR_T0_USR)
a072738e
CG		 48
49/* HT mask */
d814f301
CG		 50#define P4_ESCR_MASK_HT \
51 (P4_ESCR_MASK | P4_ESCR_T1_OS | P4_ESCR_T1_USR)
a072738e
CG		 52
53#define P4_CCCR_OVF 0x80000000U
54#define P4_CCCR_CASCADE 0x40000000U
55#define P4_CCCR_OVF_PMI_T0 0x04000000U
56#define P4_CCCR_OVF_PMI_T1 0x08000000U
57#define P4_CCCR_FORCE_OVF 0x02000000U
58#define P4_CCCR_EDGE 0x01000000U
59#define P4_CCCR_THRESHOLD_MASK 0x00f00000U
60#define P4_CCCR_THRESHOLD_SHIFT 20
a072738e
CG		 61#define P4_CCCR_COMPLEMENT 0x00080000U
62#define P4_CCCR_COMPARE 0x00040000U
63#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U
64#define P4_CCCR_ESCR_SELECT_SHIFT 13
65#define P4_CCCR_ENABLE 0x00001000U
66#define P4_CCCR_THREAD_SINGLE 0x00010000U
67#define P4_CCCR_THREAD_BOTH 0x00020000U
68#define P4_CCCR_THREAD_ANY 0x00030000U
f34edbc1 69#define P4_CCCR_RESERVED 0x00000fffU
a072738e 70
d814f301
CG		 71#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
72#define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
73
74/* Custom bits in reerved CCCR area */
75#define P4_CCCR_CACHE_OPS_MASK 0x0000003fU
76
77
a072738e
CG		 78/* Non HT mask */
79#define P4_CCCR_MASK \
80 (P4_CCCR_OVF | \
81 P4_CCCR_CASCADE | \
82 P4_CCCR_OVF_PMI_T0 | \
83 P4_CCCR_FORCE_OVF | \
84 P4_CCCR_EDGE | \
85 P4_CCCR_THRESHOLD_MASK | \
86 P4_CCCR_COMPLEMENT | \
87 P4_CCCR_COMPARE | \
88 P4_CCCR_ESCR_SELECT_MASK | \
89 P4_CCCR_ENABLE)
90
91/* HT mask */
ce7f1545
CG		 92#define P4_CCCR_MASK_HT \
93 (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY)
a072738e 94
d814f301
CG		 95#define P4_GEN_ESCR_EMASK(class, name, bit) \
96 class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
97#define P4_ESCR_EMASK_BIT(class, name) class##__##name
a072738e
CG		 98
99/*
100 * config field is 64bit width and consists of
101 * HT << 63 | ESCR << 32 | CCCR
102 * where HT is HyperThreading bit (since ESCR
103 * has it reserved we may use it for own purpose)
104 *
105 * note that this is NOT the addresses of respective
106 * ESCR and CCCR but rather an only packed value should
107 * be unpacked and written to a proper addresses
108 *
109 * the base idea is to pack as much info as
110 * possible
111 */
112#define p4_config_pack_escr(v) (((u64)(v)) << 32)
113#define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL)
114#define p4_config_unpack_escr(v) (((u64)(v)) >> 32)
d814f301 115#define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL)
a072738e
CG		 116
117#define p4_config_unpack_emask(v) \
118 ({ \
119 u32 t = p4_config_unpack_escr((v)); \
d814f301
CG		 120 t = t & P4_ESCR_EVENTMASK_MASK; \
121 t = t >> P4_ESCR_EVENTMASK_SHIFT; \
122 t; \
123 })
124
125#define p4_config_unpack_event(v) \
126 ({ \
127 u32 t = p4_config_unpack_escr((v)); \
128 t = t & P4_ESCR_EVENT_MASK; \
129 t = t >> P4_ESCR_EVENT_SHIFT; \
a072738e
CG		 130 t; \
131 })
132
d814f301 133#define p4_config_unpack_cache_event(v) (((u64)(v)) & P4_CCCR_CACHE_OPS_MASK)
f34edbc1 134
a072738e
CG		 135#define P4_CONFIG_HT_SHIFT 63
136#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)
137
a072738e
CG		 138static inline bool p4_is_event_cascaded(u64 config)
139{
140 u32 cccr = p4_config_unpack_cccr(config);
141 return !!(cccr & P4_CCCR_CASCADE);
142}
143
144static inline int p4_ht_config_thread(u64 config)
145{
146 return !!(config & P4_CONFIG_HT);
147}
148
149static inline u64 p4_set_ht_bit(u64 config)
150{
151 return config | P4_CONFIG_HT;
152}
153
154static inline u64 p4_clear_ht_bit(u64 config)
155{
156 return config & ~P4_CONFIG_HT;
157}
158
159static inline int p4_ht_active(void)
160{
161#ifdef CONFIG_SMP
162 return smp_num_siblings > 1;
163#endif
164 return 0;
165}
166
167static inline int p4_ht_thread(int cpu)
168{
169#ifdef CONFIG_SMP
170 if (smp_num_siblings == 2)
171 return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map));
172#endif
173 return 0;
174}
175
176static inline int p4_should_swap_ts(u64 config, int cpu)
177{
178 return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
179}
180
181static inline u32 p4_default_cccr_conf(int cpu)
182{
183 /*
184 * Note that P4_CCCR_THREAD_ANY is "required" on
185 * non-HT machines (on HT machines we count TS events
186 * regardless the state of second logical processor
187 */
188 u32 cccr = P4_CCCR_THREAD_ANY;
189
190 if (!p4_ht_thread(cpu))
191 cccr |= P4_CCCR_OVF_PMI_T0;
192 else
193 cccr |= P4_CCCR_OVF_PMI_T1;
194
195 return cccr;
196}
197
198static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
199{
200 u32 escr = 0;
201
202 if (!p4_ht_thread(cpu)) {
203 if (!exclude_os)
d814f301 204 escr |= P4_ESCR_T0_OS;
a072738e 205 if (!exclude_usr)
d814f301 206 escr |= P4_ESCR_T0_USR;
a072738e
CG		 207 } else {
208 if (!exclude_os)
d814f301 209 escr |= P4_ESCR_T1_OS;
a072738e 210 if (!exclude_usr)
d814f301 211 escr |= P4_ESCR_T1_USR;
a072738e
CG		 212 }
213
214 return escr;
215}
216
d814f301
CG		 217enum P4_EVENTS {
218 P4_EVENT_TC_DELIVER_MODE,
219 P4_EVENT_BPU_FETCH_REQUEST,
220 P4_EVENT_ITLB_REFERENCE,
221 P4_EVENT_MEMORY_CANCEL,
222 P4_EVENT_MEMORY_COMPLETE,
223 P4_EVENT_LOAD_PORT_REPLAY,
224 P4_EVENT_STORE_PORT_REPLAY,
225 P4_EVENT_MOB_LOAD_REPLAY,
226 P4_EVENT_PAGE_WALK_TYPE,
227 P4_EVENT_BSQ_CACHE_REFERENCE,
228 P4_EVENT_IOQ_ALLOCATION,
229 P4_EVENT_IOQ_ACTIVE_ENTRIES,
230 P4_EVENT_FSB_DATA_ACTIVITY,
231 P4_EVENT_BSQ_ALLOCATION,
232 P4_EVENT_BSQ_ACTIVE_ENTRIES,
233 P4_EVENT_SSE_INPUT_ASSIST,
234 P4_EVENT_PACKED_SP_UOP,
235 P4_EVENT_PACKED_DP_UOP,
236 P4_EVENT_SCALAR_SP_UOP,
237 P4_EVENT_SCALAR_DP_UOP,
238 P4_EVENT_64BIT_MMX_UOP,
239 P4_EVENT_128BIT_MMX_UOP,
240 P4_EVENT_X87_FP_UOP,
241 P4_EVENT_TC_MISC,
242 P4_EVENT_GLOBAL_POWER_EVENTS,
243 P4_EVENT_TC_MS_XFER,
244 P4_EVENT_UOP_QUEUE_WRITES,
245 P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
246 P4_EVENT_RETIRED_BRANCH_TYPE,
247 P4_EVENT_RESOURCE_STALL,
248 P4_EVENT_WC_BUFFER,
249 P4_EVENT_B2B_CYCLES,
250 P4_EVENT_BNR,
251 P4_EVENT_SNOOP,
252 P4_EVENT_RESPONSE,
253 P4_EVENT_FRONT_END_EVENT,
254 P4_EVENT_EXECUTION_EVENT,
255 P4_EVENT_REPLAY_EVENT,
256 P4_EVENT_INSTR_RETIRED,
257 P4_EVENT_UOPS_RETIRED,
258 P4_EVENT_UOP_TYPE,
259 P4_EVENT_BRANCH_RETIRED,
260 P4_EVENT_MISPRED_BRANCH_RETIRED,
261 P4_EVENT_X87_ASSIST,
262 P4_EVENT_MACHINE_CLEAR,
263 P4_EVENT_INSTR_COMPLETED,
264};
265
266#define P4_OPCODE(event) event##_OPCODE
267#define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0)
268#define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8)
269#define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel)
270
a072738e
CG		 271/*
272 * Comments below the event represent ESCR restriction
273 * for this event and counter index per ESCR
274 *
275 * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
276 * processor builds (family 0FH, models 01H-02H). These MSRs
277 * are not available on later versions, so that we don't use
278 * them completely
279 *
280 * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
281 * working so that we should not use this CCCR and respective
282 * counter as result
283 */
d814f301
CG		 284enum P4_EVENT_OPCODES {
285 P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),
a072738e
CG		 286 /*
287 * MSR_P4_TC_ESCR0: 4, 5
288 * MSR_P4_TC_ESCR1: 6, 7
289 */
290
d814f301 291 P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00),
a072738e
CG		 292 /*
293 * MSR_P4_BPU_ESCR0: 0, 1
294 * MSR_P4_BPU_ESCR1: 2, 3
295 */
296
d814f301 297 P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03),
a072738e
CG		 298 /*
299 * MSR_P4_ITLB_ESCR0: 0, 1
300 * MSR_P4_ITLB_ESCR1: 2, 3
301 */
302
d814f301 303 P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05),
a072738e
CG		 304 /*
305 * MSR_P4_DAC_ESCR0: 8, 9
306 * MSR_P4_DAC_ESCR1: 10, 11
307 */
308
d814f301 309 P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02),
a072738e
CG		 310 /*
311 * MSR_P4_SAAT_ESCR0: 8, 9
312 * MSR_P4_SAAT_ESCR1: 10, 11
313 */
314
d814f301 315 P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02),
a072738e
CG		 316 /*
317 * MSR_P4_SAAT_ESCR0: 8, 9
318 * MSR_P4_SAAT_ESCR1: 10, 11
319 */
320
d814f301 321 P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02),
a072738e
CG		 322 /*
323 * MSR_P4_SAAT_ESCR0: 8, 9
324 * MSR_P4_SAAT_ESCR1: 10, 11
325 */
326
d814f301 327 P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02),
a072738e
CG		 328 /*
329 * MSR_P4_MOB_ESCR0: 0, 1
330 * MSR_P4_MOB_ESCR1: 2, 3
331 */
332
d814f301 333 P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04),
a072738e
CG		 334 /*
335 * MSR_P4_PMH_ESCR0: 0, 1
336 * MSR_P4_PMH_ESCR1: 2, 3
337 */
338
d814f301 339 P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07),
a072738e
CG		 340 /*
341 * MSR_P4_BSU_ESCR0: 0, 1
342 * MSR_P4_BSU_ESCR1: 2, 3
343 */
344
d814f301 345 P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06),
a072738e
CG		 346 /*
347 * MSR_P4_FSB_ESCR0: 0, 1
348 * MSR_P4_FSB_ESCR1: 2, 3
349 */
350
d814f301 351 P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06),
a072738e
CG		 352 /*
353 * MSR_P4_FSB_ESCR1: 2, 3
354 */
355
d814f301 356 P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06),
a072738e
CG		 357 /*
358 * MSR_P4_FSB_ESCR0: 0, 1
359 * MSR_P4_FSB_ESCR1: 2, 3
360 */
361
d814f301 362 P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07),
a072738e
CG		 363 /*
364 * MSR_P4_BSU_ESCR0: 0, 1
365 */
366
d814f301 367 P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07),
a072738e 368 /*
8ea7f544 369 * NOTE: no ESCR name in docs, it's guessed
a072738e
CG		 370 * MSR_P4_BSU_ESCR1: 2, 3
371 */
372
d814f301 373 P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01),
a072738e 374 /*
e4495262
CG		 375 * MSR_P4_FIRM_ESCR0: 8, 9
376 * MSR_P4_FIRM_ESCR1: 10, 11
a072738e
CG		 377 */
378
d814f301 379 P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01),
a072738e
CG		 380 /*
381 * MSR_P4_FIRM_ESCR0: 8, 9
382 * MSR_P4_FIRM_ESCR1: 10, 11
383 */
384
d814f301 385 P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01),
a072738e
CG		 386 /*
387 * MSR_P4_FIRM_ESCR0: 8, 9
388 * MSR_P4_FIRM_ESCR1: 10, 11
389 */
390
d814f301 391 P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01),
a072738e
CG		 392 /*
393 * MSR_P4_FIRM_ESCR0: 8, 9
394 * MSR_P4_FIRM_ESCR1: 10, 11
395 */
396
d814f301 397 P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01),
a072738e
CG		 398 /*
399 * MSR_P4_FIRM_ESCR0: 8, 9
400 * MSR_P4_FIRM_ESCR1: 10, 11
401 */
402
d814f301 403 P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01),
a072738e
CG		 404 /*
405 * MSR_P4_FIRM_ESCR0: 8, 9
406 * MSR_P4_FIRM_ESCR1: 10, 11
407 */
408
d814f301 409 P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01),
a072738e
CG		 410 /*
411 * MSR_P4_FIRM_ESCR0: 8, 9
412 * MSR_P4_FIRM_ESCR1: 10, 11
413 */
414
d814f301 415 P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01),
a072738e
CG		 416 /*
417 * MSR_P4_FIRM_ESCR0: 8, 9
418 * MSR_P4_FIRM_ESCR1: 10, 11
419 */
420
d814f301 421 P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01),
a072738e
CG		 422 /*
423 * MSR_P4_TC_ESCR0: 4, 5
424 * MSR_P4_TC_ESCR1: 6, 7
425 */
426
d814f301 427 P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06),
a072738e
CG		 428 /*
429 * MSR_P4_FSB_ESCR0: 0, 1
430 * MSR_P4_FSB_ESCR1: 2, 3
431 */
432
d814f301 433 P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00),
a072738e
CG		 434 /*
435 * MSR_P4_MS_ESCR0: 4, 5
436 * MSR_P4_MS_ESCR1: 6, 7
437 */
438
d814f301 439 P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00),
a072738e
CG		 440 /*
441 * MSR_P4_MS_ESCR0: 4, 5
442 * MSR_P4_MS_ESCR1: 6, 7
443 */
444
d814f301 445 P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02),
a072738e
CG		 446 /*
447 * MSR_P4_TBPU_ESCR0: 4, 5
9c8c6bad 448 * MSR_P4_TBPU_ESCR1: 6, 7
a072738e
CG		 449 */
450
d814f301 451 P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02),
a072738e
CG		 452 /*
453 * MSR_P4_TBPU_ESCR0: 4, 5
9c8c6bad 454 * MSR_P4_TBPU_ESCR1: 6, 7
a072738e
CG		 455 */
456
d814f301 457 P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01),
a072738e
CG		 458 /*
459 * MSR_P4_ALF_ESCR0: 12, 13, 16
460 * MSR_P4_ALF_ESCR1: 14, 15, 17
461 */
462
d814f301 463 P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05),
a072738e
CG		 464 /*
465 * MSR_P4_DAC_ESCR0: 8, 9
466 * MSR_P4_DAC_ESCR1: 10, 11
467 */
468
d814f301 469 P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03),
a072738e
CG		 470 /*
471 * MSR_P4_FSB_ESCR0: 0, 1
472 * MSR_P4_FSB_ESCR1: 2, 3
473 */
474
d814f301 475 P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03),
a072738e
CG		 476 /*
477 * MSR_P4_FSB_ESCR0: 0, 1
478 * MSR_P4_FSB_ESCR1: 2, 3
479 */
480
d814f301 481 P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03),
a072738e
CG		 482 /*
483 * MSR_P4_FSB_ESCR0: 0, 1
484 * MSR_P4_FSB_ESCR1: 2, 3
485 */
486
d814f301 487 P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03),
a072738e
CG		 488 /*
489 * MSR_P4_FSB_ESCR0: 0, 1
490 * MSR_P4_FSB_ESCR1: 2, 3
491 */
492
d814f301 493 P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05),
a072738e
CG		 494 /*
495 * MSR_P4_CRU_ESCR2: 12, 13, 16
496 * MSR_P4_CRU_ESCR3: 14, 15, 17
497 */
498
d814f301 499 P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05),
a072738e
CG		 500 /*
501 * MSR_P4_CRU_ESCR2: 12, 13, 16
502 * MSR_P4_CRU_ESCR3: 14, 15, 17
503 */
504
d814f301 505 P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05),
a072738e
CG		 506 /*
507 * MSR_P4_CRU_ESCR2: 12, 13, 16
508 * MSR_P4_CRU_ESCR3: 14, 15, 17
509 */
510
d814f301 511 P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04),
a072738e 512 /*
e4495262
CG		 513 * MSR_P4_CRU_ESCR0: 12, 13, 16
514 * MSR_P4_CRU_ESCR1: 14, 15, 17
a072738e
CG		 515 */
516
d814f301 517 P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04),
a072738e 518 /*
8ea7f544
LM		 519 * MSR_P4_CRU_ESCR0: 12, 13, 16
520 * MSR_P4_CRU_ESCR1: 14, 15, 17
a072738e
CG		 521 */
522
d814f301 523 P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02),
a072738e
CG		 524 /*
525 * MSR_P4_RAT_ESCR0: 12, 13, 16
526 * MSR_P4_RAT_ESCR1: 14, 15, 17
527 */
528
d814f301 529 P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05),
a072738e
CG		 530 /*
531 * MSR_P4_CRU_ESCR2: 12, 13, 16
532 * MSR_P4_CRU_ESCR3: 14, 15, 17
533 */
534
d814f301 535 P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04),
a072738e
CG		 536 /*
537 * MSR_P4_CRU_ESCR0: 12, 13, 16
538 * MSR_P4_CRU_ESCR1: 14, 15, 17
539 */
540
d814f301 541 P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05),
a072738e
CG		 542 /*
543 * MSR_P4_CRU_ESCR2: 12, 13, 16
544 * MSR_P4_CRU_ESCR3: 14, 15, 17
545 */
546
d814f301 547 P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05),
a072738e
CG		 548 /*
549 * MSR_P4_CRU_ESCR2: 12, 13, 16
550 * MSR_P4_CRU_ESCR3: 14, 15, 17
551 */
552
d814f301 553 P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04),
a072738e
CG		 554 /*
555 * MSR_P4_CRU_ESCR0: 12, 13, 16
556 * MSR_P4_CRU_ESCR1: 14, 15, 17
557 */
d814f301 558};
a072738e
CG		 559
560/*
d814f301
CG		 561 * a caller should use P4_ESCR_EMASK_NAME helper to
562 * pick the EventMask needed, for example
a072738e 563 *
d814f301 564 * P4_ESCR_EMASK_NAME(P4_EVENT_TC_DELIVER_MODE, DD)
a072738e 565 */
d814f301
CG		 566enum P4_ESCR_EMASKS {
567 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
568 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
569 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
570 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
571 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
572 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
573 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
574
575 P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
576
577 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
578 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
579 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
580
581 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
582 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
583
584 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
585 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
586
587 P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
588
589 P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
590
591 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
592 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
593 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
594 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
595
596 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
597 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
598
599 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
600 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
601 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
602 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
603 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
604 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
605 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
606 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
607 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
608
609 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
610 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
611 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
612 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
613 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
614 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
615 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
616 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
617 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
618 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
619 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
620
621 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
622 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
623 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
624 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
625 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
626 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
627 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
628 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
629 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
630 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
631 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
632
633 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
634 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
635 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
636 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
637 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
638 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
639
640 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
641 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
642 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
643 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
644 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
645 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
646 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
647 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
648 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
649 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
650 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
651 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
652 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
653
654 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
655 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
656 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
657 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
658 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
659 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
660 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
661 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
662 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
663 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
664 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
665 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
666 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
667
668 P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
669
670 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
671
672 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
673
674 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
675
676 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
677
678 P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
679
680 P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
681
682 P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
683
684 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
685
686 P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
687
688 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
689
690 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
691 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
692 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
693
694 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
695 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
696 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
697 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
698
699 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
700 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
701 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
702 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
703
704 P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
705
706 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
707 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
708
709 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
710 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
711
712 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
713 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
714 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
715 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
716 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
717 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
718 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
719 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
720
721 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
722 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
723
724 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
725 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
726 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
727 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
728
729 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
730 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
a072738e 731
d814f301
CG		 732 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
733 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
734
735 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
736 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
737 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
738 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
a072738e 739
d814f301 740 P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
a072738e 741
d814f301
CG		 742 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
743 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
744 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
745 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
746 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
a072738e 747
d814f301
CG		 748 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
749 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
750 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
a072738e 751
d814f301
CG		 752 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
753 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
a072738e
CG		 754};
755
d814f301
CG		 756/* P4 PEBS: stale for a while */
757#define P4_PEBS_METRIC_MASK 0x00001fffU
758#define P4_PEBS_UOB_TAG 0x01000000U
759#define P4_PEBS_ENABLE 0x02000000U
760
761/* Replay metrics for MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT */
762#define P4_PEBS__1stl_cache_load_miss_retired 0x3000001
763#define P4_PEBS__2ndl_cache_load_miss_retired 0x3000002
764#define P4_PEBS__dtlb_load_miss_retired 0x3000004
765#define P4_PEBS__dtlb_store_miss_retired 0x3000004
766#define P4_PEBS__dtlb_all_miss_retired 0x3000004
767#define P4_PEBS__tagged_mispred_branch 0x3018000
768#define P4_PEBS__mob_load_replay_retired 0x3000200
769#define P4_PEBS__split_load_retired 0x3000400
770#define P4_PEBS__split_store_retired 0x3000400
771
772#define P4_VERT__1stl_cache_load_miss_retired 0x0000001
773#define P4_VERT__2ndl_cache_load_miss_retired 0x0000001
774#define P4_VERT__dtlb_load_miss_retired 0x0000001
775#define P4_VERT__dtlb_store_miss_retired 0x0000002
776#define P4_VERT__dtlb_all_miss_retired 0x0000003
777#define P4_VERT__tagged_mispred_branch 0x0000010
778#define P4_VERT__mob_load_replay_retired 0x0000001
779#define P4_VERT__split_load_retired 0x0000001
780#define P4_VERT__split_store_retired 0x0000002
781
782enum P4_CACHE_EVENTS {
783 P4_CACHE__NONE,
784
785 P4_CACHE__1stl_cache_load_miss_retired,
786 P4_CACHE__2ndl_cache_load_miss_retired,
787 P4_CACHE__dtlb_load_miss_retired,
788 P4_CACHE__dtlb_store_miss_retired,
789 P4_CACHE__itlb_reference_hit,
790 P4_CACHE__itlb_reference_miss,
791
792 P4_CACHE__MAX
cb7d6b50
LM		 793};
794
a072738e 795#endif /* PERF_EVENT_P4_H */
Linux kernel - Deliverables
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