[deliverable/linux.git] / arch / x86 / include / asm / pmc_atom.h

/*
 * Intel Atom SOC Power Management Controller Header File
 * Copyright (c) 2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#ifndef PMC_ATOM_H
#define PMC_ATOM_H

/* ValleyView Power Control Unit PCI Device ID */
#define	PCI_DEVICE_ID_VLV_PMC	0x0F1C
/* CherryTrail Power Control Unit PCI Device ID */
#define	PCI_DEVICE_ID_CHT_PMC	0x229C

/* PMC Memory mapped IO registers */
#define	PMC_BASE_ADDR_OFFSET	0x44
#define	PMC_BASE_ADDR_MASK	0xFFFFFE00
#define	PMC_MMIO_REG_LEN	0x100
#define	PMC_REG_BIT_WIDTH	32

/* BIOS uses FUNC_DIS to disable specific function */
#define	PMC_FUNC_DIS		0x34
#define	PMC_FUNC_DIS_2		0x38

/* CHT specific bits in FUNC_DIS2 register */
#define	BIT_FD_GMM		BIT(3)
#define	BIT_FD_ISH		BIT(4)

/* S0ix wake event control */
#define	PMC_S0IX_WAKE_EN	0x3C

#define	BIT_LPC_CLOCK_RUN		BIT(4)
#define	BIT_SHARED_IRQ_GPSC		BIT(5)
#define	BIT_ORED_DEDICATED_IRQ_GPSS	BIT(18)
#define	BIT_ORED_DEDICATED_IRQ_GPSC	BIT(19)
#define	BIT_SHARED_IRQ_GPSS		BIT(20)

#define	PMC_WAKE_EN_SETTING	~(BIT_LPC_CLOCK_RUN | \
				BIT_SHARED_IRQ_GPSC | \
				BIT_ORED_DEDICATED_IRQ_GPSS | \
				BIT_ORED_DEDICATED_IRQ_GPSC | \
				BIT_SHARED_IRQ_GPSS)

/* The timers acumulate time spent in sleep state */
#define	PMC_S0IR_TMR		0x80
#define	PMC_S0I1_TMR		0x84
#define	PMC_S0I2_TMR		0x88
#define	PMC_S0I3_TMR		0x8C
#define	PMC_S0_TMR		0x90
/* Sleep state counter is in units of of 32us */
#define	PMC_TMR_SHIFT		5

/* Power status of power islands */
#define	PMC_PSS			0x98

#define PMC_PSS_BIT_GBE			BIT(0)
#define PMC_PSS_BIT_SATA		BIT(1)
#define PMC_PSS_BIT_HDA			BIT(2)
#define PMC_PSS_BIT_SEC			BIT(3)
#define PMC_PSS_BIT_PCIE		BIT(4)
#define PMC_PSS_BIT_LPSS		BIT(5)
#define PMC_PSS_BIT_LPE			BIT(6)
#define PMC_PSS_BIT_DFX			BIT(7)
#define PMC_PSS_BIT_USH_CTRL		BIT(8)
#define PMC_PSS_BIT_USH_SUS		BIT(9)
#define PMC_PSS_BIT_USH_VCCS		BIT(10)
#define PMC_PSS_BIT_USH_VCCA		BIT(11)
#define PMC_PSS_BIT_OTG_CTRL		BIT(12)
#define PMC_PSS_BIT_OTG_VCCS		BIT(13)
#define PMC_PSS_BIT_OTG_VCCA_CLK	BIT(14)
#define PMC_PSS_BIT_OTG_VCCA		BIT(15)
#define PMC_PSS_BIT_USB			BIT(16)
#define PMC_PSS_BIT_USB_SUS		BIT(17)

/* CHT specific bits in PSS register */
#define	PMC_PSS_BIT_CHT_UFS		BIT(7)
#define	PMC_PSS_BIT_CHT_UXD		BIT(11)
#define	PMC_PSS_BIT_CHT_UXD_FD		BIT(12)
#define	PMC_PSS_BIT_CHT_UX_ENG		BIT(15)
#define	PMC_PSS_BIT_CHT_USB_SUS		BIT(16)
#define	PMC_PSS_BIT_CHT_GMM		BIT(17)
#define	PMC_PSS_BIT_CHT_ISH		BIT(18)
#define	PMC_PSS_BIT_CHT_DFX_MASTER	BIT(26)
#define	PMC_PSS_BIT_CHT_DFX_CLUSTER1	BIT(27)
#define	PMC_PSS_BIT_CHT_DFX_CLUSTER2	BIT(28)
#define	PMC_PSS_BIT_CHT_DFX_CLUSTER3	BIT(29)
#define	PMC_PSS_BIT_CHT_DFX_CLUSTER4	BIT(30)
#define	PMC_PSS_BIT_CHT_DFX_CLUSTER5	BIT(31)

/* These registers reflect D3 status of functions */
#define	PMC_D3_STS_0		0xA0

#define	BIT_LPSS1_F0_DMA	BIT(0)
#define	BIT_LPSS1_F1_PWM1	BIT(1)
#define	BIT_LPSS1_F2_PWM2	BIT(2)
#define	BIT_LPSS1_F3_HSUART1	BIT(3)
#define	BIT_LPSS1_F4_HSUART2	BIT(4)
#define	BIT_LPSS1_F5_SPI	BIT(5)
#define	BIT_LPSS1_F6_XXX	BIT(6)
#define	BIT_LPSS1_F7_XXX	BIT(7)
#define	BIT_SCC_EMMC		BIT(8)
#define	BIT_SCC_SDIO		BIT(9)
#define	BIT_SCC_SDCARD		BIT(10)
#define	BIT_SCC_MIPI		BIT(11)
#define	BIT_HDA			BIT(12)
#define	BIT_LPE			BIT(13)
#define	BIT_OTG			BIT(14)
#define	BIT_USH			BIT(15)
#define	BIT_GBE			BIT(16)
#define	BIT_SATA		BIT(17)
#define	BIT_USB_EHCI		BIT(18)
#define	BIT_SEC			BIT(19)
#define	BIT_PCIE_PORT0		BIT(20)
#define	BIT_PCIE_PORT1		BIT(21)
#define	BIT_PCIE_PORT2		BIT(22)
#define	BIT_PCIE_PORT3		BIT(23)
#define	BIT_LPSS2_F0_DMA	BIT(24)
#define	BIT_LPSS2_F1_I2C1	BIT(25)
#define	BIT_LPSS2_F2_I2C2	BIT(26)
#define	BIT_LPSS2_F3_I2C3	BIT(27)
#define	BIT_LPSS2_F4_I2C4	BIT(28)
#define	BIT_LPSS2_F5_I2C5	BIT(29)
#define	BIT_LPSS2_F6_I2C6	BIT(30)
#define	BIT_LPSS2_F7_I2C7	BIT(31)

#define	PMC_D3_STS_1		0xA4
#define	BIT_SMB			BIT(0)
#define	BIT_OTG_SS_PHY		BIT(1)
#define	BIT_USH_SS_PHY		BIT(2)
#define	BIT_DFX			BIT(3)

/* CHT specific bits in PMC_D3_STS_1 register */
#define	BIT_STS_GMM		BIT(1)
#define	BIT_STS_ISH		BIT(2)

/* PMC I/O Registers */
#define	ACPI_BASE_ADDR_OFFSET	0x40
#define	ACPI_BASE_ADDR_MASK	0xFFFFFE00
#define	ACPI_MMIO_REG_LEN	0x100

#define	PM1_CNT			0x4
#define	SLEEP_TYPE_MASK		0xFFFFECFF
#define	SLEEP_TYPE_S5		0x1C00
#define	SLEEP_ENABLE		0x2000

extern int pmc_atom_read(int offset, u32 *value);
extern int pmc_atom_write(int offset, u32 value);

#endif /* PMC_ATOM_H */
Commit	Line	Data
93e5eadd LA	1	/*
	2	* Intel Atom SOC Power Management Controller Header File
	3	* Copyright (c) 2014, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	*/
	15
	16	#ifndef PMC_ATOM_H
	17	#define PMC_ATOM_H
	18
	19	/* ValleyView Power Control Unit PCI Device ID */
	20	#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
2b8f8edd AS	21	/* CherryTrail Power Control Unit PCI Device ID */
2b8f8edd AS	22	#define PCI_DEVICE_ID_CHT_PMC 0x229C
93e5eadd	23
b00055ca LA	24	/* PMC Memory mapped IO registers */
	25	#define PMC_BASE_ADDR_OFFSET 0x44
	26	#define PMC_BASE_ADDR_MASK 0xFFFFFE00
	27	#define PMC_MMIO_REG_LEN 0x100
	28	#define PMC_REG_BIT_WIDTH 32
	29
f855911c LA	30	/* BIOS uses FUNC_DIS to disable specific function */
	31	#define PMC_FUNC_DIS 0x34
	32	#define PMC_FUNC_DIS_2 0x38
	33
2b8f8edd AS	34	/* CHT specific bits in FUNC_DIS2 register */
	35	#define BIT_FD_GMM BIT(3)
	36	#define BIT_FD_ISH BIT(4)
	37
b00055ca LA	38	/* S0ix wake event control */
	39	#define PMC_S0IX_WAKE_EN 0x3C
	40
	41	#define BIT_LPC_CLOCK_RUN BIT(4)
	42	#define BIT_SHARED_IRQ_GPSC BIT(5)
	43	#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
	44	#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
	45	#define BIT_SHARED_IRQ_GPSS BIT(20)
	46
	47	#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN \| \
	48	BIT_SHARED_IRQ_GPSC \| \
	49	BIT_ORED_DEDICATED_IRQ_GPSS \| \
	50	BIT_ORED_DEDICATED_IRQ_GPSC \| \
	51	BIT_SHARED_IRQ_GPSS)
	52
f855911c LA	53	/* The timers acumulate time spent in sleep state */
	54	#define PMC_S0IR_TMR 0x80
	55	#define PMC_S0I1_TMR 0x84
	56	#define PMC_S0I2_TMR 0x88
	57	#define PMC_S0I3_TMR 0x8C
	58	#define PMC_S0_TMR 0x90
	59	/* Sleep state counter is in units of of 32us */
	60	#define PMC_TMR_SHIFT 5
	61
0e154020 AS	62	/* Power status of power islands */
	63	#define PMC_PSS 0x98
	64
	65	#define PMC_PSS_BIT_GBE BIT(0)
	66	#define PMC_PSS_BIT_SATA BIT(1)
	67	#define PMC_PSS_BIT_HDA BIT(2)
	68	#define PMC_PSS_BIT_SEC BIT(3)
	69	#define PMC_PSS_BIT_PCIE BIT(4)
	70	#define PMC_PSS_BIT_LPSS BIT(5)
	71	#define PMC_PSS_BIT_LPE BIT(6)
	72	#define PMC_PSS_BIT_DFX BIT(7)
	73	#define PMC_PSS_BIT_USH_CTRL BIT(8)
	74	#define PMC_PSS_BIT_USH_SUS BIT(9)
	75	#define PMC_PSS_BIT_USH_VCCS BIT(10)
	76	#define PMC_PSS_BIT_USH_VCCA BIT(11)
	77	#define PMC_PSS_BIT_OTG_CTRL BIT(12)
	78	#define PMC_PSS_BIT_OTG_VCCS BIT(13)
	79	#define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14)
	80	#define PMC_PSS_BIT_OTG_VCCA BIT(15)
	81	#define PMC_PSS_BIT_USB BIT(16)
	82	#define PMC_PSS_BIT_USB_SUS BIT(17)
	83
2b8f8edd AS	84	/* CHT specific bits in PSS register */
	85	#define PMC_PSS_BIT_CHT_UFS BIT(7)
	86	#define PMC_PSS_BIT_CHT_UXD BIT(11)
	87	#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
	88	#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
	89	#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
	90	#define PMC_PSS_BIT_CHT_GMM BIT(17)
	91	#define PMC_PSS_BIT_CHT_ISH BIT(18)
	92	#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
	93	#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
	94	#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
	95	#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
	96	#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
	97	#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
	98
f855911c LA	99	/* These registers reflect D3 status of functions */
	100	#define PMC_D3_STS_0 0xA0
	101
	102	#define BIT_LPSS1_F0_DMA BIT(0)
	103	#define BIT_LPSS1_F1_PWM1 BIT(1)
	104	#define BIT_LPSS1_F2_PWM2 BIT(2)
	105	#define BIT_LPSS1_F3_HSUART1 BIT(3)
	106	#define BIT_LPSS1_F4_HSUART2 BIT(4)
	107	#define BIT_LPSS1_F5_SPI BIT(5)
	108	#define BIT_LPSS1_F6_XXX BIT(6)
	109	#define BIT_LPSS1_F7_XXX BIT(7)
	110	#define BIT_SCC_EMMC BIT(8)
	111	#define BIT_SCC_SDIO BIT(9)
	112	#define BIT_SCC_SDCARD BIT(10)
	113	#define BIT_SCC_MIPI BIT(11)
	114	#define BIT_HDA BIT(12)
	115	#define BIT_LPE BIT(13)
	116	#define BIT_OTG BIT(14)
	117	#define BIT_USH BIT(15)
	118	#define BIT_GBE BIT(16)
	119	#define BIT_SATA BIT(17)
	120	#define BIT_USB_EHCI BIT(18)
	121	#define BIT_SEC BIT(19)
	122	#define BIT_PCIE_PORT0 BIT(20)
	123	#define BIT_PCIE_PORT1 BIT(21)
	124	#define BIT_PCIE_PORT2 BIT(22)
	125	#define BIT_PCIE_PORT3 BIT(23)
	126	#define BIT_LPSS2_F0_DMA BIT(24)
	127	#define BIT_LPSS2_F1_I2C1 BIT(25)
	128	#define BIT_LPSS2_F2_I2C2 BIT(26)
	129	#define BIT_LPSS2_F3_I2C3 BIT(27)
	130	#define BIT_LPSS2_F4_I2C4 BIT(28)
	131	#define BIT_LPSS2_F5_I2C5 BIT(29)
	132	#define BIT_LPSS2_F6_I2C6 BIT(30)
	133	#define BIT_LPSS2_F7_I2C7 BIT(31)
	134
	135	#define PMC_D3_STS_1 0xA4
	136	#define BIT_SMB BIT(0)
	137	#define BIT_OTG_SS_PHY BIT(1)
	138	#define BIT_USH_SS_PHY BIT(2)
	139	#define BIT_DFX BIT(3)
	140
2b8f8edd AS	141	/* CHT specific bits in PMC_D3_STS_1 register */
	142	#define BIT_STS_GMM BIT(1)
	143	#define BIT_STS_ISH BIT(2)
	144
93e5eadd LA	145	/* PMC I/O Registers */
	146	#define ACPI_BASE_ADDR_OFFSET 0x40
	147	#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
	148	#define ACPI_MMIO_REG_LEN 0x100
	149
	150	#define PM1_CNT 0x4
	151	#define SLEEP_TYPE_MASK 0xFFFFECFF
	152	#define SLEEP_TYPE_S5 0x1C00
	153	#define SLEEP_ENABLE 0x2000
68872eb9 AS	154
	155	extern int pmc_atom_read(int offset, u32 *value);
	156	extern int pmc_atom_write(int offset, u32 value);
	157
93e5eadd	158	#endif /* PMC_ATOM_H */