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1965aae3 PA |
1 | #ifndef _ASM_X86_SPINLOCK_H |
2 | #define _ASM_X86_SPINLOCK_H | |
2fed0c50 | 3 | |
60063497 | 4 | #include <linux/atomic.h> |
1075cf7a TG |
5 | #include <asm/page.h> |
6 | #include <asm/processor.h> | |
314cdbef | 7 | #include <linux/compiler.h> |
74d4affd | 8 | #include <asm/paravirt.h> |
1075cf7a TG |
9 | /* |
10 | * Your basic SMP spinlocks, allowing only a single CPU anywhere | |
11 | * | |
12 | * Simple spin lock operations. There are two variants, one clears IRQ's | |
13 | * on the local processor, one does not. | |
14 | * | |
314cdbef NP |
15 | * These are fair FIFO ticket locks, which are currently limited to 256 |
16 | * CPUs. | |
1075cf7a TG |
17 | * |
18 | * (the type definitions are in asm/spinlock_types.h) | |
19 | */ | |
20 | ||
96a388de | 21 | #ifdef CONFIG_X86_32 |
1075cf7a | 22 | # define LOCK_PTR_REG "a" |
74e91604 | 23 | # define REG_PTR_MODE "k" |
96a388de | 24 | #else |
1075cf7a | 25 | # define LOCK_PTR_REG "D" |
74e91604 | 26 | # define REG_PTR_MODE "q" |
1075cf7a TG |
27 | #endif |
28 | ||
3a556b26 NP |
29 | #if defined(CONFIG_X86_32) && \ |
30 | (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)) | |
31 | /* | |
32 | * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock | |
33 | * (PPro errata 66, 92) | |
34 | */ | |
35 | # define UNLOCK_LOCK_PREFIX LOCK_PREFIX | |
36 | #else | |
37 | # define UNLOCK_LOCK_PREFIX | |
314cdbef NP |
38 | #endif |
39 | ||
3a556b26 NP |
40 | /* |
41 | * Ticket locks are conceptually two parts, one indicating the current head of | |
42 | * the queue, and the other indicating the current tail. The lock is acquired | |
43 | * by atomically noting the tail and incrementing it by one (thus adding | |
44 | * ourself to the queue and noting our position), then waiting until the head | |
45 | * becomes equal to the the initial value of the tail. | |
46 | * | |
47 | * We use an xadd covering *both* parts of the lock, to increment the tail and | |
48 | * also load the position of the head, which takes care of memory ordering | |
49 | * issues and should be optimal for the uncontended case. Note the tail must be | |
50 | * in the high part, because a wide xadd increment of the low part would carry | |
51 | * up and contaminate the high part. | |
52 | * | |
53 | * With fewer than 2^8 possible CPUs, we can use x86's partial registers to | |
54 | * save some instructions and make the code more elegant. There really isn't | |
55 | * much between them in performance though, especially as locks are out of line. | |
56 | */ | |
57 | #if (NR_CPUS < 256) | |
445c8951 | 58 | static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) |
1075cf7a | 59 | { |
c576a3ea JF |
60 | register union { |
61 | struct __raw_tickets tickets; | |
62 | unsigned short slock; | |
63 | } inc = { .slock = 1 << TICKET_SHIFT }; | |
314cdbef | 64 | |
c576a3ea JF |
65 | asm volatile (LOCK_PREFIX "xaddw %w0, %1\n" |
66 | : "+Q" (inc), "+m" (lock->slock) : : "memory", "cc"); | |
67 | ||
68 | for (;;) { | |
69 | if (inc.tickets.head == inc.tickets.tail) | |
70 | break; | |
71 | cpu_relax(); | |
72 | inc.tickets.head = ACCESS_ONCE(lock->tickets.head); | |
73 | } | |
74 | barrier(); /* make sure nothing creeps before the lock is taken */ | |
1075cf7a | 75 | } |
314cdbef | 76 | |
445c8951 | 77 | static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) |
1075cf7a | 78 | { |
84eb950d | 79 | unsigned int tmp, new; |
1075cf7a | 80 | |
74e91604 | 81 | asm volatile("movzwl %2, %0\n\t" |
d3bf60a6 | 82 | "cmpb %h0,%b0\n\t" |
74e91604 | 83 | "leal 0x100(%" REG_PTR_MODE "0), %1\n\t" |
d3bf60a6 | 84 | "jne 1f\n\t" |
5bbd4c37 | 85 | LOCK_PREFIX "cmpxchgw %w1,%2\n\t" |
d3bf60a6 JP |
86 | "1:" |
87 | "sete %b1\n\t" | |
88 | "movzbl %b1,%0\n\t" | |
74e91604 | 89 | : "=&a" (tmp), "=&q" (new), "+m" (lock->slock) |
d3bf60a6 JP |
90 | : |
91 | : "memory", "cc"); | |
314cdbef NP |
92 | |
93 | return tmp; | |
1075cf7a TG |
94 | } |
95 | ||
445c8951 | 96 | static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) |
3a556b26 | 97 | { |
d3bf60a6 JP |
98 | asm volatile(UNLOCK_LOCK_PREFIX "incb %0" |
99 | : "+m" (lock->slock) | |
100 | : | |
101 | : "memory", "cc"); | |
3a556b26 | 102 | } |
1075cf7a | 103 | #else |
445c8951 | 104 | static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) |
3a556b26 | 105 | { |
84eb950d | 106 | unsigned inc = 1 << TICKET_SHIFT; |
c576a3ea | 107 | __ticket_t tmp; |
3a556b26 | 108 | |
c576a3ea JF |
109 | asm volatile(LOCK_PREFIX "xaddl %0, %1\n\t" |
110 | : "+r" (inc), "+m" (lock->slock) | |
111 | : : "memory", "cc"); | |
112 | ||
113 | tmp = inc; | |
114 | inc >>= TICKET_SHIFT; | |
115 | ||
116 | for (;;) { | |
117 | if ((__ticket_t)inc == tmp) | |
118 | break; | |
119 | cpu_relax(); | |
120 | tmp = ACCESS_ONCE(lock->tickets.head); | |
121 | } | |
122 | barrier(); /* make sure nothing creeps before the lock is taken */ | |
3a556b26 NP |
123 | } |
124 | ||
445c8951 | 125 | static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) |
3a556b26 | 126 | { |
84eb950d JF |
127 | unsigned tmp; |
128 | unsigned new; | |
3a556b26 | 129 | |
d3bf60a6 JP |
130 | asm volatile("movl %2,%0\n\t" |
131 | "movl %0,%1\n\t" | |
132 | "roll $16, %0\n\t" | |
133 | "cmpl %0,%1\n\t" | |
74e91604 | 134 | "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t" |
d3bf60a6 | 135 | "jne 1f\n\t" |
5bbd4c37 | 136 | LOCK_PREFIX "cmpxchgl %1,%2\n\t" |
d3bf60a6 JP |
137 | "1:" |
138 | "sete %b1\n\t" | |
139 | "movzbl %b1,%0\n\t" | |
ef1f3413 | 140 | : "=&a" (tmp), "=&q" (new), "+m" (lock->slock) |
d3bf60a6 JP |
141 | : |
142 | : "memory", "cc"); | |
3a556b26 NP |
143 | |
144 | return tmp; | |
145 | } | |
1075cf7a | 146 | |
445c8951 | 147 | static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) |
1075cf7a | 148 | { |
d3bf60a6 JP |
149 | asm volatile(UNLOCK_LOCK_PREFIX "incw %0" |
150 | : "+m" (lock->slock) | |
151 | : | |
152 | : "memory", "cc"); | |
1075cf7a | 153 | } |
3a556b26 | 154 | #endif |
1075cf7a | 155 | |
445c8951 | 156 | static inline int __ticket_spin_is_locked(arch_spinlock_t *lock) |
08f5fcbe | 157 | { |
84eb950d | 158 | struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets); |
08f5fcbe | 159 | |
84eb950d | 160 | return !!(tmp.tail ^ tmp.head); |
08f5fcbe JB |
161 | } |
162 | ||
445c8951 | 163 | static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) |
08f5fcbe | 164 | { |
84eb950d | 165 | struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets); |
08f5fcbe | 166 | |
84eb950d | 167 | return ((tmp.tail - tmp.head) & TICKET_MASK) > 1; |
08f5fcbe | 168 | } |
74d4affd | 169 | |
b4ecc126 | 170 | #ifndef CONFIG_PARAVIRT_SPINLOCKS |
8efcbab6 | 171 | |
0199c4e6 | 172 | static inline int arch_spin_is_locked(arch_spinlock_t *lock) |
74d4affd JF |
173 | { |
174 | return __ticket_spin_is_locked(lock); | |
175 | } | |
176 | ||
0199c4e6 | 177 | static inline int arch_spin_is_contended(arch_spinlock_t *lock) |
74d4affd JF |
178 | { |
179 | return __ticket_spin_is_contended(lock); | |
180 | } | |
0199c4e6 | 181 | #define arch_spin_is_contended arch_spin_is_contended |
74d4affd | 182 | |
0199c4e6 | 183 | static __always_inline void arch_spin_lock(arch_spinlock_t *lock) |
74d4affd JF |
184 | { |
185 | __ticket_spin_lock(lock); | |
186 | } | |
187 | ||
0199c4e6 | 188 | static __always_inline int arch_spin_trylock(arch_spinlock_t *lock) |
74d4affd JF |
189 | { |
190 | return __ticket_spin_trylock(lock); | |
191 | } | |
192 | ||
0199c4e6 | 193 | static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) |
74d4affd JF |
194 | { |
195 | __ticket_spin_unlock(lock); | |
196 | } | |
63d3a75d | 197 | |
0199c4e6 | 198 | static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock, |
63d3a75d JF |
199 | unsigned long flags) |
200 | { | |
0199c4e6 | 201 | arch_spin_lock(lock); |
63d3a75d JF |
202 | } |
203 | ||
b4ecc126 | 204 | #endif /* CONFIG_PARAVIRT_SPINLOCKS */ |
74d4affd | 205 | |
0199c4e6 | 206 | static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) |
1075cf7a | 207 | { |
0199c4e6 | 208 | while (arch_spin_is_locked(lock)) |
1075cf7a TG |
209 | cpu_relax(); |
210 | } | |
211 | ||
212 | /* | |
213 | * Read-write spinlocks, allowing multiple readers | |
214 | * but only one writer. | |
215 | * | |
216 | * NOTE! it is quite common to have readers in interrupts | |
217 | * but no interrupt writers. For those circumstances we | |
218 | * can "mix" irq-safe locks - any writer needs to get a | |
219 | * irq-safe write-lock, but readers can get non-irqsafe | |
220 | * read-locks. | |
221 | * | |
222 | * On x86, we implement read-write locks as a 32-bit counter | |
223 | * with the high bit (sign) being the "contended" bit. | |
224 | */ | |
225 | ||
314cdbef NP |
226 | /** |
227 | * read_can_lock - would read_trylock() succeed? | |
228 | * @lock: the rwlock in question. | |
229 | */ | |
e5931943 | 230 | static inline int arch_read_can_lock(arch_rwlock_t *lock) |
1075cf7a | 231 | { |
a750036f | 232 | return lock->lock > 0; |
1075cf7a TG |
233 | } |
234 | ||
314cdbef NP |
235 | /** |
236 | * write_can_lock - would write_trylock() succeed? | |
237 | * @lock: the rwlock in question. | |
238 | */ | |
e5931943 | 239 | static inline int arch_write_can_lock(arch_rwlock_t *lock) |
1075cf7a | 240 | { |
a750036f | 241 | return lock->write == WRITE_LOCK_CMP; |
1075cf7a TG |
242 | } |
243 | ||
e5931943 | 244 | static inline void arch_read_lock(arch_rwlock_t *rw) |
1075cf7a | 245 | { |
a750036f | 246 | asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t" |
1075cf7a TG |
247 | "jns 1f\n" |
248 | "call __read_lock_failed\n\t" | |
249 | "1:\n" | |
250 | ::LOCK_PTR_REG (rw) : "memory"); | |
251 | } | |
252 | ||
e5931943 | 253 | static inline void arch_write_lock(arch_rwlock_t *rw) |
1075cf7a | 254 | { |
a750036f | 255 | asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t" |
1075cf7a TG |
256 | "jz 1f\n" |
257 | "call __write_lock_failed\n\t" | |
258 | "1:\n" | |
a750036f JB |
259 | ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS) |
260 | : "memory"); | |
1075cf7a TG |
261 | } |
262 | ||
e5931943 | 263 | static inline int arch_read_trylock(arch_rwlock_t *lock) |
1075cf7a | 264 | { |
a750036f | 265 | READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock; |
1075cf7a | 266 | |
a750036f | 267 | if (READ_LOCK_ATOMIC(dec_return)(count) >= 0) |
1075cf7a | 268 | return 1; |
a750036f | 269 | READ_LOCK_ATOMIC(inc)(count); |
1075cf7a TG |
270 | return 0; |
271 | } | |
272 | ||
e5931943 | 273 | static inline int arch_write_trylock(arch_rwlock_t *lock) |
1075cf7a | 274 | { |
a750036f | 275 | atomic_t *count = (atomic_t *)&lock->write; |
1075cf7a | 276 | |
a750036f | 277 | if (atomic_sub_and_test(WRITE_LOCK_CMP, count)) |
1075cf7a | 278 | return 1; |
a750036f | 279 | atomic_add(WRITE_LOCK_CMP, count); |
1075cf7a TG |
280 | return 0; |
281 | } | |
282 | ||
e5931943 | 283 | static inline void arch_read_unlock(arch_rwlock_t *rw) |
1075cf7a | 284 | { |
a750036f JB |
285 | asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0" |
286 | :"+m" (rw->lock) : : "memory"); | |
1075cf7a TG |
287 | } |
288 | ||
e5931943 | 289 | static inline void arch_write_unlock(arch_rwlock_t *rw) |
1075cf7a | 290 | { |
a750036f JB |
291 | asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0" |
292 | : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory"); | |
1075cf7a TG |
293 | } |
294 | ||
e5931943 TG |
295 | #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) |
296 | #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) | |
f5f7eac4 | 297 | |
a750036f JB |
298 | #undef READ_LOCK_SIZE |
299 | #undef READ_LOCK_ATOMIC | |
300 | #undef WRITE_LOCK_ADD | |
301 | #undef WRITE_LOCK_SUB | |
302 | #undef WRITE_LOCK_CMP | |
303 | ||
0199c4e6 TG |
304 | #define arch_spin_relax(lock) cpu_relax() |
305 | #define arch_read_relax(lock) cpu_relax() | |
306 | #define arch_write_relax(lock) cpu_relax() | |
1075cf7a | 307 | |
ad462769 JO |
308 | /* The {read|write|spin}_lock() on x86 are full memory barriers. */ |
309 | static inline void smp_mb__after_lock(void) { } | |
310 | #define ARCH_HAS_SMP_MB_AFTER_LOCK | |
311 | ||
1965aae3 | 312 | #endif /* _ASM_X86_SPINLOCK_H */ |