[deliverable/linux.git] / arch / x86 / include / asm / vmx.h

#ifndef VMX_H
#define VMX_H

/*
 * vmx.h: VMX Architecture related definitions
 * Copyright (c) 2004, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * A few random additions are:
 * Copyright (C) 2006 Qumranet
 *    Avi Kivity <avi@qumranet.com>
 *    Yaniv Kamay <yaniv@qumranet.com>
 *
 */

/*
 * Definitions of Primary Processor-Based VM-Execution Controls.
 */
#define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
#define CPU_BASED_USE_TSC_OFFSETING             0x00000008
#define CPU_BASED_HLT_EXITING                   0x00000080
#define CPU_BASED_INVLPG_EXITING                0x00000200
#define CPU_BASED_MWAIT_EXITING                 0x00000400
#define CPU_BASED_RDPMC_EXITING                 0x00000800
#define CPU_BASED_RDTSC_EXITING                 0x00001000
#define CPU_BASED_CR3_LOAD_EXITING		0x00008000
#define CPU_BASED_CR3_STORE_EXITING		0x00010000
#define CPU_BASED_CR8_LOAD_EXITING              0x00080000
#define CPU_BASED_CR8_STORE_EXITING             0x00100000
#define CPU_BASED_TPR_SHADOW                    0x00200000
#define CPU_BASED_VIRTUAL_NMI_PENDING		0x00400000
#define CPU_BASED_MOV_DR_EXITING                0x00800000
#define CPU_BASED_UNCOND_IO_EXITING             0x01000000
#define CPU_BASED_USE_IO_BITMAPS                0x02000000
#define CPU_BASED_USE_MSR_BITMAPS               0x10000000
#define CPU_BASED_MONITOR_EXITING               0x20000000
#define CPU_BASED_PAUSE_EXITING                 0x40000000
#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
/*
 * Definitions of Secondary Processor-Based VM-Execution Controls.
 */
#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
#define SECONDARY_EXEC_ENABLE_EPT               0x00000002
#define SECONDARY_EXEC_ENABLE_VPID              0x00000020
#define SECONDARY_EXEC_WBINVD_EXITING		0x00000040
#define SECONDARY_EXEC_UNRESTRICTED_GUEST	0x00000080


#define PIN_BASED_EXT_INTR_MASK                 0x00000001
#define PIN_BASED_NMI_EXITING                   0x00000008
#define PIN_BASED_VIRTUAL_NMIS                  0x00000020

#define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
#define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
#define VM_EXIT_SAVE_IA32_PAT			0x00040000
#define VM_EXIT_LOAD_IA32_PAT			0x00080000

#define VM_ENTRY_IA32E_MODE                     0x00000200
#define VM_ENTRY_SMM                            0x00000400
#define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
#define VM_ENTRY_LOAD_IA32_PAT			0x00004000

/* VMCS Encodings */
enum vmcs_field {
	VIRTUAL_PROCESSOR_ID            = 0x00000000,
	GUEST_ES_SELECTOR               = 0x00000800,
	GUEST_CS_SELECTOR               = 0x00000802,
	GUEST_SS_SELECTOR               = 0x00000804,
	GUEST_DS_SELECTOR               = 0x00000806,
	GUEST_FS_SELECTOR               = 0x00000808,
	GUEST_GS_SELECTOR               = 0x0000080a,
	GUEST_LDTR_SELECTOR             = 0x0000080c,
	GUEST_TR_SELECTOR               = 0x0000080e,
	HOST_ES_SELECTOR                = 0x00000c00,
	HOST_CS_SELECTOR                = 0x00000c02,
	HOST_SS_SELECTOR                = 0x00000c04,
	HOST_DS_SELECTOR                = 0x00000c06,
	HOST_FS_SELECTOR                = 0x00000c08,
	HOST_GS_SELECTOR                = 0x00000c0a,
	HOST_TR_SELECTOR                = 0x00000c0c,
	IO_BITMAP_A                     = 0x00002000,
	IO_BITMAP_A_HIGH                = 0x00002001,
	IO_BITMAP_B                     = 0x00002002,
	IO_BITMAP_B_HIGH                = 0x00002003,
	MSR_BITMAP                      = 0x00002004,
	MSR_BITMAP_HIGH                 = 0x00002005,
	VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
	VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
	VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
	VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
	VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
	VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
	TSC_OFFSET                      = 0x00002010,
	TSC_OFFSET_HIGH                 = 0x00002011,
	VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
	VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
	APIC_ACCESS_ADDR		= 0x00002014,
	APIC_ACCESS_ADDR_HIGH		= 0x00002015,
	EPT_POINTER                     = 0x0000201a,
	EPT_POINTER_HIGH                = 0x0000201b,
	GUEST_PHYSICAL_ADDRESS          = 0x00002400,
	GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
	VMCS_LINK_POINTER               = 0x00002800,
	VMCS_LINK_POINTER_HIGH          = 0x00002801,
	GUEST_IA32_DEBUGCTL             = 0x00002802,
	GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
	GUEST_IA32_PAT			= 0x00002804,
	GUEST_IA32_PAT_HIGH		= 0x00002805,
	GUEST_PDPTR0                    = 0x0000280a,
	GUEST_PDPTR0_HIGH               = 0x0000280b,
	GUEST_PDPTR1                    = 0x0000280c,
	GUEST_PDPTR1_HIGH               = 0x0000280d,
	GUEST_PDPTR2                    = 0x0000280e,
	GUEST_PDPTR2_HIGH               = 0x0000280f,
	GUEST_PDPTR3                    = 0x00002810,
	GUEST_PDPTR3_HIGH               = 0x00002811,
	HOST_IA32_PAT			= 0x00002c00,
	HOST_IA32_PAT_HIGH		= 0x00002c01,
	PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
	CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
	EXCEPTION_BITMAP                = 0x00004004,
	PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
	PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
	CR3_TARGET_COUNT                = 0x0000400a,
	VM_EXIT_CONTROLS                = 0x0000400c,
	VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
	VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
	VM_ENTRY_CONTROLS               = 0x00004012,
	VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
	VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
	VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
	VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
	TPR_THRESHOLD                   = 0x0000401c,
	SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
	VM_INSTRUCTION_ERROR            = 0x00004400,
	VM_EXIT_REASON                  = 0x00004402,
	VM_EXIT_INTR_INFO               = 0x00004404,
	VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
	IDT_VECTORING_INFO_FIELD        = 0x00004408,
	IDT_VECTORING_ERROR_CODE        = 0x0000440a,
	VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
	VMX_INSTRUCTION_INFO            = 0x0000440e,
	GUEST_ES_LIMIT                  = 0x00004800,
	GUEST_CS_LIMIT                  = 0x00004802,
	GUEST_SS_LIMIT                  = 0x00004804,
	GUEST_DS_LIMIT                  = 0x00004806,
	GUEST_FS_LIMIT                  = 0x00004808,
	GUEST_GS_LIMIT                  = 0x0000480a,
	GUEST_LDTR_LIMIT                = 0x0000480c,
	GUEST_TR_LIMIT                  = 0x0000480e,
	GUEST_GDTR_LIMIT                = 0x00004810,
	GUEST_IDTR_LIMIT                = 0x00004812,
	GUEST_ES_AR_BYTES               = 0x00004814,
	GUEST_CS_AR_BYTES               = 0x00004816,
	GUEST_SS_AR_BYTES               = 0x00004818,
	GUEST_DS_AR_BYTES               = 0x0000481a,
	GUEST_FS_AR_BYTES               = 0x0000481c,
	GUEST_GS_AR_BYTES               = 0x0000481e,
	GUEST_LDTR_AR_BYTES             = 0x00004820,
	GUEST_TR_AR_BYTES               = 0x00004822,
	GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
	GUEST_ACTIVITY_STATE            = 0X00004826,
	GUEST_SYSENTER_CS               = 0x0000482A,
	HOST_IA32_SYSENTER_CS           = 0x00004c00,
	CR0_GUEST_HOST_MASK             = 0x00006000,
	CR4_GUEST_HOST_MASK             = 0x00006002,
	CR0_READ_SHADOW                 = 0x00006004,
	CR4_READ_SHADOW                 = 0x00006006,
	CR3_TARGET_VALUE0               = 0x00006008,
	CR3_TARGET_VALUE1               = 0x0000600a,
	CR3_TARGET_VALUE2               = 0x0000600c,
	CR3_TARGET_VALUE3               = 0x0000600e,
	EXIT_QUALIFICATION              = 0x00006400,
	GUEST_LINEAR_ADDRESS            = 0x0000640a,
	GUEST_CR0                       = 0x00006800,
	GUEST_CR3                       = 0x00006802,
	GUEST_CR4                       = 0x00006804,
	GUEST_ES_BASE                   = 0x00006806,
	GUEST_CS_BASE                   = 0x00006808,
	GUEST_SS_BASE                   = 0x0000680a,
	GUEST_DS_BASE                   = 0x0000680c,
	GUEST_FS_BASE                   = 0x0000680e,
	GUEST_GS_BASE                   = 0x00006810,
	GUEST_LDTR_BASE                 = 0x00006812,
	GUEST_TR_BASE                   = 0x00006814,
	GUEST_GDTR_BASE                 = 0x00006816,
	GUEST_IDTR_BASE                 = 0x00006818,
	GUEST_DR7                       = 0x0000681a,
	GUEST_RSP                       = 0x0000681c,
	GUEST_RIP                       = 0x0000681e,
	GUEST_RFLAGS                    = 0x00006820,
	GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
	GUEST_SYSENTER_ESP              = 0x00006824,
	GUEST_SYSENTER_EIP              = 0x00006826,
	HOST_CR0                        = 0x00006c00,
	HOST_CR3                        = 0x00006c02,
	HOST_CR4                        = 0x00006c04,
	HOST_FS_BASE                    = 0x00006c06,
	HOST_GS_BASE                    = 0x00006c08,
	HOST_TR_BASE                    = 0x00006c0a,
	HOST_GDTR_BASE                  = 0x00006c0c,
	HOST_IDTR_BASE                  = 0x00006c0e,
	HOST_IA32_SYSENTER_ESP          = 0x00006c10,
	HOST_IA32_SYSENTER_EIP          = 0x00006c12,
	HOST_RSP                        = 0x00006c14,
	HOST_RIP                        = 0x00006c16,
};

#define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000

#define EXIT_REASON_EXCEPTION_NMI       0
#define EXIT_REASON_EXTERNAL_INTERRUPT  1
#define EXIT_REASON_TRIPLE_FAULT        2

#define EXIT_REASON_PENDING_INTERRUPT   7
#define EXIT_REASON_NMI_WINDOW		8
#define EXIT_REASON_TASK_SWITCH         9
#define EXIT_REASON_CPUID               10
#define EXIT_REASON_HLT                 12
#define EXIT_REASON_INVLPG              14
#define EXIT_REASON_RDPMC               15
#define EXIT_REASON_RDTSC               16
#define EXIT_REASON_VMCALL              18
#define EXIT_REASON_VMCLEAR             19
#define EXIT_REASON_VMLAUNCH            20
#define EXIT_REASON_VMPTRLD             21
#define EXIT_REASON_VMPTRST             22
#define EXIT_REASON_VMREAD              23
#define EXIT_REASON_VMRESUME            24
#define EXIT_REASON_VMWRITE             25
#define EXIT_REASON_VMOFF               26
#define EXIT_REASON_VMON                27
#define EXIT_REASON_CR_ACCESS           28
#define EXIT_REASON_DR_ACCESS           29
#define EXIT_REASON_IO_INSTRUCTION      30
#define EXIT_REASON_MSR_READ            31
#define EXIT_REASON_MSR_WRITE           32
#define EXIT_REASON_MWAIT_INSTRUCTION   36
#define EXIT_REASON_MCE_DURING_VMENTRY	 41
#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
#define EXIT_REASON_APIC_ACCESS         44
#define EXIT_REASON_EPT_VIOLATION       48
#define EXIT_REASON_EPT_MISCONFIG       49
#define EXIT_REASON_WBINVD		54

/*
 * Interruption-information format
 */
#define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
#define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
#define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
#define INTR_INFO_UNBLOCK_NMI		0x1000		/* 12 */
#define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
#define INTR_INFO_RESVD_BITS_MASK       0x7ffff000

#define VECTORING_INFO_VECTOR_MASK           	INTR_INFO_VECTOR_MASK
#define VECTORING_INFO_TYPE_MASK        	INTR_INFO_INTR_TYPE_MASK
#define VECTORING_INFO_DELIVER_CODE_MASK    	INTR_INFO_DELIVER_CODE_MASK
#define VECTORING_INFO_VALID_MASK       	INTR_INFO_VALID_MASK

#define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
#define INTR_TYPE_NMI_INTR		(2 << 8) /* NMI */
#define INTR_TYPE_HARD_EXCEPTION	(3 << 8) /* processor exception */
#define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
#define INTR_TYPE_SOFT_EXCEPTION	(6 << 8) /* software exception */

/* GUEST_INTERRUPTIBILITY_INFO flags. */
#define GUEST_INTR_STATE_STI		0x00000001
#define GUEST_INTR_STATE_MOV_SS		0x00000002
#define GUEST_INTR_STATE_SMI		0x00000004
#define GUEST_INTR_STATE_NMI		0x00000008

/*
 * Exit Qualifications for MOV for Control Register Access
 */
#define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
#define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
#define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
#define LMSW_SOURCE_DATA_SHIFT 16
#define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
#define REG_EAX                         (0 << 8)
#define REG_ECX                         (1 << 8)
#define REG_EDX                         (2 << 8)
#define REG_EBX                         (3 << 8)
#define REG_ESP                         (4 << 8)
#define REG_EBP                         (5 << 8)
#define REG_ESI                         (6 << 8)
#define REG_EDI                         (7 << 8)
#define REG_R8                         (8 << 8)
#define REG_R9                         (9 << 8)
#define REG_R10                        (10 << 8)
#define REG_R11                        (11 << 8)
#define REG_R12                        (12 << 8)
#define REG_R13                        (13 << 8)
#define REG_R14                        (14 << 8)
#define REG_R15                        (15 << 8)

/*
 * Exit Qualifications for MOV for Debug Register Access
 */
#define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
#define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
#define TYPE_MOV_TO_DR                  (0 << 4)
#define TYPE_MOV_FROM_DR                (1 << 4)
#define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */


/* segment AR */
#define SEGMENT_AR_L_MASK (1 << 13)

#define AR_TYPE_ACCESSES_MASK 1
#define AR_TYPE_READABLE_MASK (1 << 1)
#define AR_TYPE_WRITEABLE_MASK (1 << 2)
#define AR_TYPE_CODE_MASK (1 << 3)
#define AR_TYPE_MASK 0x0f
#define AR_TYPE_BUSY_64_TSS 11
#define AR_TYPE_BUSY_32_TSS 11
#define AR_TYPE_BUSY_16_TSS 3
#define AR_TYPE_LDT 2

#define AR_UNUSABLE_MASK (1 << 16)
#define AR_S_MASK (1 << 4)
#define AR_P_MASK (1 << 7)
#define AR_L_MASK (1 << 13)
#define AR_DB_MASK (1 << 14)
#define AR_G_MASK (1 << 15)
#define AR_DPL_SHIFT 5
#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)

#define AR_RESERVD_MASK 0xfffe0f00

#define TSS_PRIVATE_MEMSLOT			(KVM_MEMORY_SLOTS + 0)
#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT	(KVM_MEMORY_SLOTS + 1)
#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT	(KVM_MEMORY_SLOTS + 2)

#define VMX_NR_VPIDS				(1 << 16)
#define VMX_VPID_EXTENT_SINGLE_CONTEXT		1
#define VMX_VPID_EXTENT_ALL_CONTEXT		2

#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR		0
#define VMX_EPT_EXTENT_CONTEXT			1
#define VMX_EPT_EXTENT_GLOBAL			2

#define VMX_EPT_EXECUTE_ONLY_BIT		(1ull)
#define VMX_EPT_PAGE_WALK_4_BIT			(1ull << 6)
#define VMX_EPTP_UC_BIT				(1ull << 8)
#define VMX_EPTP_WB_BIT				(1ull << 14)
#define VMX_EPT_2MB_PAGE_BIT			(1ull << 16)
#define VMX_EPT_EXTENT_INDIVIDUAL_BIT		(1ull << 24)
#define VMX_EPT_EXTENT_CONTEXT_BIT		(1ull << 25)
#define VMX_EPT_EXTENT_GLOBAL_BIT		(1ull << 26)

#define VMX_EPT_DEFAULT_GAW			3
#define VMX_EPT_MAX_GAW				0x4
#define VMX_EPT_MT_EPTE_SHIFT			3
#define VMX_EPT_GAW_EPTP_SHIFT			3
#define VMX_EPT_DEFAULT_MT			0x6ull
#define VMX_EPT_READABLE_MASK			0x1ull
#define VMX_EPT_WRITABLE_MASK			0x2ull
#define VMX_EPT_EXECUTABLE_MASK			0x4ull
#define VMX_EPT_IGMT_BIT    			(1ull << 6)

#define VMX_EPT_IDENTITY_PAGETABLE_ADDR		0xfffbc000ul


#define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
#define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
#define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
#define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
#define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
#define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
#define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
#define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
#define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
#define ASM_VMX_INVEPT		  ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
#define ASM_VMX_INVVPID		  ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"


#endif
Commit	Line	Data
6aa8b732 AK	1	#ifndef VMX_H
	2	#define VMX_H
	3
	4	/*
	5	* vmx.h: VMX Architecture related definitions
	6	* Copyright (c) 2004, Intel Corporation.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	19	* Place - Suite 330, Boston, MA 02111-1307 USA.
	20	*
	21	* A few random additions are:
	22	* Copyright (C) 2006 Qumranet
	23	* Avi Kivity <avi@qumranet.com>
	24	* Yaniv Kamay <yaniv@qumranet.com>
	25	*
	26	*/
	27
8a70cc3d ED	28	/*
	29	* Definitions of Primary Processor-Based VM-Execution Controls.
	30	*/
62b3ffb8 YS	31	#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
	32	#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
	33	#define CPU_BASED_HLT_EXITING 0x00000080
	34	#define CPU_BASED_INVLPG_EXITING 0x00000200
	35	#define CPU_BASED_MWAIT_EXITING 0x00000400
	36	#define CPU_BASED_RDPMC_EXITING 0x00000800
	37	#define CPU_BASED_RDTSC_EXITING 0x00001000
d56f546d SY	38	#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
d56f546d SY	39	#define CPU_BASED_CR3_STORE_EXITING 0x00010000
62b3ffb8 YS	40	#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
	41	#define CPU_BASED_CR8_STORE_EXITING 0x00100000
	42	#define CPU_BASED_TPR_SHADOW 0x00200000
f08864b4	43	#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
62b3ffb8 YS	44	#define CPU_BASED_MOV_DR_EXITING 0x00800000
	45	#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
	46	#define CPU_BASED_USE_IO_BITMAPS 0x02000000
	47	#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
	48	#define CPU_BASED_MONITOR_EXITING 0x20000000
	49	#define CPU_BASED_PAUSE_EXITING 0x40000000
	50	#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
8a70cc3d ED	51	/*
	52	* Definitions of Secondary Processor-Based VM-Execution Controls.
	53	*/
	54	#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
d56f546d	55	#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
2384d2b3	56	#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
e5edaa01	57	#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
3a624e29	58	#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
8a70cc3d	59
6aa8b732	60
62b3ffb8 YS	61	#define PIN_BASED_EXT_INTR_MASK 0x00000001
	62	#define PIN_BASED_NMI_EXITING 0x00000008
	63	#define PIN_BASED_VIRTUAL_NMIS 0x00000020
6aa8b732	64
62b3ffb8 YS	65	#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
62b3ffb8 YS	66	#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
468d472f SY	67	#define VM_EXIT_SAVE_IA32_PAT 0x00040000
468d472f SY	68	#define VM_EXIT_LOAD_IA32_PAT 0x00080000
6aa8b732	69
62b3ffb8 YS	70	#define VM_ENTRY_IA32E_MODE 0x00000200
	71	#define VM_ENTRY_SMM 0x00000400
	72	#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
468d472f	73	#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
62b3ffb8	74
6aa8b732 AK	75	/* VMCS Encodings */
6aa8b732 AK	76	enum vmcs_field {
2384d2b3	77	VIRTUAL_PROCESSOR_ID = 0x00000000,
6aa8b732 AK	78	GUEST_ES_SELECTOR = 0x00000800,
	79	GUEST_CS_SELECTOR = 0x00000802,
	80	GUEST_SS_SELECTOR = 0x00000804,
	81	GUEST_DS_SELECTOR = 0x00000806,
	82	GUEST_FS_SELECTOR = 0x00000808,
	83	GUEST_GS_SELECTOR = 0x0000080a,
	84	GUEST_LDTR_SELECTOR = 0x0000080c,
	85	GUEST_TR_SELECTOR = 0x0000080e,
	86	HOST_ES_SELECTOR = 0x00000c00,
	87	HOST_CS_SELECTOR = 0x00000c02,
	88	HOST_SS_SELECTOR = 0x00000c04,
	89	HOST_DS_SELECTOR = 0x00000c06,
	90	HOST_FS_SELECTOR = 0x00000c08,
	91	HOST_GS_SELECTOR = 0x00000c0a,
	92	HOST_TR_SELECTOR = 0x00000c0c,
	93	IO_BITMAP_A = 0x00002000,
	94	IO_BITMAP_A_HIGH = 0x00002001,
	95	IO_BITMAP_B = 0x00002002,
	96	IO_BITMAP_B_HIGH = 0x00002003,
	97	MSR_BITMAP = 0x00002004,
	98	MSR_BITMAP_HIGH = 0x00002005,
	99	VM_EXIT_MSR_STORE_ADDR = 0x00002006,
	100	VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
	101	VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
	102	VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
	103	VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
	104	VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
	105	TSC_OFFSET = 0x00002010,
	106	TSC_OFFSET_HIGH = 0x00002011,
	107	VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
	108	VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
f78e0e2e SY	109	APIC_ACCESS_ADDR = 0x00002014,
f78e0e2e SY	110	APIC_ACCESS_ADDR_HIGH = 0x00002015,
d56f546d SY	111	EPT_POINTER = 0x0000201a,
	112	EPT_POINTER_HIGH = 0x0000201b,
	113	GUEST_PHYSICAL_ADDRESS = 0x00002400,
	114	GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
6aa8b732 AK	115	VMCS_LINK_POINTER = 0x00002800,
	116	VMCS_LINK_POINTER_HIGH = 0x00002801,
	117	GUEST_IA32_DEBUGCTL = 0x00002802,
	118	GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
468d472f SY	119	GUEST_IA32_PAT = 0x00002804,
468d472f SY	120	GUEST_IA32_PAT_HIGH = 0x00002805,
d56f546d SY	121	GUEST_PDPTR0 = 0x0000280a,
	122	GUEST_PDPTR0_HIGH = 0x0000280b,
	123	GUEST_PDPTR1 = 0x0000280c,
	124	GUEST_PDPTR1_HIGH = 0x0000280d,
	125	GUEST_PDPTR2 = 0x0000280e,
	126	GUEST_PDPTR2_HIGH = 0x0000280f,
	127	GUEST_PDPTR3 = 0x00002810,
	128	GUEST_PDPTR3_HIGH = 0x00002811,
468d472f SY	129	HOST_IA32_PAT = 0x00002c00,
468d472f SY	130	HOST_IA32_PAT_HIGH = 0x00002c01,
6aa8b732 AK	131	PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
	132	CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
	133	EXCEPTION_BITMAP = 0x00004004,
	134	PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
	135	PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
	136	CR3_TARGET_COUNT = 0x0000400a,
	137	VM_EXIT_CONTROLS = 0x0000400c,
	138	VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
	139	VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
	140	VM_ENTRY_CONTROLS = 0x00004012,
	141	VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
	142	VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
	143	VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
	144	VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
	145	TPR_THRESHOLD = 0x0000401c,
	146	SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
	147	VM_INSTRUCTION_ERROR = 0x00004400,
	148	VM_EXIT_REASON = 0x00004402,
	149	VM_EXIT_INTR_INFO = 0x00004404,
	150	VM_EXIT_INTR_ERROR_CODE = 0x00004406,
	151	IDT_VECTORING_INFO_FIELD = 0x00004408,
	152	IDT_VECTORING_ERROR_CODE = 0x0000440a,
	153	VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
	154	VMX_INSTRUCTION_INFO = 0x0000440e,
	155	GUEST_ES_LIMIT = 0x00004800,
	156	GUEST_CS_LIMIT = 0x00004802,
	157	GUEST_SS_LIMIT = 0x00004804,
	158	GUEST_DS_LIMIT = 0x00004806,
	159	GUEST_FS_LIMIT = 0x00004808,
	160	GUEST_GS_LIMIT = 0x0000480a,
	161	GUEST_LDTR_LIMIT = 0x0000480c,
	162	GUEST_TR_LIMIT = 0x0000480e,
	163	GUEST_GDTR_LIMIT = 0x00004810,
	164	GUEST_IDTR_LIMIT = 0x00004812,
	165	GUEST_ES_AR_BYTES = 0x00004814,
	166	GUEST_CS_AR_BYTES = 0x00004816,
	167	GUEST_SS_AR_BYTES = 0x00004818,
	168	GUEST_DS_AR_BYTES = 0x0000481a,
	169	GUEST_FS_AR_BYTES = 0x0000481c,
	170	GUEST_GS_AR_BYTES = 0x0000481e,
	171	GUEST_LDTR_AR_BYTES = 0x00004820,
	172	GUEST_TR_AR_BYTES = 0x00004822,
	173	GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
	174	GUEST_ACTIVITY_STATE = 0X00004826,
	175	GUEST_SYSENTER_CS = 0x0000482A,
	176	HOST_IA32_SYSENTER_CS = 0x00004c00,
	177	CR0_GUEST_HOST_MASK = 0x00006000,
	178	CR4_GUEST_HOST_MASK = 0x00006002,
	179	CR0_READ_SHADOW = 0x00006004,
	180	CR4_READ_SHADOW = 0x00006006,
	181	CR3_TARGET_VALUE0 = 0x00006008,
	182	CR3_TARGET_VALUE1 = 0x0000600a,
	183	CR3_TARGET_VALUE2 = 0x0000600c,
	184	CR3_TARGET_VALUE3 = 0x0000600e,
	185	EXIT_QUALIFICATION = 0x00006400,
	186	GUEST_LINEAR_ADDRESS = 0x0000640a,
	187	GUEST_CR0 = 0x00006800,
	188	GUEST_CR3 = 0x00006802,
	189	GUEST_CR4 = 0x00006804,
	190	GUEST_ES_BASE = 0x00006806,
	191	GUEST_CS_BASE = 0x00006808,
	192	GUEST_SS_BASE = 0x0000680a,
	193	GUEST_DS_BASE = 0x0000680c,
	194	GUEST_FS_BASE = 0x0000680e,
195	GUEST_GS_BASE = 0x00006810,
196	GUEST_LDTR_BASE = 0x00006812,
197	GUEST_TR_BASE = 0x00006814,
198	GUEST_GDTR_BASE = 0x00006816,
199	GUEST_IDTR_BASE = 0x00006818,
200	GUEST_DR7 = 0x0000681a,
201	GUEST_RSP = 0x0000681c,
202	GUEST_RIP = 0x0000681e,
203	GUEST_RFLAGS = 0x00006820,
204	GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
205	GUEST_SYSENTER_ESP = 0x00006824,
206	GUEST_SYSENTER_EIP = 0x00006826,
207	HOST_CR0 = 0x00006c00,
208	HOST_CR3 = 0x00006c02,
209	HOST_CR4 = 0x00006c04,
210	HOST_FS_BASE = 0x00006c06,
211	HOST_GS_BASE = 0x00006c08,
212	HOST_TR_BASE = 0x00006c0a,
213	HOST_GDTR_BASE = 0x00006c0c,
214	HOST_IDTR_BASE = 0x00006c0e,
215	HOST_IA32_SYSENTER_ESP = 0x00006c10,
216	HOST_IA32_SYSENTER_EIP = 0x00006c12,
217	HOST_RSP = 0x00006c14,
218	HOST_RIP = 0x00006c16,
219	};
220
221	#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
222
223	#define EXIT_REASON_EXCEPTION_NMI 0
224	#define EXIT_REASON_EXTERNAL_INTERRUPT 1
988ad74f	225	#define EXIT_REASON_TRIPLE_FAULT 2
6aa8b732 AK	226
6aa8b732 AK	227	#define EXIT_REASON_PENDING_INTERRUPT 7
f08864b4	228	#define EXIT_REASON_NMI_WINDOW 8
6aa8b732 AK	229	#define EXIT_REASON_TASK_SWITCH 9
	230	#define EXIT_REASON_CPUID 10
	231	#define EXIT_REASON_HLT 12
	232	#define EXIT_REASON_INVLPG 14
	233	#define EXIT_REASON_RDPMC 15
	234	#define EXIT_REASON_RDTSC 16
	235	#define EXIT_REASON_VMCALL 18
	236	#define EXIT_REASON_VMCLEAR 19
	237	#define EXIT_REASON_VMLAUNCH 20
	238	#define EXIT_REASON_VMPTRLD 21
	239	#define EXIT_REASON_VMPTRST 22
	240	#define EXIT_REASON_VMREAD 23
	241	#define EXIT_REASON_VMRESUME 24
	242	#define EXIT_REASON_VMWRITE 25
	243	#define EXIT_REASON_VMOFF 26
	244	#define EXIT_REASON_VMON 27
	245	#define EXIT_REASON_CR_ACCESS 28
	246	#define EXIT_REASON_DR_ACCESS 29
	247	#define EXIT_REASON_IO_INSTRUCTION 30
	248	#define EXIT_REASON_MSR_READ 31
	249	#define EXIT_REASON_MSR_WRITE 32
	250	#define EXIT_REASON_MWAIT_INSTRUCTION 36
a0861c02	251	#define EXIT_REASON_MCE_DURING_VMENTRY 41
6e5d865c	252	#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
f78e0e2e	253	#define EXIT_REASON_APIC_ACCESS 44
d56f546d SY	254	#define EXIT_REASON_EPT_VIOLATION 48
d56f546d SY	255	#define EXIT_REASON_EPT_MISCONFIG 49
e5edaa01	256	#define EXIT_REASON_WBINVD 54
6aa8b732 AK	257
	258	/*
	259	* Interruption-information format
	260	*/
	261	#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
	262	#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
2e11384c	263	#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
f08864b4	264	#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
6aa8b732	265	#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
f08864b4	266	#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
6aa8b732 AK	267
	268	#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
	269	#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
2e11384c	270	#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
6aa8b732 AK	271	#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
	272
	273	#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
f08864b4	274	#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
8ab2d2e2	275	#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
9c5623e3	276	#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
8ab2d2e2	277	#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
6aa8b732	278
f08864b4 SY	279	/* GUEST_INTERRUPTIBILITY_INFO flags. */
	280	#define GUEST_INTR_STATE_STI 0x00000001
	281	#define GUEST_INTR_STATE_MOV_SS 0x00000002
	282	#define GUEST_INTR_STATE_SMI 0x00000004
	283	#define GUEST_INTR_STATE_NMI 0x00000008
	284
6aa8b732 AK	285	/*
	286	* Exit Qualifications for MOV for Control Register Access
	287	*/
d77c26fc	288	#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
6aa8b732	289	#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
d77c26fc	290	#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
6aa8b732 AK	291	#define LMSW_SOURCE_DATA_SHIFT 16
	292	#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
	293	#define REG_EAX (0 << 8)
	294	#define REG_ECX (1 << 8)
	295	#define REG_EDX (2 << 8)
	296	#define REG_EBX (3 << 8)
	297	#define REG_ESP (4 << 8)
	298	#define REG_EBP (5 << 8)
	299	#define REG_ESI (6 << 8)
	300	#define REG_EDI (7 << 8)
	301	#define REG_R8 (8 << 8)
	302	#define REG_R9 (9 << 8)
	303	#define REG_R10 (10 << 8)
	304	#define REG_R11 (11 << 8)
	305	#define REG_R12 (12 << 8)
	306	#define REG_R13 (13 << 8)
	307	#define REG_R14 (14 << 8)
	308	#define REG_R15 (15 << 8)
	309
	310	/*
	311	* Exit Qualifications for MOV for Debug Register Access
	312	*/
d77c26fc	313	#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
6aa8b732 AK	314	#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
	315	#define TYPE_MOV_TO_DR (0 << 4)
	316	#define TYPE_MOV_FROM_DR (1 << 4)
42dbaa5a	317	#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
6aa8b732 AK	318
	319
	320	/* segment AR */
	321	#define SEGMENT_AR_L_MASK (1 << 13)
	322
6aa8b732 AK	323	#define AR_TYPE_ACCESSES_MASK 1
	324	#define AR_TYPE_READABLE_MASK (1 << 1)
	325	#define AR_TYPE_WRITEABLE_MASK (1 << 2)
	326	#define AR_TYPE_CODE_MASK (1 << 3)
	327	#define AR_TYPE_MASK 0x0f
	328	#define AR_TYPE_BUSY_64_TSS 11
	329	#define AR_TYPE_BUSY_32_TSS 11
	330	#define AR_TYPE_BUSY_16_TSS 3
	331	#define AR_TYPE_LDT 2
	332
	333	#define AR_UNUSABLE_MASK (1 << 16)
	334	#define AR_S_MASK (1 << 4)
	335	#define AR_P_MASK (1 << 7)
	336	#define AR_L_MASK (1 << 13)
	337	#define AR_DB_MASK (1 << 14)
	338	#define AR_G_MASK (1 << 15)
	339	#define AR_DPL_SHIFT 5
	340	#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
	341
	342	#define AR_RESERVD_MASK 0xfffe0f00
	343
6fe63979 SY	344	#define TSS_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 0)
	345	#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 1)
	346	#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_MEMORY_SLOTS + 2)
f78e0e2e	347
2384d2b3 SY	348	#define VMX_NR_VPIDS (1 << 16)
	349	#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
	350	#define VMX_VPID_EXTENT_ALL_CONTEXT 2
	351
d56f546d SY	352	#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
	353	#define VMX_EPT_EXTENT_CONTEXT 1
	354	#define VMX_EPT_EXTENT_GLOBAL 2
e799794e MT	355
	356	#define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
	357	#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
	358	#define VMX_EPTP_UC_BIT (1ull << 8)
	359	#define VMX_EPTP_WB_BIT (1ull << 14)
	360	#define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
d56f546d SY	361	#define VMX_EPT_EXTENT_INDIVIDUAL_BIT (1ull << 24)
	362	#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
	363	#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
e799794e	364
67253af5	365	#define VMX_EPT_DEFAULT_GAW 3
1439442c SY	366	#define VMX_EPT_MAX_GAW 0x4
	367	#define VMX_EPT_MT_EPTE_SHIFT 3
	368	#define VMX_EPT_GAW_EPTP_SHIFT 3
	369	#define VMX_EPT_DEFAULT_MT 0x6ull
	370	#define VMX_EPT_READABLE_MASK 0x1ull
	371	#define VMX_EPT_WRITABLE_MASK 0x2ull
	372	#define VMX_EPT_EXECUTABLE_MASK 0x4ull
928d4bf7	373	#define VMX_EPT_IGMT_BIT (1ull << 6)
d56f546d	374
b7ebfb05 SY	375	#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
b7ebfb05 SY	376
eca70fc5 EH	377
	378	#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
	379	#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
	380	#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
	381	#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
	382	#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
	383	#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
	384	#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
	385	#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
	386	#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
	387	#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
	388	#define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
	389
	390
	391
6aa8b732	392	#endif