Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 JR |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/iommu-helper.h> | |
c156e347 JR |
26 | #ifdef CONFIG_IOMMU_API |
27 | #include <linux/iommu.h> | |
28 | #endif | |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
26961efe JR |
45 | #ifdef CONFIG_IOMMU_API |
46 | static struct iommu_ops amd_iommu_ops; | |
47 | #endif | |
48 | ||
431b2a20 JR |
49 | /* |
50 | * general struct to manage commands send to an IOMMU | |
51 | */ | |
d6449536 | 52 | struct iommu_cmd { |
b6c02715 JR |
53 | u32 data[4]; |
54 | }; | |
55 | ||
bd0e5211 JR |
56 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
57 | struct unity_map_entry *e); | |
e275a2a0 JR |
58 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
59 | ||
bd0e5211 | 60 | |
7f26508b JR |
61 | #ifdef CONFIG_AMD_IOMMU_STATS |
62 | ||
63 | /* | |
64 | * Initialization code for statistics collection | |
65 | */ | |
66 | ||
da49f6df | 67 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 68 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 69 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
da49f6df | 70 | |
7f26508b JR |
71 | static struct dentry *stats_dir; |
72 | static struct dentry *de_isolate; | |
73 | static struct dentry *de_fflush; | |
74 | ||
75 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
76 | { | |
77 | if (stats_dir == NULL) | |
78 | return; | |
79 | ||
80 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
81 | &cnt->value); | |
82 | } | |
83 | ||
84 | static void amd_iommu_stats_init(void) | |
85 | { | |
86 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
87 | if (stats_dir == NULL) | |
88 | return; | |
89 | ||
90 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
91 | (u32 *)&amd_iommu_isolate); | |
92 | ||
93 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
94 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
95 | |
96 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 97 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 98 | amd_iommu_stats_add(&cnt_unmap_single); |
7f26508b JR |
99 | } |
100 | ||
101 | #endif | |
102 | ||
431b2a20 | 103 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
104 | static int iommu_has_npcache(struct amd_iommu *iommu) |
105 | { | |
ae9b9403 | 106 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
107 | } |
108 | ||
a80dc3e0 JR |
109 | /**************************************************************************** |
110 | * | |
111 | * Interrupt handling functions | |
112 | * | |
113 | ****************************************************************************/ | |
114 | ||
90008ee4 JR |
115 | static void iommu_print_event(void *__evt) |
116 | { | |
117 | u32 *event = __evt; | |
118 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
119 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
120 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
121 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
122 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
123 | ||
124 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
125 | ||
126 | switch (type) { | |
127 | case EVENT_TYPE_ILL_DEV: | |
128 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
129 | "address=0x%016llx flags=0x%04x]\n", | |
130 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
131 | address, flags); | |
132 | break; | |
133 | case EVENT_TYPE_IO_FAULT: | |
134 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
135 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
136 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
137 | domid, address, flags); | |
138 | break; | |
139 | case EVENT_TYPE_DEV_TAB_ERR: | |
140 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
141 | "address=0x%016llx flags=0x%04x]\n", | |
142 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
143 | address, flags); | |
144 | break; | |
145 | case EVENT_TYPE_PAGE_TAB_ERR: | |
146 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
147 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
148 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
149 | domid, address, flags); | |
150 | break; | |
151 | case EVENT_TYPE_ILL_CMD: | |
152 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
153 | break; | |
154 | case EVENT_TYPE_CMD_HARD_ERR: | |
155 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
156 | "flags=0x%04x]\n", address, flags); | |
157 | break; | |
158 | case EVENT_TYPE_IOTLB_INV_TO: | |
159 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
160 | "address=0x%016llx]\n", | |
161 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
162 | address); | |
163 | break; | |
164 | case EVENT_TYPE_INV_DEV_REQ: | |
165 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
166 | "address=0x%016llx flags=0x%04x]\n", | |
167 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
168 | address, flags); | |
169 | break; | |
170 | default: | |
171 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
172 | } | |
173 | } | |
174 | ||
175 | static void iommu_poll_events(struct amd_iommu *iommu) | |
176 | { | |
177 | u32 head, tail; | |
178 | unsigned long flags; | |
179 | ||
180 | spin_lock_irqsave(&iommu->lock, flags); | |
181 | ||
182 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
183 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
184 | ||
185 | while (head != tail) { | |
186 | iommu_print_event(iommu->evt_buf + head); | |
187 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
188 | } | |
189 | ||
190 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
191 | ||
192 | spin_unlock_irqrestore(&iommu->lock, flags); | |
193 | } | |
194 | ||
a80dc3e0 JR |
195 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
196 | { | |
90008ee4 JR |
197 | struct amd_iommu *iommu; |
198 | ||
199 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
200 | iommu_poll_events(iommu); | |
201 | ||
202 | return IRQ_HANDLED; | |
a80dc3e0 JR |
203 | } |
204 | ||
431b2a20 JR |
205 | /**************************************************************************** |
206 | * | |
207 | * IOMMU command queuing functions | |
208 | * | |
209 | ****************************************************************************/ | |
210 | ||
211 | /* | |
212 | * Writes the command to the IOMMUs command buffer and informs the | |
213 | * hardware about the new command. Must be called with iommu->lock held. | |
214 | */ | |
d6449536 | 215 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
216 | { |
217 | u32 tail, head; | |
218 | u8 *target; | |
219 | ||
220 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 221 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
222 | memcpy_toio(target, cmd, sizeof(*cmd)); |
223 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
224 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
225 | if (tail == head) | |
226 | return -ENOMEM; | |
227 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
431b2a20 JR |
232 | /* |
233 | * General queuing function for commands. Takes iommu->lock and calls | |
234 | * __iommu_queue_command(). | |
235 | */ | |
d6449536 | 236 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
237 | { |
238 | unsigned long flags; | |
239 | int ret; | |
240 | ||
241 | spin_lock_irqsave(&iommu->lock, flags); | |
242 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 243 | if (!ret) |
0cfd7aa9 | 244 | iommu->need_sync = true; |
a19ae1ec JR |
245 | spin_unlock_irqrestore(&iommu->lock, flags); |
246 | ||
247 | return ret; | |
248 | } | |
249 | ||
8d201968 JR |
250 | /* |
251 | * This function waits until an IOMMU has completed a completion | |
252 | * wait command | |
253 | */ | |
254 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
255 | { | |
256 | int ready = 0; | |
257 | unsigned status = 0; | |
258 | unsigned long i = 0; | |
259 | ||
da49f6df JR |
260 | INC_STATS_COUNTER(compl_wait); |
261 | ||
8d201968 JR |
262 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
263 | ++i; | |
264 | /* wait for the bit to become one */ | |
265 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
266 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
267 | } | |
268 | ||
269 | /* set bit back to zero */ | |
270 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
271 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
272 | ||
273 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
274 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
275 | } | |
276 | ||
277 | /* | |
278 | * This function queues a completion wait command into the command | |
279 | * buffer of an IOMMU | |
280 | */ | |
281 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
282 | { | |
283 | struct iommu_cmd cmd; | |
284 | ||
285 | memset(&cmd, 0, sizeof(cmd)); | |
286 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
287 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
288 | ||
289 | return __iommu_queue_command(iommu, &cmd); | |
290 | } | |
291 | ||
431b2a20 JR |
292 | /* |
293 | * This function is called whenever we need to ensure that the IOMMU has | |
294 | * completed execution of all commands we sent. It sends a | |
295 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
296 | * us about that by writing a value to a physical address we pass with | |
297 | * the command. | |
298 | */ | |
a19ae1ec JR |
299 | static int iommu_completion_wait(struct amd_iommu *iommu) |
300 | { | |
8d201968 JR |
301 | int ret = 0; |
302 | unsigned long flags; | |
a19ae1ec | 303 | |
7e4f88da JR |
304 | spin_lock_irqsave(&iommu->lock, flags); |
305 | ||
09ee17eb JR |
306 | if (!iommu->need_sync) |
307 | goto out; | |
308 | ||
8d201968 | 309 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 310 | |
0cfd7aa9 | 311 | iommu->need_sync = false; |
a19ae1ec JR |
312 | |
313 | if (ret) | |
7e4f88da | 314 | goto out; |
a19ae1ec | 315 | |
8d201968 | 316 | __iommu_wait_for_completion(iommu); |
84df8175 | 317 | |
7e4f88da JR |
318 | out: |
319 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
431b2a20 JR |
324 | /* |
325 | * Command send function for invalidating a device table entry | |
326 | */ | |
a19ae1ec JR |
327 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
328 | { | |
d6449536 | 329 | struct iommu_cmd cmd; |
ee2fa743 | 330 | int ret; |
a19ae1ec JR |
331 | |
332 | BUG_ON(iommu == NULL); | |
333 | ||
334 | memset(&cmd, 0, sizeof(cmd)); | |
335 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
336 | cmd.data[0] = devid; | |
337 | ||
ee2fa743 JR |
338 | ret = iommu_queue_command(iommu, &cmd); |
339 | ||
ee2fa743 | 340 | return ret; |
a19ae1ec JR |
341 | } |
342 | ||
237b6f33 JR |
343 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
344 | u16 domid, int pde, int s) | |
345 | { | |
346 | memset(cmd, 0, sizeof(*cmd)); | |
347 | address &= PAGE_MASK; | |
348 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
349 | cmd->data[1] |= domid; | |
350 | cmd->data[2] = lower_32_bits(address); | |
351 | cmd->data[3] = upper_32_bits(address); | |
352 | if (s) /* size bit - we flush more than one 4kb page */ | |
353 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
354 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
355 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
356 | } | |
357 | ||
431b2a20 JR |
358 | /* |
359 | * Generic command send function for invalidaing TLB entries | |
360 | */ | |
a19ae1ec JR |
361 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
362 | u64 address, u16 domid, int pde, int s) | |
363 | { | |
d6449536 | 364 | struct iommu_cmd cmd; |
ee2fa743 | 365 | int ret; |
a19ae1ec | 366 | |
237b6f33 | 367 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 368 | |
ee2fa743 JR |
369 | ret = iommu_queue_command(iommu, &cmd); |
370 | ||
ee2fa743 | 371 | return ret; |
a19ae1ec JR |
372 | } |
373 | ||
431b2a20 JR |
374 | /* |
375 | * TLB invalidation function which is called from the mapping functions. | |
376 | * It invalidates a single PTE if the range to flush is within a single | |
377 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
378 | */ | |
a19ae1ec JR |
379 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
380 | u64 address, size_t size) | |
381 | { | |
999ba417 | 382 | int s = 0; |
e3c449f5 | 383 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
384 | |
385 | address &= PAGE_MASK; | |
386 | ||
999ba417 JR |
387 | if (pages > 1) { |
388 | /* | |
389 | * If we have to flush more than one page, flush all | |
390 | * TLB entries for this domain | |
391 | */ | |
392 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
393 | s = 1; | |
a19ae1ec JR |
394 | } |
395 | ||
999ba417 JR |
396 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
397 | ||
a19ae1ec JR |
398 | return 0; |
399 | } | |
b6c02715 | 400 | |
1c655773 JR |
401 | /* Flush the whole IO/TLB for a given protection domain */ |
402 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
403 | { | |
404 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
405 | ||
406 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
407 | } | |
408 | ||
43f49609 JR |
409 | #ifdef CONFIG_IOMMU_API |
410 | /* | |
411 | * This function is used to flush the IO/TLB for a given protection domain | |
412 | * on every IOMMU in the system | |
413 | */ | |
414 | static void iommu_flush_domain(u16 domid) | |
415 | { | |
416 | unsigned long flags; | |
417 | struct amd_iommu *iommu; | |
418 | struct iommu_cmd cmd; | |
419 | ||
420 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
421 | domid, 1, 1); | |
422 | ||
423 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
424 | spin_lock_irqsave(&iommu->lock, flags); | |
425 | __iommu_queue_command(iommu, &cmd); | |
426 | __iommu_completion_wait(iommu); | |
427 | __iommu_wait_for_completion(iommu); | |
428 | spin_unlock_irqrestore(&iommu->lock, flags); | |
429 | } | |
430 | } | |
431 | #endif | |
432 | ||
431b2a20 JR |
433 | /**************************************************************************** |
434 | * | |
435 | * The functions below are used the create the page table mappings for | |
436 | * unity mapped regions. | |
437 | * | |
438 | ****************************************************************************/ | |
439 | ||
440 | /* | |
441 | * Generic mapping functions. It maps a physical address into a DMA | |
442 | * address space. It allocates the page table pages if necessary. | |
443 | * In the future it can be extended to a generic mapping function | |
444 | * supporting all features of AMD IOMMU page tables like level skipping | |
445 | * and full 64 bit address spaces. | |
446 | */ | |
38e817fe JR |
447 | static int iommu_map_page(struct protection_domain *dom, |
448 | unsigned long bus_addr, | |
449 | unsigned long phys_addr, | |
450 | int prot) | |
bd0e5211 JR |
451 | { |
452 | u64 __pte, *pte, *page; | |
453 | ||
454 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 455 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
456 | |
457 | /* only support 512GB address spaces for now */ | |
458 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
459 | return -EINVAL; | |
460 | ||
461 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
462 | ||
463 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
464 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
465 | if (!page) | |
466 | return -ENOMEM; | |
467 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
468 | } | |
469 | ||
470 | pte = IOMMU_PTE_PAGE(*pte); | |
471 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
472 | ||
473 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
474 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
475 | if (!page) | |
476 | return -ENOMEM; | |
477 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
478 | } | |
479 | ||
480 | pte = IOMMU_PTE_PAGE(*pte); | |
481 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
482 | ||
483 | if (IOMMU_PTE_PRESENT(*pte)) | |
484 | return -EBUSY; | |
485 | ||
486 | __pte = phys_addr | IOMMU_PTE_P; | |
487 | if (prot & IOMMU_PROT_IR) | |
488 | __pte |= IOMMU_PTE_IR; | |
489 | if (prot & IOMMU_PROT_IW) | |
490 | __pte |= IOMMU_PTE_IW; | |
491 | ||
492 | *pte = __pte; | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
eb74ff6c JR |
497 | #ifdef CONFIG_IOMMU_API |
498 | static void iommu_unmap_page(struct protection_domain *dom, | |
499 | unsigned long bus_addr) | |
500 | { | |
501 | u64 *pte; | |
502 | ||
503 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
504 | ||
505 | if (!IOMMU_PTE_PRESENT(*pte)) | |
506 | return; | |
507 | ||
508 | pte = IOMMU_PTE_PAGE(*pte); | |
509 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
510 | ||
511 | if (!IOMMU_PTE_PRESENT(*pte)) | |
512 | return; | |
513 | ||
514 | pte = IOMMU_PTE_PAGE(*pte); | |
515 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
516 | ||
517 | *pte = 0; | |
518 | } | |
519 | #endif | |
520 | ||
431b2a20 JR |
521 | /* |
522 | * This function checks if a specific unity mapping entry is needed for | |
523 | * this specific IOMMU. | |
524 | */ | |
bd0e5211 JR |
525 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
526 | struct unity_map_entry *entry) | |
527 | { | |
528 | u16 bdf, i; | |
529 | ||
530 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
531 | bdf = amd_iommu_alias_table[i]; | |
532 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
533 | return 1; | |
534 | } | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
431b2a20 JR |
539 | /* |
540 | * Init the unity mappings for a specific IOMMU in the system | |
541 | * | |
542 | * Basically iterates over all unity mapping entries and applies them to | |
543 | * the default domain DMA of that IOMMU if necessary. | |
544 | */ | |
bd0e5211 JR |
545 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
546 | { | |
547 | struct unity_map_entry *entry; | |
548 | int ret; | |
549 | ||
550 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
551 | if (!iommu_for_unity_map(iommu, entry)) | |
552 | continue; | |
553 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
554 | if (ret) | |
555 | return ret; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
431b2a20 JR |
561 | /* |
562 | * This function actually applies the mapping to the page table of the | |
563 | * dma_ops domain. | |
564 | */ | |
bd0e5211 JR |
565 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
566 | struct unity_map_entry *e) | |
567 | { | |
568 | u64 addr; | |
569 | int ret; | |
570 | ||
571 | for (addr = e->address_start; addr < e->address_end; | |
572 | addr += PAGE_SIZE) { | |
38e817fe | 573 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
574 | if (ret) |
575 | return ret; | |
576 | /* | |
577 | * if unity mapping is in aperture range mark the page | |
578 | * as allocated in the aperture | |
579 | */ | |
580 | if (addr < dma_dom->aperture_size) | |
581 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
582 | } | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
431b2a20 JR |
587 | /* |
588 | * Inits the unity mappings required for a specific device | |
589 | */ | |
bd0e5211 JR |
590 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
591 | u16 devid) | |
592 | { | |
593 | struct unity_map_entry *e; | |
594 | int ret; | |
595 | ||
596 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
597 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
598 | continue; | |
599 | ret = dma_ops_unity_map(dma_dom, e); | |
600 | if (ret) | |
601 | return ret; | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
431b2a20 JR |
607 | /**************************************************************************** |
608 | * | |
609 | * The next functions belong to the address allocator for the dma_ops | |
610 | * interface functions. They work like the allocators in the other IOMMU | |
611 | * drivers. Its basically a bitmap which marks the allocated pages in | |
612 | * the aperture. Maybe it could be enhanced in the future to a more | |
613 | * efficient allocator. | |
614 | * | |
615 | ****************************************************************************/ | |
d3086444 | 616 | |
431b2a20 JR |
617 | /* |
618 | * The address allocator core function. | |
619 | * | |
620 | * called with domain->lock held | |
621 | */ | |
d3086444 JR |
622 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
623 | struct dma_ops_domain *dom, | |
6d4f343f | 624 | unsigned int pages, |
832a90c3 JR |
625 | unsigned long align_mask, |
626 | u64 dma_mask) | |
d3086444 | 627 | { |
40becd8d | 628 | unsigned long limit; |
d3086444 | 629 | unsigned long address; |
d3086444 JR |
630 | unsigned long boundary_size; |
631 | ||
632 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
633 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
634 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
635 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 636 | |
1c655773 | 637 | if (dom->next_bit >= limit) { |
d3086444 | 638 | dom->next_bit = 0; |
1c655773 JR |
639 | dom->need_flush = true; |
640 | } | |
d3086444 JR |
641 | |
642 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 643 | 0 , boundary_size, align_mask); |
1c655773 | 644 | if (address == -1) { |
d3086444 | 645 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 646 | 0, boundary_size, align_mask); |
1c655773 JR |
647 | dom->need_flush = true; |
648 | } | |
d3086444 JR |
649 | |
650 | if (likely(address != -1)) { | |
d3086444 JR |
651 | dom->next_bit = address + pages; |
652 | address <<= PAGE_SHIFT; | |
653 | } else | |
654 | address = bad_dma_address; | |
655 | ||
656 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
657 | ||
658 | return address; | |
659 | } | |
660 | ||
431b2a20 JR |
661 | /* |
662 | * The address free function. | |
663 | * | |
664 | * called with domain->lock held | |
665 | */ | |
d3086444 JR |
666 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
667 | unsigned long address, | |
668 | unsigned int pages) | |
669 | { | |
670 | address >>= PAGE_SHIFT; | |
671 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 672 | |
8501c45c | 673 | if (address >= dom->next_bit) |
80be308d | 674 | dom->need_flush = true; |
d3086444 JR |
675 | } |
676 | ||
431b2a20 JR |
677 | /**************************************************************************** |
678 | * | |
679 | * The next functions belong to the domain allocation. A domain is | |
680 | * allocated for every IOMMU as the default domain. If device isolation | |
681 | * is enabled, every device get its own domain. The most important thing | |
682 | * about domains is the page table mapping the DMA address space they | |
683 | * contain. | |
684 | * | |
685 | ****************************************************************************/ | |
686 | ||
ec487d1a JR |
687 | static u16 domain_id_alloc(void) |
688 | { | |
689 | unsigned long flags; | |
690 | int id; | |
691 | ||
692 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
693 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
694 | BUG_ON(id == 0); | |
695 | if (id > 0 && id < MAX_DOMAIN_ID) | |
696 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
697 | else | |
698 | id = 0; | |
699 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
700 | ||
701 | return id; | |
702 | } | |
703 | ||
a2acfb75 JR |
704 | #ifdef CONFIG_IOMMU_API |
705 | static void domain_id_free(int id) | |
706 | { | |
707 | unsigned long flags; | |
708 | ||
709 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
710 | if (id > 0 && id < MAX_DOMAIN_ID) | |
711 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
712 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
713 | } | |
714 | #endif | |
715 | ||
431b2a20 JR |
716 | /* |
717 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
718 | * ranges. | |
719 | */ | |
ec487d1a JR |
720 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
721 | unsigned long start_page, | |
722 | unsigned int pages) | |
723 | { | |
724 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
725 | ||
726 | if (start_page + pages > last_page) | |
727 | pages = last_page - start_page; | |
728 | ||
d26dbc5c | 729 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
730 | } |
731 | ||
86db2e5d | 732 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
733 | { |
734 | int i, j; | |
735 | u64 *p1, *p2, *p3; | |
736 | ||
86db2e5d | 737 | p1 = domain->pt_root; |
ec487d1a JR |
738 | |
739 | if (!p1) | |
740 | return; | |
741 | ||
742 | for (i = 0; i < 512; ++i) { | |
743 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
744 | continue; | |
745 | ||
746 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 747 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
748 | if (!IOMMU_PTE_PRESENT(p2[j])) |
749 | continue; | |
750 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
751 | free_page((unsigned long)p3); | |
752 | } | |
753 | ||
754 | free_page((unsigned long)p2); | |
755 | } | |
756 | ||
757 | free_page((unsigned long)p1); | |
86db2e5d JR |
758 | |
759 | domain->pt_root = NULL; | |
ec487d1a JR |
760 | } |
761 | ||
431b2a20 JR |
762 | /* |
763 | * Free a domain, only used if something went wrong in the | |
764 | * allocation path and we need to free an already allocated page table | |
765 | */ | |
ec487d1a JR |
766 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
767 | { | |
768 | if (!dom) | |
769 | return; | |
770 | ||
86db2e5d | 771 | free_pagetable(&dom->domain); |
ec487d1a JR |
772 | |
773 | kfree(dom->pte_pages); | |
774 | ||
775 | kfree(dom->bitmap); | |
776 | ||
777 | kfree(dom); | |
778 | } | |
779 | ||
431b2a20 JR |
780 | /* |
781 | * Allocates a new protection domain usable for the dma_ops functions. | |
782 | * It also intializes the page table and the address allocator data | |
783 | * structures required for the dma_ops interface | |
784 | */ | |
ec487d1a JR |
785 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
786 | unsigned order) | |
787 | { | |
788 | struct dma_ops_domain *dma_dom; | |
789 | unsigned i, num_pte_pages; | |
790 | u64 *l2_pde; | |
791 | u64 address; | |
792 | ||
793 | /* | |
794 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
795 | */ | |
796 | if ((order < 25) || (order > 30)) | |
797 | return NULL; | |
798 | ||
799 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
800 | if (!dma_dom) | |
801 | return NULL; | |
802 | ||
803 | spin_lock_init(&dma_dom->domain.lock); | |
804 | ||
805 | dma_dom->domain.id = domain_id_alloc(); | |
806 | if (dma_dom->domain.id == 0) | |
807 | goto free_dma_dom; | |
808 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
809 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 810 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
811 | dma_dom->domain.priv = dma_dom; |
812 | if (!dma_dom->domain.pt_root) | |
813 | goto free_dma_dom; | |
814 | dma_dom->aperture_size = (1ULL << order); | |
815 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
816 | GFP_KERNEL); | |
817 | if (!dma_dom->bitmap) | |
818 | goto free_dma_dom; | |
819 | /* | |
820 | * mark the first page as allocated so we never return 0 as | |
821 | * a valid dma-address. So we can use 0 as error value | |
822 | */ | |
823 | dma_dom->bitmap[0] = 1; | |
824 | dma_dom->next_bit = 0; | |
825 | ||
1c655773 | 826 | dma_dom->need_flush = false; |
bd60b735 | 827 | dma_dom->target_dev = 0xffff; |
1c655773 | 828 | |
431b2a20 | 829 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
830 | if (iommu->exclusion_start && |
831 | iommu->exclusion_start < dma_dom->aperture_size) { | |
832 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
833 | int pages = iommu_num_pages(iommu->exclusion_start, |
834 | iommu->exclusion_length, | |
835 | PAGE_SIZE); | |
ec487d1a JR |
836 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
837 | } | |
838 | ||
431b2a20 JR |
839 | /* |
840 | * At the last step, build the page tables so we don't need to | |
841 | * allocate page table pages in the dma_ops mapping/unmapping | |
842 | * path. | |
843 | */ | |
ec487d1a JR |
844 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
845 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
846 | GFP_KERNEL); | |
847 | if (!dma_dom->pte_pages) | |
848 | goto free_dma_dom; | |
849 | ||
850 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
851 | if (l2_pde == NULL) | |
852 | goto free_dma_dom; | |
853 | ||
854 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
855 | ||
856 | for (i = 0; i < num_pte_pages; ++i) { | |
857 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
858 | if (!dma_dom->pte_pages[i]) | |
859 | goto free_dma_dom; | |
860 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
861 | l2_pde[i] = IOMMU_L1_PDE(address); | |
862 | } | |
863 | ||
864 | return dma_dom; | |
865 | ||
866 | free_dma_dom: | |
867 | dma_ops_domain_free(dma_dom); | |
868 | ||
869 | return NULL; | |
870 | } | |
871 | ||
5b28df6f JR |
872 | /* |
873 | * little helper function to check whether a given protection domain is a | |
874 | * dma_ops domain | |
875 | */ | |
876 | static bool dma_ops_domain(struct protection_domain *domain) | |
877 | { | |
878 | return domain->flags & PD_DMA_OPS_MASK; | |
879 | } | |
880 | ||
431b2a20 JR |
881 | /* |
882 | * Find out the protection domain structure for a given PCI device. This | |
883 | * will give us the pointer to the page table root for example. | |
884 | */ | |
b20ac0d4 JR |
885 | static struct protection_domain *domain_for_device(u16 devid) |
886 | { | |
887 | struct protection_domain *dom; | |
888 | unsigned long flags; | |
889 | ||
890 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
891 | dom = amd_iommu_pd_table[devid]; | |
892 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
893 | ||
894 | return dom; | |
895 | } | |
896 | ||
431b2a20 JR |
897 | /* |
898 | * If a device is not yet associated with a domain, this function does | |
899 | * assigns it visible for the hardware | |
900 | */ | |
f1179dc0 JR |
901 | static void attach_device(struct amd_iommu *iommu, |
902 | struct protection_domain *domain, | |
903 | u16 devid) | |
b20ac0d4 JR |
904 | { |
905 | unsigned long flags; | |
b20ac0d4 JR |
906 | u64 pte_root = virt_to_phys(domain->pt_root); |
907 | ||
863c74eb JR |
908 | domain->dev_cnt += 1; |
909 | ||
38ddf41b JR |
910 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
911 | << DEV_ENTRY_MODE_SHIFT; | |
912 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
913 | |
914 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
915 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
916 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
917 | amd_iommu_dev_table[devid].data[2] = domain->id; |
918 | ||
919 | amd_iommu_pd_table[devid] = domain; | |
920 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
921 | ||
922 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
923 | } |
924 | ||
355bf553 JR |
925 | /* |
926 | * Removes a device from a protection domain (unlocked) | |
927 | */ | |
928 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
929 | { | |
930 | ||
931 | /* lock domain */ | |
932 | spin_lock(&domain->lock); | |
933 | ||
934 | /* remove domain from the lookup table */ | |
935 | amd_iommu_pd_table[devid] = NULL; | |
936 | ||
937 | /* remove entry from the device table seen by the hardware */ | |
938 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
939 | amd_iommu_dev_table[devid].data[1] = 0; | |
940 | amd_iommu_dev_table[devid].data[2] = 0; | |
941 | ||
942 | /* decrease reference counter */ | |
943 | domain->dev_cnt -= 1; | |
944 | ||
945 | /* ready */ | |
946 | spin_unlock(&domain->lock); | |
947 | } | |
948 | ||
949 | /* | |
950 | * Removes a device from a protection domain (with devtable_lock held) | |
951 | */ | |
952 | static void detach_device(struct protection_domain *domain, u16 devid) | |
953 | { | |
954 | unsigned long flags; | |
955 | ||
956 | /* lock device table */ | |
957 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
958 | __detach_device(domain, devid); | |
959 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
960 | } | |
e275a2a0 JR |
961 | |
962 | static int device_change_notifier(struct notifier_block *nb, | |
963 | unsigned long action, void *data) | |
964 | { | |
965 | struct device *dev = data; | |
966 | struct pci_dev *pdev = to_pci_dev(dev); | |
967 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
968 | struct protection_domain *domain; | |
969 | struct dma_ops_domain *dma_domain; | |
970 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
971 | int order = amd_iommu_aperture_order; |
972 | unsigned long flags; | |
e275a2a0 JR |
973 | |
974 | if (devid > amd_iommu_last_bdf) | |
975 | goto out; | |
976 | ||
977 | devid = amd_iommu_alias_table[devid]; | |
978 | ||
979 | iommu = amd_iommu_rlookup_table[devid]; | |
980 | if (iommu == NULL) | |
981 | goto out; | |
982 | ||
983 | domain = domain_for_device(devid); | |
984 | ||
985 | if (domain && !dma_ops_domain(domain)) | |
986 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
987 | "to a non-dma-ops domain\n", dev_name(dev)); | |
988 | ||
989 | switch (action) { | |
990 | case BUS_NOTIFY_BOUND_DRIVER: | |
991 | if (domain) | |
992 | goto out; | |
993 | dma_domain = find_protection_domain(devid); | |
994 | if (!dma_domain) | |
995 | dma_domain = iommu->default_dom; | |
996 | attach_device(iommu, &dma_domain->domain, devid); | |
997 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
998 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
999 | break; | |
1000 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1001 | if (!domain) | |
1002 | goto out; | |
1003 | detach_device(domain, devid); | |
1ac4cbbc JR |
1004 | break; |
1005 | case BUS_NOTIFY_ADD_DEVICE: | |
1006 | /* allocate a protection domain if a device is added */ | |
1007 | dma_domain = find_protection_domain(devid); | |
1008 | if (dma_domain) | |
1009 | goto out; | |
1010 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1011 | if (!dma_domain) | |
1012 | goto out; | |
1013 | dma_domain->target_dev = devid; | |
1014 | ||
1015 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1016 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1017 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1018 | ||
e275a2a0 JR |
1019 | break; |
1020 | default: | |
1021 | goto out; | |
1022 | } | |
1023 | ||
1024 | iommu_queue_inv_dev_entry(iommu, devid); | |
1025 | iommu_completion_wait(iommu); | |
1026 | ||
1027 | out: | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | struct notifier_block device_nb = { | |
1032 | .notifier_call = device_change_notifier, | |
1033 | }; | |
355bf553 | 1034 | |
431b2a20 JR |
1035 | /***************************************************************************** |
1036 | * | |
1037 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1038 | * | |
1039 | *****************************************************************************/ | |
1040 | ||
dbcc112e JR |
1041 | /* |
1042 | * This function checks if the driver got a valid device from the caller to | |
1043 | * avoid dereferencing invalid pointers. | |
1044 | */ | |
1045 | static bool check_device(struct device *dev) | |
1046 | { | |
1047 | if (!dev || !dev->dma_mask) | |
1048 | return false; | |
1049 | ||
1050 | return true; | |
1051 | } | |
1052 | ||
bd60b735 JR |
1053 | /* |
1054 | * In this function the list of preallocated protection domains is traversed to | |
1055 | * find the domain for a specific device | |
1056 | */ | |
1057 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1058 | { | |
1059 | struct dma_ops_domain *entry, *ret = NULL; | |
1060 | unsigned long flags; | |
1061 | ||
1062 | if (list_empty(&iommu_pd_list)) | |
1063 | return NULL; | |
1064 | ||
1065 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1066 | ||
1067 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1068 | if (entry->target_dev == devid) { | |
1069 | ret = entry; | |
bd60b735 JR |
1070 | break; |
1071 | } | |
1072 | } | |
1073 | ||
1074 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1075 | ||
1076 | return ret; | |
1077 | } | |
1078 | ||
431b2a20 JR |
1079 | /* |
1080 | * In the dma_ops path we only have the struct device. This function | |
1081 | * finds the corresponding IOMMU, the protection domain and the | |
1082 | * requestor id for a given device. | |
1083 | * If the device is not yet associated with a domain this is also done | |
1084 | * in this function. | |
1085 | */ | |
b20ac0d4 JR |
1086 | static int get_device_resources(struct device *dev, |
1087 | struct amd_iommu **iommu, | |
1088 | struct protection_domain **domain, | |
1089 | u16 *bdf) | |
1090 | { | |
1091 | struct dma_ops_domain *dma_dom; | |
1092 | struct pci_dev *pcidev; | |
1093 | u16 _bdf; | |
1094 | ||
dbcc112e JR |
1095 | *iommu = NULL; |
1096 | *domain = NULL; | |
1097 | *bdf = 0xffff; | |
1098 | ||
1099 | if (dev->bus != &pci_bus_type) | |
1100 | return 0; | |
b20ac0d4 JR |
1101 | |
1102 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1103 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1104 | |
431b2a20 | 1105 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1106 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1107 | return 0; |
b20ac0d4 JR |
1108 | |
1109 | *bdf = amd_iommu_alias_table[_bdf]; | |
1110 | ||
1111 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1112 | if (*iommu == NULL) | |
1113 | return 0; | |
b20ac0d4 JR |
1114 | *domain = domain_for_device(*bdf); |
1115 | if (*domain == NULL) { | |
bd60b735 JR |
1116 | dma_dom = find_protection_domain(*bdf); |
1117 | if (!dma_dom) | |
1118 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1119 | *domain = &dma_dom->domain; |
f1179dc0 | 1120 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1121 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1122 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1123 | } |
1124 | ||
f91ba190 | 1125 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1126 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1127 | |
b20ac0d4 JR |
1128 | return 1; |
1129 | } | |
1130 | ||
431b2a20 JR |
1131 | /* |
1132 | * This is the generic map function. It maps one 4kb page at paddr to | |
1133 | * the given address in the DMA address space for the domain. | |
1134 | */ | |
cb76c322 JR |
1135 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1136 | struct dma_ops_domain *dom, | |
1137 | unsigned long address, | |
1138 | phys_addr_t paddr, | |
1139 | int direction) | |
1140 | { | |
1141 | u64 *pte, __pte; | |
1142 | ||
1143 | WARN_ON(address > dom->aperture_size); | |
1144 | ||
1145 | paddr &= PAGE_MASK; | |
1146 | ||
1147 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1148 | pte += IOMMU_PTE_L0_INDEX(address); | |
1149 | ||
1150 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1151 | ||
1152 | if (direction == DMA_TO_DEVICE) | |
1153 | __pte |= IOMMU_PTE_IR; | |
1154 | else if (direction == DMA_FROM_DEVICE) | |
1155 | __pte |= IOMMU_PTE_IW; | |
1156 | else if (direction == DMA_BIDIRECTIONAL) | |
1157 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1158 | ||
1159 | WARN_ON(*pte); | |
1160 | ||
1161 | *pte = __pte; | |
1162 | ||
1163 | return (dma_addr_t)address; | |
1164 | } | |
1165 | ||
431b2a20 JR |
1166 | /* |
1167 | * The generic unmapping function for on page in the DMA address space. | |
1168 | */ | |
cb76c322 JR |
1169 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1170 | struct dma_ops_domain *dom, | |
1171 | unsigned long address) | |
1172 | { | |
1173 | u64 *pte; | |
1174 | ||
1175 | if (address >= dom->aperture_size) | |
1176 | return; | |
1177 | ||
8ad909c4 | 1178 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1179 | |
1180 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1181 | pte += IOMMU_PTE_L0_INDEX(address); | |
1182 | ||
1183 | WARN_ON(!*pte); | |
1184 | ||
1185 | *pte = 0ULL; | |
1186 | } | |
1187 | ||
431b2a20 JR |
1188 | /* |
1189 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1190 | * contiguous memory region into DMA address space. It is used by all |
1191 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1192 | * Must be called with the domain lock held. |
1193 | */ | |
cb76c322 JR |
1194 | static dma_addr_t __map_single(struct device *dev, |
1195 | struct amd_iommu *iommu, | |
1196 | struct dma_ops_domain *dma_dom, | |
1197 | phys_addr_t paddr, | |
1198 | size_t size, | |
6d4f343f | 1199 | int dir, |
832a90c3 JR |
1200 | bool align, |
1201 | u64 dma_mask) | |
cb76c322 JR |
1202 | { |
1203 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1204 | dma_addr_t address, start; | |
1205 | unsigned int pages; | |
6d4f343f | 1206 | unsigned long align_mask = 0; |
cb76c322 JR |
1207 | int i; |
1208 | ||
e3c449f5 | 1209 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1210 | paddr &= PAGE_MASK; |
1211 | ||
6d4f343f JR |
1212 | if (align) |
1213 | align_mask = (1UL << get_order(size)) - 1; | |
1214 | ||
832a90c3 JR |
1215 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1216 | dma_mask); | |
cb76c322 JR |
1217 | if (unlikely(address == bad_dma_address)) |
1218 | goto out; | |
1219 | ||
1220 | start = address; | |
1221 | for (i = 0; i < pages; ++i) { | |
1222 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1223 | paddr += PAGE_SIZE; | |
1224 | start += PAGE_SIZE; | |
1225 | } | |
1226 | address += offset; | |
1227 | ||
afa9fdc2 | 1228 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1229 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1230 | dma_dom->need_flush = false; | |
1231 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1232 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1233 | ||
cb76c322 JR |
1234 | out: |
1235 | return address; | |
1236 | } | |
1237 | ||
431b2a20 JR |
1238 | /* |
1239 | * Does the reverse of the __map_single function. Must be called with | |
1240 | * the domain lock held too | |
1241 | */ | |
cb76c322 JR |
1242 | static void __unmap_single(struct amd_iommu *iommu, |
1243 | struct dma_ops_domain *dma_dom, | |
1244 | dma_addr_t dma_addr, | |
1245 | size_t size, | |
1246 | int dir) | |
1247 | { | |
1248 | dma_addr_t i, start; | |
1249 | unsigned int pages; | |
1250 | ||
b8d9905d JR |
1251 | if ((dma_addr == bad_dma_address) || |
1252 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1253 | return; |
1254 | ||
e3c449f5 | 1255 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1256 | dma_addr &= PAGE_MASK; |
1257 | start = dma_addr; | |
1258 | ||
1259 | for (i = 0; i < pages; ++i) { | |
1260 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1261 | start += PAGE_SIZE; | |
1262 | } | |
1263 | ||
1264 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 1265 | |
80be308d | 1266 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1267 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1268 | dma_dom->need_flush = false; |
1269 | } | |
cb76c322 JR |
1270 | } |
1271 | ||
431b2a20 JR |
1272 | /* |
1273 | * The exported map_single function for dma_ops. | |
1274 | */ | |
4da70b9e JR |
1275 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1276 | size_t size, int dir) | |
1277 | { | |
1278 | unsigned long flags; | |
1279 | struct amd_iommu *iommu; | |
1280 | struct protection_domain *domain; | |
1281 | u16 devid; | |
1282 | dma_addr_t addr; | |
832a90c3 | 1283 | u64 dma_mask; |
4da70b9e | 1284 | |
0f2a86f2 JR |
1285 | INC_STATS_COUNTER(cnt_map_single); |
1286 | ||
dbcc112e JR |
1287 | if (!check_device(dev)) |
1288 | return bad_dma_address; | |
1289 | ||
832a90c3 | 1290 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1291 | |
1292 | get_device_resources(dev, &iommu, &domain, &devid); | |
1293 | ||
1294 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1295 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1296 | return (dma_addr_t)paddr; |
1297 | ||
5b28df6f JR |
1298 | if (!dma_ops_domain(domain)) |
1299 | return bad_dma_address; | |
1300 | ||
4da70b9e | 1301 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1302 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1303 | dma_mask); | |
4da70b9e JR |
1304 | if (addr == bad_dma_address) |
1305 | goto out; | |
1306 | ||
09ee17eb | 1307 | iommu_completion_wait(iommu); |
4da70b9e JR |
1308 | |
1309 | out: | |
1310 | spin_unlock_irqrestore(&domain->lock, flags); | |
1311 | ||
1312 | return addr; | |
1313 | } | |
1314 | ||
431b2a20 JR |
1315 | /* |
1316 | * The exported unmap_single function for dma_ops. | |
1317 | */ | |
4da70b9e JR |
1318 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1319 | size_t size, int dir) | |
1320 | { | |
1321 | unsigned long flags; | |
1322 | struct amd_iommu *iommu; | |
1323 | struct protection_domain *domain; | |
1324 | u16 devid; | |
1325 | ||
146a6917 JR |
1326 | INC_STATS_COUNTER(cnt_unmap_single); |
1327 | ||
dbcc112e JR |
1328 | if (!check_device(dev) || |
1329 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1330 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1331 | return; |
1332 | ||
5b28df6f JR |
1333 | if (!dma_ops_domain(domain)) |
1334 | return; | |
1335 | ||
4da70b9e JR |
1336 | spin_lock_irqsave(&domain->lock, flags); |
1337 | ||
1338 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1339 | ||
09ee17eb | 1340 | iommu_completion_wait(iommu); |
4da70b9e JR |
1341 | |
1342 | spin_unlock_irqrestore(&domain->lock, flags); | |
1343 | } | |
1344 | ||
431b2a20 JR |
1345 | /* |
1346 | * This is a special map_sg function which is used if we should map a | |
1347 | * device which is not handled by an AMD IOMMU in the system. | |
1348 | */ | |
65b050ad JR |
1349 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1350 | int nelems, int dir) | |
1351 | { | |
1352 | struct scatterlist *s; | |
1353 | int i; | |
1354 | ||
1355 | for_each_sg(sglist, s, nelems, i) { | |
1356 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1357 | s->dma_length = s->length; | |
1358 | } | |
1359 | ||
1360 | return nelems; | |
1361 | } | |
1362 | ||
431b2a20 JR |
1363 | /* |
1364 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1365 | * lists). | |
1366 | */ | |
65b050ad JR |
1367 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1368 | int nelems, int dir) | |
1369 | { | |
1370 | unsigned long flags; | |
1371 | struct amd_iommu *iommu; | |
1372 | struct protection_domain *domain; | |
1373 | u16 devid; | |
1374 | int i; | |
1375 | struct scatterlist *s; | |
1376 | phys_addr_t paddr; | |
1377 | int mapped_elems = 0; | |
832a90c3 | 1378 | u64 dma_mask; |
65b050ad | 1379 | |
dbcc112e JR |
1380 | if (!check_device(dev)) |
1381 | return 0; | |
1382 | ||
832a90c3 | 1383 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1384 | |
1385 | get_device_resources(dev, &iommu, &domain, &devid); | |
1386 | ||
1387 | if (!iommu || !domain) | |
1388 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1389 | ||
5b28df6f JR |
1390 | if (!dma_ops_domain(domain)) |
1391 | return 0; | |
1392 | ||
65b050ad JR |
1393 | spin_lock_irqsave(&domain->lock, flags); |
1394 | ||
1395 | for_each_sg(sglist, s, nelems, i) { | |
1396 | paddr = sg_phys(s); | |
1397 | ||
1398 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1399 | paddr, s->length, dir, false, |
1400 | dma_mask); | |
65b050ad JR |
1401 | |
1402 | if (s->dma_address) { | |
1403 | s->dma_length = s->length; | |
1404 | mapped_elems++; | |
1405 | } else | |
1406 | goto unmap; | |
65b050ad JR |
1407 | } |
1408 | ||
09ee17eb | 1409 | iommu_completion_wait(iommu); |
65b050ad JR |
1410 | |
1411 | out: | |
1412 | spin_unlock_irqrestore(&domain->lock, flags); | |
1413 | ||
1414 | return mapped_elems; | |
1415 | unmap: | |
1416 | for_each_sg(sglist, s, mapped_elems, i) { | |
1417 | if (s->dma_address) | |
1418 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1419 | s->dma_length, dir); | |
1420 | s->dma_address = s->dma_length = 0; | |
1421 | } | |
1422 | ||
1423 | mapped_elems = 0; | |
1424 | ||
1425 | goto out; | |
1426 | } | |
1427 | ||
431b2a20 JR |
1428 | /* |
1429 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1430 | * lists). | |
1431 | */ | |
65b050ad JR |
1432 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1433 | int nelems, int dir) | |
1434 | { | |
1435 | unsigned long flags; | |
1436 | struct amd_iommu *iommu; | |
1437 | struct protection_domain *domain; | |
1438 | struct scatterlist *s; | |
1439 | u16 devid; | |
1440 | int i; | |
1441 | ||
dbcc112e JR |
1442 | if (!check_device(dev) || |
1443 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1444 | return; |
1445 | ||
5b28df6f JR |
1446 | if (!dma_ops_domain(domain)) |
1447 | return; | |
1448 | ||
65b050ad JR |
1449 | spin_lock_irqsave(&domain->lock, flags); |
1450 | ||
1451 | for_each_sg(sglist, s, nelems, i) { | |
1452 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1453 | s->dma_length, dir); | |
65b050ad JR |
1454 | s->dma_address = s->dma_length = 0; |
1455 | } | |
1456 | ||
09ee17eb | 1457 | iommu_completion_wait(iommu); |
65b050ad JR |
1458 | |
1459 | spin_unlock_irqrestore(&domain->lock, flags); | |
1460 | } | |
1461 | ||
431b2a20 JR |
1462 | /* |
1463 | * The exported alloc_coherent function for dma_ops. | |
1464 | */ | |
5d8b53cf JR |
1465 | static void *alloc_coherent(struct device *dev, size_t size, |
1466 | dma_addr_t *dma_addr, gfp_t flag) | |
1467 | { | |
1468 | unsigned long flags; | |
1469 | void *virt_addr; | |
1470 | struct amd_iommu *iommu; | |
1471 | struct protection_domain *domain; | |
1472 | u16 devid; | |
1473 | phys_addr_t paddr; | |
832a90c3 | 1474 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1475 | |
dbcc112e JR |
1476 | if (!check_device(dev)) |
1477 | return NULL; | |
5d8b53cf | 1478 | |
13d9fead FT |
1479 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1480 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1481 | |
c97ac535 | 1482 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1483 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1484 | if (!virt_addr) | |
1485 | return 0; | |
1486 | ||
5d8b53cf JR |
1487 | paddr = virt_to_phys(virt_addr); |
1488 | ||
5d8b53cf JR |
1489 | if (!iommu || !domain) { |
1490 | *dma_addr = (dma_addr_t)paddr; | |
1491 | return virt_addr; | |
1492 | } | |
1493 | ||
5b28df6f JR |
1494 | if (!dma_ops_domain(domain)) |
1495 | goto out_free; | |
1496 | ||
832a90c3 JR |
1497 | if (!dma_mask) |
1498 | dma_mask = *dev->dma_mask; | |
1499 | ||
5d8b53cf JR |
1500 | spin_lock_irqsave(&domain->lock, flags); |
1501 | ||
1502 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1503 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1504 | |
5b28df6f JR |
1505 | if (*dma_addr == bad_dma_address) |
1506 | goto out_free; | |
5d8b53cf | 1507 | |
09ee17eb | 1508 | iommu_completion_wait(iommu); |
5d8b53cf | 1509 | |
5d8b53cf JR |
1510 | spin_unlock_irqrestore(&domain->lock, flags); |
1511 | ||
1512 | return virt_addr; | |
5b28df6f JR |
1513 | |
1514 | out_free: | |
1515 | ||
1516 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1517 | ||
1518 | return NULL; | |
5d8b53cf JR |
1519 | } |
1520 | ||
431b2a20 JR |
1521 | /* |
1522 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1523 | */ |
5d8b53cf JR |
1524 | static void free_coherent(struct device *dev, size_t size, |
1525 | void *virt_addr, dma_addr_t dma_addr) | |
1526 | { | |
1527 | unsigned long flags; | |
1528 | struct amd_iommu *iommu; | |
1529 | struct protection_domain *domain; | |
1530 | u16 devid; | |
1531 | ||
dbcc112e JR |
1532 | if (!check_device(dev)) |
1533 | return; | |
1534 | ||
5d8b53cf JR |
1535 | get_device_resources(dev, &iommu, &domain, &devid); |
1536 | ||
1537 | if (!iommu || !domain) | |
1538 | goto free_mem; | |
1539 | ||
5b28df6f JR |
1540 | if (!dma_ops_domain(domain)) |
1541 | goto free_mem; | |
1542 | ||
5d8b53cf JR |
1543 | spin_lock_irqsave(&domain->lock, flags); |
1544 | ||
1545 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1546 | |
09ee17eb | 1547 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1548 | |
1549 | spin_unlock_irqrestore(&domain->lock, flags); | |
1550 | ||
1551 | free_mem: | |
1552 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1553 | } | |
1554 | ||
b39ba6ad JR |
1555 | /* |
1556 | * This function is called by the DMA layer to find out if we can handle a | |
1557 | * particular device. It is part of the dma_ops. | |
1558 | */ | |
1559 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1560 | { | |
1561 | u16 bdf; | |
1562 | struct pci_dev *pcidev; | |
1563 | ||
1564 | /* No device or no PCI device */ | |
1565 | if (!dev || dev->bus != &pci_bus_type) | |
1566 | return 0; | |
1567 | ||
1568 | pcidev = to_pci_dev(dev); | |
1569 | ||
1570 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1571 | ||
1572 | /* Out of our scope? */ | |
1573 | if (bdf > amd_iommu_last_bdf) | |
1574 | return 0; | |
1575 | ||
1576 | return 1; | |
1577 | } | |
1578 | ||
c432f3df | 1579 | /* |
431b2a20 JR |
1580 | * The function for pre-allocating protection domains. |
1581 | * | |
c432f3df JR |
1582 | * If the driver core informs the DMA layer if a driver grabs a device |
1583 | * we don't need to preallocate the protection domains anymore. | |
1584 | * For now we have to. | |
1585 | */ | |
1586 | void prealloc_protection_domains(void) | |
1587 | { | |
1588 | struct pci_dev *dev = NULL; | |
1589 | struct dma_ops_domain *dma_dom; | |
1590 | struct amd_iommu *iommu; | |
1591 | int order = amd_iommu_aperture_order; | |
1592 | u16 devid; | |
1593 | ||
1594 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1595 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1596 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1597 | continue; |
1598 | devid = amd_iommu_alias_table[devid]; | |
1599 | if (domain_for_device(devid)) | |
1600 | continue; | |
1601 | iommu = amd_iommu_rlookup_table[devid]; | |
1602 | if (!iommu) | |
1603 | continue; | |
1604 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1605 | if (!dma_dom) | |
1606 | continue; | |
1607 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1608 | dma_dom->target_dev = devid; |
1609 | ||
1610 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1611 | } |
1612 | } | |
1613 | ||
6631ee9d JR |
1614 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1615 | .alloc_coherent = alloc_coherent, | |
1616 | .free_coherent = free_coherent, | |
1617 | .map_single = map_single, | |
1618 | .unmap_single = unmap_single, | |
1619 | .map_sg = map_sg, | |
1620 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1621 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1622 | }; |
1623 | ||
431b2a20 JR |
1624 | /* |
1625 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1626 | */ | |
6631ee9d JR |
1627 | int __init amd_iommu_init_dma_ops(void) |
1628 | { | |
1629 | struct amd_iommu *iommu; | |
1630 | int order = amd_iommu_aperture_order; | |
1631 | int ret; | |
1632 | ||
431b2a20 JR |
1633 | /* |
1634 | * first allocate a default protection domain for every IOMMU we | |
1635 | * found in the system. Devices not assigned to any other | |
1636 | * protection domain will be assigned to the default one. | |
1637 | */ | |
6631ee9d JR |
1638 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1639 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1640 | if (iommu->default_dom == NULL) | |
1641 | return -ENOMEM; | |
e2dc14a2 | 1642 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1643 | ret = iommu_init_unity_mappings(iommu); |
1644 | if (ret) | |
1645 | goto free_domains; | |
1646 | } | |
1647 | ||
431b2a20 JR |
1648 | /* |
1649 | * If device isolation is enabled, pre-allocate the protection | |
1650 | * domains for each device. | |
1651 | */ | |
6631ee9d JR |
1652 | if (amd_iommu_isolate) |
1653 | prealloc_protection_domains(); | |
1654 | ||
1655 | iommu_detected = 1; | |
1656 | force_iommu = 1; | |
1657 | bad_dma_address = 0; | |
92af4e29 | 1658 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1659 | gart_iommu_aperture_disabled = 1; |
1660 | gart_iommu_aperture = 0; | |
92af4e29 | 1661 | #endif |
6631ee9d | 1662 | |
431b2a20 | 1663 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1664 | dma_ops = &amd_iommu_dma_ops; |
1665 | ||
26961efe JR |
1666 | #ifdef CONFIG_IOMMU_API |
1667 | register_iommu(&amd_iommu_ops); | |
1668 | #endif | |
1669 | ||
e275a2a0 JR |
1670 | bus_register_notifier(&pci_bus_type, &device_nb); |
1671 | ||
7f26508b JR |
1672 | amd_iommu_stats_init(); |
1673 | ||
6631ee9d JR |
1674 | return 0; |
1675 | ||
1676 | free_domains: | |
1677 | ||
1678 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1679 | if (iommu->default_dom) | |
1680 | dma_ops_domain_free(iommu->default_dom); | |
1681 | } | |
1682 | ||
1683 | return ret; | |
1684 | } | |
6d98cd80 JR |
1685 | |
1686 | /***************************************************************************** | |
1687 | * | |
1688 | * The following functions belong to the exported interface of AMD IOMMU | |
1689 | * | |
1690 | * This interface allows access to lower level functions of the IOMMU | |
1691 | * like protection domain handling and assignement of devices to domains | |
1692 | * which is not possible with the dma_ops interface. | |
1693 | * | |
1694 | *****************************************************************************/ | |
1695 | ||
1696 | #ifdef CONFIG_IOMMU_API | |
1697 | ||
1698 | static void cleanup_domain(struct protection_domain *domain) | |
1699 | { | |
1700 | unsigned long flags; | |
1701 | u16 devid; | |
1702 | ||
1703 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1704 | ||
1705 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1706 | if (amd_iommu_pd_table[devid] == domain) | |
1707 | __detach_device(domain, devid); | |
1708 | ||
1709 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1710 | } | |
1711 | ||
c156e347 JR |
1712 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1713 | { | |
1714 | struct protection_domain *domain; | |
1715 | ||
1716 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1717 | if (!domain) | |
1718 | return -ENOMEM; | |
1719 | ||
1720 | spin_lock_init(&domain->lock); | |
1721 | domain->mode = PAGE_MODE_3_LEVEL; | |
1722 | domain->id = domain_id_alloc(); | |
1723 | if (!domain->id) | |
1724 | goto out_free; | |
1725 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1726 | if (!domain->pt_root) | |
1727 | goto out_free; | |
1728 | ||
1729 | dom->priv = domain; | |
1730 | ||
1731 | return 0; | |
1732 | ||
1733 | out_free: | |
1734 | kfree(domain); | |
1735 | ||
1736 | return -ENOMEM; | |
1737 | } | |
1738 | ||
98383fc3 JR |
1739 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1740 | { | |
1741 | struct protection_domain *domain = dom->priv; | |
1742 | ||
1743 | if (!domain) | |
1744 | return; | |
1745 | ||
1746 | if (domain->dev_cnt > 0) | |
1747 | cleanup_domain(domain); | |
1748 | ||
1749 | BUG_ON(domain->dev_cnt != 0); | |
1750 | ||
1751 | free_pagetable(domain); | |
1752 | ||
1753 | domain_id_free(domain->id); | |
1754 | ||
1755 | kfree(domain); | |
1756 | ||
1757 | dom->priv = NULL; | |
1758 | } | |
1759 | ||
684f2888 JR |
1760 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1761 | struct device *dev) | |
1762 | { | |
1763 | struct protection_domain *domain = dom->priv; | |
1764 | struct amd_iommu *iommu; | |
1765 | struct pci_dev *pdev; | |
1766 | u16 devid; | |
1767 | ||
1768 | if (dev->bus != &pci_bus_type) | |
1769 | return; | |
1770 | ||
1771 | pdev = to_pci_dev(dev); | |
1772 | ||
1773 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1774 | ||
1775 | if (devid > 0) | |
1776 | detach_device(domain, devid); | |
1777 | ||
1778 | iommu = amd_iommu_rlookup_table[devid]; | |
1779 | if (!iommu) | |
1780 | return; | |
1781 | ||
1782 | iommu_queue_inv_dev_entry(iommu, devid); | |
1783 | iommu_completion_wait(iommu); | |
1784 | } | |
1785 | ||
01106066 JR |
1786 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1787 | struct device *dev) | |
1788 | { | |
1789 | struct protection_domain *domain = dom->priv; | |
1790 | struct protection_domain *old_domain; | |
1791 | struct amd_iommu *iommu; | |
1792 | struct pci_dev *pdev; | |
1793 | u16 devid; | |
1794 | ||
1795 | if (dev->bus != &pci_bus_type) | |
1796 | return -EINVAL; | |
1797 | ||
1798 | pdev = to_pci_dev(dev); | |
1799 | ||
1800 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1801 | ||
1802 | if (devid >= amd_iommu_last_bdf || | |
1803 | devid != amd_iommu_alias_table[devid]) | |
1804 | return -EINVAL; | |
1805 | ||
1806 | iommu = amd_iommu_rlookup_table[devid]; | |
1807 | if (!iommu) | |
1808 | return -EINVAL; | |
1809 | ||
1810 | old_domain = domain_for_device(devid); | |
1811 | if (old_domain) | |
1812 | return -EBUSY; | |
1813 | ||
1814 | attach_device(iommu, domain, devid); | |
1815 | ||
1816 | iommu_completion_wait(iommu); | |
1817 | ||
1818 | return 0; | |
1819 | } | |
1820 | ||
c6229ca6 JR |
1821 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1822 | unsigned long iova, phys_addr_t paddr, | |
1823 | size_t size, int iommu_prot) | |
1824 | { | |
1825 | struct protection_domain *domain = dom->priv; | |
1826 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1827 | int prot = 0; | |
1828 | int ret; | |
1829 | ||
1830 | if (iommu_prot & IOMMU_READ) | |
1831 | prot |= IOMMU_PROT_IR; | |
1832 | if (iommu_prot & IOMMU_WRITE) | |
1833 | prot |= IOMMU_PROT_IW; | |
1834 | ||
1835 | iova &= PAGE_MASK; | |
1836 | paddr &= PAGE_MASK; | |
1837 | ||
1838 | for (i = 0; i < npages; ++i) { | |
1839 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1840 | if (ret) | |
1841 | return ret; | |
1842 | ||
1843 | iova += PAGE_SIZE; | |
1844 | paddr += PAGE_SIZE; | |
1845 | } | |
1846 | ||
1847 | return 0; | |
1848 | } | |
1849 | ||
eb74ff6c JR |
1850 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1851 | unsigned long iova, size_t size) | |
1852 | { | |
1853 | ||
1854 | struct protection_domain *domain = dom->priv; | |
1855 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1856 | ||
1857 | iova &= PAGE_MASK; | |
1858 | ||
1859 | for (i = 0; i < npages; ++i) { | |
1860 | iommu_unmap_page(domain, iova); | |
1861 | iova += PAGE_SIZE; | |
1862 | } | |
1863 | ||
1864 | iommu_flush_domain(domain->id); | |
1865 | } | |
1866 | ||
645c4c8d JR |
1867 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1868 | unsigned long iova) | |
1869 | { | |
1870 | struct protection_domain *domain = dom->priv; | |
1871 | unsigned long offset = iova & ~PAGE_MASK; | |
1872 | phys_addr_t paddr; | |
1873 | u64 *pte; | |
1874 | ||
1875 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1876 | ||
1877 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1878 | return 0; | |
1879 | ||
1880 | pte = IOMMU_PTE_PAGE(*pte); | |
1881 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1882 | ||
1883 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1884 | return 0; | |
1885 | ||
1886 | pte = IOMMU_PTE_PAGE(*pte); | |
1887 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1888 | ||
1889 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1890 | return 0; | |
1891 | ||
1892 | paddr = *pte & IOMMU_PAGE_MASK; | |
1893 | paddr |= offset; | |
1894 | ||
1895 | return paddr; | |
1896 | } | |
1897 | ||
26961efe JR |
1898 | static struct iommu_ops amd_iommu_ops = { |
1899 | .domain_init = amd_iommu_domain_init, | |
1900 | .domain_destroy = amd_iommu_domain_destroy, | |
1901 | .attach_dev = amd_iommu_attach_device, | |
1902 | .detach_dev = amd_iommu_detach_device, | |
1903 | .map = amd_iommu_map_range, | |
1904 | .unmap = amd_iommu_unmap_range, | |
1905 | .iova_to_phys = amd_iommu_iova_to_phys, | |
1906 | }; | |
1907 | ||
6d98cd80 | 1908 | #endif |