Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
0feae533 JR |
44 | /* |
45 | * Domain for untranslated devices - only allocated | |
46 | * if iommu=pt passed on kernel cmd line. | |
47 | */ | |
48 | static struct protection_domain *pt_domain; | |
49 | ||
26961efe | 50 | static struct iommu_ops amd_iommu_ops; |
26961efe | 51 | |
431b2a20 JR |
52 | /* |
53 | * general struct to manage commands send to an IOMMU | |
54 | */ | |
d6449536 | 55 | struct iommu_cmd { |
b6c02715 JR |
56 | u32 data[4]; |
57 | }; | |
58 | ||
bd0e5211 JR |
59 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
60 | struct unity_map_entry *e); | |
e275a2a0 | 61 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bc3e127 | 62 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
63 | unsigned long address, int end_lvl, |
64 | u64 **pte_page, gfp_t gfp); | |
00cd122a JR |
65 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
66 | unsigned long start_page, | |
67 | unsigned int pages); | |
a345b23b | 68 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
9355a081 | 69 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 70 | unsigned long address, int map_size); |
04bfdd84 | 71 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 72 | |
7f26508b JR |
73 | #ifdef CONFIG_AMD_IOMMU_STATS |
74 | ||
75 | /* | |
76 | * Initialization code for statistics collection | |
77 | */ | |
78 | ||
da49f6df | 79 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 80 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 81 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 82 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 83 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 84 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 85 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 86 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 87 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 88 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 89 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 90 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 91 | |
7f26508b JR |
92 | static struct dentry *stats_dir; |
93 | static struct dentry *de_isolate; | |
94 | static struct dentry *de_fflush; | |
95 | ||
96 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
97 | { | |
98 | if (stats_dir == NULL) | |
99 | return; | |
100 | ||
101 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
102 | &cnt->value); | |
103 | } | |
104 | ||
105 | static void amd_iommu_stats_init(void) | |
106 | { | |
107 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
108 | if (stats_dir == NULL) | |
109 | return; | |
110 | ||
111 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
112 | (u32 *)&amd_iommu_isolate); | |
113 | ||
114 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
115 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
116 | |
117 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 118 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 119 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 120 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 121 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 122 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 123 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 124 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 125 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 126 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 127 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 128 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
129 | } |
130 | ||
131 | #endif | |
132 | ||
431b2a20 | 133 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
134 | static int iommu_has_npcache(struct amd_iommu *iommu) |
135 | { | |
ae9b9403 | 136 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
137 | } |
138 | ||
a80dc3e0 JR |
139 | /**************************************************************************** |
140 | * | |
141 | * Interrupt handling functions | |
142 | * | |
143 | ****************************************************************************/ | |
144 | ||
e3e59876 JR |
145 | static void dump_dte_entry(u16 devid) |
146 | { | |
147 | int i; | |
148 | ||
149 | for (i = 0; i < 8; ++i) | |
150 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
151 | amd_iommu_dev_table[devid].data[i]); | |
152 | } | |
153 | ||
945b4ac4 JR |
154 | static void dump_command(unsigned long phys_addr) |
155 | { | |
156 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
157 | int i; | |
158 | ||
159 | for (i = 0; i < 4; ++i) | |
160 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
161 | } | |
162 | ||
a345b23b | 163 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
164 | { |
165 | u32 *event = __evt; | |
166 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
167 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
168 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
169 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
170 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
171 | ||
4c6f40d4 | 172 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
173 | |
174 | switch (type) { | |
175 | case EVENT_TYPE_ILL_DEV: | |
176 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
177 | "address=0x%016llx flags=0x%04x]\n", | |
178 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
179 | address, flags); | |
e3e59876 | 180 | dump_dte_entry(devid); |
90008ee4 JR |
181 | break; |
182 | case EVENT_TYPE_IO_FAULT: | |
183 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
184 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
185 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
186 | domid, address, flags); | |
187 | break; | |
188 | case EVENT_TYPE_DEV_TAB_ERR: | |
189 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
190 | "address=0x%016llx flags=0x%04x]\n", | |
191 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
192 | address, flags); | |
193 | break; | |
194 | case EVENT_TYPE_PAGE_TAB_ERR: | |
195 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
196 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
197 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
198 | domid, address, flags); | |
199 | break; | |
200 | case EVENT_TYPE_ILL_CMD: | |
201 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 202 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 203 | dump_command(address); |
90008ee4 JR |
204 | break; |
205 | case EVENT_TYPE_CMD_HARD_ERR: | |
206 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
207 | "flags=0x%04x]\n", address, flags); | |
208 | break; | |
209 | case EVENT_TYPE_IOTLB_INV_TO: | |
210 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
211 | "address=0x%016llx]\n", | |
212 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
213 | address); | |
214 | break; | |
215 | case EVENT_TYPE_INV_DEV_REQ: | |
216 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
217 | "address=0x%016llx flags=0x%04x]\n", | |
218 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
219 | address, flags); | |
220 | break; | |
221 | default: | |
222 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
223 | } | |
224 | } | |
225 | ||
226 | static void iommu_poll_events(struct amd_iommu *iommu) | |
227 | { | |
228 | u32 head, tail; | |
229 | unsigned long flags; | |
230 | ||
231 | spin_lock_irqsave(&iommu->lock, flags); | |
232 | ||
233 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
234 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
235 | ||
236 | while (head != tail) { | |
a345b23b | 237 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
238 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
239 | } | |
240 | ||
241 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
242 | ||
243 | spin_unlock_irqrestore(&iommu->lock, flags); | |
244 | } | |
245 | ||
a80dc3e0 JR |
246 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
247 | { | |
90008ee4 JR |
248 | struct amd_iommu *iommu; |
249 | ||
3bd22172 | 250 | for_each_iommu(iommu) |
90008ee4 JR |
251 | iommu_poll_events(iommu); |
252 | ||
253 | return IRQ_HANDLED; | |
a80dc3e0 JR |
254 | } |
255 | ||
431b2a20 JR |
256 | /**************************************************************************** |
257 | * | |
258 | * IOMMU command queuing functions | |
259 | * | |
260 | ****************************************************************************/ | |
261 | ||
262 | /* | |
263 | * Writes the command to the IOMMUs command buffer and informs the | |
264 | * hardware about the new command. Must be called with iommu->lock held. | |
265 | */ | |
d6449536 | 266 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
267 | { |
268 | u32 tail, head; | |
269 | u8 *target; | |
270 | ||
271 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 272 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
273 | memcpy_toio(target, cmd, sizeof(*cmd)); |
274 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
275 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
276 | if (tail == head) | |
277 | return -ENOMEM; | |
278 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
431b2a20 JR |
283 | /* |
284 | * General queuing function for commands. Takes iommu->lock and calls | |
285 | * __iommu_queue_command(). | |
286 | */ | |
d6449536 | 287 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
288 | { |
289 | unsigned long flags; | |
290 | int ret; | |
291 | ||
292 | spin_lock_irqsave(&iommu->lock, flags); | |
293 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 294 | if (!ret) |
0cfd7aa9 | 295 | iommu->need_sync = true; |
a19ae1ec JR |
296 | spin_unlock_irqrestore(&iommu->lock, flags); |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
8d201968 JR |
301 | /* |
302 | * This function waits until an IOMMU has completed a completion | |
303 | * wait command | |
304 | */ | |
305 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
306 | { | |
307 | int ready = 0; | |
308 | unsigned status = 0; | |
309 | unsigned long i = 0; | |
310 | ||
da49f6df JR |
311 | INC_STATS_COUNTER(compl_wait); |
312 | ||
8d201968 JR |
313 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
314 | ++i; | |
315 | /* wait for the bit to become one */ | |
316 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
317 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
318 | } | |
319 | ||
320 | /* set bit back to zero */ | |
321 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
322 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
323 | ||
6a1eddd2 JR |
324 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
325 | spin_unlock(&iommu->lock); | |
326 | reset_iommu_command_buffer(iommu); | |
327 | spin_lock(&iommu->lock); | |
328 | } | |
8d201968 JR |
329 | } |
330 | ||
331 | /* | |
332 | * This function queues a completion wait command into the command | |
333 | * buffer of an IOMMU | |
334 | */ | |
335 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
336 | { | |
337 | struct iommu_cmd cmd; | |
338 | ||
339 | memset(&cmd, 0, sizeof(cmd)); | |
340 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
341 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
342 | ||
343 | return __iommu_queue_command(iommu, &cmd); | |
344 | } | |
345 | ||
431b2a20 JR |
346 | /* |
347 | * This function is called whenever we need to ensure that the IOMMU has | |
348 | * completed execution of all commands we sent. It sends a | |
349 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
350 | * us about that by writing a value to a physical address we pass with | |
351 | * the command. | |
352 | */ | |
a19ae1ec JR |
353 | static int iommu_completion_wait(struct amd_iommu *iommu) |
354 | { | |
8d201968 JR |
355 | int ret = 0; |
356 | unsigned long flags; | |
a19ae1ec | 357 | |
7e4f88da JR |
358 | spin_lock_irqsave(&iommu->lock, flags); |
359 | ||
09ee17eb JR |
360 | if (!iommu->need_sync) |
361 | goto out; | |
362 | ||
8d201968 | 363 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 364 | |
0cfd7aa9 | 365 | iommu->need_sync = false; |
a19ae1ec JR |
366 | |
367 | if (ret) | |
7e4f88da | 368 | goto out; |
a19ae1ec | 369 | |
8d201968 | 370 | __iommu_wait_for_completion(iommu); |
84df8175 | 371 | |
7e4f88da JR |
372 | out: |
373 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
374 | |
375 | return 0; | |
376 | } | |
377 | ||
431b2a20 JR |
378 | /* |
379 | * Command send function for invalidating a device table entry | |
380 | */ | |
a19ae1ec JR |
381 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
382 | { | |
d6449536 | 383 | struct iommu_cmd cmd; |
ee2fa743 | 384 | int ret; |
a19ae1ec JR |
385 | |
386 | BUG_ON(iommu == NULL); | |
387 | ||
388 | memset(&cmd, 0, sizeof(cmd)); | |
389 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
390 | cmd.data[0] = devid; | |
391 | ||
ee2fa743 JR |
392 | ret = iommu_queue_command(iommu, &cmd); |
393 | ||
ee2fa743 | 394 | return ret; |
a19ae1ec JR |
395 | } |
396 | ||
237b6f33 JR |
397 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
398 | u16 domid, int pde, int s) | |
399 | { | |
400 | memset(cmd, 0, sizeof(*cmd)); | |
401 | address &= PAGE_MASK; | |
402 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
403 | cmd->data[1] |= domid; | |
404 | cmd->data[2] = lower_32_bits(address); | |
405 | cmd->data[3] = upper_32_bits(address); | |
406 | if (s) /* size bit - we flush more than one 4kb page */ | |
407 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
408 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
409 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
410 | } | |
411 | ||
431b2a20 JR |
412 | /* |
413 | * Generic command send function for invalidaing TLB entries | |
414 | */ | |
a19ae1ec JR |
415 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
416 | u64 address, u16 domid, int pde, int s) | |
417 | { | |
d6449536 | 418 | struct iommu_cmd cmd; |
ee2fa743 | 419 | int ret; |
a19ae1ec | 420 | |
237b6f33 | 421 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 422 | |
ee2fa743 JR |
423 | ret = iommu_queue_command(iommu, &cmd); |
424 | ||
ee2fa743 | 425 | return ret; |
a19ae1ec JR |
426 | } |
427 | ||
431b2a20 JR |
428 | /* |
429 | * TLB invalidation function which is called from the mapping functions. | |
430 | * It invalidates a single PTE if the range to flush is within a single | |
431 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
432 | */ | |
a19ae1ec JR |
433 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
434 | u64 address, size_t size) | |
435 | { | |
999ba417 | 436 | int s = 0; |
e3c449f5 | 437 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
438 | |
439 | address &= PAGE_MASK; | |
440 | ||
999ba417 JR |
441 | if (pages > 1) { |
442 | /* | |
443 | * If we have to flush more than one page, flush all | |
444 | * TLB entries for this domain | |
445 | */ | |
446 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
447 | s = 1; | |
a19ae1ec JR |
448 | } |
449 | ||
999ba417 JR |
450 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
451 | ||
a19ae1ec JR |
452 | return 0; |
453 | } | |
b6c02715 | 454 | |
1c655773 JR |
455 | /* Flush the whole IO/TLB for a given protection domain */ |
456 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
457 | { | |
458 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
459 | ||
f57d98ae JR |
460 | INC_STATS_COUNTER(domain_flush_single); |
461 | ||
1c655773 JR |
462 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
463 | } | |
464 | ||
42a49f96 CW |
465 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
466 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
467 | { | |
468 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
469 | ||
470 | INC_STATS_COUNTER(domain_flush_single); | |
471 | ||
472 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
473 | } | |
474 | ||
43f49609 | 475 | /* |
e394d72a | 476 | * This function flushes one domain on one IOMMU |
43f49609 | 477 | */ |
e394d72a | 478 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 479 | { |
43f49609 | 480 | struct iommu_cmd cmd; |
e394d72a | 481 | unsigned long flags; |
18811f55 | 482 | |
43f49609 JR |
483 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
484 | domid, 1, 1); | |
485 | ||
e394d72a JR |
486 | spin_lock_irqsave(&iommu->lock, flags); |
487 | __iommu_queue_command(iommu, &cmd); | |
488 | __iommu_completion_wait(iommu); | |
489 | __iommu_wait_for_completion(iommu); | |
490 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 491 | } |
43f49609 | 492 | |
e394d72a | 493 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
494 | { |
495 | int i; | |
496 | ||
497 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
498 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
499 | continue; | |
e394d72a | 500 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 501 | } |
e394d72a JR |
502 | |
503 | } | |
504 | ||
43f49609 JR |
505 | /* |
506 | * This function is used to flush the IO/TLB for a given protection domain | |
507 | * on every IOMMU in the system | |
508 | */ | |
509 | static void iommu_flush_domain(u16 domid) | |
510 | { | |
43f49609 | 511 | struct amd_iommu *iommu; |
43f49609 | 512 | |
18811f55 JR |
513 | INC_STATS_COUNTER(domain_flush_all); |
514 | ||
e394d72a JR |
515 | for_each_iommu(iommu) |
516 | flush_domain_on_iommu(iommu, domid); | |
43f49609 | 517 | } |
43f49609 | 518 | |
bfd1be18 | 519 | void amd_iommu_flush_all_domains(void) |
e394d72a JR |
520 | { |
521 | struct amd_iommu *iommu; | |
522 | ||
523 | for_each_iommu(iommu) | |
524 | flush_all_domains_on_iommu(iommu); | |
bfd1be18 JR |
525 | } |
526 | ||
d586d785 | 527 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
528 | { |
529 | int i; | |
530 | ||
d586d785 JR |
531 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
532 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 533 | continue; |
d586d785 JR |
534 | |
535 | iommu_queue_inv_dev_entry(iommu, i); | |
536 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
537 | } |
538 | } | |
539 | ||
6a0dbcbe | 540 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
541 | { |
542 | struct amd_iommu *iommu; | |
543 | int i; | |
544 | ||
545 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
546 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
547 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
548 | continue; |
549 | ||
550 | iommu = amd_iommu_rlookup_table[i]; | |
551 | if (!iommu) | |
552 | continue; | |
553 | ||
554 | iommu_queue_inv_dev_entry(iommu, i); | |
555 | iommu_completion_wait(iommu); | |
556 | } | |
557 | } | |
558 | ||
a345b23b JR |
559 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
560 | { | |
561 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
562 | ||
b26e81b8 JR |
563 | if (iommu->reset_in_progress) |
564 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
565 | ||
566 | iommu->reset_in_progress = true; | |
567 | ||
a345b23b JR |
568 | amd_iommu_reset_cmd_buffer(iommu); |
569 | flush_all_devices_for_iommu(iommu); | |
570 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
571 | |
572 | iommu->reset_in_progress = false; | |
a345b23b JR |
573 | } |
574 | ||
6a0dbcbe JR |
575 | void amd_iommu_flush_all_devices(void) |
576 | { | |
577 | flush_devices_by_domain(NULL); | |
578 | } | |
579 | ||
431b2a20 JR |
580 | /**************************************************************************** |
581 | * | |
582 | * The functions below are used the create the page table mappings for | |
583 | * unity mapped regions. | |
584 | * | |
585 | ****************************************************************************/ | |
586 | ||
587 | /* | |
588 | * Generic mapping functions. It maps a physical address into a DMA | |
589 | * address space. It allocates the page table pages if necessary. | |
590 | * In the future it can be extended to a generic mapping function | |
591 | * supporting all features of AMD IOMMU page tables like level skipping | |
592 | * and full 64 bit address spaces. | |
593 | */ | |
38e817fe JR |
594 | static int iommu_map_page(struct protection_domain *dom, |
595 | unsigned long bus_addr, | |
596 | unsigned long phys_addr, | |
abdc5eb3 JR |
597 | int prot, |
598 | int map_size) | |
bd0e5211 | 599 | { |
8bda3092 | 600 | u64 __pte, *pte; |
bd0e5211 JR |
601 | |
602 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 603 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 604 | |
abdc5eb3 JR |
605 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
606 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
607 | ||
bad1cac2 | 608 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
609 | return -EINVAL; |
610 | ||
abdc5eb3 | 611 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
612 | |
613 | if (IOMMU_PTE_PRESENT(*pte)) | |
614 | return -EBUSY; | |
615 | ||
616 | __pte = phys_addr | IOMMU_PTE_P; | |
617 | if (prot & IOMMU_PROT_IR) | |
618 | __pte |= IOMMU_PTE_IR; | |
619 | if (prot & IOMMU_PROT_IW) | |
620 | __pte |= IOMMU_PTE_IW; | |
621 | ||
622 | *pte = __pte; | |
623 | ||
04bfdd84 JR |
624 | update_domain(dom); |
625 | ||
bd0e5211 JR |
626 | return 0; |
627 | } | |
628 | ||
eb74ff6c | 629 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 630 | unsigned long bus_addr, int map_size) |
eb74ff6c | 631 | { |
a6b256b4 | 632 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 633 | |
38a76eee JR |
634 | if (pte) |
635 | *pte = 0; | |
eb74ff6c | 636 | } |
eb74ff6c | 637 | |
431b2a20 JR |
638 | /* |
639 | * This function checks if a specific unity mapping entry is needed for | |
640 | * this specific IOMMU. | |
641 | */ | |
bd0e5211 JR |
642 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
643 | struct unity_map_entry *entry) | |
644 | { | |
645 | u16 bdf, i; | |
646 | ||
647 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
648 | bdf = amd_iommu_alias_table[i]; | |
649 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
650 | return 1; | |
651 | } | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
431b2a20 JR |
656 | /* |
657 | * Init the unity mappings for a specific IOMMU in the system | |
658 | * | |
659 | * Basically iterates over all unity mapping entries and applies them to | |
660 | * the default domain DMA of that IOMMU if necessary. | |
661 | */ | |
bd0e5211 JR |
662 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
663 | { | |
664 | struct unity_map_entry *entry; | |
665 | int ret; | |
666 | ||
667 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
668 | if (!iommu_for_unity_map(iommu, entry)) | |
669 | continue; | |
670 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
671 | if (ret) | |
672 | return ret; | |
673 | } | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
431b2a20 JR |
678 | /* |
679 | * This function actually applies the mapping to the page table of the | |
680 | * dma_ops domain. | |
681 | */ | |
bd0e5211 JR |
682 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
683 | struct unity_map_entry *e) | |
684 | { | |
685 | u64 addr; | |
686 | int ret; | |
687 | ||
688 | for (addr = e->address_start; addr < e->address_end; | |
689 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
690 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
691 | PM_MAP_4k); | |
bd0e5211 JR |
692 | if (ret) |
693 | return ret; | |
694 | /* | |
695 | * if unity mapping is in aperture range mark the page | |
696 | * as allocated in the aperture | |
697 | */ | |
698 | if (addr < dma_dom->aperture_size) | |
c3239567 | 699 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 700 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
701 | } |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
431b2a20 JR |
706 | /* |
707 | * Inits the unity mappings required for a specific device | |
708 | */ | |
bd0e5211 JR |
709 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
710 | u16 devid) | |
711 | { | |
712 | struct unity_map_entry *e; | |
713 | int ret; | |
714 | ||
715 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
716 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
717 | continue; | |
718 | ret = dma_ops_unity_map(dma_dom, e); | |
719 | if (ret) | |
720 | return ret; | |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
431b2a20 JR |
726 | /**************************************************************************** |
727 | * | |
728 | * The next functions belong to the address allocator for the dma_ops | |
729 | * interface functions. They work like the allocators in the other IOMMU | |
730 | * drivers. Its basically a bitmap which marks the allocated pages in | |
731 | * the aperture. Maybe it could be enhanced in the future to a more | |
732 | * efficient allocator. | |
733 | * | |
734 | ****************************************************************************/ | |
d3086444 | 735 | |
431b2a20 | 736 | /* |
384de729 | 737 | * The address allocator core functions. |
431b2a20 JR |
738 | * |
739 | * called with domain->lock held | |
740 | */ | |
384de729 | 741 | |
00cd122a JR |
742 | /* |
743 | * This function checks if there is a PTE for a given dma address. If | |
744 | * there is one, it returns the pointer to it. | |
745 | */ | |
9355a081 | 746 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 747 | unsigned long address, int map_size) |
00cd122a | 748 | { |
9355a081 | 749 | int level; |
00cd122a JR |
750 | u64 *pte; |
751 | ||
9355a081 JR |
752 | level = domain->mode - 1; |
753 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 754 | |
a6b256b4 | 755 | while (level > map_size) { |
9355a081 JR |
756 | if (!IOMMU_PTE_PRESENT(*pte)) |
757 | return NULL; | |
00cd122a | 758 | |
9355a081 | 759 | level -= 1; |
00cd122a | 760 | |
9355a081 JR |
761 | pte = IOMMU_PTE_PAGE(*pte); |
762 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 763 | |
a6b256b4 JR |
764 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { |
765 | pte = NULL; | |
766 | break; | |
767 | } | |
9355a081 | 768 | } |
00cd122a JR |
769 | |
770 | return pte; | |
771 | } | |
772 | ||
9cabe89b JR |
773 | /* |
774 | * This function is used to add a new aperture range to an existing | |
775 | * aperture in case of dma_ops domain allocation or address allocation | |
776 | * failure. | |
777 | */ | |
00cd122a JR |
778 | static int alloc_new_range(struct amd_iommu *iommu, |
779 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
780 | bool populate, gfp_t gfp) |
781 | { | |
782 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 783 | int i; |
9cabe89b | 784 | |
f5e9705c JR |
785 | #ifdef CONFIG_IOMMU_STRESS |
786 | populate = false; | |
787 | #endif | |
788 | ||
9cabe89b JR |
789 | if (index >= APERTURE_MAX_RANGES) |
790 | return -ENOMEM; | |
791 | ||
792 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
793 | if (!dma_dom->aperture[index]) | |
794 | return -ENOMEM; | |
795 | ||
796 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
797 | if (!dma_dom->aperture[index]->bitmap) | |
798 | goto out_free; | |
799 | ||
800 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
801 | ||
802 | if (populate) { | |
803 | unsigned long address = dma_dom->aperture_size; | |
804 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
805 | u64 *pte, *pte_page; | |
806 | ||
807 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 808 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
809 | &pte_page, gfp); |
810 | if (!pte) | |
811 | goto out_free; | |
812 | ||
813 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
814 | ||
815 | address += APERTURE_RANGE_SIZE / 64; | |
816 | } | |
817 | } | |
818 | ||
819 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
820 | ||
00cd122a JR |
821 | /* Intialize the exclusion range if necessary */ |
822 | if (iommu->exclusion_start && | |
823 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
824 | iommu->exclusion_start < dma_dom->aperture_size) { | |
825 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
826 | int pages = iommu_num_pages(iommu->exclusion_start, | |
827 | iommu->exclusion_length, | |
828 | PAGE_SIZE); | |
829 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
830 | } | |
831 | ||
832 | /* | |
833 | * Check for areas already mapped as present in the new aperture | |
834 | * range and mark those pages as reserved in the allocator. Such | |
835 | * mappings may already exist as a result of requested unity | |
836 | * mappings for devices. | |
837 | */ | |
838 | for (i = dma_dom->aperture[index]->offset; | |
839 | i < dma_dom->aperture_size; | |
840 | i += PAGE_SIZE) { | |
a6b256b4 | 841 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
842 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
843 | continue; | |
844 | ||
845 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
846 | } | |
847 | ||
04bfdd84 JR |
848 | update_domain(&dma_dom->domain); |
849 | ||
9cabe89b JR |
850 | return 0; |
851 | ||
852 | out_free: | |
04bfdd84 JR |
853 | update_domain(&dma_dom->domain); |
854 | ||
9cabe89b JR |
855 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
856 | ||
857 | kfree(dma_dom->aperture[index]); | |
858 | dma_dom->aperture[index] = NULL; | |
859 | ||
860 | return -ENOMEM; | |
861 | } | |
862 | ||
384de729 JR |
863 | static unsigned long dma_ops_area_alloc(struct device *dev, |
864 | struct dma_ops_domain *dom, | |
865 | unsigned int pages, | |
866 | unsigned long align_mask, | |
867 | u64 dma_mask, | |
868 | unsigned long start) | |
869 | { | |
803b8cb4 | 870 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
871 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
872 | int i = start >> APERTURE_RANGE_SHIFT; | |
873 | unsigned long boundary_size; | |
874 | unsigned long address = -1; | |
875 | unsigned long limit; | |
876 | ||
803b8cb4 JR |
877 | next_bit >>= PAGE_SHIFT; |
878 | ||
384de729 JR |
879 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
880 | PAGE_SIZE) >> PAGE_SHIFT; | |
881 | ||
882 | for (;i < max_index; ++i) { | |
883 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
884 | ||
885 | if (dom->aperture[i]->offset >= dma_mask) | |
886 | break; | |
887 | ||
888 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
889 | dma_mask >> PAGE_SHIFT); | |
890 | ||
891 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
892 | limit, next_bit, pages, 0, | |
893 | boundary_size, align_mask); | |
894 | if (address != -1) { | |
895 | address = dom->aperture[i]->offset + | |
896 | (address << PAGE_SHIFT); | |
803b8cb4 | 897 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
898 | break; |
899 | } | |
900 | ||
901 | next_bit = 0; | |
902 | } | |
903 | ||
904 | return address; | |
905 | } | |
906 | ||
d3086444 JR |
907 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
908 | struct dma_ops_domain *dom, | |
6d4f343f | 909 | unsigned int pages, |
832a90c3 JR |
910 | unsigned long align_mask, |
911 | u64 dma_mask) | |
d3086444 | 912 | { |
d3086444 | 913 | unsigned long address; |
d3086444 | 914 | |
fe16f088 JR |
915 | #ifdef CONFIG_IOMMU_STRESS |
916 | dom->next_address = 0; | |
917 | dom->need_flush = true; | |
918 | #endif | |
d3086444 | 919 | |
384de729 | 920 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 921 | dma_mask, dom->next_address); |
d3086444 | 922 | |
1c655773 | 923 | if (address == -1) { |
803b8cb4 | 924 | dom->next_address = 0; |
384de729 JR |
925 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
926 | dma_mask, 0); | |
1c655773 JR |
927 | dom->need_flush = true; |
928 | } | |
d3086444 | 929 | |
384de729 | 930 | if (unlikely(address == -1)) |
d3086444 JR |
931 | address = bad_dma_address; |
932 | ||
933 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
934 | ||
935 | return address; | |
936 | } | |
937 | ||
431b2a20 JR |
938 | /* |
939 | * The address free function. | |
940 | * | |
941 | * called with domain->lock held | |
942 | */ | |
d3086444 JR |
943 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
944 | unsigned long address, | |
945 | unsigned int pages) | |
946 | { | |
384de729 JR |
947 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
948 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 949 | |
384de729 JR |
950 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
951 | ||
47bccd6b JR |
952 | #ifdef CONFIG_IOMMU_STRESS |
953 | if (i < 4) | |
954 | return; | |
955 | #endif | |
80be308d | 956 | |
803b8cb4 | 957 | if (address >= dom->next_address) |
80be308d | 958 | dom->need_flush = true; |
384de729 JR |
959 | |
960 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 961 | |
384de729 JR |
962 | iommu_area_free(range->bitmap, address, pages); |
963 | ||
d3086444 JR |
964 | } |
965 | ||
431b2a20 JR |
966 | /**************************************************************************** |
967 | * | |
968 | * The next functions belong to the domain allocation. A domain is | |
969 | * allocated for every IOMMU as the default domain. If device isolation | |
970 | * is enabled, every device get its own domain. The most important thing | |
971 | * about domains is the page table mapping the DMA address space they | |
972 | * contain. | |
973 | * | |
974 | ****************************************************************************/ | |
975 | ||
ec487d1a JR |
976 | static u16 domain_id_alloc(void) |
977 | { | |
978 | unsigned long flags; | |
979 | int id; | |
980 | ||
981 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
982 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
983 | BUG_ON(id == 0); | |
984 | if (id > 0 && id < MAX_DOMAIN_ID) | |
985 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
986 | else | |
987 | id = 0; | |
988 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
989 | ||
990 | return id; | |
991 | } | |
992 | ||
a2acfb75 JR |
993 | static void domain_id_free(int id) |
994 | { | |
995 | unsigned long flags; | |
996 | ||
997 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
998 | if (id > 0 && id < MAX_DOMAIN_ID) | |
999 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1000 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1001 | } | |
a2acfb75 | 1002 | |
431b2a20 JR |
1003 | /* |
1004 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1005 | * ranges. | |
1006 | */ | |
ec487d1a JR |
1007 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
1008 | unsigned long start_page, | |
1009 | unsigned int pages) | |
1010 | { | |
384de729 | 1011 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
1012 | |
1013 | if (start_page + pages > last_page) | |
1014 | pages = last_page - start_page; | |
1015 | ||
384de729 JR |
1016 | for (i = start_page; i < start_page + pages; ++i) { |
1017 | int index = i / APERTURE_RANGE_PAGES; | |
1018 | int page = i % APERTURE_RANGE_PAGES; | |
1019 | __set_bit(page, dom->aperture[index]->bitmap); | |
1020 | } | |
ec487d1a JR |
1021 | } |
1022 | ||
86db2e5d | 1023 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1024 | { |
1025 | int i, j; | |
1026 | u64 *p1, *p2, *p3; | |
1027 | ||
86db2e5d | 1028 | p1 = domain->pt_root; |
ec487d1a JR |
1029 | |
1030 | if (!p1) | |
1031 | return; | |
1032 | ||
1033 | for (i = 0; i < 512; ++i) { | |
1034 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1035 | continue; | |
1036 | ||
1037 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1038 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1039 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1040 | continue; | |
1041 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1042 | free_page((unsigned long)p3); | |
1043 | } | |
1044 | ||
1045 | free_page((unsigned long)p2); | |
1046 | } | |
1047 | ||
1048 | free_page((unsigned long)p1); | |
86db2e5d JR |
1049 | |
1050 | domain->pt_root = NULL; | |
ec487d1a JR |
1051 | } |
1052 | ||
431b2a20 JR |
1053 | /* |
1054 | * Free a domain, only used if something went wrong in the | |
1055 | * allocation path and we need to free an already allocated page table | |
1056 | */ | |
ec487d1a JR |
1057 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1058 | { | |
384de729 JR |
1059 | int i; |
1060 | ||
ec487d1a JR |
1061 | if (!dom) |
1062 | return; | |
1063 | ||
86db2e5d | 1064 | free_pagetable(&dom->domain); |
ec487d1a | 1065 | |
384de729 JR |
1066 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1067 | if (!dom->aperture[i]) | |
1068 | continue; | |
1069 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1070 | kfree(dom->aperture[i]); | |
1071 | } | |
ec487d1a JR |
1072 | |
1073 | kfree(dom); | |
1074 | } | |
1075 | ||
431b2a20 JR |
1076 | /* |
1077 | * Allocates a new protection domain usable for the dma_ops functions. | |
1078 | * It also intializes the page table and the address allocator data | |
1079 | * structures required for the dma_ops interface | |
1080 | */ | |
d9cfed92 | 1081 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1082 | { |
1083 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1084 | |
1085 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1086 | if (!dma_dom) | |
1087 | return NULL; | |
1088 | ||
1089 | spin_lock_init(&dma_dom->domain.lock); | |
1090 | ||
1091 | dma_dom->domain.id = domain_id_alloc(); | |
1092 | if (dma_dom->domain.id == 0) | |
1093 | goto free_dma_dom; | |
8f7a017c | 1094 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1095 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1096 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1097 | dma_dom->domain.priv = dma_dom; |
1098 | if (!dma_dom->domain.pt_root) | |
1099 | goto free_dma_dom; | |
ec487d1a | 1100 | |
1c655773 | 1101 | dma_dom->need_flush = false; |
bd60b735 | 1102 | dma_dom->target_dev = 0xffff; |
1c655773 | 1103 | |
00cd122a | 1104 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1105 | goto free_dma_dom; |
ec487d1a | 1106 | |
431b2a20 | 1107 | /* |
ec487d1a JR |
1108 | * mark the first page as allocated so we never return 0 as |
1109 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1110 | */ |
384de729 | 1111 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1112 | dma_dom->next_address = 0; |
ec487d1a | 1113 | |
ec487d1a JR |
1114 | |
1115 | return dma_dom; | |
1116 | ||
1117 | free_dma_dom: | |
1118 | dma_ops_domain_free(dma_dom); | |
1119 | ||
1120 | return NULL; | |
1121 | } | |
1122 | ||
5b28df6f JR |
1123 | /* |
1124 | * little helper function to check whether a given protection domain is a | |
1125 | * dma_ops domain | |
1126 | */ | |
1127 | static bool dma_ops_domain(struct protection_domain *domain) | |
1128 | { | |
1129 | return domain->flags & PD_DMA_OPS_MASK; | |
1130 | } | |
1131 | ||
431b2a20 JR |
1132 | /* |
1133 | * Find out the protection domain structure for a given PCI device. This | |
1134 | * will give us the pointer to the page table root for example. | |
1135 | */ | |
b20ac0d4 JR |
1136 | static struct protection_domain *domain_for_device(u16 devid) |
1137 | { | |
1138 | struct protection_domain *dom; | |
1139 | unsigned long flags; | |
1140 | ||
1141 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1142 | dom = amd_iommu_pd_table[devid]; | |
1143 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1144 | ||
1145 | return dom; | |
1146 | } | |
1147 | ||
407d733e | 1148 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1149 | { |
b20ac0d4 | 1150 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1151 | |
38ddf41b JR |
1152 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1153 | << DEV_ENTRY_MODE_SHIFT; | |
1154 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1155 | |
b20ac0d4 | 1156 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1157 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1158 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1159 | |
1160 | amd_iommu_pd_table[devid] = domain; | |
2b681faf JR |
1161 | } |
1162 | ||
1163 | /* | |
1164 | * If a device is not yet associated with a domain, this function does | |
1165 | * assigns it visible for the hardware | |
1166 | */ | |
1167 | static void __attach_device(struct amd_iommu *iommu, | |
1168 | struct protection_domain *domain, | |
1169 | u16 devid) | |
1170 | { | |
1171 | /* lock domain */ | |
1172 | spin_lock(&domain->lock); | |
1173 | ||
1174 | /* update DTE entry */ | |
1175 | set_dte_entry(devid, domain); | |
eba6ac60 JR |
1176 | |
1177 | domain->dev_cnt += 1; | |
1178 | ||
1179 | /* ready */ | |
1180 | spin_unlock(&domain->lock); | |
0feae533 | 1181 | } |
b20ac0d4 | 1182 | |
407d733e JR |
1183 | /* |
1184 | * If a device is not yet associated with a domain, this function does | |
1185 | * assigns it visible for the hardware | |
1186 | */ | |
0feae533 JR |
1187 | static void attach_device(struct amd_iommu *iommu, |
1188 | struct protection_domain *domain, | |
1189 | u16 devid) | |
1190 | { | |
eba6ac60 JR |
1191 | unsigned long flags; |
1192 | ||
1193 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
0feae533 | 1194 | __attach_device(iommu, domain, devid); |
b20ac0d4 JR |
1195 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1196 | ||
0feae533 JR |
1197 | /* |
1198 | * We might boot into a crash-kernel here. The crashed kernel | |
1199 | * left the caches in the IOMMU dirty. So we have to flush | |
1200 | * here to evict all dirty stuff. | |
1201 | */ | |
b20ac0d4 | 1202 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1203 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1204 | } |
1205 | ||
355bf553 JR |
1206 | /* |
1207 | * Removes a device from a protection domain (unlocked) | |
1208 | */ | |
1209 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1210 | { | |
1211 | ||
1212 | /* lock domain */ | |
1213 | spin_lock(&domain->lock); | |
1214 | ||
1215 | /* remove domain from the lookup table */ | |
1216 | amd_iommu_pd_table[devid] = NULL; | |
1217 | ||
1218 | /* remove entry from the device table seen by the hardware */ | |
1219 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1220 | amd_iommu_dev_table[devid].data[1] = 0; | |
1221 | amd_iommu_dev_table[devid].data[2] = 0; | |
1222 | ||
1223 | /* decrease reference counter */ | |
1224 | domain->dev_cnt -= 1; | |
1225 | ||
1226 | /* ready */ | |
1227 | spin_unlock(&domain->lock); | |
21129f78 JR |
1228 | |
1229 | /* | |
1230 | * If we run in passthrough mode the device must be assigned to the | |
1231 | * passthrough domain if it is detached from any other domain | |
1232 | */ | |
1233 | if (iommu_pass_through) { | |
1234 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1235 | __attach_device(iommu, pt_domain, devid); | |
1236 | } | |
355bf553 JR |
1237 | } |
1238 | ||
1239 | /* | |
1240 | * Removes a device from a protection domain (with devtable_lock held) | |
1241 | */ | |
1242 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1243 | { | |
1244 | unsigned long flags; | |
1245 | ||
1246 | /* lock device table */ | |
1247 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1248 | __detach_device(domain, devid); | |
1249 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1250 | } | |
e275a2a0 JR |
1251 | |
1252 | static int device_change_notifier(struct notifier_block *nb, | |
1253 | unsigned long action, void *data) | |
1254 | { | |
1255 | struct device *dev = data; | |
1256 | struct pci_dev *pdev = to_pci_dev(dev); | |
1257 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1258 | struct protection_domain *domain; | |
1259 | struct dma_ops_domain *dma_domain; | |
1260 | struct amd_iommu *iommu; | |
1ac4cbbc | 1261 | unsigned long flags; |
e275a2a0 JR |
1262 | |
1263 | if (devid > amd_iommu_last_bdf) | |
1264 | goto out; | |
1265 | ||
1266 | devid = amd_iommu_alias_table[devid]; | |
1267 | ||
1268 | iommu = amd_iommu_rlookup_table[devid]; | |
1269 | if (iommu == NULL) | |
1270 | goto out; | |
1271 | ||
1272 | domain = domain_for_device(devid); | |
1273 | ||
1274 | if (domain && !dma_ops_domain(domain)) | |
1275 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1276 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1277 | ||
1278 | switch (action) { | |
c1eee67b | 1279 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1280 | if (!domain) |
1281 | goto out; | |
a1ca331c JR |
1282 | if (iommu_pass_through) |
1283 | break; | |
e275a2a0 | 1284 | detach_device(domain, devid); |
1ac4cbbc JR |
1285 | break; |
1286 | case BUS_NOTIFY_ADD_DEVICE: | |
1287 | /* allocate a protection domain if a device is added */ | |
1288 | dma_domain = find_protection_domain(devid); | |
1289 | if (dma_domain) | |
1290 | goto out; | |
d9cfed92 | 1291 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1292 | if (!dma_domain) |
1293 | goto out; | |
1294 | dma_domain->target_dev = devid; | |
1295 | ||
1296 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1297 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1298 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1299 | ||
e275a2a0 JR |
1300 | break; |
1301 | default: | |
1302 | goto out; | |
1303 | } | |
1304 | ||
1305 | iommu_queue_inv_dev_entry(iommu, devid); | |
1306 | iommu_completion_wait(iommu); | |
1307 | ||
1308 | out: | |
1309 | return 0; | |
1310 | } | |
1311 | ||
b25ae679 | 1312 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1313 | .notifier_call = device_change_notifier, |
1314 | }; | |
355bf553 | 1315 | |
431b2a20 JR |
1316 | /***************************************************************************** |
1317 | * | |
1318 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1319 | * | |
1320 | *****************************************************************************/ | |
1321 | ||
dbcc112e JR |
1322 | /* |
1323 | * This function checks if the driver got a valid device from the caller to | |
1324 | * avoid dereferencing invalid pointers. | |
1325 | */ | |
1326 | static bool check_device(struct device *dev) | |
1327 | { | |
1328 | if (!dev || !dev->dma_mask) | |
1329 | return false; | |
1330 | ||
1331 | return true; | |
1332 | } | |
1333 | ||
bd60b735 JR |
1334 | /* |
1335 | * In this function the list of preallocated protection domains is traversed to | |
1336 | * find the domain for a specific device | |
1337 | */ | |
1338 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1339 | { | |
1340 | struct dma_ops_domain *entry, *ret = NULL; | |
1341 | unsigned long flags; | |
1342 | ||
1343 | if (list_empty(&iommu_pd_list)) | |
1344 | return NULL; | |
1345 | ||
1346 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1347 | ||
1348 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1349 | if (entry->target_dev == devid) { | |
1350 | ret = entry; | |
bd60b735 JR |
1351 | break; |
1352 | } | |
1353 | } | |
1354 | ||
1355 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1356 | ||
1357 | return ret; | |
1358 | } | |
1359 | ||
431b2a20 JR |
1360 | /* |
1361 | * In the dma_ops path we only have the struct device. This function | |
1362 | * finds the corresponding IOMMU, the protection domain and the | |
1363 | * requestor id for a given device. | |
1364 | * If the device is not yet associated with a domain this is also done | |
1365 | * in this function. | |
1366 | */ | |
b20ac0d4 JR |
1367 | static int get_device_resources(struct device *dev, |
1368 | struct amd_iommu **iommu, | |
1369 | struct protection_domain **domain, | |
1370 | u16 *bdf) | |
1371 | { | |
1372 | struct dma_ops_domain *dma_dom; | |
1373 | struct pci_dev *pcidev; | |
1374 | u16 _bdf; | |
1375 | ||
dbcc112e JR |
1376 | *iommu = NULL; |
1377 | *domain = NULL; | |
1378 | *bdf = 0xffff; | |
1379 | ||
1380 | if (dev->bus != &pci_bus_type) | |
1381 | return 0; | |
b20ac0d4 JR |
1382 | |
1383 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1384 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1385 | |
431b2a20 | 1386 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1387 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1388 | return 0; |
b20ac0d4 JR |
1389 | |
1390 | *bdf = amd_iommu_alias_table[_bdf]; | |
1391 | ||
1392 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1393 | if (*iommu == NULL) | |
1394 | return 0; | |
b20ac0d4 JR |
1395 | *domain = domain_for_device(*bdf); |
1396 | if (*domain == NULL) { | |
bd60b735 JR |
1397 | dma_dom = find_protection_domain(*bdf); |
1398 | if (!dma_dom) | |
1399 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1400 | *domain = &dma_dom->domain; |
f1179dc0 | 1401 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1402 | DUMP_printk("Using protection domain %d for device %s\n", |
1403 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1404 | } |
1405 | ||
f91ba190 | 1406 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1407 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1408 | |
b20ac0d4 JR |
1409 | return 1; |
1410 | } | |
1411 | ||
04bfdd84 JR |
1412 | static void update_device_table(struct protection_domain *domain) |
1413 | { | |
2b681faf | 1414 | unsigned long flags; |
04bfdd84 JR |
1415 | int i; |
1416 | ||
1417 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1418 | if (amd_iommu_pd_table[i] != domain) | |
1419 | continue; | |
2b681faf | 1420 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1421 | set_dte_entry(i, domain); |
2b681faf | 1422 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1423 | } |
1424 | } | |
1425 | ||
1426 | static void update_domain(struct protection_domain *domain) | |
1427 | { | |
1428 | if (!domain->updated) | |
1429 | return; | |
1430 | ||
1431 | update_device_table(domain); | |
1432 | flush_devices_by_domain(domain); | |
1433 | iommu_flush_domain(domain->id); | |
1434 | ||
1435 | domain->updated = false; | |
1436 | } | |
1437 | ||
8bda3092 | 1438 | /* |
50020fb6 JR |
1439 | * This function is used to add another level to an IO page table. Adding |
1440 | * another level increases the size of the address space by 9 bits to a size up | |
1441 | * to 64 bits. | |
8bda3092 | 1442 | */ |
50020fb6 JR |
1443 | static bool increase_address_space(struct protection_domain *domain, |
1444 | gfp_t gfp) | |
1445 | { | |
1446 | u64 *pte; | |
1447 | ||
1448 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1449 | /* address space already 64 bit large */ | |
1450 | return false; | |
1451 | ||
1452 | pte = (void *)get_zeroed_page(gfp); | |
1453 | if (!pte) | |
1454 | return false; | |
1455 | ||
1456 | *pte = PM_LEVEL_PDE(domain->mode, | |
1457 | virt_to_phys(domain->pt_root)); | |
1458 | domain->pt_root = pte; | |
1459 | domain->mode += 1; | |
1460 | domain->updated = true; | |
1461 | ||
1462 | return true; | |
1463 | } | |
1464 | ||
8bc3e127 | 1465 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
1466 | unsigned long address, |
1467 | int end_lvl, | |
1468 | u64 **pte_page, | |
1469 | gfp_t gfp) | |
8bda3092 JR |
1470 | { |
1471 | u64 *pte, *page; | |
8bc3e127 | 1472 | int level; |
8bda3092 | 1473 | |
8bc3e127 JR |
1474 | while (address > PM_LEVEL_SIZE(domain->mode)) |
1475 | increase_address_space(domain, gfp); | |
8bda3092 | 1476 | |
8bc3e127 JR |
1477 | level = domain->mode - 1; |
1478 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
8bda3092 | 1479 | |
abdc5eb3 | 1480 | while (level > end_lvl) { |
8bc3e127 JR |
1481 | if (!IOMMU_PTE_PRESENT(*pte)) { |
1482 | page = (u64 *)get_zeroed_page(gfp); | |
1483 | if (!page) | |
1484 | return NULL; | |
1485 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1486 | } | |
8bda3092 | 1487 | |
8bc3e127 | 1488 | level -= 1; |
8bda3092 | 1489 | |
8bc3e127 | 1490 | pte = IOMMU_PTE_PAGE(*pte); |
8bda3092 | 1491 | |
abdc5eb3 | 1492 | if (pte_page && level == end_lvl) |
8bc3e127 | 1493 | *pte_page = pte; |
8bda3092 | 1494 | |
8bc3e127 JR |
1495 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
1496 | } | |
8bda3092 JR |
1497 | |
1498 | return pte; | |
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * This function fetches the PTE for a given address in the aperture | |
1503 | */ | |
1504 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1505 | unsigned long address) | |
1506 | { | |
384de729 | 1507 | struct aperture_range *aperture; |
8bda3092 JR |
1508 | u64 *pte, *pte_page; |
1509 | ||
384de729 JR |
1510 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1511 | if (!aperture) | |
1512 | return NULL; | |
1513 | ||
1514 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1515 | if (!pte) { |
abdc5eb3 JR |
1516 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1517 | GFP_ATOMIC); | |
384de729 JR |
1518 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1519 | } else | |
8c8c143c | 1520 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1521 | |
04bfdd84 | 1522 | update_domain(&dom->domain); |
8bda3092 JR |
1523 | |
1524 | return pte; | |
1525 | } | |
1526 | ||
431b2a20 JR |
1527 | /* |
1528 | * This is the generic map function. It maps one 4kb page at paddr to | |
1529 | * the given address in the DMA address space for the domain. | |
1530 | */ | |
cb76c322 JR |
1531 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1532 | struct dma_ops_domain *dom, | |
1533 | unsigned long address, | |
1534 | phys_addr_t paddr, | |
1535 | int direction) | |
1536 | { | |
1537 | u64 *pte, __pte; | |
1538 | ||
1539 | WARN_ON(address > dom->aperture_size); | |
1540 | ||
1541 | paddr &= PAGE_MASK; | |
1542 | ||
8bda3092 | 1543 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1544 | if (!pte) |
1545 | return bad_dma_address; | |
cb76c322 JR |
1546 | |
1547 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1548 | ||
1549 | if (direction == DMA_TO_DEVICE) | |
1550 | __pte |= IOMMU_PTE_IR; | |
1551 | else if (direction == DMA_FROM_DEVICE) | |
1552 | __pte |= IOMMU_PTE_IW; | |
1553 | else if (direction == DMA_BIDIRECTIONAL) | |
1554 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1555 | ||
1556 | WARN_ON(*pte); | |
1557 | ||
1558 | *pte = __pte; | |
1559 | ||
1560 | return (dma_addr_t)address; | |
1561 | } | |
1562 | ||
431b2a20 JR |
1563 | /* |
1564 | * The generic unmapping function for on page in the DMA address space. | |
1565 | */ | |
cb76c322 JR |
1566 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1567 | struct dma_ops_domain *dom, | |
1568 | unsigned long address) | |
1569 | { | |
384de729 | 1570 | struct aperture_range *aperture; |
cb76c322 JR |
1571 | u64 *pte; |
1572 | ||
1573 | if (address >= dom->aperture_size) | |
1574 | return; | |
1575 | ||
384de729 JR |
1576 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1577 | if (!aperture) | |
1578 | return; | |
1579 | ||
1580 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1581 | if (!pte) | |
1582 | return; | |
cb76c322 | 1583 | |
8c8c143c | 1584 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1585 | |
1586 | WARN_ON(!*pte); | |
1587 | ||
1588 | *pte = 0ULL; | |
1589 | } | |
1590 | ||
431b2a20 JR |
1591 | /* |
1592 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1593 | * contiguous memory region into DMA address space. It is used by all |
1594 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1595 | * Must be called with the domain lock held. |
1596 | */ | |
cb76c322 JR |
1597 | static dma_addr_t __map_single(struct device *dev, |
1598 | struct amd_iommu *iommu, | |
1599 | struct dma_ops_domain *dma_dom, | |
1600 | phys_addr_t paddr, | |
1601 | size_t size, | |
6d4f343f | 1602 | int dir, |
832a90c3 JR |
1603 | bool align, |
1604 | u64 dma_mask) | |
cb76c322 JR |
1605 | { |
1606 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1607 | dma_addr_t address, start, ret; |
cb76c322 | 1608 | unsigned int pages; |
6d4f343f | 1609 | unsigned long align_mask = 0; |
cb76c322 JR |
1610 | int i; |
1611 | ||
e3c449f5 | 1612 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1613 | paddr &= PAGE_MASK; |
1614 | ||
8ecaf8f1 JR |
1615 | INC_STATS_COUNTER(total_map_requests); |
1616 | ||
c1858976 JR |
1617 | if (pages > 1) |
1618 | INC_STATS_COUNTER(cross_page); | |
1619 | ||
6d4f343f JR |
1620 | if (align) |
1621 | align_mask = (1UL << get_order(size)) - 1; | |
1622 | ||
11b83888 | 1623 | retry: |
832a90c3 JR |
1624 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1625 | dma_mask); | |
11b83888 JR |
1626 | if (unlikely(address == bad_dma_address)) { |
1627 | /* | |
1628 | * setting next_address here will let the address | |
1629 | * allocator only scan the new allocated range in the | |
1630 | * first run. This is a small optimization. | |
1631 | */ | |
1632 | dma_dom->next_address = dma_dom->aperture_size; | |
1633 | ||
1634 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1635 | goto out; | |
1636 | ||
1637 | /* | |
1638 | * aperture was sucessfully enlarged by 128 MB, try | |
1639 | * allocation again | |
1640 | */ | |
1641 | goto retry; | |
1642 | } | |
cb76c322 JR |
1643 | |
1644 | start = address; | |
1645 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1646 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1647 | if (ret == bad_dma_address) | |
1648 | goto out_unmap; | |
1649 | ||
cb76c322 JR |
1650 | paddr += PAGE_SIZE; |
1651 | start += PAGE_SIZE; | |
1652 | } | |
1653 | address += offset; | |
1654 | ||
5774f7c5 JR |
1655 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1656 | ||
afa9fdc2 | 1657 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1658 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1659 | dma_dom->need_flush = false; | |
1660 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1661 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1662 | ||
cb76c322 JR |
1663 | out: |
1664 | return address; | |
53812c11 JR |
1665 | |
1666 | out_unmap: | |
1667 | ||
1668 | for (--i; i >= 0; --i) { | |
1669 | start -= PAGE_SIZE; | |
1670 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1671 | } | |
1672 | ||
1673 | dma_ops_free_addresses(dma_dom, address, pages); | |
1674 | ||
1675 | return bad_dma_address; | |
cb76c322 JR |
1676 | } |
1677 | ||
431b2a20 JR |
1678 | /* |
1679 | * Does the reverse of the __map_single function. Must be called with | |
1680 | * the domain lock held too | |
1681 | */ | |
cb76c322 JR |
1682 | static void __unmap_single(struct amd_iommu *iommu, |
1683 | struct dma_ops_domain *dma_dom, | |
1684 | dma_addr_t dma_addr, | |
1685 | size_t size, | |
1686 | int dir) | |
1687 | { | |
1688 | dma_addr_t i, start; | |
1689 | unsigned int pages; | |
1690 | ||
b8d9905d JR |
1691 | if ((dma_addr == bad_dma_address) || |
1692 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1693 | return; |
1694 | ||
e3c449f5 | 1695 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1696 | dma_addr &= PAGE_MASK; |
1697 | start = dma_addr; | |
1698 | ||
1699 | for (i = 0; i < pages; ++i) { | |
1700 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1701 | start += PAGE_SIZE; | |
1702 | } | |
1703 | ||
5774f7c5 JR |
1704 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1705 | ||
cb76c322 | 1706 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1707 | |
80be308d | 1708 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1709 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1710 | dma_dom->need_flush = false; |
1711 | } | |
cb76c322 JR |
1712 | } |
1713 | ||
431b2a20 JR |
1714 | /* |
1715 | * The exported map_single function for dma_ops. | |
1716 | */ | |
51491367 FT |
1717 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1718 | unsigned long offset, size_t size, | |
1719 | enum dma_data_direction dir, | |
1720 | struct dma_attrs *attrs) | |
4da70b9e JR |
1721 | { |
1722 | unsigned long flags; | |
1723 | struct amd_iommu *iommu; | |
1724 | struct protection_domain *domain; | |
1725 | u16 devid; | |
1726 | dma_addr_t addr; | |
832a90c3 | 1727 | u64 dma_mask; |
51491367 | 1728 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1729 | |
0f2a86f2 JR |
1730 | INC_STATS_COUNTER(cnt_map_single); |
1731 | ||
dbcc112e JR |
1732 | if (!check_device(dev)) |
1733 | return bad_dma_address; | |
1734 | ||
832a90c3 | 1735 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1736 | |
1737 | get_device_resources(dev, &iommu, &domain, &devid); | |
1738 | ||
1739 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1740 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1741 | return (dma_addr_t)paddr; |
1742 | ||
5b28df6f JR |
1743 | if (!dma_ops_domain(domain)) |
1744 | return bad_dma_address; | |
1745 | ||
4da70b9e | 1746 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1747 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1748 | dma_mask); | |
4da70b9e JR |
1749 | if (addr == bad_dma_address) |
1750 | goto out; | |
1751 | ||
09ee17eb | 1752 | iommu_completion_wait(iommu); |
4da70b9e JR |
1753 | |
1754 | out: | |
1755 | spin_unlock_irqrestore(&domain->lock, flags); | |
1756 | ||
1757 | return addr; | |
1758 | } | |
1759 | ||
431b2a20 JR |
1760 | /* |
1761 | * The exported unmap_single function for dma_ops. | |
1762 | */ | |
51491367 FT |
1763 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1764 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1765 | { |
1766 | unsigned long flags; | |
1767 | struct amd_iommu *iommu; | |
1768 | struct protection_domain *domain; | |
1769 | u16 devid; | |
1770 | ||
146a6917 JR |
1771 | INC_STATS_COUNTER(cnt_unmap_single); |
1772 | ||
dbcc112e JR |
1773 | if (!check_device(dev) || |
1774 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1775 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1776 | return; |
1777 | ||
5b28df6f JR |
1778 | if (!dma_ops_domain(domain)) |
1779 | return; | |
1780 | ||
4da70b9e JR |
1781 | spin_lock_irqsave(&domain->lock, flags); |
1782 | ||
1783 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1784 | ||
09ee17eb | 1785 | iommu_completion_wait(iommu); |
4da70b9e JR |
1786 | |
1787 | spin_unlock_irqrestore(&domain->lock, flags); | |
1788 | } | |
1789 | ||
431b2a20 JR |
1790 | /* |
1791 | * This is a special map_sg function which is used if we should map a | |
1792 | * device which is not handled by an AMD IOMMU in the system. | |
1793 | */ | |
65b050ad JR |
1794 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1795 | int nelems, int dir) | |
1796 | { | |
1797 | struct scatterlist *s; | |
1798 | int i; | |
1799 | ||
1800 | for_each_sg(sglist, s, nelems, i) { | |
1801 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1802 | s->dma_length = s->length; | |
1803 | } | |
1804 | ||
1805 | return nelems; | |
1806 | } | |
1807 | ||
431b2a20 JR |
1808 | /* |
1809 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1810 | * lists). | |
1811 | */ | |
65b050ad | 1812 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1813 | int nelems, enum dma_data_direction dir, |
1814 | struct dma_attrs *attrs) | |
65b050ad JR |
1815 | { |
1816 | unsigned long flags; | |
1817 | struct amd_iommu *iommu; | |
1818 | struct protection_domain *domain; | |
1819 | u16 devid; | |
1820 | int i; | |
1821 | struct scatterlist *s; | |
1822 | phys_addr_t paddr; | |
1823 | int mapped_elems = 0; | |
832a90c3 | 1824 | u64 dma_mask; |
65b050ad | 1825 | |
d03f067a JR |
1826 | INC_STATS_COUNTER(cnt_map_sg); |
1827 | ||
dbcc112e JR |
1828 | if (!check_device(dev)) |
1829 | return 0; | |
1830 | ||
832a90c3 | 1831 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1832 | |
1833 | get_device_resources(dev, &iommu, &domain, &devid); | |
1834 | ||
1835 | if (!iommu || !domain) | |
1836 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1837 | ||
5b28df6f JR |
1838 | if (!dma_ops_domain(domain)) |
1839 | return 0; | |
1840 | ||
65b050ad JR |
1841 | spin_lock_irqsave(&domain->lock, flags); |
1842 | ||
1843 | for_each_sg(sglist, s, nelems, i) { | |
1844 | paddr = sg_phys(s); | |
1845 | ||
1846 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1847 | paddr, s->length, dir, false, |
1848 | dma_mask); | |
65b050ad JR |
1849 | |
1850 | if (s->dma_address) { | |
1851 | s->dma_length = s->length; | |
1852 | mapped_elems++; | |
1853 | } else | |
1854 | goto unmap; | |
65b050ad JR |
1855 | } |
1856 | ||
09ee17eb | 1857 | iommu_completion_wait(iommu); |
65b050ad JR |
1858 | |
1859 | out: | |
1860 | spin_unlock_irqrestore(&domain->lock, flags); | |
1861 | ||
1862 | return mapped_elems; | |
1863 | unmap: | |
1864 | for_each_sg(sglist, s, mapped_elems, i) { | |
1865 | if (s->dma_address) | |
1866 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1867 | s->dma_length, dir); | |
1868 | s->dma_address = s->dma_length = 0; | |
1869 | } | |
1870 | ||
1871 | mapped_elems = 0; | |
1872 | ||
1873 | goto out; | |
1874 | } | |
1875 | ||
431b2a20 JR |
1876 | /* |
1877 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1878 | * lists). | |
1879 | */ | |
65b050ad | 1880 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1881 | int nelems, enum dma_data_direction dir, |
1882 | struct dma_attrs *attrs) | |
65b050ad JR |
1883 | { |
1884 | unsigned long flags; | |
1885 | struct amd_iommu *iommu; | |
1886 | struct protection_domain *domain; | |
1887 | struct scatterlist *s; | |
1888 | u16 devid; | |
1889 | int i; | |
1890 | ||
55877a6b JR |
1891 | INC_STATS_COUNTER(cnt_unmap_sg); |
1892 | ||
dbcc112e JR |
1893 | if (!check_device(dev) || |
1894 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1895 | return; |
1896 | ||
5b28df6f JR |
1897 | if (!dma_ops_domain(domain)) |
1898 | return; | |
1899 | ||
65b050ad JR |
1900 | spin_lock_irqsave(&domain->lock, flags); |
1901 | ||
1902 | for_each_sg(sglist, s, nelems, i) { | |
1903 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1904 | s->dma_length, dir); | |
65b050ad JR |
1905 | s->dma_address = s->dma_length = 0; |
1906 | } | |
1907 | ||
09ee17eb | 1908 | iommu_completion_wait(iommu); |
65b050ad JR |
1909 | |
1910 | spin_unlock_irqrestore(&domain->lock, flags); | |
1911 | } | |
1912 | ||
431b2a20 JR |
1913 | /* |
1914 | * The exported alloc_coherent function for dma_ops. | |
1915 | */ | |
5d8b53cf JR |
1916 | static void *alloc_coherent(struct device *dev, size_t size, |
1917 | dma_addr_t *dma_addr, gfp_t flag) | |
1918 | { | |
1919 | unsigned long flags; | |
1920 | void *virt_addr; | |
1921 | struct amd_iommu *iommu; | |
1922 | struct protection_domain *domain; | |
1923 | u16 devid; | |
1924 | phys_addr_t paddr; | |
832a90c3 | 1925 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1926 | |
c8f0fb36 JR |
1927 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1928 | ||
dbcc112e JR |
1929 | if (!check_device(dev)) |
1930 | return NULL; | |
5d8b53cf | 1931 | |
13d9fead FT |
1932 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1933 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1934 | |
c97ac535 | 1935 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1936 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1937 | if (!virt_addr) | |
b25ae679 | 1938 | return NULL; |
5d8b53cf | 1939 | |
5d8b53cf JR |
1940 | paddr = virt_to_phys(virt_addr); |
1941 | ||
5d8b53cf JR |
1942 | if (!iommu || !domain) { |
1943 | *dma_addr = (dma_addr_t)paddr; | |
1944 | return virt_addr; | |
1945 | } | |
1946 | ||
5b28df6f JR |
1947 | if (!dma_ops_domain(domain)) |
1948 | goto out_free; | |
1949 | ||
832a90c3 JR |
1950 | if (!dma_mask) |
1951 | dma_mask = *dev->dma_mask; | |
1952 | ||
5d8b53cf JR |
1953 | spin_lock_irqsave(&domain->lock, flags); |
1954 | ||
1955 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1956 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1957 | |
367d04c4 JS |
1958 | if (*dma_addr == bad_dma_address) { |
1959 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1960 | goto out_free; |
367d04c4 | 1961 | } |
5d8b53cf | 1962 | |
09ee17eb | 1963 | iommu_completion_wait(iommu); |
5d8b53cf | 1964 | |
5d8b53cf JR |
1965 | spin_unlock_irqrestore(&domain->lock, flags); |
1966 | ||
1967 | return virt_addr; | |
5b28df6f JR |
1968 | |
1969 | out_free: | |
1970 | ||
1971 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1972 | ||
1973 | return NULL; | |
5d8b53cf JR |
1974 | } |
1975 | ||
431b2a20 JR |
1976 | /* |
1977 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1978 | */ |
5d8b53cf JR |
1979 | static void free_coherent(struct device *dev, size_t size, |
1980 | void *virt_addr, dma_addr_t dma_addr) | |
1981 | { | |
1982 | unsigned long flags; | |
1983 | struct amd_iommu *iommu; | |
1984 | struct protection_domain *domain; | |
1985 | u16 devid; | |
1986 | ||
5d31ee7e JR |
1987 | INC_STATS_COUNTER(cnt_free_coherent); |
1988 | ||
dbcc112e JR |
1989 | if (!check_device(dev)) |
1990 | return; | |
1991 | ||
5d8b53cf JR |
1992 | get_device_resources(dev, &iommu, &domain, &devid); |
1993 | ||
1994 | if (!iommu || !domain) | |
1995 | goto free_mem; | |
1996 | ||
5b28df6f JR |
1997 | if (!dma_ops_domain(domain)) |
1998 | goto free_mem; | |
1999 | ||
5d8b53cf JR |
2000 | spin_lock_irqsave(&domain->lock, flags); |
2001 | ||
2002 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2003 | |
09ee17eb | 2004 | iommu_completion_wait(iommu); |
5d8b53cf JR |
2005 | |
2006 | spin_unlock_irqrestore(&domain->lock, flags); | |
2007 | ||
2008 | free_mem: | |
2009 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2010 | } | |
2011 | ||
b39ba6ad JR |
2012 | /* |
2013 | * This function is called by the DMA layer to find out if we can handle a | |
2014 | * particular device. It is part of the dma_ops. | |
2015 | */ | |
2016 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2017 | { | |
2018 | u16 bdf; | |
2019 | struct pci_dev *pcidev; | |
2020 | ||
2021 | /* No device or no PCI device */ | |
2022 | if (!dev || dev->bus != &pci_bus_type) | |
2023 | return 0; | |
2024 | ||
2025 | pcidev = to_pci_dev(dev); | |
2026 | ||
2027 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
2028 | ||
2029 | /* Out of our scope? */ | |
2030 | if (bdf > amd_iommu_last_bdf) | |
2031 | return 0; | |
2032 | ||
2033 | return 1; | |
2034 | } | |
2035 | ||
c432f3df | 2036 | /* |
431b2a20 JR |
2037 | * The function for pre-allocating protection domains. |
2038 | * | |
c432f3df JR |
2039 | * If the driver core informs the DMA layer if a driver grabs a device |
2040 | * we don't need to preallocate the protection domains anymore. | |
2041 | * For now we have to. | |
2042 | */ | |
0e93dd88 | 2043 | static void prealloc_protection_domains(void) |
c432f3df JR |
2044 | { |
2045 | struct pci_dev *dev = NULL; | |
2046 | struct dma_ops_domain *dma_dom; | |
2047 | struct amd_iommu *iommu; | |
c432f3df JR |
2048 | u16 devid; |
2049 | ||
2050 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 2051 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 2052 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
2053 | continue; |
2054 | devid = amd_iommu_alias_table[devid]; | |
2055 | if (domain_for_device(devid)) | |
2056 | continue; | |
2057 | iommu = amd_iommu_rlookup_table[devid]; | |
2058 | if (!iommu) | |
2059 | continue; | |
d9cfed92 | 2060 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
2061 | if (!dma_dom) |
2062 | continue; | |
2063 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2064 | dma_dom->target_dev = devid; |
2065 | ||
2066 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
2067 | } |
2068 | } | |
2069 | ||
160c1d8e | 2070 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2071 | .alloc_coherent = alloc_coherent, |
2072 | .free_coherent = free_coherent, | |
51491367 FT |
2073 | .map_page = map_page, |
2074 | .unmap_page = unmap_page, | |
6631ee9d JR |
2075 | .map_sg = map_sg, |
2076 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2077 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2078 | }; |
2079 | ||
431b2a20 JR |
2080 | /* |
2081 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2082 | */ | |
6631ee9d JR |
2083 | int __init amd_iommu_init_dma_ops(void) |
2084 | { | |
2085 | struct amd_iommu *iommu; | |
6631ee9d JR |
2086 | int ret; |
2087 | ||
431b2a20 JR |
2088 | /* |
2089 | * first allocate a default protection domain for every IOMMU we | |
2090 | * found in the system. Devices not assigned to any other | |
2091 | * protection domain will be assigned to the default one. | |
2092 | */ | |
3bd22172 | 2093 | for_each_iommu(iommu) { |
d9cfed92 | 2094 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
2095 | if (iommu->default_dom == NULL) |
2096 | return -ENOMEM; | |
e2dc14a2 | 2097 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2098 | ret = iommu_init_unity_mappings(iommu); |
2099 | if (ret) | |
2100 | goto free_domains; | |
2101 | } | |
2102 | ||
431b2a20 JR |
2103 | /* |
2104 | * If device isolation is enabled, pre-allocate the protection | |
2105 | * domains for each device. | |
2106 | */ | |
6631ee9d JR |
2107 | if (amd_iommu_isolate) |
2108 | prealloc_protection_domains(); | |
2109 | ||
2110 | iommu_detected = 1; | |
2111 | force_iommu = 1; | |
2112 | bad_dma_address = 0; | |
92af4e29 | 2113 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2114 | gart_iommu_aperture_disabled = 1; |
2115 | gart_iommu_aperture = 0; | |
92af4e29 | 2116 | #endif |
6631ee9d | 2117 | |
431b2a20 | 2118 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2119 | dma_ops = &amd_iommu_dma_ops; |
2120 | ||
26961efe | 2121 | register_iommu(&amd_iommu_ops); |
26961efe | 2122 | |
e275a2a0 JR |
2123 | bus_register_notifier(&pci_bus_type, &device_nb); |
2124 | ||
7f26508b JR |
2125 | amd_iommu_stats_init(); |
2126 | ||
6631ee9d JR |
2127 | return 0; |
2128 | ||
2129 | free_domains: | |
2130 | ||
3bd22172 | 2131 | for_each_iommu(iommu) { |
6631ee9d JR |
2132 | if (iommu->default_dom) |
2133 | dma_ops_domain_free(iommu->default_dom); | |
2134 | } | |
2135 | ||
2136 | return ret; | |
2137 | } | |
6d98cd80 JR |
2138 | |
2139 | /***************************************************************************** | |
2140 | * | |
2141 | * The following functions belong to the exported interface of AMD IOMMU | |
2142 | * | |
2143 | * This interface allows access to lower level functions of the IOMMU | |
2144 | * like protection domain handling and assignement of devices to domains | |
2145 | * which is not possible with the dma_ops interface. | |
2146 | * | |
2147 | *****************************************************************************/ | |
2148 | ||
6d98cd80 JR |
2149 | static void cleanup_domain(struct protection_domain *domain) |
2150 | { | |
2151 | unsigned long flags; | |
2152 | u16 devid; | |
2153 | ||
2154 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2155 | ||
2156 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2157 | if (amd_iommu_pd_table[devid] == domain) | |
2158 | __detach_device(domain, devid); | |
2159 | ||
2160 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2161 | } | |
2162 | ||
2650815f JR |
2163 | static void protection_domain_free(struct protection_domain *domain) |
2164 | { | |
2165 | if (!domain) | |
2166 | return; | |
2167 | ||
2168 | if (domain->id) | |
2169 | domain_id_free(domain->id); | |
2170 | ||
2171 | kfree(domain); | |
2172 | } | |
2173 | ||
2174 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2175 | { |
2176 | struct protection_domain *domain; | |
2177 | ||
2178 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2179 | if (!domain) | |
2650815f | 2180 | return NULL; |
c156e347 JR |
2181 | |
2182 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2183 | domain->id = domain_id_alloc(); |
2184 | if (!domain->id) | |
2650815f JR |
2185 | goto out_err; |
2186 | ||
2187 | return domain; | |
2188 | ||
2189 | out_err: | |
2190 | kfree(domain); | |
2191 | ||
2192 | return NULL; | |
2193 | } | |
2194 | ||
2195 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2196 | { | |
2197 | struct protection_domain *domain; | |
2198 | ||
2199 | domain = protection_domain_alloc(); | |
2200 | if (!domain) | |
c156e347 | 2201 | goto out_free; |
2650815f JR |
2202 | |
2203 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2204 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2205 | if (!domain->pt_root) | |
2206 | goto out_free; | |
2207 | ||
2208 | dom->priv = domain; | |
2209 | ||
2210 | return 0; | |
2211 | ||
2212 | out_free: | |
2650815f | 2213 | protection_domain_free(domain); |
c156e347 JR |
2214 | |
2215 | return -ENOMEM; | |
2216 | } | |
2217 | ||
98383fc3 JR |
2218 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2219 | { | |
2220 | struct protection_domain *domain = dom->priv; | |
2221 | ||
2222 | if (!domain) | |
2223 | return; | |
2224 | ||
2225 | if (domain->dev_cnt > 0) | |
2226 | cleanup_domain(domain); | |
2227 | ||
2228 | BUG_ON(domain->dev_cnt != 0); | |
2229 | ||
2230 | free_pagetable(domain); | |
2231 | ||
2232 | domain_id_free(domain->id); | |
2233 | ||
2234 | kfree(domain); | |
2235 | ||
2236 | dom->priv = NULL; | |
2237 | } | |
2238 | ||
684f2888 JR |
2239 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2240 | struct device *dev) | |
2241 | { | |
2242 | struct protection_domain *domain = dom->priv; | |
2243 | struct amd_iommu *iommu; | |
2244 | struct pci_dev *pdev; | |
2245 | u16 devid; | |
2246 | ||
2247 | if (dev->bus != &pci_bus_type) | |
2248 | return; | |
2249 | ||
2250 | pdev = to_pci_dev(dev); | |
2251 | ||
2252 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2253 | ||
2254 | if (devid > 0) | |
2255 | detach_device(domain, devid); | |
2256 | ||
2257 | iommu = amd_iommu_rlookup_table[devid]; | |
2258 | if (!iommu) | |
2259 | return; | |
2260 | ||
2261 | iommu_queue_inv_dev_entry(iommu, devid); | |
2262 | iommu_completion_wait(iommu); | |
2263 | } | |
2264 | ||
01106066 JR |
2265 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2266 | struct device *dev) | |
2267 | { | |
2268 | struct protection_domain *domain = dom->priv; | |
2269 | struct protection_domain *old_domain; | |
2270 | struct amd_iommu *iommu; | |
2271 | struct pci_dev *pdev; | |
2272 | u16 devid; | |
2273 | ||
2274 | if (dev->bus != &pci_bus_type) | |
2275 | return -EINVAL; | |
2276 | ||
2277 | pdev = to_pci_dev(dev); | |
2278 | ||
2279 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2280 | ||
2281 | if (devid >= amd_iommu_last_bdf || | |
2282 | devid != amd_iommu_alias_table[devid]) | |
2283 | return -EINVAL; | |
2284 | ||
2285 | iommu = amd_iommu_rlookup_table[devid]; | |
2286 | if (!iommu) | |
2287 | return -EINVAL; | |
2288 | ||
2289 | old_domain = domain_for_device(devid); | |
2290 | if (old_domain) | |
71ff3bca | 2291 | detach_device(old_domain, devid); |
01106066 JR |
2292 | |
2293 | attach_device(iommu, domain, devid); | |
2294 | ||
2295 | iommu_completion_wait(iommu); | |
2296 | ||
2297 | return 0; | |
2298 | } | |
2299 | ||
c6229ca6 JR |
2300 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2301 | unsigned long iova, phys_addr_t paddr, | |
2302 | size_t size, int iommu_prot) | |
2303 | { | |
2304 | struct protection_domain *domain = dom->priv; | |
2305 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2306 | int prot = 0; | |
2307 | int ret; | |
2308 | ||
2309 | if (iommu_prot & IOMMU_READ) | |
2310 | prot |= IOMMU_PROT_IR; | |
2311 | if (iommu_prot & IOMMU_WRITE) | |
2312 | prot |= IOMMU_PROT_IW; | |
2313 | ||
2314 | iova &= PAGE_MASK; | |
2315 | paddr &= PAGE_MASK; | |
2316 | ||
2317 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2318 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2319 | if (ret) |
2320 | return ret; | |
2321 | ||
2322 | iova += PAGE_SIZE; | |
2323 | paddr += PAGE_SIZE; | |
2324 | } | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
eb74ff6c JR |
2329 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2330 | unsigned long iova, size_t size) | |
2331 | { | |
2332 | ||
2333 | struct protection_domain *domain = dom->priv; | |
2334 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2335 | ||
2336 | iova &= PAGE_MASK; | |
2337 | ||
2338 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2339 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2340 | iova += PAGE_SIZE; |
2341 | } | |
2342 | ||
2343 | iommu_flush_domain(domain->id); | |
2344 | } | |
2345 | ||
645c4c8d JR |
2346 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2347 | unsigned long iova) | |
2348 | { | |
2349 | struct protection_domain *domain = dom->priv; | |
2350 | unsigned long offset = iova & ~PAGE_MASK; | |
2351 | phys_addr_t paddr; | |
2352 | u64 *pte; | |
2353 | ||
a6b256b4 | 2354 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2355 | |
a6d41a40 | 2356 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2357 | return 0; |
2358 | ||
2359 | paddr = *pte & IOMMU_PAGE_MASK; | |
2360 | paddr |= offset; | |
2361 | ||
2362 | return paddr; | |
2363 | } | |
2364 | ||
dbb9fd86 SY |
2365 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2366 | unsigned long cap) | |
2367 | { | |
2368 | return 0; | |
2369 | } | |
2370 | ||
26961efe JR |
2371 | static struct iommu_ops amd_iommu_ops = { |
2372 | .domain_init = amd_iommu_domain_init, | |
2373 | .domain_destroy = amd_iommu_domain_destroy, | |
2374 | .attach_dev = amd_iommu_attach_device, | |
2375 | .detach_dev = amd_iommu_detach_device, | |
2376 | .map = amd_iommu_map_range, | |
2377 | .unmap = amd_iommu_unmap_range, | |
2378 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2379 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2380 | }; |
2381 | ||
0feae533 JR |
2382 | /***************************************************************************** |
2383 | * | |
2384 | * The next functions do a basic initialization of IOMMU for pass through | |
2385 | * mode | |
2386 | * | |
2387 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2388 | * DMA-API translation. | |
2389 | * | |
2390 | *****************************************************************************/ | |
2391 | ||
2392 | int __init amd_iommu_init_passthrough(void) | |
2393 | { | |
2394 | struct pci_dev *dev = NULL; | |
2395 | u16 devid, devid2; | |
2396 | ||
2397 | /* allocate passthroug domain */ | |
2398 | pt_domain = protection_domain_alloc(); | |
2399 | if (!pt_domain) | |
2400 | return -ENOMEM; | |
2401 | ||
2402 | pt_domain->mode |= PAGE_MODE_NONE; | |
2403 | ||
2404 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2405 | struct amd_iommu *iommu; | |
2406 | ||
2407 | devid = calc_devid(dev->bus->number, dev->devfn); | |
2408 | if (devid > amd_iommu_last_bdf) | |
2409 | continue; | |
2410 | ||
2411 | devid2 = amd_iommu_alias_table[devid]; | |
2412 | ||
2413 | iommu = amd_iommu_rlookup_table[devid2]; | |
2414 | if (!iommu) | |
2415 | continue; | |
2416 | ||
2417 | __attach_device(iommu, pt_domain, devid); | |
2418 | __attach_device(iommu, pt_domain, devid2); | |
2419 | } | |
2420 | ||
2421 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2422 | ||
2423 | return 0; | |
2424 | } |