Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
b6c02715 | 27 | #include <asm/amd_iommu_types.h> |
c6da992e | 28 | #include <asm/amd_iommu.h> |
b6c02715 JR |
29 | |
30 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
31 | ||
136f78a1 JR |
32 | #define EXIT_LOOP_COUNT 10000000 |
33 | ||
b6c02715 JR |
34 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
35 | ||
431b2a20 JR |
36 | /* |
37 | * general struct to manage commands send to an IOMMU | |
38 | */ | |
d6449536 | 39 | struct iommu_cmd { |
b6c02715 JR |
40 | u32 data[4]; |
41 | }; | |
42 | ||
bd0e5211 JR |
43 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
44 | struct unity_map_entry *e); | |
45 | ||
431b2a20 | 46 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
47 | static int iommu_has_npcache(struct amd_iommu *iommu) |
48 | { | |
49 | return iommu->cap & IOMMU_CAP_NPCACHE; | |
50 | } | |
51 | ||
431b2a20 JR |
52 | /**************************************************************************** |
53 | * | |
54 | * IOMMU command queuing functions | |
55 | * | |
56 | ****************************************************************************/ | |
57 | ||
58 | /* | |
59 | * Writes the command to the IOMMUs command buffer and informs the | |
60 | * hardware about the new command. Must be called with iommu->lock held. | |
61 | */ | |
d6449536 | 62 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
63 | { |
64 | u32 tail, head; | |
65 | u8 *target; | |
66 | ||
67 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 68 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
69 | memcpy_toio(target, cmd, sizeof(*cmd)); |
70 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
71 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
72 | if (tail == head) | |
73 | return -ENOMEM; | |
74 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
431b2a20 JR |
79 | /* |
80 | * General queuing function for commands. Takes iommu->lock and calls | |
81 | * __iommu_queue_command(). | |
82 | */ | |
d6449536 | 83 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
84 | { |
85 | unsigned long flags; | |
86 | int ret; | |
87 | ||
88 | spin_lock_irqsave(&iommu->lock, flags); | |
89 | ret = __iommu_queue_command(iommu, cmd); | |
90 | spin_unlock_irqrestore(&iommu->lock, flags); | |
91 | ||
92 | return ret; | |
93 | } | |
94 | ||
431b2a20 JR |
95 | /* |
96 | * This function is called whenever we need to ensure that the IOMMU has | |
97 | * completed execution of all commands we sent. It sends a | |
98 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
99 | * us about that by writing a value to a physical address we pass with | |
100 | * the command. | |
101 | */ | |
a19ae1ec JR |
102 | static int iommu_completion_wait(struct amd_iommu *iommu) |
103 | { | |
519c31ba JR |
104 | int ret, ready = 0; |
105 | unsigned status = 0; | |
d6449536 | 106 | struct iommu_cmd cmd; |
136f78a1 | 107 | unsigned long i = 0; |
a19ae1ec JR |
108 | |
109 | memset(&cmd, 0, sizeof(cmd)); | |
519c31ba | 110 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; |
a19ae1ec JR |
111 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); |
112 | ||
113 | iommu->need_sync = 0; | |
114 | ||
115 | ret = iommu_queue_command(iommu, &cmd); | |
116 | ||
117 | if (ret) | |
118 | return ret; | |
119 | ||
136f78a1 JR |
120 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
121 | ++i; | |
519c31ba JR |
122 | /* wait for the bit to become one */ |
123 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
124 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
136f78a1 JR |
125 | } |
126 | ||
519c31ba JR |
127 | /* set bit back to zero */ |
128 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
129 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
130 | ||
136f78a1 JR |
131 | if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit())) |
132 | printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n"); | |
a19ae1ec JR |
133 | |
134 | return 0; | |
135 | } | |
136 | ||
431b2a20 JR |
137 | /* |
138 | * Command send function for invalidating a device table entry | |
139 | */ | |
a19ae1ec JR |
140 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
141 | { | |
d6449536 | 142 | struct iommu_cmd cmd; |
a19ae1ec JR |
143 | |
144 | BUG_ON(iommu == NULL); | |
145 | ||
146 | memset(&cmd, 0, sizeof(cmd)); | |
147 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
148 | cmd.data[0] = devid; | |
149 | ||
150 | iommu->need_sync = 1; | |
151 | ||
152 | return iommu_queue_command(iommu, &cmd); | |
153 | } | |
154 | ||
431b2a20 JR |
155 | /* |
156 | * Generic command send function for invalidaing TLB entries | |
157 | */ | |
a19ae1ec JR |
158 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
159 | u64 address, u16 domid, int pde, int s) | |
160 | { | |
d6449536 | 161 | struct iommu_cmd cmd; |
a19ae1ec JR |
162 | |
163 | memset(&cmd, 0, sizeof(cmd)); | |
164 | address &= PAGE_MASK; | |
165 | CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES); | |
166 | cmd.data[1] |= domid; | |
8a456695 | 167 | cmd.data[2] = lower_32_bits(address); |
8ea80d78 | 168 | cmd.data[3] = upper_32_bits(address); |
431b2a20 | 169 | if (s) /* size bit - we flush more than one 4kb page */ |
a19ae1ec | 170 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
431b2a20 | 171 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ |
a19ae1ec JR |
172 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
173 | ||
174 | iommu->need_sync = 1; | |
175 | ||
176 | return iommu_queue_command(iommu, &cmd); | |
177 | } | |
178 | ||
431b2a20 JR |
179 | /* |
180 | * TLB invalidation function which is called from the mapping functions. | |
181 | * It invalidates a single PTE if the range to flush is within a single | |
182 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
183 | */ | |
a19ae1ec JR |
184 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
185 | u64 address, size_t size) | |
186 | { | |
999ba417 | 187 | int s = 0; |
a8132e5f | 188 | unsigned pages = iommu_num_pages(address, size); |
a19ae1ec JR |
189 | |
190 | address &= PAGE_MASK; | |
191 | ||
999ba417 JR |
192 | if (pages > 1) { |
193 | /* | |
194 | * If we have to flush more than one page, flush all | |
195 | * TLB entries for this domain | |
196 | */ | |
197 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
198 | s = 1; | |
a19ae1ec JR |
199 | } |
200 | ||
999ba417 JR |
201 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
202 | ||
a19ae1ec JR |
203 | return 0; |
204 | } | |
b6c02715 | 205 | |
1c655773 JR |
206 | /* Flush the whole IO/TLB for a given protection domain */ |
207 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
208 | { | |
209 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
210 | ||
211 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
212 | } | |
213 | ||
431b2a20 JR |
214 | /**************************************************************************** |
215 | * | |
216 | * The functions below are used the create the page table mappings for | |
217 | * unity mapped regions. | |
218 | * | |
219 | ****************************************************************************/ | |
220 | ||
221 | /* | |
222 | * Generic mapping functions. It maps a physical address into a DMA | |
223 | * address space. It allocates the page table pages if necessary. | |
224 | * In the future it can be extended to a generic mapping function | |
225 | * supporting all features of AMD IOMMU page tables like level skipping | |
226 | * and full 64 bit address spaces. | |
227 | */ | |
bd0e5211 JR |
228 | static int iommu_map(struct protection_domain *dom, |
229 | unsigned long bus_addr, | |
230 | unsigned long phys_addr, | |
231 | int prot) | |
232 | { | |
233 | u64 __pte, *pte, *page; | |
234 | ||
235 | bus_addr = PAGE_ALIGN(bus_addr); | |
236 | phys_addr = PAGE_ALIGN(bus_addr); | |
237 | ||
238 | /* only support 512GB address spaces for now */ | |
239 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
240 | return -EINVAL; | |
241 | ||
242 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
243 | ||
244 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
245 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
246 | if (!page) | |
247 | return -ENOMEM; | |
248 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
249 | } | |
250 | ||
251 | pte = IOMMU_PTE_PAGE(*pte); | |
252 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
253 | ||
254 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
255 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
256 | if (!page) | |
257 | return -ENOMEM; | |
258 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
259 | } | |
260 | ||
261 | pte = IOMMU_PTE_PAGE(*pte); | |
262 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
263 | ||
264 | if (IOMMU_PTE_PRESENT(*pte)) | |
265 | return -EBUSY; | |
266 | ||
267 | __pte = phys_addr | IOMMU_PTE_P; | |
268 | if (prot & IOMMU_PROT_IR) | |
269 | __pte |= IOMMU_PTE_IR; | |
270 | if (prot & IOMMU_PROT_IW) | |
271 | __pte |= IOMMU_PTE_IW; | |
272 | ||
273 | *pte = __pte; | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
431b2a20 JR |
278 | /* |
279 | * This function checks if a specific unity mapping entry is needed for | |
280 | * this specific IOMMU. | |
281 | */ | |
bd0e5211 JR |
282 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
283 | struct unity_map_entry *entry) | |
284 | { | |
285 | u16 bdf, i; | |
286 | ||
287 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
288 | bdf = amd_iommu_alias_table[i]; | |
289 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
290 | return 1; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
431b2a20 JR |
296 | /* |
297 | * Init the unity mappings for a specific IOMMU in the system | |
298 | * | |
299 | * Basically iterates over all unity mapping entries and applies them to | |
300 | * the default domain DMA of that IOMMU if necessary. | |
301 | */ | |
bd0e5211 JR |
302 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
303 | { | |
304 | struct unity_map_entry *entry; | |
305 | int ret; | |
306 | ||
307 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
308 | if (!iommu_for_unity_map(iommu, entry)) | |
309 | continue; | |
310 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
311 | if (ret) | |
312 | return ret; | |
313 | } | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
431b2a20 JR |
318 | /* |
319 | * This function actually applies the mapping to the page table of the | |
320 | * dma_ops domain. | |
321 | */ | |
bd0e5211 JR |
322 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
323 | struct unity_map_entry *e) | |
324 | { | |
325 | u64 addr; | |
326 | int ret; | |
327 | ||
328 | for (addr = e->address_start; addr < e->address_end; | |
329 | addr += PAGE_SIZE) { | |
330 | ret = iommu_map(&dma_dom->domain, addr, addr, e->prot); | |
331 | if (ret) | |
332 | return ret; | |
333 | /* | |
334 | * if unity mapping is in aperture range mark the page | |
335 | * as allocated in the aperture | |
336 | */ | |
337 | if (addr < dma_dom->aperture_size) | |
338 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
431b2a20 JR |
344 | /* |
345 | * Inits the unity mappings required for a specific device | |
346 | */ | |
bd0e5211 JR |
347 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
348 | u16 devid) | |
349 | { | |
350 | struct unity_map_entry *e; | |
351 | int ret; | |
352 | ||
353 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
354 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
355 | continue; | |
356 | ret = dma_ops_unity_map(dma_dom, e); | |
357 | if (ret) | |
358 | return ret; | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
431b2a20 JR |
364 | /**************************************************************************** |
365 | * | |
366 | * The next functions belong to the address allocator for the dma_ops | |
367 | * interface functions. They work like the allocators in the other IOMMU | |
368 | * drivers. Its basically a bitmap which marks the allocated pages in | |
369 | * the aperture. Maybe it could be enhanced in the future to a more | |
370 | * efficient allocator. | |
371 | * | |
372 | ****************************************************************************/ | |
d3086444 JR |
373 | static unsigned long dma_mask_to_pages(unsigned long mask) |
374 | { | |
375 | return (mask >> PAGE_SHIFT) + | |
376 | (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT); | |
377 | } | |
378 | ||
431b2a20 JR |
379 | /* |
380 | * The address allocator core function. | |
381 | * | |
382 | * called with domain->lock held | |
383 | */ | |
d3086444 JR |
384 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
385 | struct dma_ops_domain *dom, | |
6d4f343f JR |
386 | unsigned int pages, |
387 | unsigned long align_mask) | |
d3086444 JR |
388 | { |
389 | unsigned long limit = dma_mask_to_pages(*dev->dma_mask); | |
390 | unsigned long address; | |
391 | unsigned long size = dom->aperture_size >> PAGE_SHIFT; | |
392 | unsigned long boundary_size; | |
393 | ||
394 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
395 | PAGE_SIZE) >> PAGE_SHIFT; | |
396 | limit = limit < size ? limit : size; | |
397 | ||
1c655773 | 398 | if (dom->next_bit >= limit) { |
d3086444 | 399 | dom->next_bit = 0; |
1c655773 JR |
400 | dom->need_flush = true; |
401 | } | |
d3086444 JR |
402 | |
403 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 404 | 0 , boundary_size, align_mask); |
1c655773 | 405 | if (address == -1) { |
d3086444 | 406 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 407 | 0, boundary_size, align_mask); |
1c655773 JR |
408 | dom->need_flush = true; |
409 | } | |
d3086444 JR |
410 | |
411 | if (likely(address != -1)) { | |
d3086444 JR |
412 | dom->next_bit = address + pages; |
413 | address <<= PAGE_SHIFT; | |
414 | } else | |
415 | address = bad_dma_address; | |
416 | ||
417 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
418 | ||
419 | return address; | |
420 | } | |
421 | ||
431b2a20 JR |
422 | /* |
423 | * The address free function. | |
424 | * | |
425 | * called with domain->lock held | |
426 | */ | |
d3086444 JR |
427 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
428 | unsigned long address, | |
429 | unsigned int pages) | |
430 | { | |
431 | address >>= PAGE_SHIFT; | |
432 | iommu_area_free(dom->bitmap, address, pages); | |
433 | } | |
434 | ||
431b2a20 JR |
435 | /**************************************************************************** |
436 | * | |
437 | * The next functions belong to the domain allocation. A domain is | |
438 | * allocated for every IOMMU as the default domain. If device isolation | |
439 | * is enabled, every device get its own domain. The most important thing | |
440 | * about domains is the page table mapping the DMA address space they | |
441 | * contain. | |
442 | * | |
443 | ****************************************************************************/ | |
444 | ||
ec487d1a JR |
445 | static u16 domain_id_alloc(void) |
446 | { | |
447 | unsigned long flags; | |
448 | int id; | |
449 | ||
450 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
451 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
452 | BUG_ON(id == 0); | |
453 | if (id > 0 && id < MAX_DOMAIN_ID) | |
454 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
455 | else | |
456 | id = 0; | |
457 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
458 | ||
459 | return id; | |
460 | } | |
461 | ||
431b2a20 JR |
462 | /* |
463 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
464 | * ranges. | |
465 | */ | |
ec487d1a JR |
466 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
467 | unsigned long start_page, | |
468 | unsigned int pages) | |
469 | { | |
470 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
471 | ||
472 | if (start_page + pages > last_page) | |
473 | pages = last_page - start_page; | |
474 | ||
475 | set_bit_string(dom->bitmap, start_page, pages); | |
476 | } | |
477 | ||
478 | static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom) | |
479 | { | |
480 | int i, j; | |
481 | u64 *p1, *p2, *p3; | |
482 | ||
483 | p1 = dma_dom->domain.pt_root; | |
484 | ||
485 | if (!p1) | |
486 | return; | |
487 | ||
488 | for (i = 0; i < 512; ++i) { | |
489 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
490 | continue; | |
491 | ||
492 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
493 | for (j = 0; j < 512; ++i) { | |
494 | if (!IOMMU_PTE_PRESENT(p2[j])) | |
495 | continue; | |
496 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
497 | free_page((unsigned long)p3); | |
498 | } | |
499 | ||
500 | free_page((unsigned long)p2); | |
501 | } | |
502 | ||
503 | free_page((unsigned long)p1); | |
504 | } | |
505 | ||
431b2a20 JR |
506 | /* |
507 | * Free a domain, only used if something went wrong in the | |
508 | * allocation path and we need to free an already allocated page table | |
509 | */ | |
ec487d1a JR |
510 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
511 | { | |
512 | if (!dom) | |
513 | return; | |
514 | ||
515 | dma_ops_free_pagetable(dom); | |
516 | ||
517 | kfree(dom->pte_pages); | |
518 | ||
519 | kfree(dom->bitmap); | |
520 | ||
521 | kfree(dom); | |
522 | } | |
523 | ||
431b2a20 JR |
524 | /* |
525 | * Allocates a new protection domain usable for the dma_ops functions. | |
526 | * It also intializes the page table and the address allocator data | |
527 | * structures required for the dma_ops interface | |
528 | */ | |
ec487d1a JR |
529 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
530 | unsigned order) | |
531 | { | |
532 | struct dma_ops_domain *dma_dom; | |
533 | unsigned i, num_pte_pages; | |
534 | u64 *l2_pde; | |
535 | u64 address; | |
536 | ||
537 | /* | |
538 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
539 | */ | |
540 | if ((order < 25) || (order > 30)) | |
541 | return NULL; | |
542 | ||
543 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
544 | if (!dma_dom) | |
545 | return NULL; | |
546 | ||
547 | spin_lock_init(&dma_dom->domain.lock); | |
548 | ||
549 | dma_dom->domain.id = domain_id_alloc(); | |
550 | if (dma_dom->domain.id == 0) | |
551 | goto free_dma_dom; | |
552 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
553 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
554 | dma_dom->domain.priv = dma_dom; | |
555 | if (!dma_dom->domain.pt_root) | |
556 | goto free_dma_dom; | |
557 | dma_dom->aperture_size = (1ULL << order); | |
558 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
559 | GFP_KERNEL); | |
560 | if (!dma_dom->bitmap) | |
561 | goto free_dma_dom; | |
562 | /* | |
563 | * mark the first page as allocated so we never return 0 as | |
564 | * a valid dma-address. So we can use 0 as error value | |
565 | */ | |
566 | dma_dom->bitmap[0] = 1; | |
567 | dma_dom->next_bit = 0; | |
568 | ||
1c655773 JR |
569 | dma_dom->need_flush = false; |
570 | ||
431b2a20 | 571 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
572 | if (iommu->exclusion_start && |
573 | iommu->exclusion_start < dma_dom->aperture_size) { | |
574 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
a8132e5f JR |
575 | int pages = iommu_num_pages(iommu->exclusion_start, |
576 | iommu->exclusion_length); | |
ec487d1a JR |
577 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
578 | } | |
579 | ||
431b2a20 JR |
580 | /* |
581 | * At the last step, build the page tables so we don't need to | |
582 | * allocate page table pages in the dma_ops mapping/unmapping | |
583 | * path. | |
584 | */ | |
ec487d1a JR |
585 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
586 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
587 | GFP_KERNEL); | |
588 | if (!dma_dom->pte_pages) | |
589 | goto free_dma_dom; | |
590 | ||
591 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
592 | if (l2_pde == NULL) | |
593 | goto free_dma_dom; | |
594 | ||
595 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
596 | ||
597 | for (i = 0; i < num_pte_pages; ++i) { | |
598 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
599 | if (!dma_dom->pte_pages[i]) | |
600 | goto free_dma_dom; | |
601 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
602 | l2_pde[i] = IOMMU_L1_PDE(address); | |
603 | } | |
604 | ||
605 | return dma_dom; | |
606 | ||
607 | free_dma_dom: | |
608 | dma_ops_domain_free(dma_dom); | |
609 | ||
610 | return NULL; | |
611 | } | |
612 | ||
431b2a20 JR |
613 | /* |
614 | * Find out the protection domain structure for a given PCI device. This | |
615 | * will give us the pointer to the page table root for example. | |
616 | */ | |
b20ac0d4 JR |
617 | static struct protection_domain *domain_for_device(u16 devid) |
618 | { | |
619 | struct protection_domain *dom; | |
620 | unsigned long flags; | |
621 | ||
622 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
623 | dom = amd_iommu_pd_table[devid]; | |
624 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
625 | ||
626 | return dom; | |
627 | } | |
628 | ||
431b2a20 JR |
629 | /* |
630 | * If a device is not yet associated with a domain, this function does | |
631 | * assigns it visible for the hardware | |
632 | */ | |
b20ac0d4 JR |
633 | static void set_device_domain(struct amd_iommu *iommu, |
634 | struct protection_domain *domain, | |
635 | u16 devid) | |
636 | { | |
637 | unsigned long flags; | |
638 | ||
639 | u64 pte_root = virt_to_phys(domain->pt_root); | |
640 | ||
641 | pte_root |= (domain->mode & 0x07) << 9; | |
642 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2; | |
643 | ||
644 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
645 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
646 | amd_iommu_dev_table[devid].data[1] = pte_root >> 32; | |
647 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
648 | ||
649 | amd_iommu_pd_table[devid] = domain; | |
650 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
651 | ||
652 | iommu_queue_inv_dev_entry(iommu, devid); | |
653 | ||
654 | iommu->need_sync = 1; | |
655 | } | |
656 | ||
431b2a20 JR |
657 | /***************************************************************************** |
658 | * | |
659 | * The next functions belong to the dma_ops mapping/unmapping code. | |
660 | * | |
661 | *****************************************************************************/ | |
662 | ||
dbcc112e JR |
663 | /* |
664 | * This function checks if the driver got a valid device from the caller to | |
665 | * avoid dereferencing invalid pointers. | |
666 | */ | |
667 | static bool check_device(struct device *dev) | |
668 | { | |
669 | if (!dev || !dev->dma_mask) | |
670 | return false; | |
671 | ||
672 | return true; | |
673 | } | |
674 | ||
431b2a20 JR |
675 | /* |
676 | * In the dma_ops path we only have the struct device. This function | |
677 | * finds the corresponding IOMMU, the protection domain and the | |
678 | * requestor id for a given device. | |
679 | * If the device is not yet associated with a domain this is also done | |
680 | * in this function. | |
681 | */ | |
b20ac0d4 JR |
682 | static int get_device_resources(struct device *dev, |
683 | struct amd_iommu **iommu, | |
684 | struct protection_domain **domain, | |
685 | u16 *bdf) | |
686 | { | |
687 | struct dma_ops_domain *dma_dom; | |
688 | struct pci_dev *pcidev; | |
689 | u16 _bdf; | |
690 | ||
dbcc112e JR |
691 | *iommu = NULL; |
692 | *domain = NULL; | |
693 | *bdf = 0xffff; | |
694 | ||
695 | if (dev->bus != &pci_bus_type) | |
696 | return 0; | |
b20ac0d4 JR |
697 | |
698 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 699 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 700 | |
431b2a20 | 701 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 702 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 703 | return 0; |
b20ac0d4 JR |
704 | |
705 | *bdf = amd_iommu_alias_table[_bdf]; | |
706 | ||
707 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
708 | if (*iommu == NULL) | |
709 | return 0; | |
710 | dma_dom = (*iommu)->default_dom; | |
711 | *domain = domain_for_device(*bdf); | |
712 | if (*domain == NULL) { | |
713 | *domain = &dma_dom->domain; | |
714 | set_device_domain(*iommu, *domain, *bdf); | |
715 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
716 | "device ", (*domain)->id); | |
717 | print_devid(_bdf, 1); | |
718 | } | |
719 | ||
720 | return 1; | |
721 | } | |
722 | ||
431b2a20 JR |
723 | /* |
724 | * This is the generic map function. It maps one 4kb page at paddr to | |
725 | * the given address in the DMA address space for the domain. | |
726 | */ | |
cb76c322 JR |
727 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
728 | struct dma_ops_domain *dom, | |
729 | unsigned long address, | |
730 | phys_addr_t paddr, | |
731 | int direction) | |
732 | { | |
733 | u64 *pte, __pte; | |
734 | ||
735 | WARN_ON(address > dom->aperture_size); | |
736 | ||
737 | paddr &= PAGE_MASK; | |
738 | ||
739 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
740 | pte += IOMMU_PTE_L0_INDEX(address); | |
741 | ||
742 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
743 | ||
744 | if (direction == DMA_TO_DEVICE) | |
745 | __pte |= IOMMU_PTE_IR; | |
746 | else if (direction == DMA_FROM_DEVICE) | |
747 | __pte |= IOMMU_PTE_IW; | |
748 | else if (direction == DMA_BIDIRECTIONAL) | |
749 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
750 | ||
751 | WARN_ON(*pte); | |
752 | ||
753 | *pte = __pte; | |
754 | ||
755 | return (dma_addr_t)address; | |
756 | } | |
757 | ||
431b2a20 JR |
758 | /* |
759 | * The generic unmapping function for on page in the DMA address space. | |
760 | */ | |
cb76c322 JR |
761 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
762 | struct dma_ops_domain *dom, | |
763 | unsigned long address) | |
764 | { | |
765 | u64 *pte; | |
766 | ||
767 | if (address >= dom->aperture_size) | |
768 | return; | |
769 | ||
770 | WARN_ON(address & 0xfffULL || address > dom->aperture_size); | |
771 | ||
772 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
773 | pte += IOMMU_PTE_L0_INDEX(address); | |
774 | ||
775 | WARN_ON(!*pte); | |
776 | ||
777 | *pte = 0ULL; | |
778 | } | |
779 | ||
431b2a20 JR |
780 | /* |
781 | * This function contains common code for mapping of a physically | |
782 | * contiguous memory region into DMA address space. It is uses by all | |
783 | * mapping functions provided by this IOMMU driver. | |
784 | * Must be called with the domain lock held. | |
785 | */ | |
cb76c322 JR |
786 | static dma_addr_t __map_single(struct device *dev, |
787 | struct amd_iommu *iommu, | |
788 | struct dma_ops_domain *dma_dom, | |
789 | phys_addr_t paddr, | |
790 | size_t size, | |
6d4f343f JR |
791 | int dir, |
792 | bool align) | |
cb76c322 JR |
793 | { |
794 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
795 | dma_addr_t address, start; | |
796 | unsigned int pages; | |
6d4f343f | 797 | unsigned long align_mask = 0; |
cb76c322 JR |
798 | int i; |
799 | ||
a8132e5f | 800 | pages = iommu_num_pages(paddr, size); |
cb76c322 JR |
801 | paddr &= PAGE_MASK; |
802 | ||
6d4f343f JR |
803 | if (align) |
804 | align_mask = (1UL << get_order(size)) - 1; | |
805 | ||
806 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask); | |
cb76c322 JR |
807 | if (unlikely(address == bad_dma_address)) |
808 | goto out; | |
809 | ||
810 | start = address; | |
811 | for (i = 0; i < pages; ++i) { | |
812 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
813 | paddr += PAGE_SIZE; | |
814 | start += PAGE_SIZE; | |
815 | } | |
816 | address += offset; | |
817 | ||
1c655773 JR |
818 | if (unlikely(dma_dom->need_flush && !iommu_fullflush)) { |
819 | iommu_flush_tlb(iommu, dma_dom->domain.id); | |
820 | dma_dom->need_flush = false; | |
821 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
822 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
823 | ||
cb76c322 JR |
824 | out: |
825 | return address; | |
826 | } | |
827 | ||
431b2a20 JR |
828 | /* |
829 | * Does the reverse of the __map_single function. Must be called with | |
830 | * the domain lock held too | |
831 | */ | |
cb76c322 JR |
832 | static void __unmap_single(struct amd_iommu *iommu, |
833 | struct dma_ops_domain *dma_dom, | |
834 | dma_addr_t dma_addr, | |
835 | size_t size, | |
836 | int dir) | |
837 | { | |
838 | dma_addr_t i, start; | |
839 | unsigned int pages; | |
840 | ||
841 | if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) | |
842 | return; | |
843 | ||
a8132e5f | 844 | pages = iommu_num_pages(dma_addr, size); |
cb76c322 JR |
845 | dma_addr &= PAGE_MASK; |
846 | start = dma_addr; | |
847 | ||
848 | for (i = 0; i < pages; ++i) { | |
849 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
850 | start += PAGE_SIZE; | |
851 | } | |
852 | ||
853 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 854 | |
1c655773 JR |
855 | if (iommu_fullflush) |
856 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); | |
cb76c322 JR |
857 | } |
858 | ||
431b2a20 JR |
859 | /* |
860 | * The exported map_single function for dma_ops. | |
861 | */ | |
4da70b9e JR |
862 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
863 | size_t size, int dir) | |
864 | { | |
865 | unsigned long flags; | |
866 | struct amd_iommu *iommu; | |
867 | struct protection_domain *domain; | |
868 | u16 devid; | |
869 | dma_addr_t addr; | |
870 | ||
dbcc112e JR |
871 | if (!check_device(dev)) |
872 | return bad_dma_address; | |
873 | ||
4da70b9e JR |
874 | get_device_resources(dev, &iommu, &domain, &devid); |
875 | ||
876 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 877 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
878 | return (dma_addr_t)paddr; |
879 | ||
880 | spin_lock_irqsave(&domain->lock, flags); | |
6d4f343f | 881 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false); |
4da70b9e JR |
882 | if (addr == bad_dma_address) |
883 | goto out; | |
884 | ||
5507eef8 | 885 | if (unlikely(iommu->need_sync)) |
4da70b9e JR |
886 | iommu_completion_wait(iommu); |
887 | ||
888 | out: | |
889 | spin_unlock_irqrestore(&domain->lock, flags); | |
890 | ||
891 | return addr; | |
892 | } | |
893 | ||
431b2a20 JR |
894 | /* |
895 | * The exported unmap_single function for dma_ops. | |
896 | */ | |
4da70b9e JR |
897 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
898 | size_t size, int dir) | |
899 | { | |
900 | unsigned long flags; | |
901 | struct amd_iommu *iommu; | |
902 | struct protection_domain *domain; | |
903 | u16 devid; | |
904 | ||
dbcc112e JR |
905 | if (!check_device(dev) || |
906 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 907 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
908 | return; |
909 | ||
910 | spin_lock_irqsave(&domain->lock, flags); | |
911 | ||
912 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
913 | ||
5507eef8 | 914 | if (unlikely(iommu->need_sync)) |
4da70b9e JR |
915 | iommu_completion_wait(iommu); |
916 | ||
917 | spin_unlock_irqrestore(&domain->lock, flags); | |
918 | } | |
919 | ||
431b2a20 JR |
920 | /* |
921 | * This is a special map_sg function which is used if we should map a | |
922 | * device which is not handled by an AMD IOMMU in the system. | |
923 | */ | |
65b050ad JR |
924 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
925 | int nelems, int dir) | |
926 | { | |
927 | struct scatterlist *s; | |
928 | int i; | |
929 | ||
930 | for_each_sg(sglist, s, nelems, i) { | |
931 | s->dma_address = (dma_addr_t)sg_phys(s); | |
932 | s->dma_length = s->length; | |
933 | } | |
934 | ||
935 | return nelems; | |
936 | } | |
937 | ||
431b2a20 JR |
938 | /* |
939 | * The exported map_sg function for dma_ops (handles scatter-gather | |
940 | * lists). | |
941 | */ | |
65b050ad JR |
942 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
943 | int nelems, int dir) | |
944 | { | |
945 | unsigned long flags; | |
946 | struct amd_iommu *iommu; | |
947 | struct protection_domain *domain; | |
948 | u16 devid; | |
949 | int i; | |
950 | struct scatterlist *s; | |
951 | phys_addr_t paddr; | |
952 | int mapped_elems = 0; | |
953 | ||
dbcc112e JR |
954 | if (!check_device(dev)) |
955 | return 0; | |
956 | ||
65b050ad JR |
957 | get_device_resources(dev, &iommu, &domain, &devid); |
958 | ||
959 | if (!iommu || !domain) | |
960 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
961 | ||
962 | spin_lock_irqsave(&domain->lock, flags); | |
963 | ||
964 | for_each_sg(sglist, s, nelems, i) { | |
965 | paddr = sg_phys(s); | |
966 | ||
967 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
6d4f343f | 968 | paddr, s->length, dir, false); |
65b050ad JR |
969 | |
970 | if (s->dma_address) { | |
971 | s->dma_length = s->length; | |
972 | mapped_elems++; | |
973 | } else | |
974 | goto unmap; | |
65b050ad JR |
975 | } |
976 | ||
5507eef8 | 977 | if (unlikely(iommu->need_sync)) |
65b050ad JR |
978 | iommu_completion_wait(iommu); |
979 | ||
980 | out: | |
981 | spin_unlock_irqrestore(&domain->lock, flags); | |
982 | ||
983 | return mapped_elems; | |
984 | unmap: | |
985 | for_each_sg(sglist, s, mapped_elems, i) { | |
986 | if (s->dma_address) | |
987 | __unmap_single(iommu, domain->priv, s->dma_address, | |
988 | s->dma_length, dir); | |
989 | s->dma_address = s->dma_length = 0; | |
990 | } | |
991 | ||
992 | mapped_elems = 0; | |
993 | ||
994 | goto out; | |
995 | } | |
996 | ||
431b2a20 JR |
997 | /* |
998 | * The exported map_sg function for dma_ops (handles scatter-gather | |
999 | * lists). | |
1000 | */ | |
65b050ad JR |
1001 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1002 | int nelems, int dir) | |
1003 | { | |
1004 | unsigned long flags; | |
1005 | struct amd_iommu *iommu; | |
1006 | struct protection_domain *domain; | |
1007 | struct scatterlist *s; | |
1008 | u16 devid; | |
1009 | int i; | |
1010 | ||
dbcc112e JR |
1011 | if (!check_device(dev) || |
1012 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1013 | return; |
1014 | ||
1015 | spin_lock_irqsave(&domain->lock, flags); | |
1016 | ||
1017 | for_each_sg(sglist, s, nelems, i) { | |
1018 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1019 | s->dma_length, dir); | |
65b050ad JR |
1020 | s->dma_address = s->dma_length = 0; |
1021 | } | |
1022 | ||
5507eef8 | 1023 | if (unlikely(iommu->need_sync)) |
65b050ad JR |
1024 | iommu_completion_wait(iommu); |
1025 | ||
1026 | spin_unlock_irqrestore(&domain->lock, flags); | |
1027 | } | |
1028 | ||
431b2a20 JR |
1029 | /* |
1030 | * The exported alloc_coherent function for dma_ops. | |
1031 | */ | |
5d8b53cf JR |
1032 | static void *alloc_coherent(struct device *dev, size_t size, |
1033 | dma_addr_t *dma_addr, gfp_t flag) | |
1034 | { | |
1035 | unsigned long flags; | |
1036 | void *virt_addr; | |
1037 | struct amd_iommu *iommu; | |
1038 | struct protection_domain *domain; | |
1039 | u16 devid; | |
1040 | phys_addr_t paddr; | |
1041 | ||
dbcc112e JR |
1042 | if (!check_device(dev)) |
1043 | return NULL; | |
1044 | ||
5d8b53cf JR |
1045 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1046 | if (!virt_addr) | |
1047 | return 0; | |
1048 | ||
1049 | memset(virt_addr, 0, size); | |
1050 | paddr = virt_to_phys(virt_addr); | |
1051 | ||
1052 | get_device_resources(dev, &iommu, &domain, &devid); | |
1053 | ||
1054 | if (!iommu || !domain) { | |
1055 | *dma_addr = (dma_addr_t)paddr; | |
1056 | return virt_addr; | |
1057 | } | |
1058 | ||
1059 | spin_lock_irqsave(&domain->lock, flags); | |
1060 | ||
1061 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
6d4f343f | 1062 | size, DMA_BIDIRECTIONAL, true); |
5d8b53cf JR |
1063 | |
1064 | if (*dma_addr == bad_dma_address) { | |
1065 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1066 | virt_addr = NULL; | |
1067 | goto out; | |
1068 | } | |
1069 | ||
5507eef8 | 1070 | if (unlikely(iommu->need_sync)) |
5d8b53cf JR |
1071 | iommu_completion_wait(iommu); |
1072 | ||
1073 | out: | |
1074 | spin_unlock_irqrestore(&domain->lock, flags); | |
1075 | ||
1076 | return virt_addr; | |
1077 | } | |
1078 | ||
431b2a20 JR |
1079 | /* |
1080 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1081 | */ |
5d8b53cf JR |
1082 | static void free_coherent(struct device *dev, size_t size, |
1083 | void *virt_addr, dma_addr_t dma_addr) | |
1084 | { | |
1085 | unsigned long flags; | |
1086 | struct amd_iommu *iommu; | |
1087 | struct protection_domain *domain; | |
1088 | u16 devid; | |
1089 | ||
dbcc112e JR |
1090 | if (!check_device(dev)) |
1091 | return; | |
1092 | ||
5d8b53cf JR |
1093 | get_device_resources(dev, &iommu, &domain, &devid); |
1094 | ||
1095 | if (!iommu || !domain) | |
1096 | goto free_mem; | |
1097 | ||
1098 | spin_lock_irqsave(&domain->lock, flags); | |
1099 | ||
1100 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1101 | |
5507eef8 | 1102 | if (unlikely(iommu->need_sync)) |
5d8b53cf JR |
1103 | iommu_completion_wait(iommu); |
1104 | ||
1105 | spin_unlock_irqrestore(&domain->lock, flags); | |
1106 | ||
1107 | free_mem: | |
1108 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1109 | } | |
1110 | ||
c432f3df | 1111 | /* |
431b2a20 JR |
1112 | * The function for pre-allocating protection domains. |
1113 | * | |
c432f3df JR |
1114 | * If the driver core informs the DMA layer if a driver grabs a device |
1115 | * we don't need to preallocate the protection domains anymore. | |
1116 | * For now we have to. | |
1117 | */ | |
1118 | void prealloc_protection_domains(void) | |
1119 | { | |
1120 | struct pci_dev *dev = NULL; | |
1121 | struct dma_ops_domain *dma_dom; | |
1122 | struct amd_iommu *iommu; | |
1123 | int order = amd_iommu_aperture_order; | |
1124 | u16 devid; | |
1125 | ||
1126 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1127 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1128 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1129 | continue; |
1130 | devid = amd_iommu_alias_table[devid]; | |
1131 | if (domain_for_device(devid)) | |
1132 | continue; | |
1133 | iommu = amd_iommu_rlookup_table[devid]; | |
1134 | if (!iommu) | |
1135 | continue; | |
1136 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1137 | if (!dma_dom) | |
1138 | continue; | |
1139 | init_unity_mappings_for_device(dma_dom, devid); | |
1140 | set_device_domain(iommu, &dma_dom->domain, devid); | |
1141 | printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ", | |
1142 | dma_dom->domain.id); | |
1143 | print_devid(devid, 1); | |
1144 | } | |
1145 | } | |
1146 | ||
6631ee9d JR |
1147 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1148 | .alloc_coherent = alloc_coherent, | |
1149 | .free_coherent = free_coherent, | |
1150 | .map_single = map_single, | |
1151 | .unmap_single = unmap_single, | |
1152 | .map_sg = map_sg, | |
1153 | .unmap_sg = unmap_sg, | |
1154 | }; | |
1155 | ||
431b2a20 JR |
1156 | /* |
1157 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1158 | */ | |
6631ee9d JR |
1159 | int __init amd_iommu_init_dma_ops(void) |
1160 | { | |
1161 | struct amd_iommu *iommu; | |
1162 | int order = amd_iommu_aperture_order; | |
1163 | int ret; | |
1164 | ||
431b2a20 JR |
1165 | /* |
1166 | * first allocate a default protection domain for every IOMMU we | |
1167 | * found in the system. Devices not assigned to any other | |
1168 | * protection domain will be assigned to the default one. | |
1169 | */ | |
6631ee9d JR |
1170 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1171 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1172 | if (iommu->default_dom == NULL) | |
1173 | return -ENOMEM; | |
1174 | ret = iommu_init_unity_mappings(iommu); | |
1175 | if (ret) | |
1176 | goto free_domains; | |
1177 | } | |
1178 | ||
431b2a20 JR |
1179 | /* |
1180 | * If device isolation is enabled, pre-allocate the protection | |
1181 | * domains for each device. | |
1182 | */ | |
6631ee9d JR |
1183 | if (amd_iommu_isolate) |
1184 | prealloc_protection_domains(); | |
1185 | ||
1186 | iommu_detected = 1; | |
1187 | force_iommu = 1; | |
1188 | bad_dma_address = 0; | |
92af4e29 | 1189 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1190 | gart_iommu_aperture_disabled = 1; |
1191 | gart_iommu_aperture = 0; | |
92af4e29 | 1192 | #endif |
6631ee9d | 1193 | |
431b2a20 | 1194 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1195 | dma_ops = &amd_iommu_dma_ops; |
1196 | ||
1197 | return 0; | |
1198 | ||
1199 | free_domains: | |
1200 | ||
1201 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1202 | if (iommu->default_dom) | |
1203 | dma_ops_domain_free(iommu->default_dom); | |
1204 | } | |
1205 | ||
1206 | return ret; | |
1207 | } |