Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
b6c02715 | 30 | #include <asm/proto.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
6a9401a7 | 33 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 34 | #include <asm/amd_iommu_types.h> |
c6da992e | 35 | #include <asm/amd_iommu.h> |
b6c02715 JR |
36 | |
37 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
38 | ||
815b33fd | 39 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 40 | |
b6c02715 JR |
41 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
42 | ||
bd60b735 JR |
43 | /* A list of preallocated protection domains */ |
44 | static LIST_HEAD(iommu_pd_list); | |
45 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
46 | ||
0feae533 JR |
47 | /* |
48 | * Domain for untranslated devices - only allocated | |
49 | * if iommu=pt passed on kernel cmd line. | |
50 | */ | |
51 | static struct protection_domain *pt_domain; | |
52 | ||
26961efe | 53 | static struct iommu_ops amd_iommu_ops; |
26961efe | 54 | |
431b2a20 JR |
55 | /* |
56 | * general struct to manage commands send to an IOMMU | |
57 | */ | |
d6449536 | 58 | struct iommu_cmd { |
b6c02715 JR |
59 | u32 data[4]; |
60 | }; | |
61 | ||
04bfdd84 | 62 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 63 | |
15898bbc JR |
64 | /**************************************************************************** |
65 | * | |
66 | * Helper functions | |
67 | * | |
68 | ****************************************************************************/ | |
69 | ||
70 | static inline u16 get_device_id(struct device *dev) | |
71 | { | |
72 | struct pci_dev *pdev = to_pci_dev(dev); | |
73 | ||
74 | return calc_devid(pdev->bus->number, pdev->devfn); | |
75 | } | |
76 | ||
657cbb6b JR |
77 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
78 | { | |
79 | return dev->archdata.iommu; | |
80 | } | |
81 | ||
71c70984 JR |
82 | /* |
83 | * In this function the list of preallocated protection domains is traversed to | |
84 | * find the domain for a specific device | |
85 | */ | |
86 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
87 | { | |
88 | struct dma_ops_domain *entry, *ret = NULL; | |
89 | unsigned long flags; | |
90 | u16 alias = amd_iommu_alias_table[devid]; | |
91 | ||
92 | if (list_empty(&iommu_pd_list)) | |
93 | return NULL; | |
94 | ||
95 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
96 | ||
97 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
98 | if (entry->target_dev == devid || | |
99 | entry->target_dev == alias) { | |
100 | ret = entry; | |
101 | break; | |
102 | } | |
103 | } | |
104 | ||
105 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
106 | ||
107 | return ret; | |
108 | } | |
109 | ||
98fc5a69 JR |
110 | /* |
111 | * This function checks if the driver got a valid device from the caller to | |
112 | * avoid dereferencing invalid pointers. | |
113 | */ | |
114 | static bool check_device(struct device *dev) | |
115 | { | |
116 | u16 devid; | |
117 | ||
118 | if (!dev || !dev->dma_mask) | |
119 | return false; | |
120 | ||
121 | /* No device or no PCI device */ | |
339d3261 | 122 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
123 | return false; |
124 | ||
125 | devid = get_device_id(dev); | |
126 | ||
127 | /* Out of our scope? */ | |
128 | if (devid > amd_iommu_last_bdf) | |
129 | return false; | |
130 | ||
131 | if (amd_iommu_rlookup_table[devid] == NULL) | |
132 | return false; | |
133 | ||
134 | return true; | |
135 | } | |
136 | ||
657cbb6b JR |
137 | static int iommu_init_device(struct device *dev) |
138 | { | |
139 | struct iommu_dev_data *dev_data; | |
140 | struct pci_dev *pdev; | |
141 | u16 devid, alias; | |
142 | ||
143 | if (dev->archdata.iommu) | |
144 | return 0; | |
145 | ||
146 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
147 | if (!dev_data) | |
148 | return -ENOMEM; | |
149 | ||
b00d3bcf JR |
150 | dev_data->dev = dev; |
151 | ||
657cbb6b JR |
152 | devid = get_device_id(dev); |
153 | alias = amd_iommu_alias_table[devid]; | |
154 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
155 | if (pdev) | |
156 | dev_data->alias = &pdev->dev; | |
157 | ||
24100055 JR |
158 | atomic_set(&dev_data->bind, 0); |
159 | ||
657cbb6b JR |
160 | dev->archdata.iommu = dev_data; |
161 | ||
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static void iommu_uninit_device(struct device *dev) | |
167 | { | |
168 | kfree(dev->archdata.iommu); | |
169 | } | |
b7cc9554 JR |
170 | |
171 | void __init amd_iommu_uninit_devices(void) | |
172 | { | |
173 | struct pci_dev *pdev = NULL; | |
174 | ||
175 | for_each_pci_dev(pdev) { | |
176 | ||
177 | if (!check_device(&pdev->dev)) | |
178 | continue; | |
179 | ||
180 | iommu_uninit_device(&pdev->dev); | |
181 | } | |
182 | } | |
183 | ||
184 | int __init amd_iommu_init_devices(void) | |
185 | { | |
186 | struct pci_dev *pdev = NULL; | |
187 | int ret = 0; | |
188 | ||
189 | for_each_pci_dev(pdev) { | |
190 | ||
191 | if (!check_device(&pdev->dev)) | |
192 | continue; | |
193 | ||
194 | ret = iommu_init_device(&pdev->dev); | |
195 | if (ret) | |
196 | goto out_free; | |
197 | } | |
198 | ||
199 | return 0; | |
200 | ||
201 | out_free: | |
202 | ||
203 | amd_iommu_uninit_devices(); | |
204 | ||
205 | return ret; | |
206 | } | |
7f26508b JR |
207 | #ifdef CONFIG_AMD_IOMMU_STATS |
208 | ||
209 | /* | |
210 | * Initialization code for statistics collection | |
211 | */ | |
212 | ||
da49f6df | 213 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 214 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 215 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 216 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 217 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 218 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 219 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 220 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 221 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 222 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 223 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 224 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 225 | |
7f26508b | 226 | static struct dentry *stats_dir; |
7f26508b JR |
227 | static struct dentry *de_fflush; |
228 | ||
229 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
230 | { | |
231 | if (stats_dir == NULL) | |
232 | return; | |
233 | ||
234 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
235 | &cnt->value); | |
236 | } | |
237 | ||
238 | static void amd_iommu_stats_init(void) | |
239 | { | |
240 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
241 | if (stats_dir == NULL) | |
242 | return; | |
243 | ||
7f26508b JR |
244 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
245 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
246 | |
247 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 248 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 249 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 250 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 251 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 252 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 253 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 254 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 255 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 256 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 257 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 258 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
259 | } |
260 | ||
261 | #endif | |
262 | ||
a80dc3e0 JR |
263 | /**************************************************************************** |
264 | * | |
265 | * Interrupt handling functions | |
266 | * | |
267 | ****************************************************************************/ | |
268 | ||
e3e59876 JR |
269 | static void dump_dte_entry(u16 devid) |
270 | { | |
271 | int i; | |
272 | ||
273 | for (i = 0; i < 8; ++i) | |
274 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
275 | amd_iommu_dev_table[devid].data[i]); | |
276 | } | |
277 | ||
945b4ac4 JR |
278 | static void dump_command(unsigned long phys_addr) |
279 | { | |
280 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
281 | int i; | |
282 | ||
283 | for (i = 0; i < 4; ++i) | |
284 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
285 | } | |
286 | ||
a345b23b | 287 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
288 | { |
289 | u32 *event = __evt; | |
290 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
291 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
292 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
293 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
294 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
295 | ||
4c6f40d4 | 296 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
297 | |
298 | switch (type) { | |
299 | case EVENT_TYPE_ILL_DEV: | |
300 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
301 | "address=0x%016llx flags=0x%04x]\n", | |
302 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
303 | address, flags); | |
e3e59876 | 304 | dump_dte_entry(devid); |
90008ee4 JR |
305 | break; |
306 | case EVENT_TYPE_IO_FAULT: | |
307 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
308 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
309 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
310 | domid, address, flags); | |
311 | break; | |
312 | case EVENT_TYPE_DEV_TAB_ERR: | |
313 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
314 | "address=0x%016llx flags=0x%04x]\n", | |
315 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
316 | address, flags); | |
317 | break; | |
318 | case EVENT_TYPE_PAGE_TAB_ERR: | |
319 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
320 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
321 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
322 | domid, address, flags); | |
323 | break; | |
324 | case EVENT_TYPE_ILL_CMD: | |
325 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 326 | dump_command(address); |
90008ee4 JR |
327 | break; |
328 | case EVENT_TYPE_CMD_HARD_ERR: | |
329 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
330 | "flags=0x%04x]\n", address, flags); | |
331 | break; | |
332 | case EVENT_TYPE_IOTLB_INV_TO: | |
333 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
334 | "address=0x%016llx]\n", | |
335 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
336 | address); | |
337 | break; | |
338 | case EVENT_TYPE_INV_DEV_REQ: | |
339 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
340 | "address=0x%016llx flags=0x%04x]\n", | |
341 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
342 | address, flags); | |
343 | break; | |
344 | default: | |
345 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
346 | } | |
347 | } | |
348 | ||
349 | static void iommu_poll_events(struct amd_iommu *iommu) | |
350 | { | |
351 | u32 head, tail; | |
352 | unsigned long flags; | |
353 | ||
354 | spin_lock_irqsave(&iommu->lock, flags); | |
355 | ||
356 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
357 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
358 | ||
359 | while (head != tail) { | |
a345b23b | 360 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
361 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
362 | } | |
363 | ||
364 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
365 | ||
366 | spin_unlock_irqrestore(&iommu->lock, flags); | |
367 | } | |
368 | ||
a80dc3e0 JR |
369 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
370 | { | |
90008ee4 JR |
371 | struct amd_iommu *iommu; |
372 | ||
3bd22172 | 373 | for_each_iommu(iommu) |
90008ee4 JR |
374 | iommu_poll_events(iommu); |
375 | ||
376 | return IRQ_HANDLED; | |
a80dc3e0 JR |
377 | } |
378 | ||
431b2a20 JR |
379 | /**************************************************************************** |
380 | * | |
381 | * IOMMU command queuing functions | |
382 | * | |
383 | ****************************************************************************/ | |
384 | ||
ac0ea6e9 JR |
385 | static int wait_on_sem(volatile u64 *sem) |
386 | { | |
387 | int i = 0; | |
388 | ||
389 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
390 | udelay(1); | |
391 | i += 1; | |
392 | } | |
393 | ||
394 | if (i == LOOP_TIMEOUT) { | |
395 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
396 | return -EIO; | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
403 | struct iommu_cmd *cmd, | |
404 | u32 tail) | |
a19ae1ec | 405 | { |
a19ae1ec JR |
406 | u8 *target; |
407 | ||
8a7c5ef3 | 408 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
409 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
410 | ||
411 | /* Copy command to buffer */ | |
412 | memcpy(target, cmd, sizeof(*cmd)); | |
413 | ||
414 | /* Tell the IOMMU about it */ | |
a19ae1ec | 415 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 416 | } |
a19ae1ec | 417 | |
815b33fd | 418 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 419 | { |
815b33fd JR |
420 | WARN_ON(address & 0x7ULL); |
421 | ||
ded46737 | 422 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
423 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
424 | cmd->data[1] = upper_32_bits(__pa(address)); | |
425 | cmd->data[2] = 1; | |
ded46737 JR |
426 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
427 | } | |
428 | ||
94fe79e2 JR |
429 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
430 | { | |
431 | memset(cmd, 0, sizeof(*cmd)); | |
432 | cmd->data[0] = devid; | |
433 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
434 | } | |
435 | ||
11b6402c JR |
436 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
437 | size_t size, u16 domid, int pde) | |
438 | { | |
439 | u64 pages; | |
440 | int s; | |
441 | ||
442 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
443 | s = 0; | |
444 | ||
445 | if (pages > 1) { | |
446 | /* | |
447 | * If we have to flush more than one page, flush all | |
448 | * TLB entries for this domain | |
449 | */ | |
450 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
451 | s = 1; | |
452 | } | |
453 | ||
454 | address &= PAGE_MASK; | |
455 | ||
456 | memset(cmd, 0, sizeof(*cmd)); | |
457 | cmd->data[1] |= domid; | |
458 | cmd->data[2] = lower_32_bits(address); | |
459 | cmd->data[3] = upper_32_bits(address); | |
460 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
461 | if (s) /* size bit - we flush more than one 4kb page */ | |
462 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
463 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
464 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
465 | } | |
466 | ||
cb41ed85 JR |
467 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
468 | u64 address, size_t size) | |
469 | { | |
470 | u64 pages; | |
471 | int s; | |
472 | ||
473 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
474 | s = 0; | |
475 | ||
476 | if (pages > 1) { | |
477 | /* | |
478 | * If we have to flush more than one page, flush all | |
479 | * TLB entries for this domain | |
480 | */ | |
481 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
482 | s = 1; | |
483 | } | |
484 | ||
485 | address &= PAGE_MASK; | |
486 | ||
487 | memset(cmd, 0, sizeof(*cmd)); | |
488 | cmd->data[0] = devid; | |
489 | cmd->data[0] |= (qdep & 0xff) << 24; | |
490 | cmd->data[1] = devid; | |
491 | cmd->data[2] = lower_32_bits(address); | |
492 | cmd->data[3] = upper_32_bits(address); | |
493 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
494 | if (s) | |
495 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
496 | } | |
497 | ||
58fc7f14 JR |
498 | static void build_inv_all(struct iommu_cmd *cmd) |
499 | { | |
500 | memset(cmd, 0, sizeof(*cmd)); | |
501 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
502 | } |
503 | ||
431b2a20 | 504 | /* |
431b2a20 | 505 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 506 | * hardware about the new command. |
431b2a20 | 507 | */ |
d6449536 | 508 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 509 | { |
ac0ea6e9 | 510 | u32 left, tail, head, next_tail; |
a19ae1ec | 511 | unsigned long flags; |
a19ae1ec | 512 | |
549c90dc | 513 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
514 | |
515 | again: | |
a19ae1ec | 516 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 517 | |
ac0ea6e9 JR |
518 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
519 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
520 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
521 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 522 | |
ac0ea6e9 JR |
523 | if (left <= 2) { |
524 | struct iommu_cmd sync_cmd; | |
525 | volatile u64 sem = 0; | |
526 | int ret; | |
8d201968 | 527 | |
ac0ea6e9 JR |
528 | build_completion_wait(&sync_cmd, (u64)&sem); |
529 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 530 | |
ac0ea6e9 JR |
531 | spin_unlock_irqrestore(&iommu->lock, flags); |
532 | ||
533 | if ((ret = wait_on_sem(&sem)) != 0) | |
534 | return ret; | |
535 | ||
536 | goto again; | |
8d201968 JR |
537 | } |
538 | ||
ac0ea6e9 JR |
539 | copy_cmd_to_buffer(iommu, cmd, tail); |
540 | ||
541 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 542 | iommu->need_sync = true; |
ac0ea6e9 | 543 | |
a19ae1ec | 544 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 545 | |
815b33fd | 546 | return 0; |
8d201968 JR |
547 | } |
548 | ||
549 | /* | |
550 | * This function queues a completion wait command into the command | |
551 | * buffer of an IOMMU | |
552 | */ | |
a19ae1ec | 553 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
554 | { |
555 | struct iommu_cmd cmd; | |
815b33fd | 556 | volatile u64 sem = 0; |
ac0ea6e9 | 557 | int ret; |
8d201968 | 558 | |
09ee17eb | 559 | if (!iommu->need_sync) |
815b33fd | 560 | return 0; |
09ee17eb | 561 | |
815b33fd | 562 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 563 | |
815b33fd | 564 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 565 | if (ret) |
815b33fd | 566 | return ret; |
8d201968 | 567 | |
ac0ea6e9 | 568 | return wait_on_sem(&sem); |
8d201968 JR |
569 | } |
570 | ||
d8c13085 | 571 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 572 | { |
d8c13085 | 573 | struct iommu_cmd cmd; |
a19ae1ec | 574 | |
d8c13085 | 575 | build_inv_dte(&cmd, devid); |
7e4f88da | 576 | |
d8c13085 JR |
577 | return iommu_queue_command(iommu, &cmd); |
578 | } | |
09ee17eb | 579 | |
7d0c5cc5 JR |
580 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
581 | { | |
582 | u32 devid; | |
09ee17eb | 583 | |
7d0c5cc5 JR |
584 | for (devid = 0; devid <= 0xffff; ++devid) |
585 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 586 | |
7d0c5cc5 JR |
587 | iommu_completion_wait(iommu); |
588 | } | |
84df8175 | 589 | |
7d0c5cc5 JR |
590 | /* |
591 | * This function uses heavy locking and may disable irqs for some time. But | |
592 | * this is no issue because it is only called during resume. | |
593 | */ | |
594 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
595 | { | |
596 | u32 dom_id; | |
a19ae1ec | 597 | |
7d0c5cc5 JR |
598 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
599 | struct iommu_cmd cmd; | |
600 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
601 | dom_id, 1); | |
602 | iommu_queue_command(iommu, &cmd); | |
603 | } | |
8eed9833 | 604 | |
7d0c5cc5 | 605 | iommu_completion_wait(iommu); |
a19ae1ec JR |
606 | } |
607 | ||
58fc7f14 | 608 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 609 | { |
58fc7f14 | 610 | struct iommu_cmd cmd; |
0518a3a4 | 611 | |
58fc7f14 | 612 | build_inv_all(&cmd); |
0518a3a4 | 613 | |
58fc7f14 JR |
614 | iommu_queue_command(iommu, &cmd); |
615 | iommu_completion_wait(iommu); | |
616 | } | |
617 | ||
7d0c5cc5 JR |
618 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
619 | { | |
58fc7f14 JR |
620 | if (iommu_feature(iommu, FEATURE_IA)) { |
621 | iommu_flush_all(iommu); | |
622 | } else { | |
623 | iommu_flush_dte_all(iommu); | |
624 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
625 | } |
626 | } | |
627 | ||
431b2a20 | 628 | /* |
cb41ed85 | 629 | * Command send function for flushing on-device TLB |
431b2a20 | 630 | */ |
cb41ed85 | 631 | static int device_flush_iotlb(struct device *dev, u64 address, size_t size) |
3fa43655 | 632 | { |
cb41ed85 | 633 | struct pci_dev *pdev = to_pci_dev(dev); |
3fa43655 | 634 | struct amd_iommu *iommu; |
b00d3bcf | 635 | struct iommu_cmd cmd; |
3fa43655 | 636 | u16 devid; |
cb41ed85 | 637 | int qdep; |
3fa43655 | 638 | |
cb41ed85 | 639 | qdep = pci_ats_queue_depth(pdev); |
3fa43655 JR |
640 | devid = get_device_id(dev); |
641 | iommu = amd_iommu_rlookup_table[devid]; | |
642 | ||
cb41ed85 | 643 | build_inv_iotlb_pages(&cmd, devid, qdep, address, size); |
b00d3bcf JR |
644 | |
645 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
646 | } |
647 | ||
431b2a20 | 648 | /* |
431b2a20 | 649 | * Command send function for invalidating a device table entry |
431b2a20 | 650 | */ |
d8c13085 | 651 | static int device_flush_dte(struct device *dev) |
a19ae1ec | 652 | { |
3fa43655 | 653 | struct amd_iommu *iommu; |
cb41ed85 | 654 | struct pci_dev *pdev; |
3fa43655 | 655 | u16 devid; |
ee2fa743 | 656 | int ret; |
a19ae1ec | 657 | |
cb41ed85 | 658 | pdev = to_pci_dev(dev); |
3fa43655 JR |
659 | devid = get_device_id(dev); |
660 | iommu = amd_iommu_rlookup_table[devid]; | |
a19ae1ec | 661 | |
cb41ed85 JR |
662 | ret = iommu_flush_dte(iommu, devid); |
663 | if (ret) | |
664 | return ret; | |
665 | ||
666 | if (pci_ats_enabled(pdev)) | |
667 | ret = device_flush_iotlb(dev, 0, ~0UL); | |
ee2fa743 | 668 | |
ee2fa743 | 669 | return ret; |
a19ae1ec JR |
670 | } |
671 | ||
431b2a20 JR |
672 | /* |
673 | * TLB invalidation function which is called from the mapping functions. | |
674 | * It invalidates a single PTE if the range to flush is within a single | |
675 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
676 | */ | |
17b124bf JR |
677 | static void __domain_flush_pages(struct protection_domain *domain, |
678 | u64 address, size_t size, int pde) | |
a19ae1ec | 679 | { |
cb41ed85 | 680 | struct iommu_dev_data *dev_data; |
11b6402c JR |
681 | struct iommu_cmd cmd; |
682 | int ret = 0, i; | |
a19ae1ec | 683 | |
11b6402c | 684 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 685 | |
6de8ad9b JR |
686 | for (i = 0; i < amd_iommus_present; ++i) { |
687 | if (!domain->dev_iommu[i]) | |
688 | continue; | |
689 | ||
690 | /* | |
691 | * Devices of this domain are behind this IOMMU | |
692 | * We need a TLB flush | |
693 | */ | |
11b6402c | 694 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
695 | } |
696 | ||
cb41ed85 JR |
697 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
698 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); | |
699 | ||
700 | if (!pci_ats_enabled(pdev)) | |
701 | continue; | |
702 | ||
703 | ret |= device_flush_iotlb(dev_data->dev, address, size); | |
704 | } | |
705 | ||
11b6402c | 706 | WARN_ON(ret); |
6de8ad9b JR |
707 | } |
708 | ||
17b124bf JR |
709 | static void domain_flush_pages(struct protection_domain *domain, |
710 | u64 address, size_t size) | |
6de8ad9b | 711 | { |
17b124bf | 712 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 713 | } |
b6c02715 | 714 | |
1c655773 | 715 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 716 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 717 | { |
17b124bf | 718 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
719 | } |
720 | ||
42a49f96 | 721 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 722 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 723 | { |
17b124bf | 724 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
725 | } |
726 | ||
17b124bf | 727 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 728 | { |
17b124bf | 729 | int i; |
18811f55 | 730 | |
17b124bf JR |
731 | for (i = 0; i < amd_iommus_present; ++i) { |
732 | if (!domain->dev_iommu[i]) | |
733 | continue; | |
bfd1be18 | 734 | |
17b124bf JR |
735 | /* |
736 | * Devices of this domain are behind this IOMMU | |
737 | * We need to wait for completion of all commands. | |
738 | */ | |
739 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 740 | } |
e394d72a JR |
741 | } |
742 | ||
b00d3bcf | 743 | |
09b42804 | 744 | /* |
b00d3bcf | 745 | * This function flushes the DTEs for all devices in domain |
09b42804 | 746 | */ |
17b124bf | 747 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 748 | { |
b00d3bcf | 749 | struct iommu_dev_data *dev_data; |
09b42804 JR |
750 | unsigned long flags; |
751 | ||
b00d3bcf | 752 | spin_lock_irqsave(&domain->lock, flags); |
b26e81b8 | 753 | |
b00d3bcf | 754 | list_for_each_entry(dev_data, &domain->dev_list, list) |
d8c13085 | 755 | device_flush_dte(dev_data->dev); |
b26e81b8 | 756 | |
b00d3bcf | 757 | spin_unlock_irqrestore(&domain->lock, flags); |
a345b23b JR |
758 | } |
759 | ||
431b2a20 JR |
760 | /**************************************************************************** |
761 | * | |
762 | * The functions below are used the create the page table mappings for | |
763 | * unity mapped regions. | |
764 | * | |
765 | ****************************************************************************/ | |
766 | ||
308973d3 JR |
767 | /* |
768 | * This function is used to add another level to an IO page table. Adding | |
769 | * another level increases the size of the address space by 9 bits to a size up | |
770 | * to 64 bits. | |
771 | */ | |
772 | static bool increase_address_space(struct protection_domain *domain, | |
773 | gfp_t gfp) | |
774 | { | |
775 | u64 *pte; | |
776 | ||
777 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
778 | /* address space already 64 bit large */ | |
779 | return false; | |
780 | ||
781 | pte = (void *)get_zeroed_page(gfp); | |
782 | if (!pte) | |
783 | return false; | |
784 | ||
785 | *pte = PM_LEVEL_PDE(domain->mode, | |
786 | virt_to_phys(domain->pt_root)); | |
787 | domain->pt_root = pte; | |
788 | domain->mode += 1; | |
789 | domain->updated = true; | |
790 | ||
791 | return true; | |
792 | } | |
793 | ||
794 | static u64 *alloc_pte(struct protection_domain *domain, | |
795 | unsigned long address, | |
cbb9d729 | 796 | unsigned long page_size, |
308973d3 JR |
797 | u64 **pte_page, |
798 | gfp_t gfp) | |
799 | { | |
cbb9d729 | 800 | int level, end_lvl; |
308973d3 | 801 | u64 *pte, *page; |
cbb9d729 JR |
802 | |
803 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
804 | |
805 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
806 | increase_address_space(domain, gfp); | |
807 | ||
cbb9d729 JR |
808 | level = domain->mode - 1; |
809 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
810 | address = PAGE_SIZE_ALIGN(address, page_size); | |
811 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
812 | |
813 | while (level > end_lvl) { | |
814 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
815 | page = (u64 *)get_zeroed_page(gfp); | |
816 | if (!page) | |
817 | return NULL; | |
818 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
819 | } | |
820 | ||
cbb9d729 JR |
821 | /* No level skipping support yet */ |
822 | if (PM_PTE_LEVEL(*pte) != level) | |
823 | return NULL; | |
824 | ||
308973d3 JR |
825 | level -= 1; |
826 | ||
827 | pte = IOMMU_PTE_PAGE(*pte); | |
828 | ||
829 | if (pte_page && level == end_lvl) | |
830 | *pte_page = pte; | |
831 | ||
832 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
833 | } | |
834 | ||
835 | return pte; | |
836 | } | |
837 | ||
838 | /* | |
839 | * This function checks if there is a PTE for a given dma address. If | |
840 | * there is one, it returns the pointer to it. | |
841 | */ | |
24cd7723 | 842 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
843 | { |
844 | int level; | |
845 | u64 *pte; | |
846 | ||
24cd7723 JR |
847 | if (address > PM_LEVEL_SIZE(domain->mode)) |
848 | return NULL; | |
849 | ||
850 | level = domain->mode - 1; | |
851 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 852 | |
24cd7723 JR |
853 | while (level > 0) { |
854 | ||
855 | /* Not Present */ | |
308973d3 JR |
856 | if (!IOMMU_PTE_PRESENT(*pte)) |
857 | return NULL; | |
858 | ||
24cd7723 JR |
859 | /* Large PTE */ |
860 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
861 | unsigned long pte_mask, __pte; | |
862 | ||
863 | /* | |
864 | * If we have a series of large PTEs, make | |
865 | * sure to return a pointer to the first one. | |
866 | */ | |
867 | pte_mask = PTE_PAGE_SIZE(*pte); | |
868 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
869 | __pte = ((unsigned long)pte) & pte_mask; | |
870 | ||
871 | return (u64 *)__pte; | |
872 | } | |
873 | ||
874 | /* No level skipping support yet */ | |
875 | if (PM_PTE_LEVEL(*pte) != level) | |
876 | return NULL; | |
877 | ||
308973d3 JR |
878 | level -= 1; |
879 | ||
24cd7723 | 880 | /* Walk to the next level */ |
308973d3 JR |
881 | pte = IOMMU_PTE_PAGE(*pte); |
882 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
883 | } |
884 | ||
885 | return pte; | |
886 | } | |
887 | ||
431b2a20 JR |
888 | /* |
889 | * Generic mapping functions. It maps a physical address into a DMA | |
890 | * address space. It allocates the page table pages if necessary. | |
891 | * In the future it can be extended to a generic mapping function | |
892 | * supporting all features of AMD IOMMU page tables like level skipping | |
893 | * and full 64 bit address spaces. | |
894 | */ | |
38e817fe JR |
895 | static int iommu_map_page(struct protection_domain *dom, |
896 | unsigned long bus_addr, | |
897 | unsigned long phys_addr, | |
abdc5eb3 | 898 | int prot, |
cbb9d729 | 899 | unsigned long page_size) |
bd0e5211 | 900 | { |
8bda3092 | 901 | u64 __pte, *pte; |
cbb9d729 | 902 | int i, count; |
abdc5eb3 | 903 | |
bad1cac2 | 904 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
905 | return -EINVAL; |
906 | ||
cbb9d729 JR |
907 | bus_addr = PAGE_ALIGN(bus_addr); |
908 | phys_addr = PAGE_ALIGN(phys_addr); | |
909 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
910 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
911 | ||
912 | for (i = 0; i < count; ++i) | |
913 | if (IOMMU_PTE_PRESENT(pte[i])) | |
914 | return -EBUSY; | |
bd0e5211 | 915 | |
cbb9d729 JR |
916 | if (page_size > PAGE_SIZE) { |
917 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
918 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
919 | } else | |
920 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 921 | |
bd0e5211 JR |
922 | if (prot & IOMMU_PROT_IR) |
923 | __pte |= IOMMU_PTE_IR; | |
924 | if (prot & IOMMU_PROT_IW) | |
925 | __pte |= IOMMU_PTE_IW; | |
926 | ||
cbb9d729 JR |
927 | for (i = 0; i < count; ++i) |
928 | pte[i] = __pte; | |
bd0e5211 | 929 | |
04bfdd84 JR |
930 | update_domain(dom); |
931 | ||
bd0e5211 JR |
932 | return 0; |
933 | } | |
934 | ||
24cd7723 JR |
935 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
936 | unsigned long bus_addr, | |
937 | unsigned long page_size) | |
eb74ff6c | 938 | { |
24cd7723 JR |
939 | unsigned long long unmap_size, unmapped; |
940 | u64 *pte; | |
941 | ||
942 | BUG_ON(!is_power_of_2(page_size)); | |
943 | ||
944 | unmapped = 0; | |
eb74ff6c | 945 | |
24cd7723 JR |
946 | while (unmapped < page_size) { |
947 | ||
948 | pte = fetch_pte(dom, bus_addr); | |
949 | ||
950 | if (!pte) { | |
951 | /* | |
952 | * No PTE for this address | |
953 | * move forward in 4kb steps | |
954 | */ | |
955 | unmap_size = PAGE_SIZE; | |
956 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
957 | /* 4kb PTE found for this address */ | |
958 | unmap_size = PAGE_SIZE; | |
959 | *pte = 0ULL; | |
960 | } else { | |
961 | int count, i; | |
962 | ||
963 | /* Large PTE found which maps this address */ | |
964 | unmap_size = PTE_PAGE_SIZE(*pte); | |
965 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
966 | for (i = 0; i < count; i++) | |
967 | pte[i] = 0ULL; | |
968 | } | |
969 | ||
970 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
971 | unmapped += unmap_size; | |
972 | } | |
973 | ||
974 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 975 | |
24cd7723 | 976 | return unmapped; |
eb74ff6c | 977 | } |
eb74ff6c | 978 | |
431b2a20 JR |
979 | /* |
980 | * This function checks if a specific unity mapping entry is needed for | |
981 | * this specific IOMMU. | |
982 | */ | |
bd0e5211 JR |
983 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
984 | struct unity_map_entry *entry) | |
985 | { | |
986 | u16 bdf, i; | |
987 | ||
988 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
989 | bdf = amd_iommu_alias_table[i]; | |
990 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
991 | return 1; | |
992 | } | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
431b2a20 JR |
997 | /* |
998 | * This function actually applies the mapping to the page table of the | |
999 | * dma_ops domain. | |
1000 | */ | |
bd0e5211 JR |
1001 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1002 | struct unity_map_entry *e) | |
1003 | { | |
1004 | u64 addr; | |
1005 | int ret; | |
1006 | ||
1007 | for (addr = e->address_start; addr < e->address_end; | |
1008 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1009 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1010 | PAGE_SIZE); |
bd0e5211 JR |
1011 | if (ret) |
1012 | return ret; | |
1013 | /* | |
1014 | * if unity mapping is in aperture range mark the page | |
1015 | * as allocated in the aperture | |
1016 | */ | |
1017 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1018 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1019 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1020 | } |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
171e7b37 JR |
1025 | /* |
1026 | * Init the unity mappings for a specific IOMMU in the system | |
1027 | * | |
1028 | * Basically iterates over all unity mapping entries and applies them to | |
1029 | * the default domain DMA of that IOMMU if necessary. | |
1030 | */ | |
1031 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1032 | { | |
1033 | struct unity_map_entry *entry; | |
1034 | int ret; | |
1035 | ||
1036 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1037 | if (!iommu_for_unity_map(iommu, entry)) | |
1038 | continue; | |
1039 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1040 | if (ret) | |
1041 | return ret; | |
1042 | } | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
431b2a20 JR |
1047 | /* |
1048 | * Inits the unity mappings required for a specific device | |
1049 | */ | |
bd0e5211 JR |
1050 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1051 | u16 devid) | |
1052 | { | |
1053 | struct unity_map_entry *e; | |
1054 | int ret; | |
1055 | ||
1056 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1057 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1058 | continue; | |
1059 | ret = dma_ops_unity_map(dma_dom, e); | |
1060 | if (ret) | |
1061 | return ret; | |
1062 | } | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
431b2a20 JR |
1067 | /**************************************************************************** |
1068 | * | |
1069 | * The next functions belong to the address allocator for the dma_ops | |
1070 | * interface functions. They work like the allocators in the other IOMMU | |
1071 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1072 | * the aperture. Maybe it could be enhanced in the future to a more | |
1073 | * efficient allocator. | |
1074 | * | |
1075 | ****************************************************************************/ | |
d3086444 | 1076 | |
431b2a20 | 1077 | /* |
384de729 | 1078 | * The address allocator core functions. |
431b2a20 JR |
1079 | * |
1080 | * called with domain->lock held | |
1081 | */ | |
384de729 | 1082 | |
171e7b37 JR |
1083 | /* |
1084 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1085 | * ranges. | |
1086 | */ | |
1087 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1088 | unsigned long start_page, | |
1089 | unsigned int pages) | |
1090 | { | |
1091 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1092 | ||
1093 | if (start_page + pages > last_page) | |
1094 | pages = last_page - start_page; | |
1095 | ||
1096 | for (i = start_page; i < start_page + pages; ++i) { | |
1097 | int index = i / APERTURE_RANGE_PAGES; | |
1098 | int page = i % APERTURE_RANGE_PAGES; | |
1099 | __set_bit(page, dom->aperture[index]->bitmap); | |
1100 | } | |
1101 | } | |
1102 | ||
9cabe89b JR |
1103 | /* |
1104 | * This function is used to add a new aperture range to an existing | |
1105 | * aperture in case of dma_ops domain allocation or address allocation | |
1106 | * failure. | |
1107 | */ | |
576175c2 | 1108 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1109 | bool populate, gfp_t gfp) |
1110 | { | |
1111 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1112 | struct amd_iommu *iommu; |
d91afd15 | 1113 | unsigned long i; |
9cabe89b | 1114 | |
f5e9705c JR |
1115 | #ifdef CONFIG_IOMMU_STRESS |
1116 | populate = false; | |
1117 | #endif | |
1118 | ||
9cabe89b JR |
1119 | if (index >= APERTURE_MAX_RANGES) |
1120 | return -ENOMEM; | |
1121 | ||
1122 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1123 | if (!dma_dom->aperture[index]) | |
1124 | return -ENOMEM; | |
1125 | ||
1126 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1127 | if (!dma_dom->aperture[index]->bitmap) | |
1128 | goto out_free; | |
1129 | ||
1130 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1131 | ||
1132 | if (populate) { | |
1133 | unsigned long address = dma_dom->aperture_size; | |
1134 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1135 | u64 *pte, *pte_page; | |
1136 | ||
1137 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1138 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1139 | &pte_page, gfp); |
1140 | if (!pte) | |
1141 | goto out_free; | |
1142 | ||
1143 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1144 | ||
1145 | address += APERTURE_RANGE_SIZE / 64; | |
1146 | } | |
1147 | } | |
1148 | ||
1149 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1150 | ||
b595076a | 1151 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1152 | for_each_iommu(iommu) { |
1153 | if (iommu->exclusion_start && | |
1154 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1155 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1156 | unsigned long startpage; | |
1157 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1158 | iommu->exclusion_length, | |
1159 | PAGE_SIZE); | |
1160 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1161 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1162 | } | |
00cd122a JR |
1163 | } |
1164 | ||
1165 | /* | |
1166 | * Check for areas already mapped as present in the new aperture | |
1167 | * range and mark those pages as reserved in the allocator. Such | |
1168 | * mappings may already exist as a result of requested unity | |
1169 | * mappings for devices. | |
1170 | */ | |
1171 | for (i = dma_dom->aperture[index]->offset; | |
1172 | i < dma_dom->aperture_size; | |
1173 | i += PAGE_SIZE) { | |
24cd7723 | 1174 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1175 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1176 | continue; | |
1177 | ||
1178 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1179 | } | |
1180 | ||
04bfdd84 JR |
1181 | update_domain(&dma_dom->domain); |
1182 | ||
9cabe89b JR |
1183 | return 0; |
1184 | ||
1185 | out_free: | |
04bfdd84 JR |
1186 | update_domain(&dma_dom->domain); |
1187 | ||
9cabe89b JR |
1188 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1189 | ||
1190 | kfree(dma_dom->aperture[index]); | |
1191 | dma_dom->aperture[index] = NULL; | |
1192 | ||
1193 | return -ENOMEM; | |
1194 | } | |
1195 | ||
384de729 JR |
1196 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1197 | struct dma_ops_domain *dom, | |
1198 | unsigned int pages, | |
1199 | unsigned long align_mask, | |
1200 | u64 dma_mask, | |
1201 | unsigned long start) | |
1202 | { | |
803b8cb4 | 1203 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1204 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1205 | int i = start >> APERTURE_RANGE_SHIFT; | |
1206 | unsigned long boundary_size; | |
1207 | unsigned long address = -1; | |
1208 | unsigned long limit; | |
1209 | ||
803b8cb4 JR |
1210 | next_bit >>= PAGE_SHIFT; |
1211 | ||
384de729 JR |
1212 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1213 | PAGE_SIZE) >> PAGE_SHIFT; | |
1214 | ||
1215 | for (;i < max_index; ++i) { | |
1216 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1217 | ||
1218 | if (dom->aperture[i]->offset >= dma_mask) | |
1219 | break; | |
1220 | ||
1221 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1222 | dma_mask >> PAGE_SHIFT); | |
1223 | ||
1224 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1225 | limit, next_bit, pages, 0, | |
1226 | boundary_size, align_mask); | |
1227 | if (address != -1) { | |
1228 | address = dom->aperture[i]->offset + | |
1229 | (address << PAGE_SHIFT); | |
803b8cb4 | 1230 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1231 | break; |
1232 | } | |
1233 | ||
1234 | next_bit = 0; | |
1235 | } | |
1236 | ||
1237 | return address; | |
1238 | } | |
1239 | ||
d3086444 JR |
1240 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1241 | struct dma_ops_domain *dom, | |
6d4f343f | 1242 | unsigned int pages, |
832a90c3 JR |
1243 | unsigned long align_mask, |
1244 | u64 dma_mask) | |
d3086444 | 1245 | { |
d3086444 | 1246 | unsigned long address; |
d3086444 | 1247 | |
fe16f088 JR |
1248 | #ifdef CONFIG_IOMMU_STRESS |
1249 | dom->next_address = 0; | |
1250 | dom->need_flush = true; | |
1251 | #endif | |
d3086444 | 1252 | |
384de729 | 1253 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1254 | dma_mask, dom->next_address); |
d3086444 | 1255 | |
1c655773 | 1256 | if (address == -1) { |
803b8cb4 | 1257 | dom->next_address = 0; |
384de729 JR |
1258 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1259 | dma_mask, 0); | |
1c655773 JR |
1260 | dom->need_flush = true; |
1261 | } | |
d3086444 | 1262 | |
384de729 | 1263 | if (unlikely(address == -1)) |
8fd524b3 | 1264 | address = DMA_ERROR_CODE; |
d3086444 JR |
1265 | |
1266 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1267 | ||
1268 | return address; | |
1269 | } | |
1270 | ||
431b2a20 JR |
1271 | /* |
1272 | * The address free function. | |
1273 | * | |
1274 | * called with domain->lock held | |
1275 | */ | |
d3086444 JR |
1276 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1277 | unsigned long address, | |
1278 | unsigned int pages) | |
1279 | { | |
384de729 JR |
1280 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1281 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1282 | |
384de729 JR |
1283 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1284 | ||
47bccd6b JR |
1285 | #ifdef CONFIG_IOMMU_STRESS |
1286 | if (i < 4) | |
1287 | return; | |
1288 | #endif | |
80be308d | 1289 | |
803b8cb4 | 1290 | if (address >= dom->next_address) |
80be308d | 1291 | dom->need_flush = true; |
384de729 JR |
1292 | |
1293 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1294 | |
a66022c4 | 1295 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1296 | |
d3086444 JR |
1297 | } |
1298 | ||
431b2a20 JR |
1299 | /**************************************************************************** |
1300 | * | |
1301 | * The next functions belong to the domain allocation. A domain is | |
1302 | * allocated for every IOMMU as the default domain. If device isolation | |
1303 | * is enabled, every device get its own domain. The most important thing | |
1304 | * about domains is the page table mapping the DMA address space they | |
1305 | * contain. | |
1306 | * | |
1307 | ****************************************************************************/ | |
1308 | ||
aeb26f55 JR |
1309 | /* |
1310 | * This function adds a protection domain to the global protection domain list | |
1311 | */ | |
1312 | static void add_domain_to_list(struct protection_domain *domain) | |
1313 | { | |
1314 | unsigned long flags; | |
1315 | ||
1316 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1317 | list_add(&domain->list, &amd_iommu_pd_list); | |
1318 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1319 | } | |
1320 | ||
1321 | /* | |
1322 | * This function removes a protection domain to the global | |
1323 | * protection domain list | |
1324 | */ | |
1325 | static void del_domain_from_list(struct protection_domain *domain) | |
1326 | { | |
1327 | unsigned long flags; | |
1328 | ||
1329 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1330 | list_del(&domain->list); | |
1331 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1332 | } | |
1333 | ||
ec487d1a JR |
1334 | static u16 domain_id_alloc(void) |
1335 | { | |
1336 | unsigned long flags; | |
1337 | int id; | |
1338 | ||
1339 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1340 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1341 | BUG_ON(id == 0); | |
1342 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1343 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1344 | else | |
1345 | id = 0; | |
1346 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1347 | ||
1348 | return id; | |
1349 | } | |
1350 | ||
a2acfb75 JR |
1351 | static void domain_id_free(int id) |
1352 | { | |
1353 | unsigned long flags; | |
1354 | ||
1355 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1356 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1357 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1358 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1359 | } | |
a2acfb75 | 1360 | |
86db2e5d | 1361 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1362 | { |
1363 | int i, j; | |
1364 | u64 *p1, *p2, *p3; | |
1365 | ||
86db2e5d | 1366 | p1 = domain->pt_root; |
ec487d1a JR |
1367 | |
1368 | if (!p1) | |
1369 | return; | |
1370 | ||
1371 | for (i = 0; i < 512; ++i) { | |
1372 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1373 | continue; | |
1374 | ||
1375 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1376 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1377 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1378 | continue; | |
1379 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1380 | free_page((unsigned long)p3); | |
1381 | } | |
1382 | ||
1383 | free_page((unsigned long)p2); | |
1384 | } | |
1385 | ||
1386 | free_page((unsigned long)p1); | |
86db2e5d JR |
1387 | |
1388 | domain->pt_root = NULL; | |
ec487d1a JR |
1389 | } |
1390 | ||
431b2a20 JR |
1391 | /* |
1392 | * Free a domain, only used if something went wrong in the | |
1393 | * allocation path and we need to free an already allocated page table | |
1394 | */ | |
ec487d1a JR |
1395 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1396 | { | |
384de729 JR |
1397 | int i; |
1398 | ||
ec487d1a JR |
1399 | if (!dom) |
1400 | return; | |
1401 | ||
aeb26f55 JR |
1402 | del_domain_from_list(&dom->domain); |
1403 | ||
86db2e5d | 1404 | free_pagetable(&dom->domain); |
ec487d1a | 1405 | |
384de729 JR |
1406 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1407 | if (!dom->aperture[i]) | |
1408 | continue; | |
1409 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1410 | kfree(dom->aperture[i]); | |
1411 | } | |
ec487d1a JR |
1412 | |
1413 | kfree(dom); | |
1414 | } | |
1415 | ||
431b2a20 JR |
1416 | /* |
1417 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1418 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1419 | * structures required for the dma_ops interface |
1420 | */ | |
87a64d52 | 1421 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1422 | { |
1423 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1424 | |
1425 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1426 | if (!dma_dom) | |
1427 | return NULL; | |
1428 | ||
1429 | spin_lock_init(&dma_dom->domain.lock); | |
1430 | ||
1431 | dma_dom->domain.id = domain_id_alloc(); | |
1432 | if (dma_dom->domain.id == 0) | |
1433 | goto free_dma_dom; | |
7c392cbe | 1434 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1435 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1436 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1437 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1438 | dma_dom->domain.priv = dma_dom; |
1439 | if (!dma_dom->domain.pt_root) | |
1440 | goto free_dma_dom; | |
ec487d1a | 1441 | |
1c655773 | 1442 | dma_dom->need_flush = false; |
bd60b735 | 1443 | dma_dom->target_dev = 0xffff; |
1c655773 | 1444 | |
aeb26f55 JR |
1445 | add_domain_to_list(&dma_dom->domain); |
1446 | ||
576175c2 | 1447 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1448 | goto free_dma_dom; |
ec487d1a | 1449 | |
431b2a20 | 1450 | /* |
ec487d1a JR |
1451 | * mark the first page as allocated so we never return 0 as |
1452 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1453 | */ |
384de729 | 1454 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1455 | dma_dom->next_address = 0; |
ec487d1a | 1456 | |
ec487d1a JR |
1457 | |
1458 | return dma_dom; | |
1459 | ||
1460 | free_dma_dom: | |
1461 | dma_ops_domain_free(dma_dom); | |
1462 | ||
1463 | return NULL; | |
1464 | } | |
1465 | ||
5b28df6f JR |
1466 | /* |
1467 | * little helper function to check whether a given protection domain is a | |
1468 | * dma_ops domain | |
1469 | */ | |
1470 | static bool dma_ops_domain(struct protection_domain *domain) | |
1471 | { | |
1472 | return domain->flags & PD_DMA_OPS_MASK; | |
1473 | } | |
1474 | ||
fd7b5535 | 1475 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1476 | { |
b20ac0d4 | 1477 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1478 | u32 flags = 0; |
863c74eb | 1479 | |
38ddf41b JR |
1480 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1481 | << DEV_ENTRY_MODE_SHIFT; | |
1482 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1483 | |
fd7b5535 JR |
1484 | if (ats) |
1485 | flags |= DTE_FLAG_IOTLB; | |
1486 | ||
1487 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1488 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1489 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1490 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1491 | } |
1492 | ||
1493 | static void clear_dte_entry(u16 devid) | |
1494 | { | |
15898bbc JR |
1495 | /* remove entry from the device table seen by the hardware */ |
1496 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1497 | amd_iommu_dev_table[devid].data[1] = 0; | |
1498 | amd_iommu_dev_table[devid].data[2] = 0; | |
1499 | ||
1500 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1501 | } |
1502 | ||
1503 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1504 | { | |
1505 | struct iommu_dev_data *dev_data; | |
1506 | struct amd_iommu *iommu; | |
fd7b5535 JR |
1507 | struct pci_dev *pdev; |
1508 | bool ats = false; | |
7f760ddd JR |
1509 | u16 devid; |
1510 | ||
1511 | devid = get_device_id(dev); | |
1512 | iommu = amd_iommu_rlookup_table[devid]; | |
1513 | dev_data = get_dev_data(dev); | |
fd7b5535 JR |
1514 | pdev = to_pci_dev(dev); |
1515 | ||
1516 | if (amd_iommu_iotlb_sup) | |
1517 | ats = pci_ats_enabled(pdev); | |
7f760ddd JR |
1518 | |
1519 | /* Update data structures */ | |
1520 | dev_data->domain = domain; | |
1521 | list_add(&dev_data->list, &domain->dev_list); | |
fd7b5535 | 1522 | set_dte_entry(devid, domain, ats); |
7f760ddd JR |
1523 | |
1524 | /* Do reference counting */ | |
1525 | domain->dev_iommu[iommu->index] += 1; | |
1526 | domain->dev_cnt += 1; | |
1527 | ||
1528 | /* Flush the DTE entry */ | |
d8c13085 | 1529 | device_flush_dte(dev); |
7f760ddd JR |
1530 | } |
1531 | ||
1532 | static void do_detach(struct device *dev) | |
1533 | { | |
1534 | struct iommu_dev_data *dev_data; | |
1535 | struct amd_iommu *iommu; | |
fd7b5535 | 1536 | struct pci_dev *pdev; |
7f760ddd JR |
1537 | u16 devid; |
1538 | ||
1539 | devid = get_device_id(dev); | |
1540 | iommu = amd_iommu_rlookup_table[devid]; | |
1541 | dev_data = get_dev_data(dev); | |
fd7b5535 | 1542 | pdev = to_pci_dev(dev); |
15898bbc JR |
1543 | |
1544 | /* decrease reference counters */ | |
7f760ddd JR |
1545 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1546 | dev_data->domain->dev_cnt -= 1; | |
1547 | ||
1548 | /* Update data structures */ | |
1549 | dev_data->domain = NULL; | |
1550 | list_del(&dev_data->list); | |
1551 | clear_dte_entry(devid); | |
15898bbc | 1552 | |
7f760ddd | 1553 | /* Flush the DTE entry */ |
d8c13085 | 1554 | device_flush_dte(dev); |
2b681faf JR |
1555 | } |
1556 | ||
1557 | /* | |
1558 | * If a device is not yet associated with a domain, this function does | |
1559 | * assigns it visible for the hardware | |
1560 | */ | |
15898bbc JR |
1561 | static int __attach_device(struct device *dev, |
1562 | struct protection_domain *domain) | |
2b681faf | 1563 | { |
657cbb6b | 1564 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1565 | int ret; |
657cbb6b | 1566 | |
657cbb6b JR |
1567 | dev_data = get_dev_data(dev); |
1568 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1569 | |
657cbb6b JR |
1570 | if (!alias_data) |
1571 | return -EINVAL; | |
15898bbc | 1572 | |
2b681faf JR |
1573 | /* lock domain */ |
1574 | spin_lock(&domain->lock); | |
1575 | ||
15898bbc | 1576 | /* Some sanity checks */ |
84fe6c19 | 1577 | ret = -EBUSY; |
657cbb6b JR |
1578 | if (alias_data->domain != NULL && |
1579 | alias_data->domain != domain) | |
84fe6c19 | 1580 | goto out_unlock; |
eba6ac60 | 1581 | |
657cbb6b JR |
1582 | if (dev_data->domain != NULL && |
1583 | dev_data->domain != domain) | |
84fe6c19 | 1584 | goto out_unlock; |
15898bbc JR |
1585 | |
1586 | /* Do real assignment */ | |
7f760ddd JR |
1587 | if (dev_data->alias != dev) { |
1588 | alias_data = get_dev_data(dev_data->alias); | |
1589 | if (alias_data->domain == NULL) | |
1590 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1591 | |
1592 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1593 | } |
15898bbc | 1594 | |
7f760ddd JR |
1595 | if (dev_data->domain == NULL) |
1596 | do_attach(dev, domain); | |
eba6ac60 | 1597 | |
24100055 JR |
1598 | atomic_inc(&dev_data->bind); |
1599 | ||
84fe6c19 JL |
1600 | ret = 0; |
1601 | ||
1602 | out_unlock: | |
1603 | ||
eba6ac60 JR |
1604 | /* ready */ |
1605 | spin_unlock(&domain->lock); | |
15898bbc | 1606 | |
84fe6c19 | 1607 | return ret; |
0feae533 | 1608 | } |
b20ac0d4 | 1609 | |
407d733e JR |
1610 | /* |
1611 | * If a device is not yet associated with a domain, this function does | |
1612 | * assigns it visible for the hardware | |
1613 | */ | |
15898bbc JR |
1614 | static int attach_device(struct device *dev, |
1615 | struct protection_domain *domain) | |
0feae533 | 1616 | { |
fd7b5535 | 1617 | struct pci_dev *pdev = to_pci_dev(dev); |
eba6ac60 | 1618 | unsigned long flags; |
15898bbc | 1619 | int ret; |
eba6ac60 | 1620 | |
fd7b5535 JR |
1621 | if (amd_iommu_iotlb_sup) |
1622 | pci_enable_ats(pdev, PAGE_SHIFT); | |
1623 | ||
eba6ac60 | 1624 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
15898bbc | 1625 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1626 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1627 | ||
0feae533 JR |
1628 | /* |
1629 | * We might boot into a crash-kernel here. The crashed kernel | |
1630 | * left the caches in the IOMMU dirty. So we have to flush | |
1631 | * here to evict all dirty stuff. | |
1632 | */ | |
17b124bf | 1633 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1634 | |
1635 | return ret; | |
b20ac0d4 JR |
1636 | } |
1637 | ||
355bf553 JR |
1638 | /* |
1639 | * Removes a device from a protection domain (unlocked) | |
1640 | */ | |
15898bbc | 1641 | static void __detach_device(struct device *dev) |
355bf553 | 1642 | { |
657cbb6b | 1643 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1644 | struct iommu_dev_data *alias_data; |
2ca76279 | 1645 | struct protection_domain *domain; |
7c392cbe | 1646 | unsigned long flags; |
c4596114 | 1647 | |
7f760ddd | 1648 | BUG_ON(!dev_data->domain); |
355bf553 | 1649 | |
2ca76279 JR |
1650 | domain = dev_data->domain; |
1651 | ||
1652 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1653 | |
7f760ddd | 1654 | if (dev_data->alias != dev) { |
24100055 | 1655 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1656 | if (atomic_dec_and_test(&alias_data->bind)) |
1657 | do_detach(dev_data->alias); | |
24100055 JR |
1658 | } |
1659 | ||
7f760ddd JR |
1660 | if (atomic_dec_and_test(&dev_data->bind)) |
1661 | do_detach(dev); | |
1662 | ||
2ca76279 | 1663 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1664 | |
1665 | /* | |
1666 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1667 | * passthrough domain if it is detached from any other domain. |
1668 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1669 | */ |
d3ad9373 JR |
1670 | if (iommu_pass_through && |
1671 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1672 | __attach_device(dev, pt_domain); |
355bf553 JR |
1673 | } |
1674 | ||
1675 | /* | |
1676 | * Removes a device from a protection domain (with devtable_lock held) | |
1677 | */ | |
15898bbc | 1678 | static void detach_device(struct device *dev) |
355bf553 | 1679 | { |
fd7b5535 | 1680 | struct pci_dev *pdev = to_pci_dev(dev); |
355bf553 JR |
1681 | unsigned long flags; |
1682 | ||
1683 | /* lock device table */ | |
1684 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1685 | __detach_device(dev); |
355bf553 | 1686 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 JR |
1687 | |
1688 | if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev)) | |
1689 | pci_disable_ats(pdev); | |
355bf553 | 1690 | } |
e275a2a0 | 1691 | |
15898bbc JR |
1692 | /* |
1693 | * Find out the protection domain structure for a given PCI device. This | |
1694 | * will give us the pointer to the page table root for example. | |
1695 | */ | |
1696 | static struct protection_domain *domain_for_device(struct device *dev) | |
1697 | { | |
1698 | struct protection_domain *dom; | |
657cbb6b | 1699 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1700 | unsigned long flags; |
1701 | u16 devid, alias; | |
1702 | ||
657cbb6b JR |
1703 | devid = get_device_id(dev); |
1704 | alias = amd_iommu_alias_table[devid]; | |
1705 | dev_data = get_dev_data(dev); | |
1706 | alias_data = get_dev_data(dev_data->alias); | |
1707 | if (!alias_data) | |
1708 | return NULL; | |
15898bbc JR |
1709 | |
1710 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1711 | dom = dev_data->domain; |
15898bbc | 1712 | if (dom == NULL && |
657cbb6b JR |
1713 | alias_data->domain != NULL) { |
1714 | __attach_device(dev, alias_data->domain); | |
1715 | dom = alias_data->domain; | |
15898bbc JR |
1716 | } |
1717 | ||
1718 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1719 | ||
1720 | return dom; | |
1721 | } | |
1722 | ||
e275a2a0 JR |
1723 | static int device_change_notifier(struct notifier_block *nb, |
1724 | unsigned long action, void *data) | |
1725 | { | |
1726 | struct device *dev = data; | |
98fc5a69 | 1727 | u16 devid; |
e275a2a0 JR |
1728 | struct protection_domain *domain; |
1729 | struct dma_ops_domain *dma_domain; | |
1730 | struct amd_iommu *iommu; | |
1ac4cbbc | 1731 | unsigned long flags; |
e275a2a0 | 1732 | |
98fc5a69 JR |
1733 | if (!check_device(dev)) |
1734 | return 0; | |
e275a2a0 | 1735 | |
98fc5a69 JR |
1736 | devid = get_device_id(dev); |
1737 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1738 | |
1739 | switch (action) { | |
c1eee67b | 1740 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1741 | |
1742 | domain = domain_for_device(dev); | |
1743 | ||
e275a2a0 JR |
1744 | if (!domain) |
1745 | goto out; | |
a1ca331c JR |
1746 | if (iommu_pass_through) |
1747 | break; | |
15898bbc | 1748 | detach_device(dev); |
1ac4cbbc JR |
1749 | break; |
1750 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1751 | |
1752 | iommu_init_device(dev); | |
1753 | ||
1754 | domain = domain_for_device(dev); | |
1755 | ||
1ac4cbbc JR |
1756 | /* allocate a protection domain if a device is added */ |
1757 | dma_domain = find_protection_domain(devid); | |
1758 | if (dma_domain) | |
1759 | goto out; | |
87a64d52 | 1760 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1761 | if (!dma_domain) |
1762 | goto out; | |
1763 | dma_domain->target_dev = devid; | |
1764 | ||
1765 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1766 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1767 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1768 | ||
e275a2a0 | 1769 | break; |
657cbb6b JR |
1770 | case BUS_NOTIFY_DEL_DEVICE: |
1771 | ||
1772 | iommu_uninit_device(dev); | |
1773 | ||
e275a2a0 JR |
1774 | default: |
1775 | goto out; | |
1776 | } | |
1777 | ||
d8c13085 | 1778 | device_flush_dte(dev); |
e275a2a0 JR |
1779 | iommu_completion_wait(iommu); |
1780 | ||
1781 | out: | |
1782 | return 0; | |
1783 | } | |
1784 | ||
b25ae679 | 1785 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1786 | .notifier_call = device_change_notifier, |
1787 | }; | |
355bf553 | 1788 | |
8638c491 JR |
1789 | void amd_iommu_init_notifier(void) |
1790 | { | |
1791 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1792 | } | |
1793 | ||
431b2a20 JR |
1794 | /***************************************************************************** |
1795 | * | |
1796 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1797 | * | |
1798 | *****************************************************************************/ | |
1799 | ||
1800 | /* | |
1801 | * In the dma_ops path we only have the struct device. This function | |
1802 | * finds the corresponding IOMMU, the protection domain and the | |
1803 | * requestor id for a given device. | |
1804 | * If the device is not yet associated with a domain this is also done | |
1805 | * in this function. | |
1806 | */ | |
94f6d190 | 1807 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1808 | { |
94f6d190 | 1809 | struct protection_domain *domain; |
b20ac0d4 | 1810 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1811 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1812 | |
f99c0f1c | 1813 | if (!check_device(dev)) |
94f6d190 | 1814 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1815 | |
94f6d190 JR |
1816 | domain = domain_for_device(dev); |
1817 | if (domain != NULL && !dma_ops_domain(domain)) | |
1818 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1819 | |
94f6d190 JR |
1820 | if (domain != NULL) |
1821 | return domain; | |
b20ac0d4 | 1822 | |
15898bbc | 1823 | /* Device not bount yet - bind it */ |
94f6d190 | 1824 | dma_dom = find_protection_domain(devid); |
15898bbc | 1825 | if (!dma_dom) |
94f6d190 JR |
1826 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1827 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1828 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1829 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1830 | |
94f6d190 | 1831 | return &dma_dom->domain; |
b20ac0d4 JR |
1832 | } |
1833 | ||
04bfdd84 JR |
1834 | static void update_device_table(struct protection_domain *domain) |
1835 | { | |
492667da | 1836 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1837 | |
492667da | 1838 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
fd7b5535 | 1839 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); |
492667da | 1840 | u16 devid = get_device_id(dev_data->dev); |
fd7b5535 | 1841 | set_dte_entry(devid, domain, pci_ats_enabled(pdev)); |
04bfdd84 JR |
1842 | } |
1843 | } | |
1844 | ||
1845 | static void update_domain(struct protection_domain *domain) | |
1846 | { | |
1847 | if (!domain->updated) | |
1848 | return; | |
1849 | ||
1850 | update_device_table(domain); | |
17b124bf JR |
1851 | |
1852 | domain_flush_devices(domain); | |
1853 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1854 | |
1855 | domain->updated = false; | |
1856 | } | |
1857 | ||
8bda3092 JR |
1858 | /* |
1859 | * This function fetches the PTE for a given address in the aperture | |
1860 | */ | |
1861 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1862 | unsigned long address) | |
1863 | { | |
384de729 | 1864 | struct aperture_range *aperture; |
8bda3092 JR |
1865 | u64 *pte, *pte_page; |
1866 | ||
384de729 JR |
1867 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1868 | if (!aperture) | |
1869 | return NULL; | |
1870 | ||
1871 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1872 | if (!pte) { |
cbb9d729 | 1873 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1874 | GFP_ATOMIC); |
384de729 JR |
1875 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1876 | } else | |
8c8c143c | 1877 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1878 | |
04bfdd84 | 1879 | update_domain(&dom->domain); |
8bda3092 JR |
1880 | |
1881 | return pte; | |
1882 | } | |
1883 | ||
431b2a20 JR |
1884 | /* |
1885 | * This is the generic map function. It maps one 4kb page at paddr to | |
1886 | * the given address in the DMA address space for the domain. | |
1887 | */ | |
680525e0 | 1888 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1889 | unsigned long address, |
1890 | phys_addr_t paddr, | |
1891 | int direction) | |
1892 | { | |
1893 | u64 *pte, __pte; | |
1894 | ||
1895 | WARN_ON(address > dom->aperture_size); | |
1896 | ||
1897 | paddr &= PAGE_MASK; | |
1898 | ||
8bda3092 | 1899 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1900 | if (!pte) |
8fd524b3 | 1901 | return DMA_ERROR_CODE; |
cb76c322 JR |
1902 | |
1903 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1904 | ||
1905 | if (direction == DMA_TO_DEVICE) | |
1906 | __pte |= IOMMU_PTE_IR; | |
1907 | else if (direction == DMA_FROM_DEVICE) | |
1908 | __pte |= IOMMU_PTE_IW; | |
1909 | else if (direction == DMA_BIDIRECTIONAL) | |
1910 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1911 | ||
1912 | WARN_ON(*pte); | |
1913 | ||
1914 | *pte = __pte; | |
1915 | ||
1916 | return (dma_addr_t)address; | |
1917 | } | |
1918 | ||
431b2a20 JR |
1919 | /* |
1920 | * The generic unmapping function for on page in the DMA address space. | |
1921 | */ | |
680525e0 | 1922 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1923 | unsigned long address) |
1924 | { | |
384de729 | 1925 | struct aperture_range *aperture; |
cb76c322 JR |
1926 | u64 *pte; |
1927 | ||
1928 | if (address >= dom->aperture_size) | |
1929 | return; | |
1930 | ||
384de729 JR |
1931 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1932 | if (!aperture) | |
1933 | return; | |
1934 | ||
1935 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1936 | if (!pte) | |
1937 | return; | |
cb76c322 | 1938 | |
8c8c143c | 1939 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1940 | |
1941 | WARN_ON(!*pte); | |
1942 | ||
1943 | *pte = 0ULL; | |
1944 | } | |
1945 | ||
431b2a20 JR |
1946 | /* |
1947 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1948 | * contiguous memory region into DMA address space. It is used by all |
1949 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1950 | * Must be called with the domain lock held. |
1951 | */ | |
cb76c322 | 1952 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1953 | struct dma_ops_domain *dma_dom, |
1954 | phys_addr_t paddr, | |
1955 | size_t size, | |
6d4f343f | 1956 | int dir, |
832a90c3 JR |
1957 | bool align, |
1958 | u64 dma_mask) | |
cb76c322 JR |
1959 | { |
1960 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1961 | dma_addr_t address, start, ret; |
cb76c322 | 1962 | unsigned int pages; |
6d4f343f | 1963 | unsigned long align_mask = 0; |
cb76c322 JR |
1964 | int i; |
1965 | ||
e3c449f5 | 1966 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1967 | paddr &= PAGE_MASK; |
1968 | ||
8ecaf8f1 JR |
1969 | INC_STATS_COUNTER(total_map_requests); |
1970 | ||
c1858976 JR |
1971 | if (pages > 1) |
1972 | INC_STATS_COUNTER(cross_page); | |
1973 | ||
6d4f343f JR |
1974 | if (align) |
1975 | align_mask = (1UL << get_order(size)) - 1; | |
1976 | ||
11b83888 | 1977 | retry: |
832a90c3 JR |
1978 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1979 | dma_mask); | |
8fd524b3 | 1980 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1981 | /* |
1982 | * setting next_address here will let the address | |
1983 | * allocator only scan the new allocated range in the | |
1984 | * first run. This is a small optimization. | |
1985 | */ | |
1986 | dma_dom->next_address = dma_dom->aperture_size; | |
1987 | ||
576175c2 | 1988 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1989 | goto out; |
1990 | ||
1991 | /* | |
af901ca1 | 1992 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1993 | * allocation again |
1994 | */ | |
1995 | goto retry; | |
1996 | } | |
cb76c322 JR |
1997 | |
1998 | start = address; | |
1999 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2000 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2001 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2002 | goto out_unmap; |
2003 | ||
cb76c322 JR |
2004 | paddr += PAGE_SIZE; |
2005 | start += PAGE_SIZE; | |
2006 | } | |
2007 | address += offset; | |
2008 | ||
5774f7c5 JR |
2009 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2010 | ||
afa9fdc2 | 2011 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2012 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2013 | dma_dom->need_flush = false; |
318afd41 | 2014 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2015 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2016 | |
cb76c322 JR |
2017 | out: |
2018 | return address; | |
53812c11 JR |
2019 | |
2020 | out_unmap: | |
2021 | ||
2022 | for (--i; i >= 0; --i) { | |
2023 | start -= PAGE_SIZE; | |
680525e0 | 2024 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2025 | } |
2026 | ||
2027 | dma_ops_free_addresses(dma_dom, address, pages); | |
2028 | ||
8fd524b3 | 2029 | return DMA_ERROR_CODE; |
cb76c322 JR |
2030 | } |
2031 | ||
431b2a20 JR |
2032 | /* |
2033 | * Does the reverse of the __map_single function. Must be called with | |
2034 | * the domain lock held too | |
2035 | */ | |
cd8c82e8 | 2036 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2037 | dma_addr_t dma_addr, |
2038 | size_t size, | |
2039 | int dir) | |
2040 | { | |
04e0463e | 2041 | dma_addr_t flush_addr; |
cb76c322 JR |
2042 | dma_addr_t i, start; |
2043 | unsigned int pages; | |
2044 | ||
8fd524b3 | 2045 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2046 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2047 | return; |
2048 | ||
04e0463e | 2049 | flush_addr = dma_addr; |
e3c449f5 | 2050 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2051 | dma_addr &= PAGE_MASK; |
2052 | start = dma_addr; | |
2053 | ||
2054 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2055 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2056 | start += PAGE_SIZE; |
2057 | } | |
2058 | ||
5774f7c5 JR |
2059 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2060 | ||
cb76c322 | 2061 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2062 | |
80be308d | 2063 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2064 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2065 | dma_dom->need_flush = false; |
2066 | } | |
cb76c322 JR |
2067 | } |
2068 | ||
431b2a20 JR |
2069 | /* |
2070 | * The exported map_single function for dma_ops. | |
2071 | */ | |
51491367 FT |
2072 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2073 | unsigned long offset, size_t size, | |
2074 | enum dma_data_direction dir, | |
2075 | struct dma_attrs *attrs) | |
4da70b9e JR |
2076 | { |
2077 | unsigned long flags; | |
4da70b9e | 2078 | struct protection_domain *domain; |
4da70b9e | 2079 | dma_addr_t addr; |
832a90c3 | 2080 | u64 dma_mask; |
51491367 | 2081 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2082 | |
0f2a86f2 JR |
2083 | INC_STATS_COUNTER(cnt_map_single); |
2084 | ||
94f6d190 JR |
2085 | domain = get_domain(dev); |
2086 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2087 | return (dma_addr_t)paddr; |
94f6d190 JR |
2088 | else if (IS_ERR(domain)) |
2089 | return DMA_ERROR_CODE; | |
4da70b9e | 2090 | |
f99c0f1c JR |
2091 | dma_mask = *dev->dma_mask; |
2092 | ||
4da70b9e | 2093 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2094 | |
cd8c82e8 | 2095 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2096 | dma_mask); |
8fd524b3 | 2097 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2098 | goto out; |
2099 | ||
17b124bf | 2100 | domain_flush_complete(domain); |
4da70b9e JR |
2101 | |
2102 | out: | |
2103 | spin_unlock_irqrestore(&domain->lock, flags); | |
2104 | ||
2105 | return addr; | |
2106 | } | |
2107 | ||
431b2a20 JR |
2108 | /* |
2109 | * The exported unmap_single function for dma_ops. | |
2110 | */ | |
51491367 FT |
2111 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2112 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2113 | { |
2114 | unsigned long flags; | |
4da70b9e | 2115 | struct protection_domain *domain; |
4da70b9e | 2116 | |
146a6917 JR |
2117 | INC_STATS_COUNTER(cnt_unmap_single); |
2118 | ||
94f6d190 JR |
2119 | domain = get_domain(dev); |
2120 | if (IS_ERR(domain)) | |
5b28df6f JR |
2121 | return; |
2122 | ||
4da70b9e JR |
2123 | spin_lock_irqsave(&domain->lock, flags); |
2124 | ||
cd8c82e8 | 2125 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2126 | |
17b124bf | 2127 | domain_flush_complete(domain); |
4da70b9e JR |
2128 | |
2129 | spin_unlock_irqrestore(&domain->lock, flags); | |
2130 | } | |
2131 | ||
431b2a20 JR |
2132 | /* |
2133 | * This is a special map_sg function which is used if we should map a | |
2134 | * device which is not handled by an AMD IOMMU in the system. | |
2135 | */ | |
65b050ad JR |
2136 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2137 | int nelems, int dir) | |
2138 | { | |
2139 | struct scatterlist *s; | |
2140 | int i; | |
2141 | ||
2142 | for_each_sg(sglist, s, nelems, i) { | |
2143 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2144 | s->dma_length = s->length; | |
2145 | } | |
2146 | ||
2147 | return nelems; | |
2148 | } | |
2149 | ||
431b2a20 JR |
2150 | /* |
2151 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2152 | * lists). | |
2153 | */ | |
65b050ad | 2154 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2155 | int nelems, enum dma_data_direction dir, |
2156 | struct dma_attrs *attrs) | |
65b050ad JR |
2157 | { |
2158 | unsigned long flags; | |
65b050ad | 2159 | struct protection_domain *domain; |
65b050ad JR |
2160 | int i; |
2161 | struct scatterlist *s; | |
2162 | phys_addr_t paddr; | |
2163 | int mapped_elems = 0; | |
832a90c3 | 2164 | u64 dma_mask; |
65b050ad | 2165 | |
d03f067a JR |
2166 | INC_STATS_COUNTER(cnt_map_sg); |
2167 | ||
94f6d190 JR |
2168 | domain = get_domain(dev); |
2169 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2170 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2171 | else if (IS_ERR(domain)) |
2172 | return 0; | |
dbcc112e | 2173 | |
832a90c3 | 2174 | dma_mask = *dev->dma_mask; |
65b050ad | 2175 | |
65b050ad JR |
2176 | spin_lock_irqsave(&domain->lock, flags); |
2177 | ||
2178 | for_each_sg(sglist, s, nelems, i) { | |
2179 | paddr = sg_phys(s); | |
2180 | ||
cd8c82e8 | 2181 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2182 | paddr, s->length, dir, false, |
2183 | dma_mask); | |
65b050ad JR |
2184 | |
2185 | if (s->dma_address) { | |
2186 | s->dma_length = s->length; | |
2187 | mapped_elems++; | |
2188 | } else | |
2189 | goto unmap; | |
65b050ad JR |
2190 | } |
2191 | ||
17b124bf | 2192 | domain_flush_complete(domain); |
65b050ad JR |
2193 | |
2194 | out: | |
2195 | spin_unlock_irqrestore(&domain->lock, flags); | |
2196 | ||
2197 | return mapped_elems; | |
2198 | unmap: | |
2199 | for_each_sg(sglist, s, mapped_elems, i) { | |
2200 | if (s->dma_address) | |
cd8c82e8 | 2201 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2202 | s->dma_length, dir); |
2203 | s->dma_address = s->dma_length = 0; | |
2204 | } | |
2205 | ||
2206 | mapped_elems = 0; | |
2207 | ||
2208 | goto out; | |
2209 | } | |
2210 | ||
431b2a20 JR |
2211 | /* |
2212 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2213 | * lists). | |
2214 | */ | |
65b050ad | 2215 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2216 | int nelems, enum dma_data_direction dir, |
2217 | struct dma_attrs *attrs) | |
65b050ad JR |
2218 | { |
2219 | unsigned long flags; | |
65b050ad JR |
2220 | struct protection_domain *domain; |
2221 | struct scatterlist *s; | |
65b050ad JR |
2222 | int i; |
2223 | ||
55877a6b JR |
2224 | INC_STATS_COUNTER(cnt_unmap_sg); |
2225 | ||
94f6d190 JR |
2226 | domain = get_domain(dev); |
2227 | if (IS_ERR(domain)) | |
5b28df6f JR |
2228 | return; |
2229 | ||
65b050ad JR |
2230 | spin_lock_irqsave(&domain->lock, flags); |
2231 | ||
2232 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2233 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2234 | s->dma_length, dir); |
65b050ad JR |
2235 | s->dma_address = s->dma_length = 0; |
2236 | } | |
2237 | ||
17b124bf | 2238 | domain_flush_complete(domain); |
65b050ad JR |
2239 | |
2240 | spin_unlock_irqrestore(&domain->lock, flags); | |
2241 | } | |
2242 | ||
431b2a20 JR |
2243 | /* |
2244 | * The exported alloc_coherent function for dma_ops. | |
2245 | */ | |
5d8b53cf JR |
2246 | static void *alloc_coherent(struct device *dev, size_t size, |
2247 | dma_addr_t *dma_addr, gfp_t flag) | |
2248 | { | |
2249 | unsigned long flags; | |
2250 | void *virt_addr; | |
5d8b53cf | 2251 | struct protection_domain *domain; |
5d8b53cf | 2252 | phys_addr_t paddr; |
832a90c3 | 2253 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2254 | |
c8f0fb36 JR |
2255 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2256 | ||
94f6d190 JR |
2257 | domain = get_domain(dev); |
2258 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2259 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2260 | *dma_addr = __pa(virt_addr); | |
2261 | return virt_addr; | |
94f6d190 JR |
2262 | } else if (IS_ERR(domain)) |
2263 | return NULL; | |
5d8b53cf | 2264 | |
f99c0f1c JR |
2265 | dma_mask = dev->coherent_dma_mask; |
2266 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2267 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2268 | |
2269 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2270 | if (!virt_addr) | |
b25ae679 | 2271 | return NULL; |
5d8b53cf | 2272 | |
5d8b53cf JR |
2273 | paddr = virt_to_phys(virt_addr); |
2274 | ||
832a90c3 JR |
2275 | if (!dma_mask) |
2276 | dma_mask = *dev->dma_mask; | |
2277 | ||
5d8b53cf JR |
2278 | spin_lock_irqsave(&domain->lock, flags); |
2279 | ||
cd8c82e8 | 2280 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2281 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2282 | |
8fd524b3 | 2283 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2284 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2285 | goto out_free; |
367d04c4 | 2286 | } |
5d8b53cf | 2287 | |
17b124bf | 2288 | domain_flush_complete(domain); |
5d8b53cf | 2289 | |
5d8b53cf JR |
2290 | spin_unlock_irqrestore(&domain->lock, flags); |
2291 | ||
2292 | return virt_addr; | |
5b28df6f JR |
2293 | |
2294 | out_free: | |
2295 | ||
2296 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2297 | ||
2298 | return NULL; | |
5d8b53cf JR |
2299 | } |
2300 | ||
431b2a20 JR |
2301 | /* |
2302 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2303 | */ |
5d8b53cf JR |
2304 | static void free_coherent(struct device *dev, size_t size, |
2305 | void *virt_addr, dma_addr_t dma_addr) | |
2306 | { | |
2307 | unsigned long flags; | |
5d8b53cf | 2308 | struct protection_domain *domain; |
5d8b53cf | 2309 | |
5d31ee7e JR |
2310 | INC_STATS_COUNTER(cnt_free_coherent); |
2311 | ||
94f6d190 JR |
2312 | domain = get_domain(dev); |
2313 | if (IS_ERR(domain)) | |
5b28df6f JR |
2314 | goto free_mem; |
2315 | ||
5d8b53cf JR |
2316 | spin_lock_irqsave(&domain->lock, flags); |
2317 | ||
cd8c82e8 | 2318 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2319 | |
17b124bf | 2320 | domain_flush_complete(domain); |
5d8b53cf JR |
2321 | |
2322 | spin_unlock_irqrestore(&domain->lock, flags); | |
2323 | ||
2324 | free_mem: | |
2325 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2326 | } | |
2327 | ||
b39ba6ad JR |
2328 | /* |
2329 | * This function is called by the DMA layer to find out if we can handle a | |
2330 | * particular device. It is part of the dma_ops. | |
2331 | */ | |
2332 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2333 | { | |
420aef8a | 2334 | return check_device(dev); |
b39ba6ad JR |
2335 | } |
2336 | ||
c432f3df | 2337 | /* |
431b2a20 JR |
2338 | * The function for pre-allocating protection domains. |
2339 | * | |
c432f3df JR |
2340 | * If the driver core informs the DMA layer if a driver grabs a device |
2341 | * we don't need to preallocate the protection domains anymore. | |
2342 | * For now we have to. | |
2343 | */ | |
0e93dd88 | 2344 | static void prealloc_protection_domains(void) |
c432f3df JR |
2345 | { |
2346 | struct pci_dev *dev = NULL; | |
2347 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2348 | u16 devid; |
c432f3df | 2349 | |
d18c69d3 | 2350 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2351 | |
2352 | /* Do we handle this device? */ | |
2353 | if (!check_device(&dev->dev)) | |
c432f3df | 2354 | continue; |
98fc5a69 JR |
2355 | |
2356 | /* Is there already any domain for it? */ | |
15898bbc | 2357 | if (domain_for_device(&dev->dev)) |
c432f3df | 2358 | continue; |
98fc5a69 JR |
2359 | |
2360 | devid = get_device_id(&dev->dev); | |
2361 | ||
87a64d52 | 2362 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2363 | if (!dma_dom) |
2364 | continue; | |
2365 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2366 | dma_dom->target_dev = devid; |
2367 | ||
15898bbc | 2368 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2369 | |
bd60b735 | 2370 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2371 | } |
2372 | } | |
2373 | ||
160c1d8e | 2374 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2375 | .alloc_coherent = alloc_coherent, |
2376 | .free_coherent = free_coherent, | |
51491367 FT |
2377 | .map_page = map_page, |
2378 | .unmap_page = unmap_page, | |
6631ee9d JR |
2379 | .map_sg = map_sg, |
2380 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2381 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2382 | }; |
2383 | ||
431b2a20 JR |
2384 | /* |
2385 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2386 | */ | |
f5325094 JR |
2387 | |
2388 | void __init amd_iommu_init_api(void) | |
2389 | { | |
2390 | register_iommu(&amd_iommu_ops); | |
2391 | } | |
2392 | ||
6631ee9d JR |
2393 | int __init amd_iommu_init_dma_ops(void) |
2394 | { | |
2395 | struct amd_iommu *iommu; | |
6631ee9d JR |
2396 | int ret; |
2397 | ||
431b2a20 JR |
2398 | /* |
2399 | * first allocate a default protection domain for every IOMMU we | |
2400 | * found in the system. Devices not assigned to any other | |
2401 | * protection domain will be assigned to the default one. | |
2402 | */ | |
3bd22172 | 2403 | for_each_iommu(iommu) { |
87a64d52 | 2404 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2405 | if (iommu->default_dom == NULL) |
2406 | return -ENOMEM; | |
e2dc14a2 | 2407 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2408 | ret = iommu_init_unity_mappings(iommu); |
2409 | if (ret) | |
2410 | goto free_domains; | |
2411 | } | |
2412 | ||
431b2a20 | 2413 | /* |
8793abeb | 2414 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2415 | */ |
8793abeb | 2416 | prealloc_protection_domains(); |
6631ee9d JR |
2417 | |
2418 | iommu_detected = 1; | |
75f1cdf1 | 2419 | swiotlb = 0; |
6631ee9d | 2420 | |
431b2a20 | 2421 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2422 | dma_ops = &amd_iommu_dma_ops; |
2423 | ||
7f26508b JR |
2424 | amd_iommu_stats_init(); |
2425 | ||
6631ee9d JR |
2426 | return 0; |
2427 | ||
2428 | free_domains: | |
2429 | ||
3bd22172 | 2430 | for_each_iommu(iommu) { |
6631ee9d JR |
2431 | if (iommu->default_dom) |
2432 | dma_ops_domain_free(iommu->default_dom); | |
2433 | } | |
2434 | ||
2435 | return ret; | |
2436 | } | |
6d98cd80 JR |
2437 | |
2438 | /***************************************************************************** | |
2439 | * | |
2440 | * The following functions belong to the exported interface of AMD IOMMU | |
2441 | * | |
2442 | * This interface allows access to lower level functions of the IOMMU | |
2443 | * like protection domain handling and assignement of devices to domains | |
2444 | * which is not possible with the dma_ops interface. | |
2445 | * | |
2446 | *****************************************************************************/ | |
2447 | ||
6d98cd80 JR |
2448 | static void cleanup_domain(struct protection_domain *domain) |
2449 | { | |
492667da | 2450 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2451 | unsigned long flags; |
6d98cd80 JR |
2452 | |
2453 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2454 | ||
492667da JR |
2455 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2456 | struct device *dev = dev_data->dev; | |
2457 | ||
04e856c0 | 2458 | __detach_device(dev); |
492667da JR |
2459 | atomic_set(&dev_data->bind, 0); |
2460 | } | |
6d98cd80 JR |
2461 | |
2462 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2463 | } | |
2464 | ||
2650815f JR |
2465 | static void protection_domain_free(struct protection_domain *domain) |
2466 | { | |
2467 | if (!domain) | |
2468 | return; | |
2469 | ||
aeb26f55 JR |
2470 | del_domain_from_list(domain); |
2471 | ||
2650815f JR |
2472 | if (domain->id) |
2473 | domain_id_free(domain->id); | |
2474 | ||
2475 | kfree(domain); | |
2476 | } | |
2477 | ||
2478 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2479 | { |
2480 | struct protection_domain *domain; | |
2481 | ||
2482 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2483 | if (!domain) | |
2650815f | 2484 | return NULL; |
c156e347 JR |
2485 | |
2486 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2487 | mutex_init(&domain->api_lock); |
c156e347 JR |
2488 | domain->id = domain_id_alloc(); |
2489 | if (!domain->id) | |
2650815f | 2490 | goto out_err; |
7c392cbe | 2491 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2492 | |
aeb26f55 JR |
2493 | add_domain_to_list(domain); |
2494 | ||
2650815f JR |
2495 | return domain; |
2496 | ||
2497 | out_err: | |
2498 | kfree(domain); | |
2499 | ||
2500 | return NULL; | |
2501 | } | |
2502 | ||
2503 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2504 | { | |
2505 | struct protection_domain *domain; | |
2506 | ||
2507 | domain = protection_domain_alloc(); | |
2508 | if (!domain) | |
c156e347 | 2509 | goto out_free; |
2650815f JR |
2510 | |
2511 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2512 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2513 | if (!domain->pt_root) | |
2514 | goto out_free; | |
2515 | ||
2516 | dom->priv = domain; | |
2517 | ||
2518 | return 0; | |
2519 | ||
2520 | out_free: | |
2650815f | 2521 | protection_domain_free(domain); |
c156e347 JR |
2522 | |
2523 | return -ENOMEM; | |
2524 | } | |
2525 | ||
98383fc3 JR |
2526 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2527 | { | |
2528 | struct protection_domain *domain = dom->priv; | |
2529 | ||
2530 | if (!domain) | |
2531 | return; | |
2532 | ||
2533 | if (domain->dev_cnt > 0) | |
2534 | cleanup_domain(domain); | |
2535 | ||
2536 | BUG_ON(domain->dev_cnt != 0); | |
2537 | ||
2538 | free_pagetable(domain); | |
2539 | ||
8b408fe4 | 2540 | protection_domain_free(domain); |
98383fc3 JR |
2541 | |
2542 | dom->priv = NULL; | |
2543 | } | |
2544 | ||
684f2888 JR |
2545 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2546 | struct device *dev) | |
2547 | { | |
657cbb6b | 2548 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2549 | struct amd_iommu *iommu; |
684f2888 JR |
2550 | u16 devid; |
2551 | ||
98fc5a69 | 2552 | if (!check_device(dev)) |
684f2888 JR |
2553 | return; |
2554 | ||
98fc5a69 | 2555 | devid = get_device_id(dev); |
684f2888 | 2556 | |
657cbb6b | 2557 | if (dev_data->domain != NULL) |
15898bbc | 2558 | detach_device(dev); |
684f2888 JR |
2559 | |
2560 | iommu = amd_iommu_rlookup_table[devid]; | |
2561 | if (!iommu) | |
2562 | return; | |
2563 | ||
d8c13085 | 2564 | device_flush_dte(dev); |
684f2888 JR |
2565 | iommu_completion_wait(iommu); |
2566 | } | |
2567 | ||
01106066 JR |
2568 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2569 | struct device *dev) | |
2570 | { | |
2571 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2572 | struct iommu_dev_data *dev_data; |
01106066 | 2573 | struct amd_iommu *iommu; |
15898bbc | 2574 | int ret; |
01106066 JR |
2575 | u16 devid; |
2576 | ||
98fc5a69 | 2577 | if (!check_device(dev)) |
01106066 JR |
2578 | return -EINVAL; |
2579 | ||
657cbb6b JR |
2580 | dev_data = dev->archdata.iommu; |
2581 | ||
98fc5a69 | 2582 | devid = get_device_id(dev); |
01106066 JR |
2583 | |
2584 | iommu = amd_iommu_rlookup_table[devid]; | |
2585 | if (!iommu) | |
2586 | return -EINVAL; | |
2587 | ||
657cbb6b | 2588 | if (dev_data->domain) |
15898bbc | 2589 | detach_device(dev); |
01106066 | 2590 | |
15898bbc | 2591 | ret = attach_device(dev, domain); |
01106066 JR |
2592 | |
2593 | iommu_completion_wait(iommu); | |
2594 | ||
15898bbc | 2595 | return ret; |
01106066 JR |
2596 | } |
2597 | ||
468e2366 JR |
2598 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2599 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2600 | { |
468e2366 | 2601 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2602 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2603 | int prot = 0; |
2604 | int ret; | |
2605 | ||
2606 | if (iommu_prot & IOMMU_READ) | |
2607 | prot |= IOMMU_PROT_IR; | |
2608 | if (iommu_prot & IOMMU_WRITE) | |
2609 | prot |= IOMMU_PROT_IW; | |
2610 | ||
5d214fe6 | 2611 | mutex_lock(&domain->api_lock); |
795e74f7 | 2612 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2613 | mutex_unlock(&domain->api_lock); |
2614 | ||
795e74f7 | 2615 | return ret; |
c6229ca6 JR |
2616 | } |
2617 | ||
468e2366 JR |
2618 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2619 | int gfp_order) | |
eb74ff6c | 2620 | { |
eb74ff6c | 2621 | struct protection_domain *domain = dom->priv; |
468e2366 | 2622 | unsigned long page_size, unmap_size; |
eb74ff6c | 2623 | |
468e2366 | 2624 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2625 | |
5d214fe6 | 2626 | mutex_lock(&domain->api_lock); |
468e2366 | 2627 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2628 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2629 | |
17b124bf | 2630 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2631 | |
468e2366 | 2632 | return get_order(unmap_size); |
eb74ff6c JR |
2633 | } |
2634 | ||
645c4c8d JR |
2635 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2636 | unsigned long iova) | |
2637 | { | |
2638 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2639 | unsigned long offset_mask; |
645c4c8d | 2640 | phys_addr_t paddr; |
f03152bb | 2641 | u64 *pte, __pte; |
645c4c8d | 2642 | |
24cd7723 | 2643 | pte = fetch_pte(domain, iova); |
645c4c8d | 2644 | |
a6d41a40 | 2645 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2646 | return 0; |
2647 | ||
f03152bb JR |
2648 | if (PM_PTE_LEVEL(*pte) == 0) |
2649 | offset_mask = PAGE_SIZE - 1; | |
2650 | else | |
2651 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2652 | ||
2653 | __pte = *pte & PM_ADDR_MASK; | |
2654 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2655 | |
2656 | return paddr; | |
2657 | } | |
2658 | ||
dbb9fd86 SY |
2659 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2660 | unsigned long cap) | |
2661 | { | |
80a506b8 JR |
2662 | switch (cap) { |
2663 | case IOMMU_CAP_CACHE_COHERENCY: | |
2664 | return 1; | |
2665 | } | |
2666 | ||
dbb9fd86 SY |
2667 | return 0; |
2668 | } | |
2669 | ||
26961efe JR |
2670 | static struct iommu_ops amd_iommu_ops = { |
2671 | .domain_init = amd_iommu_domain_init, | |
2672 | .domain_destroy = amd_iommu_domain_destroy, | |
2673 | .attach_dev = amd_iommu_attach_device, | |
2674 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2675 | .map = amd_iommu_map, |
2676 | .unmap = amd_iommu_unmap, | |
26961efe | 2677 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2678 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2679 | }; |
2680 | ||
0feae533 JR |
2681 | /***************************************************************************** |
2682 | * | |
2683 | * The next functions do a basic initialization of IOMMU for pass through | |
2684 | * mode | |
2685 | * | |
2686 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2687 | * DMA-API translation. | |
2688 | * | |
2689 | *****************************************************************************/ | |
2690 | ||
2691 | int __init amd_iommu_init_passthrough(void) | |
2692 | { | |
15898bbc | 2693 | struct amd_iommu *iommu; |
0feae533 | 2694 | struct pci_dev *dev = NULL; |
15898bbc | 2695 | u16 devid; |
0feae533 | 2696 | |
af901ca1 | 2697 | /* allocate passthrough domain */ |
0feae533 JR |
2698 | pt_domain = protection_domain_alloc(); |
2699 | if (!pt_domain) | |
2700 | return -ENOMEM; | |
2701 | ||
2702 | pt_domain->mode |= PAGE_MODE_NONE; | |
2703 | ||
6c54aabd | 2704 | for_each_pci_dev(dev) { |
98fc5a69 | 2705 | if (!check_device(&dev->dev)) |
0feae533 JR |
2706 | continue; |
2707 | ||
98fc5a69 JR |
2708 | devid = get_device_id(&dev->dev); |
2709 | ||
15898bbc | 2710 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2711 | if (!iommu) |
2712 | continue; | |
2713 | ||
15898bbc | 2714 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2715 | } |
2716 | ||
2717 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2718 | ||
2719 | return 0; | |
2720 | } |