Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
b6c02715 | 30 | #include <asm/proto.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
27c2127a | 33 | #include <asm/dma.h> |
6a9401a7 | 34 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 35 | #include <asm/amd_iommu_types.h> |
c6da992e | 36 | #include <asm/amd_iommu.h> |
b6c02715 JR |
37 | |
38 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
39 | ||
815b33fd | 40 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 41 | |
b6c02715 JR |
42 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
43 | ||
bd60b735 JR |
44 | /* A list of preallocated protection domains */ |
45 | static LIST_HEAD(iommu_pd_list); | |
46 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
47 | ||
8fa5f802 JR |
48 | /* List of all available dev_data structures */ |
49 | static LIST_HEAD(dev_data_list); | |
50 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
51 | ||
0feae533 JR |
52 | /* |
53 | * Domain for untranslated devices - only allocated | |
54 | * if iommu=pt passed on kernel cmd line. | |
55 | */ | |
56 | static struct protection_domain *pt_domain; | |
57 | ||
26961efe | 58 | static struct iommu_ops amd_iommu_ops; |
26961efe | 59 | |
431b2a20 JR |
60 | /* |
61 | * general struct to manage commands send to an IOMMU | |
62 | */ | |
d6449536 | 63 | struct iommu_cmd { |
b6c02715 JR |
64 | u32 data[4]; |
65 | }; | |
66 | ||
04bfdd84 | 67 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 68 | |
15898bbc JR |
69 | /**************************************************************************** |
70 | * | |
71 | * Helper functions | |
72 | * | |
73 | ****************************************************************************/ | |
74 | ||
8fa5f802 JR |
75 | static struct iommu_dev_data *alloc_dev_data(void) |
76 | { | |
77 | struct iommu_dev_data *dev_data; | |
78 | unsigned long flags; | |
79 | ||
80 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
81 | if (!dev_data) | |
82 | return NULL; | |
83 | ||
84 | atomic_set(&dev_data->bind, 0); | |
85 | ||
86 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
87 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
88 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
89 | ||
90 | return dev_data; | |
91 | } | |
92 | ||
93 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
94 | { | |
95 | unsigned long flags; | |
96 | ||
97 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
98 | list_del(&dev_data->dev_data_list); | |
99 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
100 | ||
101 | kfree(dev_data); | |
102 | } | |
103 | ||
15898bbc JR |
104 | static inline u16 get_device_id(struct device *dev) |
105 | { | |
106 | struct pci_dev *pdev = to_pci_dev(dev); | |
107 | ||
108 | return calc_devid(pdev->bus->number, pdev->devfn); | |
109 | } | |
110 | ||
657cbb6b JR |
111 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
112 | { | |
113 | return dev->archdata.iommu; | |
114 | } | |
115 | ||
71c70984 JR |
116 | /* |
117 | * In this function the list of preallocated protection domains is traversed to | |
118 | * find the domain for a specific device | |
119 | */ | |
120 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
121 | { | |
122 | struct dma_ops_domain *entry, *ret = NULL; | |
123 | unsigned long flags; | |
124 | u16 alias = amd_iommu_alias_table[devid]; | |
125 | ||
126 | if (list_empty(&iommu_pd_list)) | |
127 | return NULL; | |
128 | ||
129 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
130 | ||
131 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
132 | if (entry->target_dev == devid || | |
133 | entry->target_dev == alias) { | |
134 | ret = entry; | |
135 | break; | |
136 | } | |
137 | } | |
138 | ||
139 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
140 | ||
141 | return ret; | |
142 | } | |
143 | ||
98fc5a69 JR |
144 | /* |
145 | * This function checks if the driver got a valid device from the caller to | |
146 | * avoid dereferencing invalid pointers. | |
147 | */ | |
148 | static bool check_device(struct device *dev) | |
149 | { | |
150 | u16 devid; | |
151 | ||
152 | if (!dev || !dev->dma_mask) | |
153 | return false; | |
154 | ||
155 | /* No device or no PCI device */ | |
339d3261 | 156 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
157 | return false; |
158 | ||
159 | devid = get_device_id(dev); | |
160 | ||
161 | /* Out of our scope? */ | |
162 | if (devid > amd_iommu_last_bdf) | |
163 | return false; | |
164 | ||
165 | if (amd_iommu_rlookup_table[devid] == NULL) | |
166 | return false; | |
167 | ||
168 | return true; | |
169 | } | |
170 | ||
657cbb6b JR |
171 | static int iommu_init_device(struct device *dev) |
172 | { | |
173 | struct iommu_dev_data *dev_data; | |
174 | struct pci_dev *pdev; | |
8fa5f802 | 175 | u16 alias; |
657cbb6b JR |
176 | |
177 | if (dev->archdata.iommu) | |
178 | return 0; | |
179 | ||
8fa5f802 | 180 | dev_data = alloc_dev_data(); |
657cbb6b JR |
181 | if (!dev_data) |
182 | return -ENOMEM; | |
183 | ||
b00d3bcf JR |
184 | dev_data->dev = dev; |
185 | ||
8fa5f802 | 186 | alias = amd_iommu_alias_table[get_device_id(dev)]; |
657cbb6b JR |
187 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); |
188 | if (pdev) | |
189 | dev_data->alias = &pdev->dev; | |
26018874 | 190 | else { |
8fa5f802 | 191 | free_dev_data(dev_data); |
26018874 JR |
192 | return -ENOTSUPP; |
193 | } | |
657cbb6b JR |
194 | |
195 | dev->archdata.iommu = dev_data; | |
196 | ||
657cbb6b JR |
197 | return 0; |
198 | } | |
199 | ||
26018874 JR |
200 | static void iommu_ignore_device(struct device *dev) |
201 | { | |
202 | u16 devid, alias; | |
203 | ||
204 | devid = get_device_id(dev); | |
205 | alias = amd_iommu_alias_table[devid]; | |
206 | ||
207 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
208 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
209 | ||
210 | amd_iommu_rlookup_table[devid] = NULL; | |
211 | amd_iommu_rlookup_table[alias] = NULL; | |
212 | } | |
213 | ||
657cbb6b JR |
214 | static void iommu_uninit_device(struct device *dev) |
215 | { | |
8fa5f802 JR |
216 | /* |
217 | * Nothing to do here - we keep dev_data around for unplugged devices | |
218 | * and reuse it when the device is re-plugged - not doing so would | |
219 | * introduce a ton of races. | |
220 | */ | |
657cbb6b | 221 | } |
b7cc9554 JR |
222 | |
223 | void __init amd_iommu_uninit_devices(void) | |
224 | { | |
8fa5f802 | 225 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
226 | struct pci_dev *pdev = NULL; |
227 | ||
228 | for_each_pci_dev(pdev) { | |
229 | ||
230 | if (!check_device(&pdev->dev)) | |
231 | continue; | |
232 | ||
233 | iommu_uninit_device(&pdev->dev); | |
234 | } | |
8fa5f802 JR |
235 | |
236 | /* Free all of our dev_data structures */ | |
237 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
238 | free_dev_data(dev_data); | |
b7cc9554 JR |
239 | } |
240 | ||
241 | int __init amd_iommu_init_devices(void) | |
242 | { | |
243 | struct pci_dev *pdev = NULL; | |
244 | int ret = 0; | |
245 | ||
246 | for_each_pci_dev(pdev) { | |
247 | ||
248 | if (!check_device(&pdev->dev)) | |
249 | continue; | |
250 | ||
251 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
252 | if (ret == -ENOTSUPP) |
253 | iommu_ignore_device(&pdev->dev); | |
254 | else if (ret) | |
b7cc9554 JR |
255 | goto out_free; |
256 | } | |
257 | ||
258 | return 0; | |
259 | ||
260 | out_free: | |
261 | ||
262 | amd_iommu_uninit_devices(); | |
263 | ||
264 | return ret; | |
265 | } | |
7f26508b JR |
266 | #ifdef CONFIG_AMD_IOMMU_STATS |
267 | ||
268 | /* | |
269 | * Initialization code for statistics collection | |
270 | */ | |
271 | ||
da49f6df | 272 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 273 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 274 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 275 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 276 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 277 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 278 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 279 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 280 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 281 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 282 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 283 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 284 | |
7f26508b | 285 | static struct dentry *stats_dir; |
7f26508b JR |
286 | static struct dentry *de_fflush; |
287 | ||
288 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
289 | { | |
290 | if (stats_dir == NULL) | |
291 | return; | |
292 | ||
293 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
294 | &cnt->value); | |
295 | } | |
296 | ||
297 | static void amd_iommu_stats_init(void) | |
298 | { | |
299 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
300 | if (stats_dir == NULL) | |
301 | return; | |
302 | ||
7f26508b JR |
303 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
304 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
305 | |
306 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 307 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 308 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 309 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 310 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 311 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 312 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 313 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 314 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 315 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 316 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 317 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
318 | } |
319 | ||
320 | #endif | |
321 | ||
a80dc3e0 JR |
322 | /**************************************************************************** |
323 | * | |
324 | * Interrupt handling functions | |
325 | * | |
326 | ****************************************************************************/ | |
327 | ||
e3e59876 JR |
328 | static void dump_dte_entry(u16 devid) |
329 | { | |
330 | int i; | |
331 | ||
332 | for (i = 0; i < 8; ++i) | |
333 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
334 | amd_iommu_dev_table[devid].data[i]); | |
335 | } | |
336 | ||
945b4ac4 JR |
337 | static void dump_command(unsigned long phys_addr) |
338 | { | |
339 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
340 | int i; | |
341 | ||
342 | for (i = 0; i < 4; ++i) | |
343 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
344 | } | |
345 | ||
a345b23b | 346 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
347 | { |
348 | u32 *event = __evt; | |
349 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
350 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
351 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
352 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
353 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
354 | ||
4c6f40d4 | 355 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
356 | |
357 | switch (type) { | |
358 | case EVENT_TYPE_ILL_DEV: | |
359 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
360 | "address=0x%016llx flags=0x%04x]\n", | |
361 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
362 | address, flags); | |
e3e59876 | 363 | dump_dte_entry(devid); |
90008ee4 JR |
364 | break; |
365 | case EVENT_TYPE_IO_FAULT: | |
366 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
367 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
368 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
369 | domid, address, flags); | |
370 | break; | |
371 | case EVENT_TYPE_DEV_TAB_ERR: | |
372 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
373 | "address=0x%016llx flags=0x%04x]\n", | |
374 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
375 | address, flags); | |
376 | break; | |
377 | case EVENT_TYPE_PAGE_TAB_ERR: | |
378 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
379 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
380 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
381 | domid, address, flags); | |
382 | break; | |
383 | case EVENT_TYPE_ILL_CMD: | |
384 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 385 | dump_command(address); |
90008ee4 JR |
386 | break; |
387 | case EVENT_TYPE_CMD_HARD_ERR: | |
388 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
389 | "flags=0x%04x]\n", address, flags); | |
390 | break; | |
391 | case EVENT_TYPE_IOTLB_INV_TO: | |
392 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
393 | "address=0x%016llx]\n", | |
394 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
395 | address); | |
396 | break; | |
397 | case EVENT_TYPE_INV_DEV_REQ: | |
398 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
399 | "address=0x%016llx flags=0x%04x]\n", | |
400 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
401 | address, flags); | |
402 | break; | |
403 | default: | |
404 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
405 | } | |
406 | } | |
407 | ||
408 | static void iommu_poll_events(struct amd_iommu *iommu) | |
409 | { | |
410 | u32 head, tail; | |
411 | unsigned long flags; | |
412 | ||
413 | spin_lock_irqsave(&iommu->lock, flags); | |
414 | ||
415 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
416 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
417 | ||
418 | while (head != tail) { | |
a345b23b | 419 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
420 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
421 | } | |
422 | ||
423 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
424 | ||
425 | spin_unlock_irqrestore(&iommu->lock, flags); | |
426 | } | |
427 | ||
72fe00f0 | 428 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 429 | { |
90008ee4 JR |
430 | struct amd_iommu *iommu; |
431 | ||
3bd22172 | 432 | for_each_iommu(iommu) |
90008ee4 JR |
433 | iommu_poll_events(iommu); |
434 | ||
435 | return IRQ_HANDLED; | |
a80dc3e0 JR |
436 | } |
437 | ||
72fe00f0 JR |
438 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
439 | { | |
440 | return IRQ_WAKE_THREAD; | |
441 | } | |
442 | ||
431b2a20 JR |
443 | /**************************************************************************** |
444 | * | |
445 | * IOMMU command queuing functions | |
446 | * | |
447 | ****************************************************************************/ | |
448 | ||
ac0ea6e9 JR |
449 | static int wait_on_sem(volatile u64 *sem) |
450 | { | |
451 | int i = 0; | |
452 | ||
453 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
454 | udelay(1); | |
455 | i += 1; | |
456 | } | |
457 | ||
458 | if (i == LOOP_TIMEOUT) { | |
459 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
460 | return -EIO; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
467 | struct iommu_cmd *cmd, | |
468 | u32 tail) | |
a19ae1ec | 469 | { |
a19ae1ec JR |
470 | u8 *target; |
471 | ||
8a7c5ef3 | 472 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
473 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
474 | ||
475 | /* Copy command to buffer */ | |
476 | memcpy(target, cmd, sizeof(*cmd)); | |
477 | ||
478 | /* Tell the IOMMU about it */ | |
a19ae1ec | 479 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 480 | } |
a19ae1ec | 481 | |
815b33fd | 482 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 483 | { |
815b33fd JR |
484 | WARN_ON(address & 0x7ULL); |
485 | ||
ded46737 | 486 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
487 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
488 | cmd->data[1] = upper_32_bits(__pa(address)); | |
489 | cmd->data[2] = 1; | |
ded46737 JR |
490 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
491 | } | |
492 | ||
94fe79e2 JR |
493 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
494 | { | |
495 | memset(cmd, 0, sizeof(*cmd)); | |
496 | cmd->data[0] = devid; | |
497 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
498 | } | |
499 | ||
11b6402c JR |
500 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
501 | size_t size, u16 domid, int pde) | |
502 | { | |
503 | u64 pages; | |
504 | int s; | |
505 | ||
506 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
507 | s = 0; | |
508 | ||
509 | if (pages > 1) { | |
510 | /* | |
511 | * If we have to flush more than one page, flush all | |
512 | * TLB entries for this domain | |
513 | */ | |
514 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
515 | s = 1; | |
516 | } | |
517 | ||
518 | address &= PAGE_MASK; | |
519 | ||
520 | memset(cmd, 0, sizeof(*cmd)); | |
521 | cmd->data[1] |= domid; | |
522 | cmd->data[2] = lower_32_bits(address); | |
523 | cmd->data[3] = upper_32_bits(address); | |
524 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
525 | if (s) /* size bit - we flush more than one 4kb page */ | |
526 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
527 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
528 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
529 | } | |
530 | ||
cb41ed85 JR |
531 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
532 | u64 address, size_t size) | |
533 | { | |
534 | u64 pages; | |
535 | int s; | |
536 | ||
537 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
538 | s = 0; | |
539 | ||
540 | if (pages > 1) { | |
541 | /* | |
542 | * If we have to flush more than one page, flush all | |
543 | * TLB entries for this domain | |
544 | */ | |
545 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
546 | s = 1; | |
547 | } | |
548 | ||
549 | address &= PAGE_MASK; | |
550 | ||
551 | memset(cmd, 0, sizeof(*cmd)); | |
552 | cmd->data[0] = devid; | |
553 | cmd->data[0] |= (qdep & 0xff) << 24; | |
554 | cmd->data[1] = devid; | |
555 | cmd->data[2] = lower_32_bits(address); | |
556 | cmd->data[3] = upper_32_bits(address); | |
557 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
558 | if (s) | |
559 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
560 | } | |
561 | ||
58fc7f14 JR |
562 | static void build_inv_all(struct iommu_cmd *cmd) |
563 | { | |
564 | memset(cmd, 0, sizeof(*cmd)); | |
565 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
566 | } |
567 | ||
431b2a20 | 568 | /* |
431b2a20 | 569 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 570 | * hardware about the new command. |
431b2a20 | 571 | */ |
d6449536 | 572 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 573 | { |
ac0ea6e9 | 574 | u32 left, tail, head, next_tail; |
a19ae1ec | 575 | unsigned long flags; |
a19ae1ec | 576 | |
549c90dc | 577 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
578 | |
579 | again: | |
a19ae1ec | 580 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 581 | |
ac0ea6e9 JR |
582 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
583 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
584 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
585 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 586 | |
ac0ea6e9 JR |
587 | if (left <= 2) { |
588 | struct iommu_cmd sync_cmd; | |
589 | volatile u64 sem = 0; | |
590 | int ret; | |
8d201968 | 591 | |
ac0ea6e9 JR |
592 | build_completion_wait(&sync_cmd, (u64)&sem); |
593 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 594 | |
ac0ea6e9 JR |
595 | spin_unlock_irqrestore(&iommu->lock, flags); |
596 | ||
597 | if ((ret = wait_on_sem(&sem)) != 0) | |
598 | return ret; | |
599 | ||
600 | goto again; | |
8d201968 JR |
601 | } |
602 | ||
ac0ea6e9 JR |
603 | copy_cmd_to_buffer(iommu, cmd, tail); |
604 | ||
605 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 606 | iommu->need_sync = true; |
ac0ea6e9 | 607 | |
a19ae1ec | 608 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 609 | |
815b33fd | 610 | return 0; |
8d201968 JR |
611 | } |
612 | ||
613 | /* | |
614 | * This function queues a completion wait command into the command | |
615 | * buffer of an IOMMU | |
616 | */ | |
a19ae1ec | 617 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
618 | { |
619 | struct iommu_cmd cmd; | |
815b33fd | 620 | volatile u64 sem = 0; |
ac0ea6e9 | 621 | int ret; |
8d201968 | 622 | |
09ee17eb | 623 | if (!iommu->need_sync) |
815b33fd | 624 | return 0; |
09ee17eb | 625 | |
815b33fd | 626 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 627 | |
815b33fd | 628 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 629 | if (ret) |
815b33fd | 630 | return ret; |
8d201968 | 631 | |
ac0ea6e9 | 632 | return wait_on_sem(&sem); |
8d201968 JR |
633 | } |
634 | ||
d8c13085 | 635 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 636 | { |
d8c13085 | 637 | struct iommu_cmd cmd; |
a19ae1ec | 638 | |
d8c13085 | 639 | build_inv_dte(&cmd, devid); |
7e4f88da | 640 | |
d8c13085 JR |
641 | return iommu_queue_command(iommu, &cmd); |
642 | } | |
09ee17eb | 643 | |
7d0c5cc5 JR |
644 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
645 | { | |
646 | u32 devid; | |
09ee17eb | 647 | |
7d0c5cc5 JR |
648 | for (devid = 0; devid <= 0xffff; ++devid) |
649 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 650 | |
7d0c5cc5 JR |
651 | iommu_completion_wait(iommu); |
652 | } | |
84df8175 | 653 | |
7d0c5cc5 JR |
654 | /* |
655 | * This function uses heavy locking and may disable irqs for some time. But | |
656 | * this is no issue because it is only called during resume. | |
657 | */ | |
658 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
659 | { | |
660 | u32 dom_id; | |
a19ae1ec | 661 | |
7d0c5cc5 JR |
662 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
663 | struct iommu_cmd cmd; | |
664 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
665 | dom_id, 1); | |
666 | iommu_queue_command(iommu, &cmd); | |
667 | } | |
8eed9833 | 668 | |
7d0c5cc5 | 669 | iommu_completion_wait(iommu); |
a19ae1ec JR |
670 | } |
671 | ||
58fc7f14 | 672 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 673 | { |
58fc7f14 | 674 | struct iommu_cmd cmd; |
0518a3a4 | 675 | |
58fc7f14 | 676 | build_inv_all(&cmd); |
0518a3a4 | 677 | |
58fc7f14 JR |
678 | iommu_queue_command(iommu, &cmd); |
679 | iommu_completion_wait(iommu); | |
680 | } | |
681 | ||
7d0c5cc5 JR |
682 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
683 | { | |
58fc7f14 JR |
684 | if (iommu_feature(iommu, FEATURE_IA)) { |
685 | iommu_flush_all(iommu); | |
686 | } else { | |
687 | iommu_flush_dte_all(iommu); | |
688 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
689 | } |
690 | } | |
691 | ||
431b2a20 | 692 | /* |
cb41ed85 | 693 | * Command send function for flushing on-device TLB |
431b2a20 | 694 | */ |
cb41ed85 | 695 | static int device_flush_iotlb(struct device *dev, u64 address, size_t size) |
3fa43655 | 696 | { |
cb41ed85 | 697 | struct pci_dev *pdev = to_pci_dev(dev); |
3fa43655 | 698 | struct amd_iommu *iommu; |
b00d3bcf | 699 | struct iommu_cmd cmd; |
3fa43655 | 700 | u16 devid; |
cb41ed85 | 701 | int qdep; |
3fa43655 | 702 | |
cb41ed85 | 703 | qdep = pci_ats_queue_depth(pdev); |
3fa43655 JR |
704 | devid = get_device_id(dev); |
705 | iommu = amd_iommu_rlookup_table[devid]; | |
706 | ||
cb41ed85 | 707 | build_inv_iotlb_pages(&cmd, devid, qdep, address, size); |
b00d3bcf JR |
708 | |
709 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
710 | } |
711 | ||
431b2a20 | 712 | /* |
431b2a20 | 713 | * Command send function for invalidating a device table entry |
431b2a20 | 714 | */ |
d8c13085 | 715 | static int device_flush_dte(struct device *dev) |
a19ae1ec | 716 | { |
3fa43655 | 717 | struct amd_iommu *iommu; |
cb41ed85 | 718 | struct pci_dev *pdev; |
3fa43655 | 719 | u16 devid; |
ee2fa743 | 720 | int ret; |
a19ae1ec | 721 | |
cb41ed85 | 722 | pdev = to_pci_dev(dev); |
3fa43655 JR |
723 | devid = get_device_id(dev); |
724 | iommu = amd_iommu_rlookup_table[devid]; | |
a19ae1ec | 725 | |
cb41ed85 JR |
726 | ret = iommu_flush_dte(iommu, devid); |
727 | if (ret) | |
728 | return ret; | |
729 | ||
730 | if (pci_ats_enabled(pdev)) | |
731 | ret = device_flush_iotlb(dev, 0, ~0UL); | |
ee2fa743 | 732 | |
ee2fa743 | 733 | return ret; |
a19ae1ec JR |
734 | } |
735 | ||
431b2a20 JR |
736 | /* |
737 | * TLB invalidation function which is called from the mapping functions. | |
738 | * It invalidates a single PTE if the range to flush is within a single | |
739 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
740 | */ | |
17b124bf JR |
741 | static void __domain_flush_pages(struct protection_domain *domain, |
742 | u64 address, size_t size, int pde) | |
a19ae1ec | 743 | { |
cb41ed85 | 744 | struct iommu_dev_data *dev_data; |
11b6402c JR |
745 | struct iommu_cmd cmd; |
746 | int ret = 0, i; | |
a19ae1ec | 747 | |
11b6402c | 748 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 749 | |
6de8ad9b JR |
750 | for (i = 0; i < amd_iommus_present; ++i) { |
751 | if (!domain->dev_iommu[i]) | |
752 | continue; | |
753 | ||
754 | /* | |
755 | * Devices of this domain are behind this IOMMU | |
756 | * We need a TLB flush | |
757 | */ | |
11b6402c | 758 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
759 | } |
760 | ||
cb41ed85 JR |
761 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
762 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); | |
763 | ||
764 | if (!pci_ats_enabled(pdev)) | |
765 | continue; | |
766 | ||
767 | ret |= device_flush_iotlb(dev_data->dev, address, size); | |
768 | } | |
769 | ||
11b6402c | 770 | WARN_ON(ret); |
6de8ad9b JR |
771 | } |
772 | ||
17b124bf JR |
773 | static void domain_flush_pages(struct protection_domain *domain, |
774 | u64 address, size_t size) | |
6de8ad9b | 775 | { |
17b124bf | 776 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 777 | } |
b6c02715 | 778 | |
1c655773 | 779 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 780 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 781 | { |
17b124bf | 782 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
783 | } |
784 | ||
42a49f96 | 785 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 786 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 787 | { |
17b124bf | 788 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
789 | } |
790 | ||
17b124bf | 791 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 792 | { |
17b124bf | 793 | int i; |
18811f55 | 794 | |
17b124bf JR |
795 | for (i = 0; i < amd_iommus_present; ++i) { |
796 | if (!domain->dev_iommu[i]) | |
797 | continue; | |
bfd1be18 | 798 | |
17b124bf JR |
799 | /* |
800 | * Devices of this domain are behind this IOMMU | |
801 | * We need to wait for completion of all commands. | |
802 | */ | |
803 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 804 | } |
e394d72a JR |
805 | } |
806 | ||
b00d3bcf | 807 | |
09b42804 | 808 | /* |
b00d3bcf | 809 | * This function flushes the DTEs for all devices in domain |
09b42804 | 810 | */ |
17b124bf | 811 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 812 | { |
b00d3bcf | 813 | struct iommu_dev_data *dev_data; |
09b42804 JR |
814 | unsigned long flags; |
815 | ||
b00d3bcf | 816 | spin_lock_irqsave(&domain->lock, flags); |
b26e81b8 | 817 | |
b00d3bcf | 818 | list_for_each_entry(dev_data, &domain->dev_list, list) |
d8c13085 | 819 | device_flush_dte(dev_data->dev); |
b26e81b8 | 820 | |
b00d3bcf | 821 | spin_unlock_irqrestore(&domain->lock, flags); |
a345b23b JR |
822 | } |
823 | ||
431b2a20 JR |
824 | /**************************************************************************** |
825 | * | |
826 | * The functions below are used the create the page table mappings for | |
827 | * unity mapped regions. | |
828 | * | |
829 | ****************************************************************************/ | |
830 | ||
308973d3 JR |
831 | /* |
832 | * This function is used to add another level to an IO page table. Adding | |
833 | * another level increases the size of the address space by 9 bits to a size up | |
834 | * to 64 bits. | |
835 | */ | |
836 | static bool increase_address_space(struct protection_domain *domain, | |
837 | gfp_t gfp) | |
838 | { | |
839 | u64 *pte; | |
840 | ||
841 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
842 | /* address space already 64 bit large */ | |
843 | return false; | |
844 | ||
845 | pte = (void *)get_zeroed_page(gfp); | |
846 | if (!pte) | |
847 | return false; | |
848 | ||
849 | *pte = PM_LEVEL_PDE(domain->mode, | |
850 | virt_to_phys(domain->pt_root)); | |
851 | domain->pt_root = pte; | |
852 | domain->mode += 1; | |
853 | domain->updated = true; | |
854 | ||
855 | return true; | |
856 | } | |
857 | ||
858 | static u64 *alloc_pte(struct protection_domain *domain, | |
859 | unsigned long address, | |
cbb9d729 | 860 | unsigned long page_size, |
308973d3 JR |
861 | u64 **pte_page, |
862 | gfp_t gfp) | |
863 | { | |
cbb9d729 | 864 | int level, end_lvl; |
308973d3 | 865 | u64 *pte, *page; |
cbb9d729 JR |
866 | |
867 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
868 | |
869 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
870 | increase_address_space(domain, gfp); | |
871 | ||
cbb9d729 JR |
872 | level = domain->mode - 1; |
873 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
874 | address = PAGE_SIZE_ALIGN(address, page_size); | |
875 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
876 | |
877 | while (level > end_lvl) { | |
878 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
879 | page = (u64 *)get_zeroed_page(gfp); | |
880 | if (!page) | |
881 | return NULL; | |
882 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
883 | } | |
884 | ||
cbb9d729 JR |
885 | /* No level skipping support yet */ |
886 | if (PM_PTE_LEVEL(*pte) != level) | |
887 | return NULL; | |
888 | ||
308973d3 JR |
889 | level -= 1; |
890 | ||
891 | pte = IOMMU_PTE_PAGE(*pte); | |
892 | ||
893 | if (pte_page && level == end_lvl) | |
894 | *pte_page = pte; | |
895 | ||
896 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
897 | } | |
898 | ||
899 | return pte; | |
900 | } | |
901 | ||
902 | /* | |
903 | * This function checks if there is a PTE for a given dma address. If | |
904 | * there is one, it returns the pointer to it. | |
905 | */ | |
24cd7723 | 906 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
907 | { |
908 | int level; | |
909 | u64 *pte; | |
910 | ||
24cd7723 JR |
911 | if (address > PM_LEVEL_SIZE(domain->mode)) |
912 | return NULL; | |
913 | ||
914 | level = domain->mode - 1; | |
915 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 916 | |
24cd7723 JR |
917 | while (level > 0) { |
918 | ||
919 | /* Not Present */ | |
308973d3 JR |
920 | if (!IOMMU_PTE_PRESENT(*pte)) |
921 | return NULL; | |
922 | ||
24cd7723 JR |
923 | /* Large PTE */ |
924 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
925 | unsigned long pte_mask, __pte; | |
926 | ||
927 | /* | |
928 | * If we have a series of large PTEs, make | |
929 | * sure to return a pointer to the first one. | |
930 | */ | |
931 | pte_mask = PTE_PAGE_SIZE(*pte); | |
932 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
933 | __pte = ((unsigned long)pte) & pte_mask; | |
934 | ||
935 | return (u64 *)__pte; | |
936 | } | |
937 | ||
938 | /* No level skipping support yet */ | |
939 | if (PM_PTE_LEVEL(*pte) != level) | |
940 | return NULL; | |
941 | ||
308973d3 JR |
942 | level -= 1; |
943 | ||
24cd7723 | 944 | /* Walk to the next level */ |
308973d3 JR |
945 | pte = IOMMU_PTE_PAGE(*pte); |
946 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
947 | } |
948 | ||
949 | return pte; | |
950 | } | |
951 | ||
431b2a20 JR |
952 | /* |
953 | * Generic mapping functions. It maps a physical address into a DMA | |
954 | * address space. It allocates the page table pages if necessary. | |
955 | * In the future it can be extended to a generic mapping function | |
956 | * supporting all features of AMD IOMMU page tables like level skipping | |
957 | * and full 64 bit address spaces. | |
958 | */ | |
38e817fe JR |
959 | static int iommu_map_page(struct protection_domain *dom, |
960 | unsigned long bus_addr, | |
961 | unsigned long phys_addr, | |
abdc5eb3 | 962 | int prot, |
cbb9d729 | 963 | unsigned long page_size) |
bd0e5211 | 964 | { |
8bda3092 | 965 | u64 __pte, *pte; |
cbb9d729 | 966 | int i, count; |
abdc5eb3 | 967 | |
bad1cac2 | 968 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
969 | return -EINVAL; |
970 | ||
cbb9d729 JR |
971 | bus_addr = PAGE_ALIGN(bus_addr); |
972 | phys_addr = PAGE_ALIGN(phys_addr); | |
973 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
974 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
975 | ||
976 | for (i = 0; i < count; ++i) | |
977 | if (IOMMU_PTE_PRESENT(pte[i])) | |
978 | return -EBUSY; | |
bd0e5211 | 979 | |
cbb9d729 JR |
980 | if (page_size > PAGE_SIZE) { |
981 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
982 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
983 | } else | |
984 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 985 | |
bd0e5211 JR |
986 | if (prot & IOMMU_PROT_IR) |
987 | __pte |= IOMMU_PTE_IR; | |
988 | if (prot & IOMMU_PROT_IW) | |
989 | __pte |= IOMMU_PTE_IW; | |
990 | ||
cbb9d729 JR |
991 | for (i = 0; i < count; ++i) |
992 | pte[i] = __pte; | |
bd0e5211 | 993 | |
04bfdd84 JR |
994 | update_domain(dom); |
995 | ||
bd0e5211 JR |
996 | return 0; |
997 | } | |
998 | ||
24cd7723 JR |
999 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1000 | unsigned long bus_addr, | |
1001 | unsigned long page_size) | |
eb74ff6c | 1002 | { |
24cd7723 JR |
1003 | unsigned long long unmap_size, unmapped; |
1004 | u64 *pte; | |
1005 | ||
1006 | BUG_ON(!is_power_of_2(page_size)); | |
1007 | ||
1008 | unmapped = 0; | |
eb74ff6c | 1009 | |
24cd7723 JR |
1010 | while (unmapped < page_size) { |
1011 | ||
1012 | pte = fetch_pte(dom, bus_addr); | |
1013 | ||
1014 | if (!pte) { | |
1015 | /* | |
1016 | * No PTE for this address | |
1017 | * move forward in 4kb steps | |
1018 | */ | |
1019 | unmap_size = PAGE_SIZE; | |
1020 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1021 | /* 4kb PTE found for this address */ | |
1022 | unmap_size = PAGE_SIZE; | |
1023 | *pte = 0ULL; | |
1024 | } else { | |
1025 | int count, i; | |
1026 | ||
1027 | /* Large PTE found which maps this address */ | |
1028 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1029 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1030 | for (i = 0; i < count; i++) | |
1031 | pte[i] = 0ULL; | |
1032 | } | |
1033 | ||
1034 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1035 | unmapped += unmap_size; | |
1036 | } | |
1037 | ||
1038 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1039 | |
24cd7723 | 1040 | return unmapped; |
eb74ff6c | 1041 | } |
eb74ff6c | 1042 | |
431b2a20 JR |
1043 | /* |
1044 | * This function checks if a specific unity mapping entry is needed for | |
1045 | * this specific IOMMU. | |
1046 | */ | |
bd0e5211 JR |
1047 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1048 | struct unity_map_entry *entry) | |
1049 | { | |
1050 | u16 bdf, i; | |
1051 | ||
1052 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1053 | bdf = amd_iommu_alias_table[i]; | |
1054 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1055 | return 1; | |
1056 | } | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
431b2a20 JR |
1061 | /* |
1062 | * This function actually applies the mapping to the page table of the | |
1063 | * dma_ops domain. | |
1064 | */ | |
bd0e5211 JR |
1065 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1066 | struct unity_map_entry *e) | |
1067 | { | |
1068 | u64 addr; | |
1069 | int ret; | |
1070 | ||
1071 | for (addr = e->address_start; addr < e->address_end; | |
1072 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1073 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1074 | PAGE_SIZE); |
bd0e5211 JR |
1075 | if (ret) |
1076 | return ret; | |
1077 | /* | |
1078 | * if unity mapping is in aperture range mark the page | |
1079 | * as allocated in the aperture | |
1080 | */ | |
1081 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1082 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1083 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1084 | } |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
171e7b37 JR |
1089 | /* |
1090 | * Init the unity mappings for a specific IOMMU in the system | |
1091 | * | |
1092 | * Basically iterates over all unity mapping entries and applies them to | |
1093 | * the default domain DMA of that IOMMU if necessary. | |
1094 | */ | |
1095 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1096 | { | |
1097 | struct unity_map_entry *entry; | |
1098 | int ret; | |
1099 | ||
1100 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1101 | if (!iommu_for_unity_map(iommu, entry)) | |
1102 | continue; | |
1103 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1104 | if (ret) | |
1105 | return ret; | |
1106 | } | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
431b2a20 JR |
1111 | /* |
1112 | * Inits the unity mappings required for a specific device | |
1113 | */ | |
bd0e5211 JR |
1114 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1115 | u16 devid) | |
1116 | { | |
1117 | struct unity_map_entry *e; | |
1118 | int ret; | |
1119 | ||
1120 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1121 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1122 | continue; | |
1123 | ret = dma_ops_unity_map(dma_dom, e); | |
1124 | if (ret) | |
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
431b2a20 JR |
1131 | /**************************************************************************** |
1132 | * | |
1133 | * The next functions belong to the address allocator for the dma_ops | |
1134 | * interface functions. They work like the allocators in the other IOMMU | |
1135 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1136 | * the aperture. Maybe it could be enhanced in the future to a more | |
1137 | * efficient allocator. | |
1138 | * | |
1139 | ****************************************************************************/ | |
d3086444 | 1140 | |
431b2a20 | 1141 | /* |
384de729 | 1142 | * The address allocator core functions. |
431b2a20 JR |
1143 | * |
1144 | * called with domain->lock held | |
1145 | */ | |
384de729 | 1146 | |
171e7b37 JR |
1147 | /* |
1148 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1149 | * ranges. | |
1150 | */ | |
1151 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1152 | unsigned long start_page, | |
1153 | unsigned int pages) | |
1154 | { | |
1155 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1156 | ||
1157 | if (start_page + pages > last_page) | |
1158 | pages = last_page - start_page; | |
1159 | ||
1160 | for (i = start_page; i < start_page + pages; ++i) { | |
1161 | int index = i / APERTURE_RANGE_PAGES; | |
1162 | int page = i % APERTURE_RANGE_PAGES; | |
1163 | __set_bit(page, dom->aperture[index]->bitmap); | |
1164 | } | |
1165 | } | |
1166 | ||
9cabe89b JR |
1167 | /* |
1168 | * This function is used to add a new aperture range to an existing | |
1169 | * aperture in case of dma_ops domain allocation or address allocation | |
1170 | * failure. | |
1171 | */ | |
576175c2 | 1172 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1173 | bool populate, gfp_t gfp) |
1174 | { | |
1175 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1176 | struct amd_iommu *iommu; |
d91afd15 | 1177 | unsigned long i; |
9cabe89b | 1178 | |
f5e9705c JR |
1179 | #ifdef CONFIG_IOMMU_STRESS |
1180 | populate = false; | |
1181 | #endif | |
1182 | ||
9cabe89b JR |
1183 | if (index >= APERTURE_MAX_RANGES) |
1184 | return -ENOMEM; | |
1185 | ||
1186 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1187 | if (!dma_dom->aperture[index]) | |
1188 | return -ENOMEM; | |
1189 | ||
1190 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1191 | if (!dma_dom->aperture[index]->bitmap) | |
1192 | goto out_free; | |
1193 | ||
1194 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1195 | ||
1196 | if (populate) { | |
1197 | unsigned long address = dma_dom->aperture_size; | |
1198 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1199 | u64 *pte, *pte_page; | |
1200 | ||
1201 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1202 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1203 | &pte_page, gfp); |
1204 | if (!pte) | |
1205 | goto out_free; | |
1206 | ||
1207 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1208 | ||
1209 | address += APERTURE_RANGE_SIZE / 64; | |
1210 | } | |
1211 | } | |
1212 | ||
1213 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1214 | ||
b595076a | 1215 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1216 | for_each_iommu(iommu) { |
1217 | if (iommu->exclusion_start && | |
1218 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1219 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1220 | unsigned long startpage; | |
1221 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1222 | iommu->exclusion_length, | |
1223 | PAGE_SIZE); | |
1224 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1225 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1226 | } | |
00cd122a JR |
1227 | } |
1228 | ||
1229 | /* | |
1230 | * Check for areas already mapped as present in the new aperture | |
1231 | * range and mark those pages as reserved in the allocator. Such | |
1232 | * mappings may already exist as a result of requested unity | |
1233 | * mappings for devices. | |
1234 | */ | |
1235 | for (i = dma_dom->aperture[index]->offset; | |
1236 | i < dma_dom->aperture_size; | |
1237 | i += PAGE_SIZE) { | |
24cd7723 | 1238 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1239 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1240 | continue; | |
1241 | ||
1242 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1243 | } | |
1244 | ||
04bfdd84 JR |
1245 | update_domain(&dma_dom->domain); |
1246 | ||
9cabe89b JR |
1247 | return 0; |
1248 | ||
1249 | out_free: | |
04bfdd84 JR |
1250 | update_domain(&dma_dom->domain); |
1251 | ||
9cabe89b JR |
1252 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1253 | ||
1254 | kfree(dma_dom->aperture[index]); | |
1255 | dma_dom->aperture[index] = NULL; | |
1256 | ||
1257 | return -ENOMEM; | |
1258 | } | |
1259 | ||
384de729 JR |
1260 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1261 | struct dma_ops_domain *dom, | |
1262 | unsigned int pages, | |
1263 | unsigned long align_mask, | |
1264 | u64 dma_mask, | |
1265 | unsigned long start) | |
1266 | { | |
803b8cb4 | 1267 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1268 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1269 | int i = start >> APERTURE_RANGE_SHIFT; | |
1270 | unsigned long boundary_size; | |
1271 | unsigned long address = -1; | |
1272 | unsigned long limit; | |
1273 | ||
803b8cb4 JR |
1274 | next_bit >>= PAGE_SHIFT; |
1275 | ||
384de729 JR |
1276 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1277 | PAGE_SIZE) >> PAGE_SHIFT; | |
1278 | ||
1279 | for (;i < max_index; ++i) { | |
1280 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1281 | ||
1282 | if (dom->aperture[i]->offset >= dma_mask) | |
1283 | break; | |
1284 | ||
1285 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1286 | dma_mask >> PAGE_SHIFT); | |
1287 | ||
1288 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1289 | limit, next_bit, pages, 0, | |
1290 | boundary_size, align_mask); | |
1291 | if (address != -1) { | |
1292 | address = dom->aperture[i]->offset + | |
1293 | (address << PAGE_SHIFT); | |
803b8cb4 | 1294 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1295 | break; |
1296 | } | |
1297 | ||
1298 | next_bit = 0; | |
1299 | } | |
1300 | ||
1301 | return address; | |
1302 | } | |
1303 | ||
d3086444 JR |
1304 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1305 | struct dma_ops_domain *dom, | |
6d4f343f | 1306 | unsigned int pages, |
832a90c3 JR |
1307 | unsigned long align_mask, |
1308 | u64 dma_mask) | |
d3086444 | 1309 | { |
d3086444 | 1310 | unsigned long address; |
d3086444 | 1311 | |
fe16f088 JR |
1312 | #ifdef CONFIG_IOMMU_STRESS |
1313 | dom->next_address = 0; | |
1314 | dom->need_flush = true; | |
1315 | #endif | |
d3086444 | 1316 | |
384de729 | 1317 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1318 | dma_mask, dom->next_address); |
d3086444 | 1319 | |
1c655773 | 1320 | if (address == -1) { |
803b8cb4 | 1321 | dom->next_address = 0; |
384de729 JR |
1322 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1323 | dma_mask, 0); | |
1c655773 JR |
1324 | dom->need_flush = true; |
1325 | } | |
d3086444 | 1326 | |
384de729 | 1327 | if (unlikely(address == -1)) |
8fd524b3 | 1328 | address = DMA_ERROR_CODE; |
d3086444 JR |
1329 | |
1330 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1331 | ||
1332 | return address; | |
1333 | } | |
1334 | ||
431b2a20 JR |
1335 | /* |
1336 | * The address free function. | |
1337 | * | |
1338 | * called with domain->lock held | |
1339 | */ | |
d3086444 JR |
1340 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1341 | unsigned long address, | |
1342 | unsigned int pages) | |
1343 | { | |
384de729 JR |
1344 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1345 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1346 | |
384de729 JR |
1347 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1348 | ||
47bccd6b JR |
1349 | #ifdef CONFIG_IOMMU_STRESS |
1350 | if (i < 4) | |
1351 | return; | |
1352 | #endif | |
80be308d | 1353 | |
803b8cb4 | 1354 | if (address >= dom->next_address) |
80be308d | 1355 | dom->need_flush = true; |
384de729 JR |
1356 | |
1357 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1358 | |
a66022c4 | 1359 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1360 | |
d3086444 JR |
1361 | } |
1362 | ||
431b2a20 JR |
1363 | /**************************************************************************** |
1364 | * | |
1365 | * The next functions belong to the domain allocation. A domain is | |
1366 | * allocated for every IOMMU as the default domain. If device isolation | |
1367 | * is enabled, every device get its own domain. The most important thing | |
1368 | * about domains is the page table mapping the DMA address space they | |
1369 | * contain. | |
1370 | * | |
1371 | ****************************************************************************/ | |
1372 | ||
aeb26f55 JR |
1373 | /* |
1374 | * This function adds a protection domain to the global protection domain list | |
1375 | */ | |
1376 | static void add_domain_to_list(struct protection_domain *domain) | |
1377 | { | |
1378 | unsigned long flags; | |
1379 | ||
1380 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1381 | list_add(&domain->list, &amd_iommu_pd_list); | |
1382 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1383 | } | |
1384 | ||
1385 | /* | |
1386 | * This function removes a protection domain to the global | |
1387 | * protection domain list | |
1388 | */ | |
1389 | static void del_domain_from_list(struct protection_domain *domain) | |
1390 | { | |
1391 | unsigned long flags; | |
1392 | ||
1393 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1394 | list_del(&domain->list); | |
1395 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1396 | } | |
1397 | ||
ec487d1a JR |
1398 | static u16 domain_id_alloc(void) |
1399 | { | |
1400 | unsigned long flags; | |
1401 | int id; | |
1402 | ||
1403 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1404 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1405 | BUG_ON(id == 0); | |
1406 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1407 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1408 | else | |
1409 | id = 0; | |
1410 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1411 | ||
1412 | return id; | |
1413 | } | |
1414 | ||
a2acfb75 JR |
1415 | static void domain_id_free(int id) |
1416 | { | |
1417 | unsigned long flags; | |
1418 | ||
1419 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1420 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1421 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1422 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1423 | } | |
a2acfb75 | 1424 | |
86db2e5d | 1425 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1426 | { |
1427 | int i, j; | |
1428 | u64 *p1, *p2, *p3; | |
1429 | ||
86db2e5d | 1430 | p1 = domain->pt_root; |
ec487d1a JR |
1431 | |
1432 | if (!p1) | |
1433 | return; | |
1434 | ||
1435 | for (i = 0; i < 512; ++i) { | |
1436 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1437 | continue; | |
1438 | ||
1439 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1440 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1441 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1442 | continue; | |
1443 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1444 | free_page((unsigned long)p3); | |
1445 | } | |
1446 | ||
1447 | free_page((unsigned long)p2); | |
1448 | } | |
1449 | ||
1450 | free_page((unsigned long)p1); | |
86db2e5d JR |
1451 | |
1452 | domain->pt_root = NULL; | |
ec487d1a JR |
1453 | } |
1454 | ||
431b2a20 JR |
1455 | /* |
1456 | * Free a domain, only used if something went wrong in the | |
1457 | * allocation path and we need to free an already allocated page table | |
1458 | */ | |
ec487d1a JR |
1459 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1460 | { | |
384de729 JR |
1461 | int i; |
1462 | ||
ec487d1a JR |
1463 | if (!dom) |
1464 | return; | |
1465 | ||
aeb26f55 JR |
1466 | del_domain_from_list(&dom->domain); |
1467 | ||
86db2e5d | 1468 | free_pagetable(&dom->domain); |
ec487d1a | 1469 | |
384de729 JR |
1470 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1471 | if (!dom->aperture[i]) | |
1472 | continue; | |
1473 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1474 | kfree(dom->aperture[i]); | |
1475 | } | |
ec487d1a JR |
1476 | |
1477 | kfree(dom); | |
1478 | } | |
1479 | ||
431b2a20 JR |
1480 | /* |
1481 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1482 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1483 | * structures required for the dma_ops interface |
1484 | */ | |
87a64d52 | 1485 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1486 | { |
1487 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1488 | |
1489 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1490 | if (!dma_dom) | |
1491 | return NULL; | |
1492 | ||
1493 | spin_lock_init(&dma_dom->domain.lock); | |
1494 | ||
1495 | dma_dom->domain.id = domain_id_alloc(); | |
1496 | if (dma_dom->domain.id == 0) | |
1497 | goto free_dma_dom; | |
7c392cbe | 1498 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1499 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1500 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1501 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1502 | dma_dom->domain.priv = dma_dom; |
1503 | if (!dma_dom->domain.pt_root) | |
1504 | goto free_dma_dom; | |
ec487d1a | 1505 | |
1c655773 | 1506 | dma_dom->need_flush = false; |
bd60b735 | 1507 | dma_dom->target_dev = 0xffff; |
1c655773 | 1508 | |
aeb26f55 JR |
1509 | add_domain_to_list(&dma_dom->domain); |
1510 | ||
576175c2 | 1511 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1512 | goto free_dma_dom; |
ec487d1a | 1513 | |
431b2a20 | 1514 | /* |
ec487d1a JR |
1515 | * mark the first page as allocated so we never return 0 as |
1516 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1517 | */ |
384de729 | 1518 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1519 | dma_dom->next_address = 0; |
ec487d1a | 1520 | |
ec487d1a JR |
1521 | |
1522 | return dma_dom; | |
1523 | ||
1524 | free_dma_dom: | |
1525 | dma_ops_domain_free(dma_dom); | |
1526 | ||
1527 | return NULL; | |
1528 | } | |
1529 | ||
5b28df6f JR |
1530 | /* |
1531 | * little helper function to check whether a given protection domain is a | |
1532 | * dma_ops domain | |
1533 | */ | |
1534 | static bool dma_ops_domain(struct protection_domain *domain) | |
1535 | { | |
1536 | return domain->flags & PD_DMA_OPS_MASK; | |
1537 | } | |
1538 | ||
fd7b5535 | 1539 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1540 | { |
b20ac0d4 | 1541 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1542 | u32 flags = 0; |
863c74eb | 1543 | |
38ddf41b JR |
1544 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1545 | << DEV_ENTRY_MODE_SHIFT; | |
1546 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1547 | |
fd7b5535 JR |
1548 | if (ats) |
1549 | flags |= DTE_FLAG_IOTLB; | |
1550 | ||
1551 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1552 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1553 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1554 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1555 | } |
1556 | ||
1557 | static void clear_dte_entry(u16 devid) | |
1558 | { | |
15898bbc JR |
1559 | /* remove entry from the device table seen by the hardware */ |
1560 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1561 | amd_iommu_dev_table[devid].data[1] = 0; | |
1562 | amd_iommu_dev_table[devid].data[2] = 0; | |
1563 | ||
1564 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1565 | } |
1566 | ||
1567 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1568 | { | |
1569 | struct iommu_dev_data *dev_data; | |
1570 | struct amd_iommu *iommu; | |
fd7b5535 JR |
1571 | struct pci_dev *pdev; |
1572 | bool ats = false; | |
7f760ddd JR |
1573 | u16 devid; |
1574 | ||
1575 | devid = get_device_id(dev); | |
1576 | iommu = amd_iommu_rlookup_table[devid]; | |
1577 | dev_data = get_dev_data(dev); | |
fd7b5535 JR |
1578 | pdev = to_pci_dev(dev); |
1579 | ||
1580 | if (amd_iommu_iotlb_sup) | |
1581 | ats = pci_ats_enabled(pdev); | |
7f760ddd JR |
1582 | |
1583 | /* Update data structures */ | |
1584 | dev_data->domain = domain; | |
1585 | list_add(&dev_data->list, &domain->dev_list); | |
fd7b5535 | 1586 | set_dte_entry(devid, domain, ats); |
7f760ddd JR |
1587 | |
1588 | /* Do reference counting */ | |
1589 | domain->dev_iommu[iommu->index] += 1; | |
1590 | domain->dev_cnt += 1; | |
1591 | ||
1592 | /* Flush the DTE entry */ | |
d8c13085 | 1593 | device_flush_dte(dev); |
7f760ddd JR |
1594 | } |
1595 | ||
1596 | static void do_detach(struct device *dev) | |
1597 | { | |
1598 | struct iommu_dev_data *dev_data; | |
1599 | struct amd_iommu *iommu; | |
1600 | u16 devid; | |
1601 | ||
1602 | devid = get_device_id(dev); | |
1603 | iommu = amd_iommu_rlookup_table[devid]; | |
1604 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1605 | |
1606 | /* decrease reference counters */ | |
7f760ddd JR |
1607 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1608 | dev_data->domain->dev_cnt -= 1; | |
1609 | ||
1610 | /* Update data structures */ | |
1611 | dev_data->domain = NULL; | |
1612 | list_del(&dev_data->list); | |
1613 | clear_dte_entry(devid); | |
15898bbc | 1614 | |
7f760ddd | 1615 | /* Flush the DTE entry */ |
d8c13085 | 1616 | device_flush_dte(dev); |
2b681faf JR |
1617 | } |
1618 | ||
1619 | /* | |
1620 | * If a device is not yet associated with a domain, this function does | |
1621 | * assigns it visible for the hardware | |
1622 | */ | |
15898bbc JR |
1623 | static int __attach_device(struct device *dev, |
1624 | struct protection_domain *domain) | |
2b681faf | 1625 | { |
657cbb6b | 1626 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1627 | int ret; |
657cbb6b | 1628 | |
657cbb6b JR |
1629 | dev_data = get_dev_data(dev); |
1630 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1631 | |
657cbb6b JR |
1632 | if (!alias_data) |
1633 | return -EINVAL; | |
15898bbc | 1634 | |
2b681faf JR |
1635 | /* lock domain */ |
1636 | spin_lock(&domain->lock); | |
1637 | ||
15898bbc | 1638 | /* Some sanity checks */ |
84fe6c19 | 1639 | ret = -EBUSY; |
657cbb6b JR |
1640 | if (alias_data->domain != NULL && |
1641 | alias_data->domain != domain) | |
84fe6c19 | 1642 | goto out_unlock; |
eba6ac60 | 1643 | |
657cbb6b JR |
1644 | if (dev_data->domain != NULL && |
1645 | dev_data->domain != domain) | |
84fe6c19 | 1646 | goto out_unlock; |
15898bbc JR |
1647 | |
1648 | /* Do real assignment */ | |
7f760ddd JR |
1649 | if (dev_data->alias != dev) { |
1650 | alias_data = get_dev_data(dev_data->alias); | |
1651 | if (alias_data->domain == NULL) | |
1652 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1653 | |
1654 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1655 | } |
15898bbc | 1656 | |
7f760ddd JR |
1657 | if (dev_data->domain == NULL) |
1658 | do_attach(dev, domain); | |
eba6ac60 | 1659 | |
24100055 JR |
1660 | atomic_inc(&dev_data->bind); |
1661 | ||
84fe6c19 JL |
1662 | ret = 0; |
1663 | ||
1664 | out_unlock: | |
1665 | ||
eba6ac60 JR |
1666 | /* ready */ |
1667 | spin_unlock(&domain->lock); | |
15898bbc | 1668 | |
84fe6c19 | 1669 | return ret; |
0feae533 | 1670 | } |
b20ac0d4 | 1671 | |
407d733e JR |
1672 | /* |
1673 | * If a device is not yet associated with a domain, this function does | |
1674 | * assigns it visible for the hardware | |
1675 | */ | |
15898bbc JR |
1676 | static int attach_device(struct device *dev, |
1677 | struct protection_domain *domain) | |
0feae533 | 1678 | { |
fd7b5535 | 1679 | struct pci_dev *pdev = to_pci_dev(dev); |
eba6ac60 | 1680 | unsigned long flags; |
15898bbc | 1681 | int ret; |
eba6ac60 | 1682 | |
fd7b5535 JR |
1683 | if (amd_iommu_iotlb_sup) |
1684 | pci_enable_ats(pdev, PAGE_SHIFT); | |
1685 | ||
eba6ac60 | 1686 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
15898bbc | 1687 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1688 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1689 | ||
0feae533 JR |
1690 | /* |
1691 | * We might boot into a crash-kernel here. The crashed kernel | |
1692 | * left the caches in the IOMMU dirty. So we have to flush | |
1693 | * here to evict all dirty stuff. | |
1694 | */ | |
17b124bf | 1695 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1696 | |
1697 | return ret; | |
b20ac0d4 JR |
1698 | } |
1699 | ||
355bf553 JR |
1700 | /* |
1701 | * Removes a device from a protection domain (unlocked) | |
1702 | */ | |
15898bbc | 1703 | static void __detach_device(struct device *dev) |
355bf553 | 1704 | { |
657cbb6b | 1705 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1706 | struct iommu_dev_data *alias_data; |
2ca76279 | 1707 | struct protection_domain *domain; |
7c392cbe | 1708 | unsigned long flags; |
c4596114 | 1709 | |
7f760ddd | 1710 | BUG_ON(!dev_data->domain); |
355bf553 | 1711 | |
2ca76279 JR |
1712 | domain = dev_data->domain; |
1713 | ||
1714 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1715 | |
7f760ddd | 1716 | if (dev_data->alias != dev) { |
24100055 | 1717 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1718 | if (atomic_dec_and_test(&alias_data->bind)) |
1719 | do_detach(dev_data->alias); | |
24100055 JR |
1720 | } |
1721 | ||
7f760ddd JR |
1722 | if (atomic_dec_and_test(&dev_data->bind)) |
1723 | do_detach(dev); | |
1724 | ||
2ca76279 | 1725 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1726 | |
1727 | /* | |
1728 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1729 | * passthrough domain if it is detached from any other domain. |
1730 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1731 | */ |
d3ad9373 JR |
1732 | if (iommu_pass_through && |
1733 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1734 | __attach_device(dev, pt_domain); |
355bf553 JR |
1735 | } |
1736 | ||
1737 | /* | |
1738 | * Removes a device from a protection domain (with devtable_lock held) | |
1739 | */ | |
15898bbc | 1740 | static void detach_device(struct device *dev) |
355bf553 | 1741 | { |
fd7b5535 | 1742 | struct pci_dev *pdev = to_pci_dev(dev); |
355bf553 JR |
1743 | unsigned long flags; |
1744 | ||
1745 | /* lock device table */ | |
1746 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1747 | __detach_device(dev); |
355bf553 | 1748 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 JR |
1749 | |
1750 | if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev)) | |
1751 | pci_disable_ats(pdev); | |
355bf553 | 1752 | } |
e275a2a0 | 1753 | |
15898bbc JR |
1754 | /* |
1755 | * Find out the protection domain structure for a given PCI device. This | |
1756 | * will give us the pointer to the page table root for example. | |
1757 | */ | |
1758 | static struct protection_domain *domain_for_device(struct device *dev) | |
1759 | { | |
1760 | struct protection_domain *dom; | |
657cbb6b | 1761 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc | 1762 | unsigned long flags; |
6ec5ff4b | 1763 | u16 devid; |
15898bbc | 1764 | |
657cbb6b | 1765 | devid = get_device_id(dev); |
657cbb6b JR |
1766 | dev_data = get_dev_data(dev); |
1767 | alias_data = get_dev_data(dev_data->alias); | |
1768 | if (!alias_data) | |
1769 | return NULL; | |
15898bbc JR |
1770 | |
1771 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1772 | dom = dev_data->domain; |
15898bbc | 1773 | if (dom == NULL && |
657cbb6b JR |
1774 | alias_data->domain != NULL) { |
1775 | __attach_device(dev, alias_data->domain); | |
1776 | dom = alias_data->domain; | |
15898bbc JR |
1777 | } |
1778 | ||
1779 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1780 | ||
1781 | return dom; | |
1782 | } | |
1783 | ||
e275a2a0 JR |
1784 | static int device_change_notifier(struct notifier_block *nb, |
1785 | unsigned long action, void *data) | |
1786 | { | |
1787 | struct device *dev = data; | |
98fc5a69 | 1788 | u16 devid; |
e275a2a0 JR |
1789 | struct protection_domain *domain; |
1790 | struct dma_ops_domain *dma_domain; | |
1791 | struct amd_iommu *iommu; | |
1ac4cbbc | 1792 | unsigned long flags; |
e275a2a0 | 1793 | |
98fc5a69 JR |
1794 | if (!check_device(dev)) |
1795 | return 0; | |
e275a2a0 | 1796 | |
98fc5a69 JR |
1797 | devid = get_device_id(dev); |
1798 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1799 | |
1800 | switch (action) { | |
c1eee67b | 1801 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1802 | |
1803 | domain = domain_for_device(dev); | |
1804 | ||
e275a2a0 JR |
1805 | if (!domain) |
1806 | goto out; | |
a1ca331c JR |
1807 | if (iommu_pass_through) |
1808 | break; | |
15898bbc | 1809 | detach_device(dev); |
1ac4cbbc JR |
1810 | break; |
1811 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1812 | |
1813 | iommu_init_device(dev); | |
1814 | ||
1815 | domain = domain_for_device(dev); | |
1816 | ||
1ac4cbbc JR |
1817 | /* allocate a protection domain if a device is added */ |
1818 | dma_domain = find_protection_domain(devid); | |
1819 | if (dma_domain) | |
1820 | goto out; | |
87a64d52 | 1821 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1822 | if (!dma_domain) |
1823 | goto out; | |
1824 | dma_domain->target_dev = devid; | |
1825 | ||
1826 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1827 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1828 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1829 | ||
e275a2a0 | 1830 | break; |
657cbb6b JR |
1831 | case BUS_NOTIFY_DEL_DEVICE: |
1832 | ||
1833 | iommu_uninit_device(dev); | |
1834 | ||
e275a2a0 JR |
1835 | default: |
1836 | goto out; | |
1837 | } | |
1838 | ||
e275a2a0 JR |
1839 | iommu_completion_wait(iommu); |
1840 | ||
1841 | out: | |
1842 | return 0; | |
1843 | } | |
1844 | ||
b25ae679 | 1845 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1846 | .notifier_call = device_change_notifier, |
1847 | }; | |
355bf553 | 1848 | |
8638c491 JR |
1849 | void amd_iommu_init_notifier(void) |
1850 | { | |
1851 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1852 | } | |
1853 | ||
431b2a20 JR |
1854 | /***************************************************************************** |
1855 | * | |
1856 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1857 | * | |
1858 | *****************************************************************************/ | |
1859 | ||
1860 | /* | |
1861 | * In the dma_ops path we only have the struct device. This function | |
1862 | * finds the corresponding IOMMU, the protection domain and the | |
1863 | * requestor id for a given device. | |
1864 | * If the device is not yet associated with a domain this is also done | |
1865 | * in this function. | |
1866 | */ | |
94f6d190 | 1867 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1868 | { |
94f6d190 | 1869 | struct protection_domain *domain; |
b20ac0d4 | 1870 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1871 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1872 | |
f99c0f1c | 1873 | if (!check_device(dev)) |
94f6d190 | 1874 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1875 | |
94f6d190 JR |
1876 | domain = domain_for_device(dev); |
1877 | if (domain != NULL && !dma_ops_domain(domain)) | |
1878 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1879 | |
94f6d190 JR |
1880 | if (domain != NULL) |
1881 | return domain; | |
b20ac0d4 | 1882 | |
15898bbc | 1883 | /* Device not bount yet - bind it */ |
94f6d190 | 1884 | dma_dom = find_protection_domain(devid); |
15898bbc | 1885 | if (!dma_dom) |
94f6d190 JR |
1886 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1887 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1888 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1889 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1890 | |
94f6d190 | 1891 | return &dma_dom->domain; |
b20ac0d4 JR |
1892 | } |
1893 | ||
04bfdd84 JR |
1894 | static void update_device_table(struct protection_domain *domain) |
1895 | { | |
492667da | 1896 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1897 | |
492667da | 1898 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
fd7b5535 | 1899 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); |
492667da | 1900 | u16 devid = get_device_id(dev_data->dev); |
fd7b5535 | 1901 | set_dte_entry(devid, domain, pci_ats_enabled(pdev)); |
04bfdd84 JR |
1902 | } |
1903 | } | |
1904 | ||
1905 | static void update_domain(struct protection_domain *domain) | |
1906 | { | |
1907 | if (!domain->updated) | |
1908 | return; | |
1909 | ||
1910 | update_device_table(domain); | |
17b124bf JR |
1911 | |
1912 | domain_flush_devices(domain); | |
1913 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1914 | |
1915 | domain->updated = false; | |
1916 | } | |
1917 | ||
8bda3092 JR |
1918 | /* |
1919 | * This function fetches the PTE for a given address in the aperture | |
1920 | */ | |
1921 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1922 | unsigned long address) | |
1923 | { | |
384de729 | 1924 | struct aperture_range *aperture; |
8bda3092 JR |
1925 | u64 *pte, *pte_page; |
1926 | ||
384de729 JR |
1927 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1928 | if (!aperture) | |
1929 | return NULL; | |
1930 | ||
1931 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1932 | if (!pte) { |
cbb9d729 | 1933 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1934 | GFP_ATOMIC); |
384de729 JR |
1935 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1936 | } else | |
8c8c143c | 1937 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1938 | |
04bfdd84 | 1939 | update_domain(&dom->domain); |
8bda3092 JR |
1940 | |
1941 | return pte; | |
1942 | } | |
1943 | ||
431b2a20 JR |
1944 | /* |
1945 | * This is the generic map function. It maps one 4kb page at paddr to | |
1946 | * the given address in the DMA address space for the domain. | |
1947 | */ | |
680525e0 | 1948 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1949 | unsigned long address, |
1950 | phys_addr_t paddr, | |
1951 | int direction) | |
1952 | { | |
1953 | u64 *pte, __pte; | |
1954 | ||
1955 | WARN_ON(address > dom->aperture_size); | |
1956 | ||
1957 | paddr &= PAGE_MASK; | |
1958 | ||
8bda3092 | 1959 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1960 | if (!pte) |
8fd524b3 | 1961 | return DMA_ERROR_CODE; |
cb76c322 JR |
1962 | |
1963 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1964 | ||
1965 | if (direction == DMA_TO_DEVICE) | |
1966 | __pte |= IOMMU_PTE_IR; | |
1967 | else if (direction == DMA_FROM_DEVICE) | |
1968 | __pte |= IOMMU_PTE_IW; | |
1969 | else if (direction == DMA_BIDIRECTIONAL) | |
1970 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1971 | ||
1972 | WARN_ON(*pte); | |
1973 | ||
1974 | *pte = __pte; | |
1975 | ||
1976 | return (dma_addr_t)address; | |
1977 | } | |
1978 | ||
431b2a20 JR |
1979 | /* |
1980 | * The generic unmapping function for on page in the DMA address space. | |
1981 | */ | |
680525e0 | 1982 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1983 | unsigned long address) |
1984 | { | |
384de729 | 1985 | struct aperture_range *aperture; |
cb76c322 JR |
1986 | u64 *pte; |
1987 | ||
1988 | if (address >= dom->aperture_size) | |
1989 | return; | |
1990 | ||
384de729 JR |
1991 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1992 | if (!aperture) | |
1993 | return; | |
1994 | ||
1995 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1996 | if (!pte) | |
1997 | return; | |
cb76c322 | 1998 | |
8c8c143c | 1999 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2000 | |
2001 | WARN_ON(!*pte); | |
2002 | ||
2003 | *pte = 0ULL; | |
2004 | } | |
2005 | ||
431b2a20 JR |
2006 | /* |
2007 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2008 | * contiguous memory region into DMA address space. It is used by all |
2009 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2010 | * Must be called with the domain lock held. |
2011 | */ | |
cb76c322 | 2012 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2013 | struct dma_ops_domain *dma_dom, |
2014 | phys_addr_t paddr, | |
2015 | size_t size, | |
6d4f343f | 2016 | int dir, |
832a90c3 JR |
2017 | bool align, |
2018 | u64 dma_mask) | |
cb76c322 JR |
2019 | { |
2020 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2021 | dma_addr_t address, start, ret; |
cb76c322 | 2022 | unsigned int pages; |
6d4f343f | 2023 | unsigned long align_mask = 0; |
cb76c322 JR |
2024 | int i; |
2025 | ||
e3c449f5 | 2026 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2027 | paddr &= PAGE_MASK; |
2028 | ||
8ecaf8f1 JR |
2029 | INC_STATS_COUNTER(total_map_requests); |
2030 | ||
c1858976 JR |
2031 | if (pages > 1) |
2032 | INC_STATS_COUNTER(cross_page); | |
2033 | ||
6d4f343f JR |
2034 | if (align) |
2035 | align_mask = (1UL << get_order(size)) - 1; | |
2036 | ||
11b83888 | 2037 | retry: |
832a90c3 JR |
2038 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2039 | dma_mask); | |
8fd524b3 | 2040 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2041 | /* |
2042 | * setting next_address here will let the address | |
2043 | * allocator only scan the new allocated range in the | |
2044 | * first run. This is a small optimization. | |
2045 | */ | |
2046 | dma_dom->next_address = dma_dom->aperture_size; | |
2047 | ||
576175c2 | 2048 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2049 | goto out; |
2050 | ||
2051 | /* | |
af901ca1 | 2052 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2053 | * allocation again |
2054 | */ | |
2055 | goto retry; | |
2056 | } | |
cb76c322 JR |
2057 | |
2058 | start = address; | |
2059 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2060 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2061 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2062 | goto out_unmap; |
2063 | ||
cb76c322 JR |
2064 | paddr += PAGE_SIZE; |
2065 | start += PAGE_SIZE; | |
2066 | } | |
2067 | address += offset; | |
2068 | ||
5774f7c5 JR |
2069 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2070 | ||
afa9fdc2 | 2071 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2072 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2073 | dma_dom->need_flush = false; |
318afd41 | 2074 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2075 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2076 | |
cb76c322 JR |
2077 | out: |
2078 | return address; | |
53812c11 JR |
2079 | |
2080 | out_unmap: | |
2081 | ||
2082 | for (--i; i >= 0; --i) { | |
2083 | start -= PAGE_SIZE; | |
680525e0 | 2084 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2085 | } |
2086 | ||
2087 | dma_ops_free_addresses(dma_dom, address, pages); | |
2088 | ||
8fd524b3 | 2089 | return DMA_ERROR_CODE; |
cb76c322 JR |
2090 | } |
2091 | ||
431b2a20 JR |
2092 | /* |
2093 | * Does the reverse of the __map_single function. Must be called with | |
2094 | * the domain lock held too | |
2095 | */ | |
cd8c82e8 | 2096 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2097 | dma_addr_t dma_addr, |
2098 | size_t size, | |
2099 | int dir) | |
2100 | { | |
04e0463e | 2101 | dma_addr_t flush_addr; |
cb76c322 JR |
2102 | dma_addr_t i, start; |
2103 | unsigned int pages; | |
2104 | ||
8fd524b3 | 2105 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2106 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2107 | return; |
2108 | ||
04e0463e | 2109 | flush_addr = dma_addr; |
e3c449f5 | 2110 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2111 | dma_addr &= PAGE_MASK; |
2112 | start = dma_addr; | |
2113 | ||
2114 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2115 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2116 | start += PAGE_SIZE; |
2117 | } | |
2118 | ||
5774f7c5 JR |
2119 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2120 | ||
cb76c322 | 2121 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2122 | |
80be308d | 2123 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2124 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2125 | dma_dom->need_flush = false; |
2126 | } | |
cb76c322 JR |
2127 | } |
2128 | ||
431b2a20 JR |
2129 | /* |
2130 | * The exported map_single function for dma_ops. | |
2131 | */ | |
51491367 FT |
2132 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2133 | unsigned long offset, size_t size, | |
2134 | enum dma_data_direction dir, | |
2135 | struct dma_attrs *attrs) | |
4da70b9e JR |
2136 | { |
2137 | unsigned long flags; | |
4da70b9e | 2138 | struct protection_domain *domain; |
4da70b9e | 2139 | dma_addr_t addr; |
832a90c3 | 2140 | u64 dma_mask; |
51491367 | 2141 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2142 | |
0f2a86f2 JR |
2143 | INC_STATS_COUNTER(cnt_map_single); |
2144 | ||
94f6d190 JR |
2145 | domain = get_domain(dev); |
2146 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2147 | return (dma_addr_t)paddr; |
94f6d190 JR |
2148 | else if (IS_ERR(domain)) |
2149 | return DMA_ERROR_CODE; | |
4da70b9e | 2150 | |
f99c0f1c JR |
2151 | dma_mask = *dev->dma_mask; |
2152 | ||
4da70b9e | 2153 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2154 | |
cd8c82e8 | 2155 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2156 | dma_mask); |
8fd524b3 | 2157 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2158 | goto out; |
2159 | ||
17b124bf | 2160 | domain_flush_complete(domain); |
4da70b9e JR |
2161 | |
2162 | out: | |
2163 | spin_unlock_irqrestore(&domain->lock, flags); | |
2164 | ||
2165 | return addr; | |
2166 | } | |
2167 | ||
431b2a20 JR |
2168 | /* |
2169 | * The exported unmap_single function for dma_ops. | |
2170 | */ | |
51491367 FT |
2171 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2172 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2173 | { |
2174 | unsigned long flags; | |
4da70b9e | 2175 | struct protection_domain *domain; |
4da70b9e | 2176 | |
146a6917 JR |
2177 | INC_STATS_COUNTER(cnt_unmap_single); |
2178 | ||
94f6d190 JR |
2179 | domain = get_domain(dev); |
2180 | if (IS_ERR(domain)) | |
5b28df6f JR |
2181 | return; |
2182 | ||
4da70b9e JR |
2183 | spin_lock_irqsave(&domain->lock, flags); |
2184 | ||
cd8c82e8 | 2185 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2186 | |
17b124bf | 2187 | domain_flush_complete(domain); |
4da70b9e JR |
2188 | |
2189 | spin_unlock_irqrestore(&domain->lock, flags); | |
2190 | } | |
2191 | ||
431b2a20 JR |
2192 | /* |
2193 | * This is a special map_sg function which is used if we should map a | |
2194 | * device which is not handled by an AMD IOMMU in the system. | |
2195 | */ | |
65b050ad JR |
2196 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2197 | int nelems, int dir) | |
2198 | { | |
2199 | struct scatterlist *s; | |
2200 | int i; | |
2201 | ||
2202 | for_each_sg(sglist, s, nelems, i) { | |
2203 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2204 | s->dma_length = s->length; | |
2205 | } | |
2206 | ||
2207 | return nelems; | |
2208 | } | |
2209 | ||
431b2a20 JR |
2210 | /* |
2211 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2212 | * lists). | |
2213 | */ | |
65b050ad | 2214 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2215 | int nelems, enum dma_data_direction dir, |
2216 | struct dma_attrs *attrs) | |
65b050ad JR |
2217 | { |
2218 | unsigned long flags; | |
65b050ad | 2219 | struct protection_domain *domain; |
65b050ad JR |
2220 | int i; |
2221 | struct scatterlist *s; | |
2222 | phys_addr_t paddr; | |
2223 | int mapped_elems = 0; | |
832a90c3 | 2224 | u64 dma_mask; |
65b050ad | 2225 | |
d03f067a JR |
2226 | INC_STATS_COUNTER(cnt_map_sg); |
2227 | ||
94f6d190 JR |
2228 | domain = get_domain(dev); |
2229 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2230 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2231 | else if (IS_ERR(domain)) |
2232 | return 0; | |
dbcc112e | 2233 | |
832a90c3 | 2234 | dma_mask = *dev->dma_mask; |
65b050ad | 2235 | |
65b050ad JR |
2236 | spin_lock_irqsave(&domain->lock, flags); |
2237 | ||
2238 | for_each_sg(sglist, s, nelems, i) { | |
2239 | paddr = sg_phys(s); | |
2240 | ||
cd8c82e8 | 2241 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2242 | paddr, s->length, dir, false, |
2243 | dma_mask); | |
65b050ad JR |
2244 | |
2245 | if (s->dma_address) { | |
2246 | s->dma_length = s->length; | |
2247 | mapped_elems++; | |
2248 | } else | |
2249 | goto unmap; | |
65b050ad JR |
2250 | } |
2251 | ||
17b124bf | 2252 | domain_flush_complete(domain); |
65b050ad JR |
2253 | |
2254 | out: | |
2255 | spin_unlock_irqrestore(&domain->lock, flags); | |
2256 | ||
2257 | return mapped_elems; | |
2258 | unmap: | |
2259 | for_each_sg(sglist, s, mapped_elems, i) { | |
2260 | if (s->dma_address) | |
cd8c82e8 | 2261 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2262 | s->dma_length, dir); |
2263 | s->dma_address = s->dma_length = 0; | |
2264 | } | |
2265 | ||
2266 | mapped_elems = 0; | |
2267 | ||
2268 | goto out; | |
2269 | } | |
2270 | ||
431b2a20 JR |
2271 | /* |
2272 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2273 | * lists). | |
2274 | */ | |
65b050ad | 2275 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2276 | int nelems, enum dma_data_direction dir, |
2277 | struct dma_attrs *attrs) | |
65b050ad JR |
2278 | { |
2279 | unsigned long flags; | |
65b050ad JR |
2280 | struct protection_domain *domain; |
2281 | struct scatterlist *s; | |
65b050ad JR |
2282 | int i; |
2283 | ||
55877a6b JR |
2284 | INC_STATS_COUNTER(cnt_unmap_sg); |
2285 | ||
94f6d190 JR |
2286 | domain = get_domain(dev); |
2287 | if (IS_ERR(domain)) | |
5b28df6f JR |
2288 | return; |
2289 | ||
65b050ad JR |
2290 | spin_lock_irqsave(&domain->lock, flags); |
2291 | ||
2292 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2293 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2294 | s->dma_length, dir); |
65b050ad JR |
2295 | s->dma_address = s->dma_length = 0; |
2296 | } | |
2297 | ||
17b124bf | 2298 | domain_flush_complete(domain); |
65b050ad JR |
2299 | |
2300 | spin_unlock_irqrestore(&domain->lock, flags); | |
2301 | } | |
2302 | ||
431b2a20 JR |
2303 | /* |
2304 | * The exported alloc_coherent function for dma_ops. | |
2305 | */ | |
5d8b53cf JR |
2306 | static void *alloc_coherent(struct device *dev, size_t size, |
2307 | dma_addr_t *dma_addr, gfp_t flag) | |
2308 | { | |
2309 | unsigned long flags; | |
2310 | void *virt_addr; | |
5d8b53cf | 2311 | struct protection_domain *domain; |
5d8b53cf | 2312 | phys_addr_t paddr; |
832a90c3 | 2313 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2314 | |
c8f0fb36 JR |
2315 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2316 | ||
94f6d190 JR |
2317 | domain = get_domain(dev); |
2318 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2319 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2320 | *dma_addr = __pa(virt_addr); | |
2321 | return virt_addr; | |
94f6d190 JR |
2322 | } else if (IS_ERR(domain)) |
2323 | return NULL; | |
5d8b53cf | 2324 | |
f99c0f1c JR |
2325 | dma_mask = dev->coherent_dma_mask; |
2326 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2327 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2328 | |
2329 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2330 | if (!virt_addr) | |
b25ae679 | 2331 | return NULL; |
5d8b53cf | 2332 | |
5d8b53cf JR |
2333 | paddr = virt_to_phys(virt_addr); |
2334 | ||
832a90c3 JR |
2335 | if (!dma_mask) |
2336 | dma_mask = *dev->dma_mask; | |
2337 | ||
5d8b53cf JR |
2338 | spin_lock_irqsave(&domain->lock, flags); |
2339 | ||
cd8c82e8 | 2340 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2341 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2342 | |
8fd524b3 | 2343 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2344 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2345 | goto out_free; |
367d04c4 | 2346 | } |
5d8b53cf | 2347 | |
17b124bf | 2348 | domain_flush_complete(domain); |
5d8b53cf | 2349 | |
5d8b53cf JR |
2350 | spin_unlock_irqrestore(&domain->lock, flags); |
2351 | ||
2352 | return virt_addr; | |
5b28df6f JR |
2353 | |
2354 | out_free: | |
2355 | ||
2356 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2357 | ||
2358 | return NULL; | |
5d8b53cf JR |
2359 | } |
2360 | ||
431b2a20 JR |
2361 | /* |
2362 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2363 | */ |
5d8b53cf JR |
2364 | static void free_coherent(struct device *dev, size_t size, |
2365 | void *virt_addr, dma_addr_t dma_addr) | |
2366 | { | |
2367 | unsigned long flags; | |
5d8b53cf | 2368 | struct protection_domain *domain; |
5d8b53cf | 2369 | |
5d31ee7e JR |
2370 | INC_STATS_COUNTER(cnt_free_coherent); |
2371 | ||
94f6d190 JR |
2372 | domain = get_domain(dev); |
2373 | if (IS_ERR(domain)) | |
5b28df6f JR |
2374 | goto free_mem; |
2375 | ||
5d8b53cf JR |
2376 | spin_lock_irqsave(&domain->lock, flags); |
2377 | ||
cd8c82e8 | 2378 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2379 | |
17b124bf | 2380 | domain_flush_complete(domain); |
5d8b53cf JR |
2381 | |
2382 | spin_unlock_irqrestore(&domain->lock, flags); | |
2383 | ||
2384 | free_mem: | |
2385 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2386 | } | |
2387 | ||
b39ba6ad JR |
2388 | /* |
2389 | * This function is called by the DMA layer to find out if we can handle a | |
2390 | * particular device. It is part of the dma_ops. | |
2391 | */ | |
2392 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2393 | { | |
420aef8a | 2394 | return check_device(dev); |
b39ba6ad JR |
2395 | } |
2396 | ||
c432f3df | 2397 | /* |
431b2a20 JR |
2398 | * The function for pre-allocating protection domains. |
2399 | * | |
c432f3df JR |
2400 | * If the driver core informs the DMA layer if a driver grabs a device |
2401 | * we don't need to preallocate the protection domains anymore. | |
2402 | * For now we have to. | |
2403 | */ | |
0e93dd88 | 2404 | static void prealloc_protection_domains(void) |
c432f3df JR |
2405 | { |
2406 | struct pci_dev *dev = NULL; | |
2407 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2408 | u16 devid; |
c432f3df | 2409 | |
d18c69d3 | 2410 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2411 | |
2412 | /* Do we handle this device? */ | |
2413 | if (!check_device(&dev->dev)) | |
c432f3df | 2414 | continue; |
98fc5a69 JR |
2415 | |
2416 | /* Is there already any domain for it? */ | |
15898bbc | 2417 | if (domain_for_device(&dev->dev)) |
c432f3df | 2418 | continue; |
98fc5a69 JR |
2419 | |
2420 | devid = get_device_id(&dev->dev); | |
2421 | ||
87a64d52 | 2422 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2423 | if (!dma_dom) |
2424 | continue; | |
2425 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2426 | dma_dom->target_dev = devid; |
2427 | ||
15898bbc | 2428 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2429 | |
bd60b735 | 2430 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2431 | } |
2432 | } | |
2433 | ||
160c1d8e | 2434 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2435 | .alloc_coherent = alloc_coherent, |
2436 | .free_coherent = free_coherent, | |
51491367 FT |
2437 | .map_page = map_page, |
2438 | .unmap_page = unmap_page, | |
6631ee9d JR |
2439 | .map_sg = map_sg, |
2440 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2441 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2442 | }; |
2443 | ||
27c2127a JR |
2444 | static unsigned device_dma_ops_init(void) |
2445 | { | |
2446 | struct pci_dev *pdev = NULL; | |
2447 | unsigned unhandled = 0; | |
2448 | ||
2449 | for_each_pci_dev(pdev) { | |
2450 | if (!check_device(&pdev->dev)) { | |
2451 | unhandled += 1; | |
2452 | continue; | |
2453 | } | |
2454 | ||
2455 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2456 | } | |
2457 | ||
2458 | return unhandled; | |
2459 | } | |
2460 | ||
431b2a20 JR |
2461 | /* |
2462 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2463 | */ | |
f5325094 JR |
2464 | |
2465 | void __init amd_iommu_init_api(void) | |
2466 | { | |
2467 | register_iommu(&amd_iommu_ops); | |
2468 | } | |
2469 | ||
6631ee9d JR |
2470 | int __init amd_iommu_init_dma_ops(void) |
2471 | { | |
2472 | struct amd_iommu *iommu; | |
27c2127a | 2473 | int ret, unhandled; |
6631ee9d | 2474 | |
431b2a20 JR |
2475 | /* |
2476 | * first allocate a default protection domain for every IOMMU we | |
2477 | * found in the system. Devices not assigned to any other | |
2478 | * protection domain will be assigned to the default one. | |
2479 | */ | |
3bd22172 | 2480 | for_each_iommu(iommu) { |
87a64d52 | 2481 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2482 | if (iommu->default_dom == NULL) |
2483 | return -ENOMEM; | |
e2dc14a2 | 2484 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2485 | ret = iommu_init_unity_mappings(iommu); |
2486 | if (ret) | |
2487 | goto free_domains; | |
2488 | } | |
2489 | ||
431b2a20 | 2490 | /* |
8793abeb | 2491 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2492 | */ |
8793abeb | 2493 | prealloc_protection_domains(); |
6631ee9d JR |
2494 | |
2495 | iommu_detected = 1; | |
75f1cdf1 | 2496 | swiotlb = 0; |
6631ee9d | 2497 | |
431b2a20 | 2498 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2499 | unhandled = device_dma_ops_init(); |
2500 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2501 | /* There are unhandled devices - initialize swiotlb for them */ | |
2502 | swiotlb = 1; | |
2503 | } | |
6631ee9d | 2504 | |
7f26508b JR |
2505 | amd_iommu_stats_init(); |
2506 | ||
6631ee9d JR |
2507 | return 0; |
2508 | ||
2509 | free_domains: | |
2510 | ||
3bd22172 | 2511 | for_each_iommu(iommu) { |
6631ee9d JR |
2512 | if (iommu->default_dom) |
2513 | dma_ops_domain_free(iommu->default_dom); | |
2514 | } | |
2515 | ||
2516 | return ret; | |
2517 | } | |
6d98cd80 JR |
2518 | |
2519 | /***************************************************************************** | |
2520 | * | |
2521 | * The following functions belong to the exported interface of AMD IOMMU | |
2522 | * | |
2523 | * This interface allows access to lower level functions of the IOMMU | |
2524 | * like protection domain handling and assignement of devices to domains | |
2525 | * which is not possible with the dma_ops interface. | |
2526 | * | |
2527 | *****************************************************************************/ | |
2528 | ||
6d98cd80 JR |
2529 | static void cleanup_domain(struct protection_domain *domain) |
2530 | { | |
492667da | 2531 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2532 | unsigned long flags; |
6d98cd80 JR |
2533 | |
2534 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2535 | ||
492667da JR |
2536 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2537 | struct device *dev = dev_data->dev; | |
2538 | ||
04e856c0 | 2539 | __detach_device(dev); |
492667da JR |
2540 | atomic_set(&dev_data->bind, 0); |
2541 | } | |
6d98cd80 JR |
2542 | |
2543 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2544 | } | |
2545 | ||
2650815f JR |
2546 | static void protection_domain_free(struct protection_domain *domain) |
2547 | { | |
2548 | if (!domain) | |
2549 | return; | |
2550 | ||
aeb26f55 JR |
2551 | del_domain_from_list(domain); |
2552 | ||
2650815f JR |
2553 | if (domain->id) |
2554 | domain_id_free(domain->id); | |
2555 | ||
2556 | kfree(domain); | |
2557 | } | |
2558 | ||
2559 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2560 | { |
2561 | struct protection_domain *domain; | |
2562 | ||
2563 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2564 | if (!domain) | |
2650815f | 2565 | return NULL; |
c156e347 JR |
2566 | |
2567 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2568 | mutex_init(&domain->api_lock); |
c156e347 JR |
2569 | domain->id = domain_id_alloc(); |
2570 | if (!domain->id) | |
2650815f | 2571 | goto out_err; |
7c392cbe | 2572 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2573 | |
aeb26f55 JR |
2574 | add_domain_to_list(domain); |
2575 | ||
2650815f JR |
2576 | return domain; |
2577 | ||
2578 | out_err: | |
2579 | kfree(domain); | |
2580 | ||
2581 | return NULL; | |
2582 | } | |
2583 | ||
2584 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2585 | { | |
2586 | struct protection_domain *domain; | |
2587 | ||
2588 | domain = protection_domain_alloc(); | |
2589 | if (!domain) | |
c156e347 | 2590 | goto out_free; |
2650815f JR |
2591 | |
2592 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2593 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2594 | if (!domain->pt_root) | |
2595 | goto out_free; | |
2596 | ||
2597 | dom->priv = domain; | |
2598 | ||
2599 | return 0; | |
2600 | ||
2601 | out_free: | |
2650815f | 2602 | protection_domain_free(domain); |
c156e347 JR |
2603 | |
2604 | return -ENOMEM; | |
2605 | } | |
2606 | ||
98383fc3 JR |
2607 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2608 | { | |
2609 | struct protection_domain *domain = dom->priv; | |
2610 | ||
2611 | if (!domain) | |
2612 | return; | |
2613 | ||
2614 | if (domain->dev_cnt > 0) | |
2615 | cleanup_domain(domain); | |
2616 | ||
2617 | BUG_ON(domain->dev_cnt != 0); | |
2618 | ||
2619 | free_pagetable(domain); | |
2620 | ||
8b408fe4 | 2621 | protection_domain_free(domain); |
98383fc3 JR |
2622 | |
2623 | dom->priv = NULL; | |
2624 | } | |
2625 | ||
684f2888 JR |
2626 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2627 | struct device *dev) | |
2628 | { | |
657cbb6b | 2629 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2630 | struct amd_iommu *iommu; |
684f2888 JR |
2631 | u16 devid; |
2632 | ||
98fc5a69 | 2633 | if (!check_device(dev)) |
684f2888 JR |
2634 | return; |
2635 | ||
98fc5a69 | 2636 | devid = get_device_id(dev); |
684f2888 | 2637 | |
657cbb6b | 2638 | if (dev_data->domain != NULL) |
15898bbc | 2639 | detach_device(dev); |
684f2888 JR |
2640 | |
2641 | iommu = amd_iommu_rlookup_table[devid]; | |
2642 | if (!iommu) | |
2643 | return; | |
2644 | ||
684f2888 JR |
2645 | iommu_completion_wait(iommu); |
2646 | } | |
2647 | ||
01106066 JR |
2648 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2649 | struct device *dev) | |
2650 | { | |
2651 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2652 | struct iommu_dev_data *dev_data; |
01106066 | 2653 | struct amd_iommu *iommu; |
15898bbc | 2654 | int ret; |
01106066 JR |
2655 | u16 devid; |
2656 | ||
98fc5a69 | 2657 | if (!check_device(dev)) |
01106066 JR |
2658 | return -EINVAL; |
2659 | ||
657cbb6b JR |
2660 | dev_data = dev->archdata.iommu; |
2661 | ||
98fc5a69 | 2662 | devid = get_device_id(dev); |
01106066 JR |
2663 | |
2664 | iommu = amd_iommu_rlookup_table[devid]; | |
2665 | if (!iommu) | |
2666 | return -EINVAL; | |
2667 | ||
657cbb6b | 2668 | if (dev_data->domain) |
15898bbc | 2669 | detach_device(dev); |
01106066 | 2670 | |
15898bbc | 2671 | ret = attach_device(dev, domain); |
01106066 JR |
2672 | |
2673 | iommu_completion_wait(iommu); | |
2674 | ||
15898bbc | 2675 | return ret; |
01106066 JR |
2676 | } |
2677 | ||
468e2366 JR |
2678 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2679 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2680 | { |
468e2366 | 2681 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2682 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2683 | int prot = 0; |
2684 | int ret; | |
2685 | ||
2686 | if (iommu_prot & IOMMU_READ) | |
2687 | prot |= IOMMU_PROT_IR; | |
2688 | if (iommu_prot & IOMMU_WRITE) | |
2689 | prot |= IOMMU_PROT_IW; | |
2690 | ||
5d214fe6 | 2691 | mutex_lock(&domain->api_lock); |
795e74f7 | 2692 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2693 | mutex_unlock(&domain->api_lock); |
2694 | ||
795e74f7 | 2695 | return ret; |
c6229ca6 JR |
2696 | } |
2697 | ||
468e2366 JR |
2698 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2699 | int gfp_order) | |
eb74ff6c | 2700 | { |
eb74ff6c | 2701 | struct protection_domain *domain = dom->priv; |
468e2366 | 2702 | unsigned long page_size, unmap_size; |
eb74ff6c | 2703 | |
468e2366 | 2704 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2705 | |
5d214fe6 | 2706 | mutex_lock(&domain->api_lock); |
468e2366 | 2707 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2708 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2709 | |
17b124bf | 2710 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2711 | |
468e2366 | 2712 | return get_order(unmap_size); |
eb74ff6c JR |
2713 | } |
2714 | ||
645c4c8d JR |
2715 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2716 | unsigned long iova) | |
2717 | { | |
2718 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2719 | unsigned long offset_mask; |
645c4c8d | 2720 | phys_addr_t paddr; |
f03152bb | 2721 | u64 *pte, __pte; |
645c4c8d | 2722 | |
24cd7723 | 2723 | pte = fetch_pte(domain, iova); |
645c4c8d | 2724 | |
a6d41a40 | 2725 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2726 | return 0; |
2727 | ||
f03152bb JR |
2728 | if (PM_PTE_LEVEL(*pte) == 0) |
2729 | offset_mask = PAGE_SIZE - 1; | |
2730 | else | |
2731 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2732 | ||
2733 | __pte = *pte & PM_ADDR_MASK; | |
2734 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2735 | |
2736 | return paddr; | |
2737 | } | |
2738 | ||
dbb9fd86 SY |
2739 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2740 | unsigned long cap) | |
2741 | { | |
80a506b8 JR |
2742 | switch (cap) { |
2743 | case IOMMU_CAP_CACHE_COHERENCY: | |
2744 | return 1; | |
2745 | } | |
2746 | ||
dbb9fd86 SY |
2747 | return 0; |
2748 | } | |
2749 | ||
26961efe JR |
2750 | static struct iommu_ops amd_iommu_ops = { |
2751 | .domain_init = amd_iommu_domain_init, | |
2752 | .domain_destroy = amd_iommu_domain_destroy, | |
2753 | .attach_dev = amd_iommu_attach_device, | |
2754 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2755 | .map = amd_iommu_map, |
2756 | .unmap = amd_iommu_unmap, | |
26961efe | 2757 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2758 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2759 | }; |
2760 | ||
0feae533 JR |
2761 | /***************************************************************************** |
2762 | * | |
2763 | * The next functions do a basic initialization of IOMMU for pass through | |
2764 | * mode | |
2765 | * | |
2766 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2767 | * DMA-API translation. | |
2768 | * | |
2769 | *****************************************************************************/ | |
2770 | ||
2771 | int __init amd_iommu_init_passthrough(void) | |
2772 | { | |
15898bbc | 2773 | struct amd_iommu *iommu; |
0feae533 | 2774 | struct pci_dev *dev = NULL; |
15898bbc | 2775 | u16 devid; |
0feae533 | 2776 | |
af901ca1 | 2777 | /* allocate passthrough domain */ |
0feae533 JR |
2778 | pt_domain = protection_domain_alloc(); |
2779 | if (!pt_domain) | |
2780 | return -ENOMEM; | |
2781 | ||
2782 | pt_domain->mode |= PAGE_MODE_NONE; | |
2783 | ||
6c54aabd | 2784 | for_each_pci_dev(dev) { |
98fc5a69 | 2785 | if (!check_device(&dev->dev)) |
0feae533 JR |
2786 | continue; |
2787 | ||
98fc5a69 JR |
2788 | devid = get_device_id(&dev->dev); |
2789 | ||
15898bbc | 2790 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2791 | if (!iommu) |
2792 | continue; | |
2793 | ||
15898bbc | 2794 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2795 | } |
2796 | ||
2797 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2798 | ||
2799 | return 0; | |
2800 | } |