Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
a66022c4 | 21 | #include <linux/bitmap.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
a345b23b | 60 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
657cbb6b JR |
76 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
77 | { | |
78 | return dev->archdata.iommu; | |
79 | } | |
80 | ||
71c70984 JR |
81 | /* |
82 | * In this function the list of preallocated protection domains is traversed to | |
83 | * find the domain for a specific device | |
84 | */ | |
85 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
86 | { | |
87 | struct dma_ops_domain *entry, *ret = NULL; | |
88 | unsigned long flags; | |
89 | u16 alias = amd_iommu_alias_table[devid]; | |
90 | ||
91 | if (list_empty(&iommu_pd_list)) | |
92 | return NULL; | |
93 | ||
94 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
95 | ||
96 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
97 | if (entry->target_dev == devid || | |
98 | entry->target_dev == alias) { | |
99 | ret = entry; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
98fc5a69 JR |
109 | /* |
110 | * This function checks if the driver got a valid device from the caller to | |
111 | * avoid dereferencing invalid pointers. | |
112 | */ | |
113 | static bool check_device(struct device *dev) | |
114 | { | |
115 | u16 devid; | |
116 | ||
117 | if (!dev || !dev->dma_mask) | |
118 | return false; | |
119 | ||
120 | /* No device or no PCI device */ | |
339d3261 | 121 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
122 | return false; |
123 | ||
124 | devid = get_device_id(dev); | |
125 | ||
126 | /* Out of our scope? */ | |
127 | if (devid > amd_iommu_last_bdf) | |
128 | return false; | |
129 | ||
130 | if (amd_iommu_rlookup_table[devid] == NULL) | |
131 | return false; | |
132 | ||
133 | return true; | |
134 | } | |
135 | ||
657cbb6b JR |
136 | static int iommu_init_device(struct device *dev) |
137 | { | |
138 | struct iommu_dev_data *dev_data; | |
139 | struct pci_dev *pdev; | |
140 | u16 devid, alias; | |
141 | ||
142 | if (dev->archdata.iommu) | |
143 | return 0; | |
144 | ||
145 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
146 | if (!dev_data) | |
147 | return -ENOMEM; | |
148 | ||
b00d3bcf JR |
149 | dev_data->dev = dev; |
150 | ||
657cbb6b JR |
151 | devid = get_device_id(dev); |
152 | alias = amd_iommu_alias_table[devid]; | |
153 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
154 | if (pdev) | |
155 | dev_data->alias = &pdev->dev; | |
156 | ||
24100055 JR |
157 | atomic_set(&dev_data->bind, 0); |
158 | ||
657cbb6b JR |
159 | dev->archdata.iommu = dev_data; |
160 | ||
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static void iommu_uninit_device(struct device *dev) | |
166 | { | |
167 | kfree(dev->archdata.iommu); | |
168 | } | |
b7cc9554 JR |
169 | |
170 | void __init amd_iommu_uninit_devices(void) | |
171 | { | |
172 | struct pci_dev *pdev = NULL; | |
173 | ||
174 | for_each_pci_dev(pdev) { | |
175 | ||
176 | if (!check_device(&pdev->dev)) | |
177 | continue; | |
178 | ||
179 | iommu_uninit_device(&pdev->dev); | |
180 | } | |
181 | } | |
182 | ||
183 | int __init amd_iommu_init_devices(void) | |
184 | { | |
185 | struct pci_dev *pdev = NULL; | |
186 | int ret = 0; | |
187 | ||
188 | for_each_pci_dev(pdev) { | |
189 | ||
190 | if (!check_device(&pdev->dev)) | |
191 | continue; | |
192 | ||
193 | ret = iommu_init_device(&pdev->dev); | |
194 | if (ret) | |
195 | goto out_free; | |
196 | } | |
197 | ||
198 | return 0; | |
199 | ||
200 | out_free: | |
201 | ||
202 | amd_iommu_uninit_devices(); | |
203 | ||
204 | return ret; | |
205 | } | |
7f26508b JR |
206 | #ifdef CONFIG_AMD_IOMMU_STATS |
207 | ||
208 | /* | |
209 | * Initialization code for statistics collection | |
210 | */ | |
211 | ||
da49f6df | 212 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 213 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 214 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 215 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 216 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 217 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 218 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 219 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 220 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 221 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 222 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 223 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 224 | |
7f26508b | 225 | static struct dentry *stats_dir; |
7f26508b JR |
226 | static struct dentry *de_fflush; |
227 | ||
228 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
229 | { | |
230 | if (stats_dir == NULL) | |
231 | return; | |
232 | ||
233 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
234 | &cnt->value); | |
235 | } | |
236 | ||
237 | static void amd_iommu_stats_init(void) | |
238 | { | |
239 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
240 | if (stats_dir == NULL) | |
241 | return; | |
242 | ||
7f26508b JR |
243 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
244 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
245 | |
246 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 247 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 248 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 249 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 250 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 251 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 252 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 253 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 254 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 255 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 256 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 257 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
258 | } |
259 | ||
260 | #endif | |
261 | ||
a80dc3e0 JR |
262 | /**************************************************************************** |
263 | * | |
264 | * Interrupt handling functions | |
265 | * | |
266 | ****************************************************************************/ | |
267 | ||
e3e59876 JR |
268 | static void dump_dte_entry(u16 devid) |
269 | { | |
270 | int i; | |
271 | ||
272 | for (i = 0; i < 8; ++i) | |
273 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
274 | amd_iommu_dev_table[devid].data[i]); | |
275 | } | |
276 | ||
945b4ac4 JR |
277 | static void dump_command(unsigned long phys_addr) |
278 | { | |
279 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < 4; ++i) | |
283 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
284 | } | |
285 | ||
a345b23b | 286 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
287 | { |
288 | u32 *event = __evt; | |
289 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
290 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
291 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
292 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
293 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
294 | ||
4c6f40d4 | 295 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
296 | |
297 | switch (type) { | |
298 | case EVENT_TYPE_ILL_DEV: | |
299 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
300 | "address=0x%016llx flags=0x%04x]\n", | |
301 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
302 | address, flags); | |
e3e59876 | 303 | dump_dte_entry(devid); |
90008ee4 JR |
304 | break; |
305 | case EVENT_TYPE_IO_FAULT: | |
306 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
307 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
308 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
309 | domid, address, flags); | |
310 | break; | |
311 | case EVENT_TYPE_DEV_TAB_ERR: | |
312 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
313 | "address=0x%016llx flags=0x%04x]\n", | |
314 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
315 | address, flags); | |
316 | break; | |
317 | case EVENT_TYPE_PAGE_TAB_ERR: | |
318 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
319 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
320 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
321 | domid, address, flags); | |
322 | break; | |
323 | case EVENT_TYPE_ILL_CMD: | |
324 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
8eed9833 | 325 | iommu->reset_in_progress = true; |
a345b23b | 326 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 327 | dump_command(address); |
90008ee4 JR |
328 | break; |
329 | case EVENT_TYPE_CMD_HARD_ERR: | |
330 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
331 | "flags=0x%04x]\n", address, flags); | |
332 | break; | |
333 | case EVENT_TYPE_IOTLB_INV_TO: | |
334 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
335 | "address=0x%016llx]\n", | |
336 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
337 | address); | |
338 | break; | |
339 | case EVENT_TYPE_INV_DEV_REQ: | |
340 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
341 | "address=0x%016llx flags=0x%04x]\n", | |
342 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
343 | address, flags); | |
344 | break; | |
345 | default: | |
346 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
347 | } | |
348 | } | |
349 | ||
350 | static void iommu_poll_events(struct amd_iommu *iommu) | |
351 | { | |
352 | u32 head, tail; | |
353 | unsigned long flags; | |
354 | ||
355 | spin_lock_irqsave(&iommu->lock, flags); | |
356 | ||
357 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
358 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
359 | ||
360 | while (head != tail) { | |
a345b23b | 361 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
362 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
363 | } | |
364 | ||
365 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
366 | ||
367 | spin_unlock_irqrestore(&iommu->lock, flags); | |
368 | } | |
369 | ||
a80dc3e0 JR |
370 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
371 | { | |
90008ee4 JR |
372 | struct amd_iommu *iommu; |
373 | ||
3bd22172 | 374 | for_each_iommu(iommu) |
90008ee4 JR |
375 | iommu_poll_events(iommu); |
376 | ||
377 | return IRQ_HANDLED; | |
a80dc3e0 JR |
378 | } |
379 | ||
431b2a20 JR |
380 | /**************************************************************************** |
381 | * | |
382 | * IOMMU command queuing functions | |
383 | * | |
384 | ****************************************************************************/ | |
385 | ||
ded46737 JR |
386 | static void build_completion_wait(struct iommu_cmd *cmd) |
387 | { | |
388 | memset(cmd, 0, sizeof(*cmd)); | |
389 | cmd->data[0] = CMD_COMPL_WAIT_INT_MASK; | |
390 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); | |
391 | } | |
392 | ||
94fe79e2 JR |
393 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
394 | { | |
395 | memset(cmd, 0, sizeof(*cmd)); | |
396 | cmd->data[0] = devid; | |
397 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
398 | } | |
399 | ||
431b2a20 JR |
400 | /* |
401 | * Writes the command to the IOMMUs command buffer and informs the | |
402 | * hardware about the new command. Must be called with iommu->lock held. | |
403 | */ | |
d6449536 | 404 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
405 | { |
406 | u32 tail, head; | |
407 | u8 *target; | |
408 | ||
549c90dc | 409 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
a19ae1ec | 410 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
8a7c5ef3 | 411 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
412 | memcpy_toio(target, cmd, sizeof(*cmd)); |
413 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
414 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
415 | if (tail == head) | |
416 | return -ENOMEM; | |
417 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
431b2a20 JR |
422 | /* |
423 | * General queuing function for commands. Takes iommu->lock and calls | |
424 | * __iommu_queue_command(). | |
425 | */ | |
d6449536 | 426 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
427 | { |
428 | unsigned long flags; | |
429 | int ret; | |
430 | ||
431 | spin_lock_irqsave(&iommu->lock, flags); | |
432 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 433 | if (!ret) |
0cfd7aa9 | 434 | iommu->need_sync = true; |
a19ae1ec JR |
435 | spin_unlock_irqrestore(&iommu->lock, flags); |
436 | ||
437 | return ret; | |
438 | } | |
439 | ||
8d201968 JR |
440 | /* |
441 | * This function waits until an IOMMU has completed a completion | |
442 | * wait command | |
443 | */ | |
444 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
445 | { | |
446 | int ready = 0; | |
447 | unsigned status = 0; | |
448 | unsigned long i = 0; | |
449 | ||
da49f6df JR |
450 | INC_STATS_COUNTER(compl_wait); |
451 | ||
8d201968 JR |
452 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
453 | ++i; | |
454 | /* wait for the bit to become one */ | |
455 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
456 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
457 | } | |
458 | ||
459 | /* set bit back to zero */ | |
460 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
461 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
462 | ||
8eed9833 JR |
463 | if (unlikely(i == EXIT_LOOP_COUNT)) |
464 | iommu->reset_in_progress = true; | |
8d201968 JR |
465 | } |
466 | ||
467 | /* | |
468 | * This function queues a completion wait command into the command | |
469 | * buffer of an IOMMU | |
470 | */ | |
471 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
472 | { | |
473 | struct iommu_cmd cmd; | |
474 | ||
ded46737 | 475 | build_completion_wait(&cmd); |
8d201968 JR |
476 | |
477 | return __iommu_queue_command(iommu, &cmd); | |
478 | } | |
479 | ||
431b2a20 JR |
480 | /* |
481 | * This function is called whenever we need to ensure that the IOMMU has | |
482 | * completed execution of all commands we sent. It sends a | |
483 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
484 | * us about that by writing a value to a physical address we pass with | |
485 | * the command. | |
486 | */ | |
a19ae1ec JR |
487 | static int iommu_completion_wait(struct amd_iommu *iommu) |
488 | { | |
8d201968 JR |
489 | int ret = 0; |
490 | unsigned long flags; | |
a19ae1ec | 491 | |
7e4f88da JR |
492 | spin_lock_irqsave(&iommu->lock, flags); |
493 | ||
09ee17eb JR |
494 | if (!iommu->need_sync) |
495 | goto out; | |
496 | ||
8d201968 | 497 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 498 | |
0cfd7aa9 | 499 | iommu->need_sync = false; |
a19ae1ec JR |
500 | |
501 | if (ret) | |
7e4f88da | 502 | goto out; |
a19ae1ec | 503 | |
8d201968 | 504 | __iommu_wait_for_completion(iommu); |
84df8175 | 505 | |
7e4f88da JR |
506 | out: |
507 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec | 508 | |
8eed9833 JR |
509 | if (iommu->reset_in_progress) |
510 | reset_iommu_command_buffer(iommu); | |
511 | ||
a19ae1ec JR |
512 | return 0; |
513 | } | |
514 | ||
0518a3a4 JR |
515 | static void iommu_flush_complete(struct protection_domain *domain) |
516 | { | |
517 | int i; | |
518 | ||
519 | for (i = 0; i < amd_iommus_present; ++i) { | |
520 | if (!domain->dev_iommu[i]) | |
521 | continue; | |
522 | ||
523 | /* | |
524 | * Devices of this domain are behind this IOMMU | |
525 | * We need to wait for completion of all commands. | |
526 | */ | |
527 | iommu_completion_wait(amd_iommus[i]); | |
528 | } | |
529 | } | |
530 | ||
431b2a20 JR |
531 | /* |
532 | * Command send function for invalidating a device table entry | |
533 | */ | |
3fa43655 JR |
534 | static int iommu_flush_device(struct device *dev) |
535 | { | |
536 | struct amd_iommu *iommu; | |
b00d3bcf | 537 | struct iommu_cmd cmd; |
3fa43655 JR |
538 | u16 devid; |
539 | ||
540 | devid = get_device_id(dev); | |
541 | iommu = amd_iommu_rlookup_table[devid]; | |
542 | ||
94fe79e2 | 543 | build_inv_dte(&cmd, devid); |
b00d3bcf JR |
544 | |
545 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
546 | } |
547 | ||
237b6f33 JR |
548 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
549 | u16 domid, int pde, int s) | |
550 | { | |
551 | memset(cmd, 0, sizeof(*cmd)); | |
552 | address &= PAGE_MASK; | |
553 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
554 | cmd->data[1] |= domid; | |
555 | cmd->data[2] = lower_32_bits(address); | |
556 | cmd->data[3] = upper_32_bits(address); | |
557 | if (s) /* size bit - we flush more than one 4kb page */ | |
558 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
559 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
560 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
561 | } | |
562 | ||
431b2a20 JR |
563 | /* |
564 | * Generic command send function for invalidaing TLB entries | |
565 | */ | |
a19ae1ec JR |
566 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
567 | u64 address, u16 domid, int pde, int s) | |
568 | { | |
d6449536 | 569 | struct iommu_cmd cmd; |
ee2fa743 | 570 | int ret; |
a19ae1ec | 571 | |
237b6f33 | 572 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 573 | |
ee2fa743 JR |
574 | ret = iommu_queue_command(iommu, &cmd); |
575 | ||
ee2fa743 | 576 | return ret; |
a19ae1ec JR |
577 | } |
578 | ||
431b2a20 JR |
579 | /* |
580 | * TLB invalidation function which is called from the mapping functions. | |
581 | * It invalidates a single PTE if the range to flush is within a single | |
582 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
583 | */ | |
6de8ad9b JR |
584 | static void __iommu_flush_pages(struct protection_domain *domain, |
585 | u64 address, size_t size, int pde) | |
a19ae1ec | 586 | { |
6de8ad9b | 587 | int s = 0, i; |
dcd1e92e | 588 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
589 | |
590 | address &= PAGE_MASK; | |
591 | ||
999ba417 JR |
592 | if (pages > 1) { |
593 | /* | |
594 | * If we have to flush more than one page, flush all | |
595 | * TLB entries for this domain | |
596 | */ | |
597 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
598 | s = 1; | |
a19ae1ec JR |
599 | } |
600 | ||
999ba417 | 601 | |
6de8ad9b JR |
602 | for (i = 0; i < amd_iommus_present; ++i) { |
603 | if (!domain->dev_iommu[i]) | |
604 | continue; | |
605 | ||
606 | /* | |
607 | * Devices of this domain are behind this IOMMU | |
608 | * We need a TLB flush | |
609 | */ | |
610 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
611 | domain->id, pde, s); | |
612 | } | |
613 | ||
614 | return; | |
615 | } | |
616 | ||
617 | static void iommu_flush_pages(struct protection_domain *domain, | |
618 | u64 address, size_t size) | |
619 | { | |
620 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 621 | } |
b6c02715 | 622 | |
1c655773 | 623 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 624 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 625 | { |
dcd1e92e | 626 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
627 | } |
628 | ||
42a49f96 | 629 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 630 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 631 | { |
dcd1e92e | 632 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
633 | } |
634 | ||
b00d3bcf | 635 | |
43f49609 | 636 | /* |
b00d3bcf | 637 | * This function flushes the DTEs for all devices in domain |
43f49609 | 638 | */ |
b00d3bcf JR |
639 | static void iommu_flush_domain_devices(struct protection_domain *domain) |
640 | { | |
641 | struct iommu_dev_data *dev_data; | |
642 | unsigned long flags; | |
643 | ||
644 | spin_lock_irqsave(&domain->lock, flags); | |
645 | ||
646 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
647 | iommu_flush_device(dev_data->dev); | |
648 | ||
649 | spin_unlock_irqrestore(&domain->lock, flags); | |
650 | } | |
651 | ||
652 | static void iommu_flush_all_domain_devices(void) | |
43f49609 | 653 | { |
09b42804 | 654 | struct protection_domain *domain; |
e394d72a | 655 | unsigned long flags; |
18811f55 | 656 | |
09b42804 | 657 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 658 | |
09b42804 | 659 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
b00d3bcf | 660 | iommu_flush_domain_devices(domain); |
09b42804 | 661 | iommu_flush_complete(domain); |
bfd1be18 | 662 | } |
e394d72a | 663 | |
09b42804 | 664 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
665 | } |
666 | ||
b00d3bcf JR |
667 | void amd_iommu_flush_all_devices(void) |
668 | { | |
669 | iommu_flush_all_domain_devices(); | |
670 | } | |
671 | ||
09b42804 JR |
672 | /* |
673 | * This function uses heavy locking and may disable irqs for some time. But | |
674 | * this is no issue because it is only called during resume. | |
675 | */ | |
bfd1be18 | 676 | void amd_iommu_flush_all_domains(void) |
e394d72a | 677 | { |
e3306664 | 678 | struct protection_domain *domain; |
09b42804 JR |
679 | unsigned long flags; |
680 | ||
681 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 682 | |
e3306664 | 683 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 684 | spin_lock(&domain->lock); |
e3306664 JR |
685 | iommu_flush_tlb_pde(domain); |
686 | iommu_flush_complete(domain); | |
09b42804 | 687 | spin_unlock(&domain->lock); |
e3306664 | 688 | } |
09b42804 JR |
689 | |
690 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
691 | } |
692 | ||
a345b23b JR |
693 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
694 | { | |
695 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
696 | ||
b26e81b8 JR |
697 | if (iommu->reset_in_progress) |
698 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
699 | ||
a345b23b | 700 | amd_iommu_reset_cmd_buffer(iommu); |
b00d3bcf JR |
701 | amd_iommu_flush_all_devices(); |
702 | amd_iommu_flush_all_domains(); | |
b26e81b8 JR |
703 | |
704 | iommu->reset_in_progress = false; | |
a345b23b JR |
705 | } |
706 | ||
431b2a20 JR |
707 | /**************************************************************************** |
708 | * | |
709 | * The functions below are used the create the page table mappings for | |
710 | * unity mapped regions. | |
711 | * | |
712 | ****************************************************************************/ | |
713 | ||
308973d3 JR |
714 | /* |
715 | * This function is used to add another level to an IO page table. Adding | |
716 | * another level increases the size of the address space by 9 bits to a size up | |
717 | * to 64 bits. | |
718 | */ | |
719 | static bool increase_address_space(struct protection_domain *domain, | |
720 | gfp_t gfp) | |
721 | { | |
722 | u64 *pte; | |
723 | ||
724 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
725 | /* address space already 64 bit large */ | |
726 | return false; | |
727 | ||
728 | pte = (void *)get_zeroed_page(gfp); | |
729 | if (!pte) | |
730 | return false; | |
731 | ||
732 | *pte = PM_LEVEL_PDE(domain->mode, | |
733 | virt_to_phys(domain->pt_root)); | |
734 | domain->pt_root = pte; | |
735 | domain->mode += 1; | |
736 | domain->updated = true; | |
737 | ||
738 | return true; | |
739 | } | |
740 | ||
741 | static u64 *alloc_pte(struct protection_domain *domain, | |
742 | unsigned long address, | |
cbb9d729 | 743 | unsigned long page_size, |
308973d3 JR |
744 | u64 **pte_page, |
745 | gfp_t gfp) | |
746 | { | |
cbb9d729 | 747 | int level, end_lvl; |
308973d3 | 748 | u64 *pte, *page; |
cbb9d729 JR |
749 | |
750 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
751 | |
752 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
753 | increase_address_space(domain, gfp); | |
754 | ||
cbb9d729 JR |
755 | level = domain->mode - 1; |
756 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
757 | address = PAGE_SIZE_ALIGN(address, page_size); | |
758 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
759 | |
760 | while (level > end_lvl) { | |
761 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
762 | page = (u64 *)get_zeroed_page(gfp); | |
763 | if (!page) | |
764 | return NULL; | |
765 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
766 | } | |
767 | ||
cbb9d729 JR |
768 | /* No level skipping support yet */ |
769 | if (PM_PTE_LEVEL(*pte) != level) | |
770 | return NULL; | |
771 | ||
308973d3 JR |
772 | level -= 1; |
773 | ||
774 | pte = IOMMU_PTE_PAGE(*pte); | |
775 | ||
776 | if (pte_page && level == end_lvl) | |
777 | *pte_page = pte; | |
778 | ||
779 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
780 | } | |
781 | ||
782 | return pte; | |
783 | } | |
784 | ||
785 | /* | |
786 | * This function checks if there is a PTE for a given dma address. If | |
787 | * there is one, it returns the pointer to it. | |
788 | */ | |
24cd7723 | 789 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
790 | { |
791 | int level; | |
792 | u64 *pte; | |
793 | ||
24cd7723 JR |
794 | if (address > PM_LEVEL_SIZE(domain->mode)) |
795 | return NULL; | |
796 | ||
797 | level = domain->mode - 1; | |
798 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 799 | |
24cd7723 JR |
800 | while (level > 0) { |
801 | ||
802 | /* Not Present */ | |
308973d3 JR |
803 | if (!IOMMU_PTE_PRESENT(*pte)) |
804 | return NULL; | |
805 | ||
24cd7723 JR |
806 | /* Large PTE */ |
807 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
808 | unsigned long pte_mask, __pte; | |
809 | ||
810 | /* | |
811 | * If we have a series of large PTEs, make | |
812 | * sure to return a pointer to the first one. | |
813 | */ | |
814 | pte_mask = PTE_PAGE_SIZE(*pte); | |
815 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
816 | __pte = ((unsigned long)pte) & pte_mask; | |
817 | ||
818 | return (u64 *)__pte; | |
819 | } | |
820 | ||
821 | /* No level skipping support yet */ | |
822 | if (PM_PTE_LEVEL(*pte) != level) | |
823 | return NULL; | |
824 | ||
308973d3 JR |
825 | level -= 1; |
826 | ||
24cd7723 | 827 | /* Walk to the next level */ |
308973d3 JR |
828 | pte = IOMMU_PTE_PAGE(*pte); |
829 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
830 | } |
831 | ||
832 | return pte; | |
833 | } | |
834 | ||
431b2a20 JR |
835 | /* |
836 | * Generic mapping functions. It maps a physical address into a DMA | |
837 | * address space. It allocates the page table pages if necessary. | |
838 | * In the future it can be extended to a generic mapping function | |
839 | * supporting all features of AMD IOMMU page tables like level skipping | |
840 | * and full 64 bit address spaces. | |
841 | */ | |
38e817fe JR |
842 | static int iommu_map_page(struct protection_domain *dom, |
843 | unsigned long bus_addr, | |
844 | unsigned long phys_addr, | |
abdc5eb3 | 845 | int prot, |
cbb9d729 | 846 | unsigned long page_size) |
bd0e5211 | 847 | { |
8bda3092 | 848 | u64 __pte, *pte; |
cbb9d729 | 849 | int i, count; |
abdc5eb3 | 850 | |
bad1cac2 | 851 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
852 | return -EINVAL; |
853 | ||
cbb9d729 JR |
854 | bus_addr = PAGE_ALIGN(bus_addr); |
855 | phys_addr = PAGE_ALIGN(phys_addr); | |
856 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
857 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
858 | ||
859 | for (i = 0; i < count; ++i) | |
860 | if (IOMMU_PTE_PRESENT(pte[i])) | |
861 | return -EBUSY; | |
bd0e5211 | 862 | |
cbb9d729 JR |
863 | if (page_size > PAGE_SIZE) { |
864 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
865 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
866 | } else | |
867 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 868 | |
bd0e5211 JR |
869 | if (prot & IOMMU_PROT_IR) |
870 | __pte |= IOMMU_PTE_IR; | |
871 | if (prot & IOMMU_PROT_IW) | |
872 | __pte |= IOMMU_PTE_IW; | |
873 | ||
cbb9d729 JR |
874 | for (i = 0; i < count; ++i) |
875 | pte[i] = __pte; | |
bd0e5211 | 876 | |
04bfdd84 JR |
877 | update_domain(dom); |
878 | ||
bd0e5211 JR |
879 | return 0; |
880 | } | |
881 | ||
24cd7723 JR |
882 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
883 | unsigned long bus_addr, | |
884 | unsigned long page_size) | |
eb74ff6c | 885 | { |
24cd7723 JR |
886 | unsigned long long unmap_size, unmapped; |
887 | u64 *pte; | |
888 | ||
889 | BUG_ON(!is_power_of_2(page_size)); | |
890 | ||
891 | unmapped = 0; | |
eb74ff6c | 892 | |
24cd7723 JR |
893 | while (unmapped < page_size) { |
894 | ||
895 | pte = fetch_pte(dom, bus_addr); | |
896 | ||
897 | if (!pte) { | |
898 | /* | |
899 | * No PTE for this address | |
900 | * move forward in 4kb steps | |
901 | */ | |
902 | unmap_size = PAGE_SIZE; | |
903 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
904 | /* 4kb PTE found for this address */ | |
905 | unmap_size = PAGE_SIZE; | |
906 | *pte = 0ULL; | |
907 | } else { | |
908 | int count, i; | |
909 | ||
910 | /* Large PTE found which maps this address */ | |
911 | unmap_size = PTE_PAGE_SIZE(*pte); | |
912 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
913 | for (i = 0; i < count; i++) | |
914 | pte[i] = 0ULL; | |
915 | } | |
916 | ||
917 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
918 | unmapped += unmap_size; | |
919 | } | |
920 | ||
921 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 922 | |
24cd7723 | 923 | return unmapped; |
eb74ff6c | 924 | } |
eb74ff6c | 925 | |
431b2a20 JR |
926 | /* |
927 | * This function checks if a specific unity mapping entry is needed for | |
928 | * this specific IOMMU. | |
929 | */ | |
bd0e5211 JR |
930 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
931 | struct unity_map_entry *entry) | |
932 | { | |
933 | u16 bdf, i; | |
934 | ||
935 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
936 | bdf = amd_iommu_alias_table[i]; | |
937 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
938 | return 1; | |
939 | } | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
431b2a20 JR |
944 | /* |
945 | * This function actually applies the mapping to the page table of the | |
946 | * dma_ops domain. | |
947 | */ | |
bd0e5211 JR |
948 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
949 | struct unity_map_entry *e) | |
950 | { | |
951 | u64 addr; | |
952 | int ret; | |
953 | ||
954 | for (addr = e->address_start; addr < e->address_end; | |
955 | addr += PAGE_SIZE) { | |
abdc5eb3 | 956 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 957 | PAGE_SIZE); |
bd0e5211 JR |
958 | if (ret) |
959 | return ret; | |
960 | /* | |
961 | * if unity mapping is in aperture range mark the page | |
962 | * as allocated in the aperture | |
963 | */ | |
964 | if (addr < dma_dom->aperture_size) | |
c3239567 | 965 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 966 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
967 | } |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
171e7b37 JR |
972 | /* |
973 | * Init the unity mappings for a specific IOMMU in the system | |
974 | * | |
975 | * Basically iterates over all unity mapping entries and applies them to | |
976 | * the default domain DMA of that IOMMU if necessary. | |
977 | */ | |
978 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
979 | { | |
980 | struct unity_map_entry *entry; | |
981 | int ret; | |
982 | ||
983 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
984 | if (!iommu_for_unity_map(iommu, entry)) | |
985 | continue; | |
986 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
987 | if (ret) | |
988 | return ret; | |
989 | } | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
431b2a20 JR |
994 | /* |
995 | * Inits the unity mappings required for a specific device | |
996 | */ | |
bd0e5211 JR |
997 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
998 | u16 devid) | |
999 | { | |
1000 | struct unity_map_entry *e; | |
1001 | int ret; | |
1002 | ||
1003 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1004 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1005 | continue; | |
1006 | ret = dma_ops_unity_map(dma_dom, e); | |
1007 | if (ret) | |
1008 | return ret; | |
1009 | } | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
431b2a20 JR |
1014 | /**************************************************************************** |
1015 | * | |
1016 | * The next functions belong to the address allocator for the dma_ops | |
1017 | * interface functions. They work like the allocators in the other IOMMU | |
1018 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1019 | * the aperture. Maybe it could be enhanced in the future to a more | |
1020 | * efficient allocator. | |
1021 | * | |
1022 | ****************************************************************************/ | |
d3086444 | 1023 | |
431b2a20 | 1024 | /* |
384de729 | 1025 | * The address allocator core functions. |
431b2a20 JR |
1026 | * |
1027 | * called with domain->lock held | |
1028 | */ | |
384de729 | 1029 | |
171e7b37 JR |
1030 | /* |
1031 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1032 | * ranges. | |
1033 | */ | |
1034 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1035 | unsigned long start_page, | |
1036 | unsigned int pages) | |
1037 | { | |
1038 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1039 | ||
1040 | if (start_page + pages > last_page) | |
1041 | pages = last_page - start_page; | |
1042 | ||
1043 | for (i = start_page; i < start_page + pages; ++i) { | |
1044 | int index = i / APERTURE_RANGE_PAGES; | |
1045 | int page = i % APERTURE_RANGE_PAGES; | |
1046 | __set_bit(page, dom->aperture[index]->bitmap); | |
1047 | } | |
1048 | } | |
1049 | ||
9cabe89b JR |
1050 | /* |
1051 | * This function is used to add a new aperture range to an existing | |
1052 | * aperture in case of dma_ops domain allocation or address allocation | |
1053 | * failure. | |
1054 | */ | |
576175c2 | 1055 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1056 | bool populate, gfp_t gfp) |
1057 | { | |
1058 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1059 | struct amd_iommu *iommu; |
d91afd15 | 1060 | unsigned long i; |
9cabe89b | 1061 | |
f5e9705c JR |
1062 | #ifdef CONFIG_IOMMU_STRESS |
1063 | populate = false; | |
1064 | #endif | |
1065 | ||
9cabe89b JR |
1066 | if (index >= APERTURE_MAX_RANGES) |
1067 | return -ENOMEM; | |
1068 | ||
1069 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1070 | if (!dma_dom->aperture[index]) | |
1071 | return -ENOMEM; | |
1072 | ||
1073 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1074 | if (!dma_dom->aperture[index]->bitmap) | |
1075 | goto out_free; | |
1076 | ||
1077 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1078 | ||
1079 | if (populate) { | |
1080 | unsigned long address = dma_dom->aperture_size; | |
1081 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1082 | u64 *pte, *pte_page; | |
1083 | ||
1084 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1085 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1086 | &pte_page, gfp); |
1087 | if (!pte) | |
1088 | goto out_free; | |
1089 | ||
1090 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1091 | ||
1092 | address += APERTURE_RANGE_SIZE / 64; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1097 | ||
b595076a | 1098 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1099 | for_each_iommu(iommu) { |
1100 | if (iommu->exclusion_start && | |
1101 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1102 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1103 | unsigned long startpage; | |
1104 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1105 | iommu->exclusion_length, | |
1106 | PAGE_SIZE); | |
1107 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1108 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1109 | } | |
00cd122a JR |
1110 | } |
1111 | ||
1112 | /* | |
1113 | * Check for areas already mapped as present in the new aperture | |
1114 | * range and mark those pages as reserved in the allocator. Such | |
1115 | * mappings may already exist as a result of requested unity | |
1116 | * mappings for devices. | |
1117 | */ | |
1118 | for (i = dma_dom->aperture[index]->offset; | |
1119 | i < dma_dom->aperture_size; | |
1120 | i += PAGE_SIZE) { | |
24cd7723 | 1121 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1122 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1123 | continue; | |
1124 | ||
1125 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1126 | } | |
1127 | ||
04bfdd84 JR |
1128 | update_domain(&dma_dom->domain); |
1129 | ||
9cabe89b JR |
1130 | return 0; |
1131 | ||
1132 | out_free: | |
04bfdd84 JR |
1133 | update_domain(&dma_dom->domain); |
1134 | ||
9cabe89b JR |
1135 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1136 | ||
1137 | kfree(dma_dom->aperture[index]); | |
1138 | dma_dom->aperture[index] = NULL; | |
1139 | ||
1140 | return -ENOMEM; | |
1141 | } | |
1142 | ||
384de729 JR |
1143 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1144 | struct dma_ops_domain *dom, | |
1145 | unsigned int pages, | |
1146 | unsigned long align_mask, | |
1147 | u64 dma_mask, | |
1148 | unsigned long start) | |
1149 | { | |
803b8cb4 | 1150 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1151 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1152 | int i = start >> APERTURE_RANGE_SHIFT; | |
1153 | unsigned long boundary_size; | |
1154 | unsigned long address = -1; | |
1155 | unsigned long limit; | |
1156 | ||
803b8cb4 JR |
1157 | next_bit >>= PAGE_SHIFT; |
1158 | ||
384de729 JR |
1159 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1160 | PAGE_SIZE) >> PAGE_SHIFT; | |
1161 | ||
1162 | for (;i < max_index; ++i) { | |
1163 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1164 | ||
1165 | if (dom->aperture[i]->offset >= dma_mask) | |
1166 | break; | |
1167 | ||
1168 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1169 | dma_mask >> PAGE_SHIFT); | |
1170 | ||
1171 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1172 | limit, next_bit, pages, 0, | |
1173 | boundary_size, align_mask); | |
1174 | if (address != -1) { | |
1175 | address = dom->aperture[i]->offset + | |
1176 | (address << PAGE_SHIFT); | |
803b8cb4 | 1177 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1178 | break; |
1179 | } | |
1180 | ||
1181 | next_bit = 0; | |
1182 | } | |
1183 | ||
1184 | return address; | |
1185 | } | |
1186 | ||
d3086444 JR |
1187 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1188 | struct dma_ops_domain *dom, | |
6d4f343f | 1189 | unsigned int pages, |
832a90c3 JR |
1190 | unsigned long align_mask, |
1191 | u64 dma_mask) | |
d3086444 | 1192 | { |
d3086444 | 1193 | unsigned long address; |
d3086444 | 1194 | |
fe16f088 JR |
1195 | #ifdef CONFIG_IOMMU_STRESS |
1196 | dom->next_address = 0; | |
1197 | dom->need_flush = true; | |
1198 | #endif | |
d3086444 | 1199 | |
384de729 | 1200 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1201 | dma_mask, dom->next_address); |
d3086444 | 1202 | |
1c655773 | 1203 | if (address == -1) { |
803b8cb4 | 1204 | dom->next_address = 0; |
384de729 JR |
1205 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1206 | dma_mask, 0); | |
1c655773 JR |
1207 | dom->need_flush = true; |
1208 | } | |
d3086444 | 1209 | |
384de729 | 1210 | if (unlikely(address == -1)) |
8fd524b3 | 1211 | address = DMA_ERROR_CODE; |
d3086444 JR |
1212 | |
1213 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1214 | ||
1215 | return address; | |
1216 | } | |
1217 | ||
431b2a20 JR |
1218 | /* |
1219 | * The address free function. | |
1220 | * | |
1221 | * called with domain->lock held | |
1222 | */ | |
d3086444 JR |
1223 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1224 | unsigned long address, | |
1225 | unsigned int pages) | |
1226 | { | |
384de729 JR |
1227 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1228 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1229 | |
384de729 JR |
1230 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1231 | ||
47bccd6b JR |
1232 | #ifdef CONFIG_IOMMU_STRESS |
1233 | if (i < 4) | |
1234 | return; | |
1235 | #endif | |
80be308d | 1236 | |
803b8cb4 | 1237 | if (address >= dom->next_address) |
80be308d | 1238 | dom->need_flush = true; |
384de729 JR |
1239 | |
1240 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1241 | |
a66022c4 | 1242 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1243 | |
d3086444 JR |
1244 | } |
1245 | ||
431b2a20 JR |
1246 | /**************************************************************************** |
1247 | * | |
1248 | * The next functions belong to the domain allocation. A domain is | |
1249 | * allocated for every IOMMU as the default domain. If device isolation | |
1250 | * is enabled, every device get its own domain. The most important thing | |
1251 | * about domains is the page table mapping the DMA address space they | |
1252 | * contain. | |
1253 | * | |
1254 | ****************************************************************************/ | |
1255 | ||
aeb26f55 JR |
1256 | /* |
1257 | * This function adds a protection domain to the global protection domain list | |
1258 | */ | |
1259 | static void add_domain_to_list(struct protection_domain *domain) | |
1260 | { | |
1261 | unsigned long flags; | |
1262 | ||
1263 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1264 | list_add(&domain->list, &amd_iommu_pd_list); | |
1265 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1266 | } | |
1267 | ||
1268 | /* | |
1269 | * This function removes a protection domain to the global | |
1270 | * protection domain list | |
1271 | */ | |
1272 | static void del_domain_from_list(struct protection_domain *domain) | |
1273 | { | |
1274 | unsigned long flags; | |
1275 | ||
1276 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1277 | list_del(&domain->list); | |
1278 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1279 | } | |
1280 | ||
ec487d1a JR |
1281 | static u16 domain_id_alloc(void) |
1282 | { | |
1283 | unsigned long flags; | |
1284 | int id; | |
1285 | ||
1286 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1287 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1288 | BUG_ON(id == 0); | |
1289 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1290 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1291 | else | |
1292 | id = 0; | |
1293 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1294 | ||
1295 | return id; | |
1296 | } | |
1297 | ||
a2acfb75 JR |
1298 | static void domain_id_free(int id) |
1299 | { | |
1300 | unsigned long flags; | |
1301 | ||
1302 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1303 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1304 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1305 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1306 | } | |
a2acfb75 | 1307 | |
86db2e5d | 1308 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1309 | { |
1310 | int i, j; | |
1311 | u64 *p1, *p2, *p3; | |
1312 | ||
86db2e5d | 1313 | p1 = domain->pt_root; |
ec487d1a JR |
1314 | |
1315 | if (!p1) | |
1316 | return; | |
1317 | ||
1318 | for (i = 0; i < 512; ++i) { | |
1319 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1320 | continue; | |
1321 | ||
1322 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1323 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1324 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1325 | continue; | |
1326 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1327 | free_page((unsigned long)p3); | |
1328 | } | |
1329 | ||
1330 | free_page((unsigned long)p2); | |
1331 | } | |
1332 | ||
1333 | free_page((unsigned long)p1); | |
86db2e5d JR |
1334 | |
1335 | domain->pt_root = NULL; | |
ec487d1a JR |
1336 | } |
1337 | ||
431b2a20 JR |
1338 | /* |
1339 | * Free a domain, only used if something went wrong in the | |
1340 | * allocation path and we need to free an already allocated page table | |
1341 | */ | |
ec487d1a JR |
1342 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1343 | { | |
384de729 JR |
1344 | int i; |
1345 | ||
ec487d1a JR |
1346 | if (!dom) |
1347 | return; | |
1348 | ||
aeb26f55 JR |
1349 | del_domain_from_list(&dom->domain); |
1350 | ||
86db2e5d | 1351 | free_pagetable(&dom->domain); |
ec487d1a | 1352 | |
384de729 JR |
1353 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1354 | if (!dom->aperture[i]) | |
1355 | continue; | |
1356 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1357 | kfree(dom->aperture[i]); | |
1358 | } | |
ec487d1a JR |
1359 | |
1360 | kfree(dom); | |
1361 | } | |
1362 | ||
431b2a20 JR |
1363 | /* |
1364 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1365 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1366 | * structures required for the dma_ops interface |
1367 | */ | |
87a64d52 | 1368 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1369 | { |
1370 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1371 | |
1372 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1373 | if (!dma_dom) | |
1374 | return NULL; | |
1375 | ||
1376 | spin_lock_init(&dma_dom->domain.lock); | |
1377 | ||
1378 | dma_dom->domain.id = domain_id_alloc(); | |
1379 | if (dma_dom->domain.id == 0) | |
1380 | goto free_dma_dom; | |
7c392cbe | 1381 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1382 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1383 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1384 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1385 | dma_dom->domain.priv = dma_dom; |
1386 | if (!dma_dom->domain.pt_root) | |
1387 | goto free_dma_dom; | |
ec487d1a | 1388 | |
1c655773 | 1389 | dma_dom->need_flush = false; |
bd60b735 | 1390 | dma_dom->target_dev = 0xffff; |
1c655773 | 1391 | |
aeb26f55 JR |
1392 | add_domain_to_list(&dma_dom->domain); |
1393 | ||
576175c2 | 1394 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1395 | goto free_dma_dom; |
ec487d1a | 1396 | |
431b2a20 | 1397 | /* |
ec487d1a JR |
1398 | * mark the first page as allocated so we never return 0 as |
1399 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1400 | */ |
384de729 | 1401 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1402 | dma_dom->next_address = 0; |
ec487d1a | 1403 | |
ec487d1a JR |
1404 | |
1405 | return dma_dom; | |
1406 | ||
1407 | free_dma_dom: | |
1408 | dma_ops_domain_free(dma_dom); | |
1409 | ||
1410 | return NULL; | |
1411 | } | |
1412 | ||
5b28df6f JR |
1413 | /* |
1414 | * little helper function to check whether a given protection domain is a | |
1415 | * dma_ops domain | |
1416 | */ | |
1417 | static bool dma_ops_domain(struct protection_domain *domain) | |
1418 | { | |
1419 | return domain->flags & PD_DMA_OPS_MASK; | |
1420 | } | |
1421 | ||
407d733e | 1422 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1423 | { |
b20ac0d4 | 1424 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1425 | |
38ddf41b JR |
1426 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1427 | << DEV_ENTRY_MODE_SHIFT; | |
1428 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1429 | |
b20ac0d4 | 1430 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1431 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1432 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1433 | } |
1434 | ||
1435 | static void clear_dte_entry(u16 devid) | |
1436 | { | |
15898bbc JR |
1437 | /* remove entry from the device table seen by the hardware */ |
1438 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1439 | amd_iommu_dev_table[devid].data[1] = 0; | |
1440 | amd_iommu_dev_table[devid].data[2] = 0; | |
1441 | ||
1442 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1443 | } |
1444 | ||
1445 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1446 | { | |
1447 | struct iommu_dev_data *dev_data; | |
1448 | struct amd_iommu *iommu; | |
1449 | u16 devid; | |
1450 | ||
1451 | devid = get_device_id(dev); | |
1452 | iommu = amd_iommu_rlookup_table[devid]; | |
1453 | dev_data = get_dev_data(dev); | |
1454 | ||
1455 | /* Update data structures */ | |
1456 | dev_data->domain = domain; | |
1457 | list_add(&dev_data->list, &domain->dev_list); | |
1458 | set_dte_entry(devid, domain); | |
1459 | ||
1460 | /* Do reference counting */ | |
1461 | domain->dev_iommu[iommu->index] += 1; | |
1462 | domain->dev_cnt += 1; | |
1463 | ||
1464 | /* Flush the DTE entry */ | |
3fa43655 | 1465 | iommu_flush_device(dev); |
7f760ddd JR |
1466 | } |
1467 | ||
1468 | static void do_detach(struct device *dev) | |
1469 | { | |
1470 | struct iommu_dev_data *dev_data; | |
1471 | struct amd_iommu *iommu; | |
1472 | u16 devid; | |
1473 | ||
1474 | devid = get_device_id(dev); | |
1475 | iommu = amd_iommu_rlookup_table[devid]; | |
1476 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1477 | |
1478 | /* decrease reference counters */ | |
7f760ddd JR |
1479 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1480 | dev_data->domain->dev_cnt -= 1; | |
1481 | ||
1482 | /* Update data structures */ | |
1483 | dev_data->domain = NULL; | |
1484 | list_del(&dev_data->list); | |
1485 | clear_dte_entry(devid); | |
15898bbc | 1486 | |
7f760ddd | 1487 | /* Flush the DTE entry */ |
3fa43655 | 1488 | iommu_flush_device(dev); |
2b681faf JR |
1489 | } |
1490 | ||
1491 | /* | |
1492 | * If a device is not yet associated with a domain, this function does | |
1493 | * assigns it visible for the hardware | |
1494 | */ | |
15898bbc JR |
1495 | static int __attach_device(struct device *dev, |
1496 | struct protection_domain *domain) | |
2b681faf | 1497 | { |
657cbb6b | 1498 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1499 | int ret; |
657cbb6b | 1500 | |
657cbb6b JR |
1501 | dev_data = get_dev_data(dev); |
1502 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1503 | |
657cbb6b JR |
1504 | if (!alias_data) |
1505 | return -EINVAL; | |
15898bbc | 1506 | |
2b681faf JR |
1507 | /* lock domain */ |
1508 | spin_lock(&domain->lock); | |
1509 | ||
15898bbc | 1510 | /* Some sanity checks */ |
84fe6c19 | 1511 | ret = -EBUSY; |
657cbb6b JR |
1512 | if (alias_data->domain != NULL && |
1513 | alias_data->domain != domain) | |
84fe6c19 | 1514 | goto out_unlock; |
eba6ac60 | 1515 | |
657cbb6b JR |
1516 | if (dev_data->domain != NULL && |
1517 | dev_data->domain != domain) | |
84fe6c19 | 1518 | goto out_unlock; |
15898bbc JR |
1519 | |
1520 | /* Do real assignment */ | |
7f760ddd JR |
1521 | if (dev_data->alias != dev) { |
1522 | alias_data = get_dev_data(dev_data->alias); | |
1523 | if (alias_data->domain == NULL) | |
1524 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1525 | |
1526 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1527 | } |
15898bbc | 1528 | |
7f760ddd JR |
1529 | if (dev_data->domain == NULL) |
1530 | do_attach(dev, domain); | |
eba6ac60 | 1531 | |
24100055 JR |
1532 | atomic_inc(&dev_data->bind); |
1533 | ||
84fe6c19 JL |
1534 | ret = 0; |
1535 | ||
1536 | out_unlock: | |
1537 | ||
eba6ac60 JR |
1538 | /* ready */ |
1539 | spin_unlock(&domain->lock); | |
15898bbc | 1540 | |
84fe6c19 | 1541 | return ret; |
0feae533 | 1542 | } |
b20ac0d4 | 1543 | |
407d733e JR |
1544 | /* |
1545 | * If a device is not yet associated with a domain, this function does | |
1546 | * assigns it visible for the hardware | |
1547 | */ | |
15898bbc JR |
1548 | static int attach_device(struct device *dev, |
1549 | struct protection_domain *domain) | |
0feae533 | 1550 | { |
eba6ac60 | 1551 | unsigned long flags; |
15898bbc | 1552 | int ret; |
eba6ac60 JR |
1553 | |
1554 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1555 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1556 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1557 | ||
0feae533 JR |
1558 | /* |
1559 | * We might boot into a crash-kernel here. The crashed kernel | |
1560 | * left the caches in the IOMMU dirty. So we have to flush | |
1561 | * here to evict all dirty stuff. | |
1562 | */ | |
dcd1e92e | 1563 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1564 | |
1565 | return ret; | |
b20ac0d4 JR |
1566 | } |
1567 | ||
355bf553 JR |
1568 | /* |
1569 | * Removes a device from a protection domain (unlocked) | |
1570 | */ | |
15898bbc | 1571 | static void __detach_device(struct device *dev) |
355bf553 | 1572 | { |
657cbb6b | 1573 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1574 | struct iommu_dev_data *alias_data; |
2ca76279 | 1575 | struct protection_domain *domain; |
7c392cbe | 1576 | unsigned long flags; |
c4596114 | 1577 | |
7f760ddd | 1578 | BUG_ON(!dev_data->domain); |
355bf553 | 1579 | |
2ca76279 JR |
1580 | domain = dev_data->domain; |
1581 | ||
1582 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1583 | |
7f760ddd | 1584 | if (dev_data->alias != dev) { |
24100055 | 1585 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1586 | if (atomic_dec_and_test(&alias_data->bind)) |
1587 | do_detach(dev_data->alias); | |
24100055 JR |
1588 | } |
1589 | ||
7f760ddd JR |
1590 | if (atomic_dec_and_test(&dev_data->bind)) |
1591 | do_detach(dev); | |
1592 | ||
2ca76279 | 1593 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1594 | |
1595 | /* | |
1596 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1597 | * passthrough domain if it is detached from any other domain. |
1598 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1599 | */ |
d3ad9373 JR |
1600 | if (iommu_pass_through && |
1601 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1602 | __attach_device(dev, pt_domain); |
355bf553 JR |
1603 | } |
1604 | ||
1605 | /* | |
1606 | * Removes a device from a protection domain (with devtable_lock held) | |
1607 | */ | |
15898bbc | 1608 | static void detach_device(struct device *dev) |
355bf553 JR |
1609 | { |
1610 | unsigned long flags; | |
1611 | ||
1612 | /* lock device table */ | |
1613 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1614 | __detach_device(dev); |
355bf553 JR |
1615 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1616 | } | |
e275a2a0 | 1617 | |
15898bbc JR |
1618 | /* |
1619 | * Find out the protection domain structure for a given PCI device. This | |
1620 | * will give us the pointer to the page table root for example. | |
1621 | */ | |
1622 | static struct protection_domain *domain_for_device(struct device *dev) | |
1623 | { | |
1624 | struct protection_domain *dom; | |
657cbb6b | 1625 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1626 | unsigned long flags; |
1627 | u16 devid, alias; | |
1628 | ||
657cbb6b JR |
1629 | devid = get_device_id(dev); |
1630 | alias = amd_iommu_alias_table[devid]; | |
1631 | dev_data = get_dev_data(dev); | |
1632 | alias_data = get_dev_data(dev_data->alias); | |
1633 | if (!alias_data) | |
1634 | return NULL; | |
15898bbc JR |
1635 | |
1636 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1637 | dom = dev_data->domain; |
15898bbc | 1638 | if (dom == NULL && |
657cbb6b JR |
1639 | alias_data->domain != NULL) { |
1640 | __attach_device(dev, alias_data->domain); | |
1641 | dom = alias_data->domain; | |
15898bbc JR |
1642 | } |
1643 | ||
1644 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1645 | ||
1646 | return dom; | |
1647 | } | |
1648 | ||
e275a2a0 JR |
1649 | static int device_change_notifier(struct notifier_block *nb, |
1650 | unsigned long action, void *data) | |
1651 | { | |
1652 | struct device *dev = data; | |
98fc5a69 | 1653 | u16 devid; |
e275a2a0 JR |
1654 | struct protection_domain *domain; |
1655 | struct dma_ops_domain *dma_domain; | |
1656 | struct amd_iommu *iommu; | |
1ac4cbbc | 1657 | unsigned long flags; |
e275a2a0 | 1658 | |
98fc5a69 JR |
1659 | if (!check_device(dev)) |
1660 | return 0; | |
e275a2a0 | 1661 | |
98fc5a69 JR |
1662 | devid = get_device_id(dev); |
1663 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1664 | |
1665 | switch (action) { | |
c1eee67b | 1666 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1667 | |
1668 | domain = domain_for_device(dev); | |
1669 | ||
e275a2a0 JR |
1670 | if (!domain) |
1671 | goto out; | |
a1ca331c JR |
1672 | if (iommu_pass_through) |
1673 | break; | |
15898bbc | 1674 | detach_device(dev); |
1ac4cbbc JR |
1675 | break; |
1676 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1677 | |
1678 | iommu_init_device(dev); | |
1679 | ||
1680 | domain = domain_for_device(dev); | |
1681 | ||
1ac4cbbc JR |
1682 | /* allocate a protection domain if a device is added */ |
1683 | dma_domain = find_protection_domain(devid); | |
1684 | if (dma_domain) | |
1685 | goto out; | |
87a64d52 | 1686 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1687 | if (!dma_domain) |
1688 | goto out; | |
1689 | dma_domain->target_dev = devid; | |
1690 | ||
1691 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1692 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1693 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1694 | ||
e275a2a0 | 1695 | break; |
657cbb6b JR |
1696 | case BUS_NOTIFY_DEL_DEVICE: |
1697 | ||
1698 | iommu_uninit_device(dev); | |
1699 | ||
e275a2a0 JR |
1700 | default: |
1701 | goto out; | |
1702 | } | |
1703 | ||
3fa43655 | 1704 | iommu_flush_device(dev); |
e275a2a0 JR |
1705 | iommu_completion_wait(iommu); |
1706 | ||
1707 | out: | |
1708 | return 0; | |
1709 | } | |
1710 | ||
b25ae679 | 1711 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1712 | .notifier_call = device_change_notifier, |
1713 | }; | |
355bf553 | 1714 | |
8638c491 JR |
1715 | void amd_iommu_init_notifier(void) |
1716 | { | |
1717 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1718 | } | |
1719 | ||
431b2a20 JR |
1720 | /***************************************************************************** |
1721 | * | |
1722 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1723 | * | |
1724 | *****************************************************************************/ | |
1725 | ||
1726 | /* | |
1727 | * In the dma_ops path we only have the struct device. This function | |
1728 | * finds the corresponding IOMMU, the protection domain and the | |
1729 | * requestor id for a given device. | |
1730 | * If the device is not yet associated with a domain this is also done | |
1731 | * in this function. | |
1732 | */ | |
94f6d190 | 1733 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1734 | { |
94f6d190 | 1735 | struct protection_domain *domain; |
b20ac0d4 | 1736 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1737 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1738 | |
f99c0f1c | 1739 | if (!check_device(dev)) |
94f6d190 | 1740 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1741 | |
94f6d190 JR |
1742 | domain = domain_for_device(dev); |
1743 | if (domain != NULL && !dma_ops_domain(domain)) | |
1744 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1745 | |
94f6d190 JR |
1746 | if (domain != NULL) |
1747 | return domain; | |
b20ac0d4 | 1748 | |
15898bbc | 1749 | /* Device not bount yet - bind it */ |
94f6d190 | 1750 | dma_dom = find_protection_domain(devid); |
15898bbc | 1751 | if (!dma_dom) |
94f6d190 JR |
1752 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1753 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1754 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1755 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1756 | |
94f6d190 | 1757 | return &dma_dom->domain; |
b20ac0d4 JR |
1758 | } |
1759 | ||
04bfdd84 JR |
1760 | static void update_device_table(struct protection_domain *domain) |
1761 | { | |
492667da | 1762 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1763 | |
492667da JR |
1764 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
1765 | u16 devid = get_device_id(dev_data->dev); | |
1766 | set_dte_entry(devid, domain); | |
04bfdd84 JR |
1767 | } |
1768 | } | |
1769 | ||
1770 | static void update_domain(struct protection_domain *domain) | |
1771 | { | |
1772 | if (!domain->updated) | |
1773 | return; | |
1774 | ||
1775 | update_device_table(domain); | |
b00d3bcf | 1776 | iommu_flush_domain_devices(domain); |
601367d7 | 1777 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1778 | |
1779 | domain->updated = false; | |
1780 | } | |
1781 | ||
8bda3092 JR |
1782 | /* |
1783 | * This function fetches the PTE for a given address in the aperture | |
1784 | */ | |
1785 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1786 | unsigned long address) | |
1787 | { | |
384de729 | 1788 | struct aperture_range *aperture; |
8bda3092 JR |
1789 | u64 *pte, *pte_page; |
1790 | ||
384de729 JR |
1791 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1792 | if (!aperture) | |
1793 | return NULL; | |
1794 | ||
1795 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1796 | if (!pte) { |
cbb9d729 | 1797 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1798 | GFP_ATOMIC); |
384de729 JR |
1799 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1800 | } else | |
8c8c143c | 1801 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1802 | |
04bfdd84 | 1803 | update_domain(&dom->domain); |
8bda3092 JR |
1804 | |
1805 | return pte; | |
1806 | } | |
1807 | ||
431b2a20 JR |
1808 | /* |
1809 | * This is the generic map function. It maps one 4kb page at paddr to | |
1810 | * the given address in the DMA address space for the domain. | |
1811 | */ | |
680525e0 | 1812 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1813 | unsigned long address, |
1814 | phys_addr_t paddr, | |
1815 | int direction) | |
1816 | { | |
1817 | u64 *pte, __pte; | |
1818 | ||
1819 | WARN_ON(address > dom->aperture_size); | |
1820 | ||
1821 | paddr &= PAGE_MASK; | |
1822 | ||
8bda3092 | 1823 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1824 | if (!pte) |
8fd524b3 | 1825 | return DMA_ERROR_CODE; |
cb76c322 JR |
1826 | |
1827 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1828 | ||
1829 | if (direction == DMA_TO_DEVICE) | |
1830 | __pte |= IOMMU_PTE_IR; | |
1831 | else if (direction == DMA_FROM_DEVICE) | |
1832 | __pte |= IOMMU_PTE_IW; | |
1833 | else if (direction == DMA_BIDIRECTIONAL) | |
1834 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1835 | ||
1836 | WARN_ON(*pte); | |
1837 | ||
1838 | *pte = __pte; | |
1839 | ||
1840 | return (dma_addr_t)address; | |
1841 | } | |
1842 | ||
431b2a20 JR |
1843 | /* |
1844 | * The generic unmapping function for on page in the DMA address space. | |
1845 | */ | |
680525e0 | 1846 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1847 | unsigned long address) |
1848 | { | |
384de729 | 1849 | struct aperture_range *aperture; |
cb76c322 JR |
1850 | u64 *pte; |
1851 | ||
1852 | if (address >= dom->aperture_size) | |
1853 | return; | |
1854 | ||
384de729 JR |
1855 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1856 | if (!aperture) | |
1857 | return; | |
1858 | ||
1859 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1860 | if (!pte) | |
1861 | return; | |
cb76c322 | 1862 | |
8c8c143c | 1863 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1864 | |
1865 | WARN_ON(!*pte); | |
1866 | ||
1867 | *pte = 0ULL; | |
1868 | } | |
1869 | ||
431b2a20 JR |
1870 | /* |
1871 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1872 | * contiguous memory region into DMA address space. It is used by all |
1873 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1874 | * Must be called with the domain lock held. |
1875 | */ | |
cb76c322 | 1876 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1877 | struct dma_ops_domain *dma_dom, |
1878 | phys_addr_t paddr, | |
1879 | size_t size, | |
6d4f343f | 1880 | int dir, |
832a90c3 JR |
1881 | bool align, |
1882 | u64 dma_mask) | |
cb76c322 JR |
1883 | { |
1884 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1885 | dma_addr_t address, start, ret; |
cb76c322 | 1886 | unsigned int pages; |
6d4f343f | 1887 | unsigned long align_mask = 0; |
cb76c322 JR |
1888 | int i; |
1889 | ||
e3c449f5 | 1890 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1891 | paddr &= PAGE_MASK; |
1892 | ||
8ecaf8f1 JR |
1893 | INC_STATS_COUNTER(total_map_requests); |
1894 | ||
c1858976 JR |
1895 | if (pages > 1) |
1896 | INC_STATS_COUNTER(cross_page); | |
1897 | ||
6d4f343f JR |
1898 | if (align) |
1899 | align_mask = (1UL << get_order(size)) - 1; | |
1900 | ||
11b83888 | 1901 | retry: |
832a90c3 JR |
1902 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1903 | dma_mask); | |
8fd524b3 | 1904 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1905 | /* |
1906 | * setting next_address here will let the address | |
1907 | * allocator only scan the new allocated range in the | |
1908 | * first run. This is a small optimization. | |
1909 | */ | |
1910 | dma_dom->next_address = dma_dom->aperture_size; | |
1911 | ||
576175c2 | 1912 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1913 | goto out; |
1914 | ||
1915 | /* | |
af901ca1 | 1916 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1917 | * allocation again |
1918 | */ | |
1919 | goto retry; | |
1920 | } | |
cb76c322 JR |
1921 | |
1922 | start = address; | |
1923 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1924 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1925 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1926 | goto out_unmap; |
1927 | ||
cb76c322 JR |
1928 | paddr += PAGE_SIZE; |
1929 | start += PAGE_SIZE; | |
1930 | } | |
1931 | address += offset; | |
1932 | ||
5774f7c5 JR |
1933 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1934 | ||
afa9fdc2 | 1935 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1936 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1937 | dma_dom->need_flush = false; |
318afd41 | 1938 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1939 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1940 | |
cb76c322 JR |
1941 | out: |
1942 | return address; | |
53812c11 JR |
1943 | |
1944 | out_unmap: | |
1945 | ||
1946 | for (--i; i >= 0; --i) { | |
1947 | start -= PAGE_SIZE; | |
680525e0 | 1948 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1949 | } |
1950 | ||
1951 | dma_ops_free_addresses(dma_dom, address, pages); | |
1952 | ||
8fd524b3 | 1953 | return DMA_ERROR_CODE; |
cb76c322 JR |
1954 | } |
1955 | ||
431b2a20 JR |
1956 | /* |
1957 | * Does the reverse of the __map_single function. Must be called with | |
1958 | * the domain lock held too | |
1959 | */ | |
cd8c82e8 | 1960 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1961 | dma_addr_t dma_addr, |
1962 | size_t size, | |
1963 | int dir) | |
1964 | { | |
04e0463e | 1965 | dma_addr_t flush_addr; |
cb76c322 JR |
1966 | dma_addr_t i, start; |
1967 | unsigned int pages; | |
1968 | ||
8fd524b3 | 1969 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1970 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1971 | return; |
1972 | ||
04e0463e | 1973 | flush_addr = dma_addr; |
e3c449f5 | 1974 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1975 | dma_addr &= PAGE_MASK; |
1976 | start = dma_addr; | |
1977 | ||
1978 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1979 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1980 | start += PAGE_SIZE; |
1981 | } | |
1982 | ||
5774f7c5 JR |
1983 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1984 | ||
cb76c322 | 1985 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1986 | |
80be308d | 1987 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
04e0463e | 1988 | iommu_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
1989 | dma_dom->need_flush = false; |
1990 | } | |
cb76c322 JR |
1991 | } |
1992 | ||
431b2a20 JR |
1993 | /* |
1994 | * The exported map_single function for dma_ops. | |
1995 | */ | |
51491367 FT |
1996 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1997 | unsigned long offset, size_t size, | |
1998 | enum dma_data_direction dir, | |
1999 | struct dma_attrs *attrs) | |
4da70b9e JR |
2000 | { |
2001 | unsigned long flags; | |
4da70b9e | 2002 | struct protection_domain *domain; |
4da70b9e | 2003 | dma_addr_t addr; |
832a90c3 | 2004 | u64 dma_mask; |
51491367 | 2005 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2006 | |
0f2a86f2 JR |
2007 | INC_STATS_COUNTER(cnt_map_single); |
2008 | ||
94f6d190 JR |
2009 | domain = get_domain(dev); |
2010 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2011 | return (dma_addr_t)paddr; |
94f6d190 JR |
2012 | else if (IS_ERR(domain)) |
2013 | return DMA_ERROR_CODE; | |
4da70b9e | 2014 | |
f99c0f1c JR |
2015 | dma_mask = *dev->dma_mask; |
2016 | ||
4da70b9e | 2017 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2018 | |
cd8c82e8 | 2019 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2020 | dma_mask); |
8fd524b3 | 2021 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2022 | goto out; |
2023 | ||
0518a3a4 | 2024 | iommu_flush_complete(domain); |
4da70b9e JR |
2025 | |
2026 | out: | |
2027 | spin_unlock_irqrestore(&domain->lock, flags); | |
2028 | ||
2029 | return addr; | |
2030 | } | |
2031 | ||
431b2a20 JR |
2032 | /* |
2033 | * The exported unmap_single function for dma_ops. | |
2034 | */ | |
51491367 FT |
2035 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2036 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2037 | { |
2038 | unsigned long flags; | |
4da70b9e | 2039 | struct protection_domain *domain; |
4da70b9e | 2040 | |
146a6917 JR |
2041 | INC_STATS_COUNTER(cnt_unmap_single); |
2042 | ||
94f6d190 JR |
2043 | domain = get_domain(dev); |
2044 | if (IS_ERR(domain)) | |
5b28df6f JR |
2045 | return; |
2046 | ||
4da70b9e JR |
2047 | spin_lock_irqsave(&domain->lock, flags); |
2048 | ||
cd8c82e8 | 2049 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2050 | |
0518a3a4 | 2051 | iommu_flush_complete(domain); |
4da70b9e JR |
2052 | |
2053 | spin_unlock_irqrestore(&domain->lock, flags); | |
2054 | } | |
2055 | ||
431b2a20 JR |
2056 | /* |
2057 | * This is a special map_sg function which is used if we should map a | |
2058 | * device which is not handled by an AMD IOMMU in the system. | |
2059 | */ | |
65b050ad JR |
2060 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2061 | int nelems, int dir) | |
2062 | { | |
2063 | struct scatterlist *s; | |
2064 | int i; | |
2065 | ||
2066 | for_each_sg(sglist, s, nelems, i) { | |
2067 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2068 | s->dma_length = s->length; | |
2069 | } | |
2070 | ||
2071 | return nelems; | |
2072 | } | |
2073 | ||
431b2a20 JR |
2074 | /* |
2075 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2076 | * lists). | |
2077 | */ | |
65b050ad | 2078 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2079 | int nelems, enum dma_data_direction dir, |
2080 | struct dma_attrs *attrs) | |
65b050ad JR |
2081 | { |
2082 | unsigned long flags; | |
65b050ad | 2083 | struct protection_domain *domain; |
65b050ad JR |
2084 | int i; |
2085 | struct scatterlist *s; | |
2086 | phys_addr_t paddr; | |
2087 | int mapped_elems = 0; | |
832a90c3 | 2088 | u64 dma_mask; |
65b050ad | 2089 | |
d03f067a JR |
2090 | INC_STATS_COUNTER(cnt_map_sg); |
2091 | ||
94f6d190 JR |
2092 | domain = get_domain(dev); |
2093 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2094 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2095 | else if (IS_ERR(domain)) |
2096 | return 0; | |
dbcc112e | 2097 | |
832a90c3 | 2098 | dma_mask = *dev->dma_mask; |
65b050ad | 2099 | |
65b050ad JR |
2100 | spin_lock_irqsave(&domain->lock, flags); |
2101 | ||
2102 | for_each_sg(sglist, s, nelems, i) { | |
2103 | paddr = sg_phys(s); | |
2104 | ||
cd8c82e8 | 2105 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2106 | paddr, s->length, dir, false, |
2107 | dma_mask); | |
65b050ad JR |
2108 | |
2109 | if (s->dma_address) { | |
2110 | s->dma_length = s->length; | |
2111 | mapped_elems++; | |
2112 | } else | |
2113 | goto unmap; | |
65b050ad JR |
2114 | } |
2115 | ||
0518a3a4 | 2116 | iommu_flush_complete(domain); |
65b050ad JR |
2117 | |
2118 | out: | |
2119 | spin_unlock_irqrestore(&domain->lock, flags); | |
2120 | ||
2121 | return mapped_elems; | |
2122 | unmap: | |
2123 | for_each_sg(sglist, s, mapped_elems, i) { | |
2124 | if (s->dma_address) | |
cd8c82e8 | 2125 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2126 | s->dma_length, dir); |
2127 | s->dma_address = s->dma_length = 0; | |
2128 | } | |
2129 | ||
2130 | mapped_elems = 0; | |
2131 | ||
2132 | goto out; | |
2133 | } | |
2134 | ||
431b2a20 JR |
2135 | /* |
2136 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2137 | * lists). | |
2138 | */ | |
65b050ad | 2139 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2140 | int nelems, enum dma_data_direction dir, |
2141 | struct dma_attrs *attrs) | |
65b050ad JR |
2142 | { |
2143 | unsigned long flags; | |
65b050ad JR |
2144 | struct protection_domain *domain; |
2145 | struct scatterlist *s; | |
65b050ad JR |
2146 | int i; |
2147 | ||
55877a6b JR |
2148 | INC_STATS_COUNTER(cnt_unmap_sg); |
2149 | ||
94f6d190 JR |
2150 | domain = get_domain(dev); |
2151 | if (IS_ERR(domain)) | |
5b28df6f JR |
2152 | return; |
2153 | ||
65b050ad JR |
2154 | spin_lock_irqsave(&domain->lock, flags); |
2155 | ||
2156 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2157 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2158 | s->dma_length, dir); |
65b050ad JR |
2159 | s->dma_address = s->dma_length = 0; |
2160 | } | |
2161 | ||
0518a3a4 | 2162 | iommu_flush_complete(domain); |
65b050ad JR |
2163 | |
2164 | spin_unlock_irqrestore(&domain->lock, flags); | |
2165 | } | |
2166 | ||
431b2a20 JR |
2167 | /* |
2168 | * The exported alloc_coherent function for dma_ops. | |
2169 | */ | |
5d8b53cf JR |
2170 | static void *alloc_coherent(struct device *dev, size_t size, |
2171 | dma_addr_t *dma_addr, gfp_t flag) | |
2172 | { | |
2173 | unsigned long flags; | |
2174 | void *virt_addr; | |
5d8b53cf | 2175 | struct protection_domain *domain; |
5d8b53cf | 2176 | phys_addr_t paddr; |
832a90c3 | 2177 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2178 | |
c8f0fb36 JR |
2179 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2180 | ||
94f6d190 JR |
2181 | domain = get_domain(dev); |
2182 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2183 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2184 | *dma_addr = __pa(virt_addr); | |
2185 | return virt_addr; | |
94f6d190 JR |
2186 | } else if (IS_ERR(domain)) |
2187 | return NULL; | |
5d8b53cf | 2188 | |
f99c0f1c JR |
2189 | dma_mask = dev->coherent_dma_mask; |
2190 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2191 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2192 | |
2193 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2194 | if (!virt_addr) | |
b25ae679 | 2195 | return NULL; |
5d8b53cf | 2196 | |
5d8b53cf JR |
2197 | paddr = virt_to_phys(virt_addr); |
2198 | ||
832a90c3 JR |
2199 | if (!dma_mask) |
2200 | dma_mask = *dev->dma_mask; | |
2201 | ||
5d8b53cf JR |
2202 | spin_lock_irqsave(&domain->lock, flags); |
2203 | ||
cd8c82e8 | 2204 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2205 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2206 | |
8fd524b3 | 2207 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2208 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2209 | goto out_free; |
367d04c4 | 2210 | } |
5d8b53cf | 2211 | |
0518a3a4 | 2212 | iommu_flush_complete(domain); |
5d8b53cf | 2213 | |
5d8b53cf JR |
2214 | spin_unlock_irqrestore(&domain->lock, flags); |
2215 | ||
2216 | return virt_addr; | |
5b28df6f JR |
2217 | |
2218 | out_free: | |
2219 | ||
2220 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2221 | ||
2222 | return NULL; | |
5d8b53cf JR |
2223 | } |
2224 | ||
431b2a20 JR |
2225 | /* |
2226 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2227 | */ |
5d8b53cf JR |
2228 | static void free_coherent(struct device *dev, size_t size, |
2229 | void *virt_addr, dma_addr_t dma_addr) | |
2230 | { | |
2231 | unsigned long flags; | |
5d8b53cf | 2232 | struct protection_domain *domain; |
5d8b53cf | 2233 | |
5d31ee7e JR |
2234 | INC_STATS_COUNTER(cnt_free_coherent); |
2235 | ||
94f6d190 JR |
2236 | domain = get_domain(dev); |
2237 | if (IS_ERR(domain)) | |
5b28df6f JR |
2238 | goto free_mem; |
2239 | ||
5d8b53cf JR |
2240 | spin_lock_irqsave(&domain->lock, flags); |
2241 | ||
cd8c82e8 | 2242 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2243 | |
0518a3a4 | 2244 | iommu_flush_complete(domain); |
5d8b53cf JR |
2245 | |
2246 | spin_unlock_irqrestore(&domain->lock, flags); | |
2247 | ||
2248 | free_mem: | |
2249 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2250 | } | |
2251 | ||
b39ba6ad JR |
2252 | /* |
2253 | * This function is called by the DMA layer to find out if we can handle a | |
2254 | * particular device. It is part of the dma_ops. | |
2255 | */ | |
2256 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2257 | { | |
420aef8a | 2258 | return check_device(dev); |
b39ba6ad JR |
2259 | } |
2260 | ||
c432f3df | 2261 | /* |
431b2a20 JR |
2262 | * The function for pre-allocating protection domains. |
2263 | * | |
c432f3df JR |
2264 | * If the driver core informs the DMA layer if a driver grabs a device |
2265 | * we don't need to preallocate the protection domains anymore. | |
2266 | * For now we have to. | |
2267 | */ | |
0e93dd88 | 2268 | static void prealloc_protection_domains(void) |
c432f3df JR |
2269 | { |
2270 | struct pci_dev *dev = NULL; | |
2271 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2272 | u16 devid; |
c432f3df | 2273 | |
d18c69d3 | 2274 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2275 | |
2276 | /* Do we handle this device? */ | |
2277 | if (!check_device(&dev->dev)) | |
c432f3df | 2278 | continue; |
98fc5a69 JR |
2279 | |
2280 | /* Is there already any domain for it? */ | |
15898bbc | 2281 | if (domain_for_device(&dev->dev)) |
c432f3df | 2282 | continue; |
98fc5a69 JR |
2283 | |
2284 | devid = get_device_id(&dev->dev); | |
2285 | ||
87a64d52 | 2286 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2287 | if (!dma_dom) |
2288 | continue; | |
2289 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2290 | dma_dom->target_dev = devid; |
2291 | ||
15898bbc | 2292 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2293 | |
bd60b735 | 2294 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2295 | } |
2296 | } | |
2297 | ||
160c1d8e | 2298 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2299 | .alloc_coherent = alloc_coherent, |
2300 | .free_coherent = free_coherent, | |
51491367 FT |
2301 | .map_page = map_page, |
2302 | .unmap_page = unmap_page, | |
6631ee9d JR |
2303 | .map_sg = map_sg, |
2304 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2305 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2306 | }; |
2307 | ||
431b2a20 JR |
2308 | /* |
2309 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2310 | */ | |
f5325094 JR |
2311 | |
2312 | void __init amd_iommu_init_api(void) | |
2313 | { | |
2314 | register_iommu(&amd_iommu_ops); | |
2315 | } | |
2316 | ||
6631ee9d JR |
2317 | int __init amd_iommu_init_dma_ops(void) |
2318 | { | |
2319 | struct amd_iommu *iommu; | |
6631ee9d JR |
2320 | int ret; |
2321 | ||
431b2a20 JR |
2322 | /* |
2323 | * first allocate a default protection domain for every IOMMU we | |
2324 | * found in the system. Devices not assigned to any other | |
2325 | * protection domain will be assigned to the default one. | |
2326 | */ | |
3bd22172 | 2327 | for_each_iommu(iommu) { |
87a64d52 | 2328 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2329 | if (iommu->default_dom == NULL) |
2330 | return -ENOMEM; | |
e2dc14a2 | 2331 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2332 | ret = iommu_init_unity_mappings(iommu); |
2333 | if (ret) | |
2334 | goto free_domains; | |
2335 | } | |
2336 | ||
431b2a20 | 2337 | /* |
8793abeb | 2338 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2339 | */ |
8793abeb | 2340 | prealloc_protection_domains(); |
6631ee9d JR |
2341 | |
2342 | iommu_detected = 1; | |
75f1cdf1 | 2343 | swiotlb = 0; |
6631ee9d | 2344 | |
431b2a20 | 2345 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2346 | dma_ops = &amd_iommu_dma_ops; |
2347 | ||
7f26508b JR |
2348 | amd_iommu_stats_init(); |
2349 | ||
6631ee9d JR |
2350 | return 0; |
2351 | ||
2352 | free_domains: | |
2353 | ||
3bd22172 | 2354 | for_each_iommu(iommu) { |
6631ee9d JR |
2355 | if (iommu->default_dom) |
2356 | dma_ops_domain_free(iommu->default_dom); | |
2357 | } | |
2358 | ||
2359 | return ret; | |
2360 | } | |
6d98cd80 JR |
2361 | |
2362 | /***************************************************************************** | |
2363 | * | |
2364 | * The following functions belong to the exported interface of AMD IOMMU | |
2365 | * | |
2366 | * This interface allows access to lower level functions of the IOMMU | |
2367 | * like protection domain handling and assignement of devices to domains | |
2368 | * which is not possible with the dma_ops interface. | |
2369 | * | |
2370 | *****************************************************************************/ | |
2371 | ||
6d98cd80 JR |
2372 | static void cleanup_domain(struct protection_domain *domain) |
2373 | { | |
492667da | 2374 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2375 | unsigned long flags; |
6d98cd80 JR |
2376 | |
2377 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2378 | ||
492667da JR |
2379 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2380 | struct device *dev = dev_data->dev; | |
2381 | ||
04e856c0 | 2382 | __detach_device(dev); |
492667da JR |
2383 | atomic_set(&dev_data->bind, 0); |
2384 | } | |
6d98cd80 JR |
2385 | |
2386 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2387 | } | |
2388 | ||
2650815f JR |
2389 | static void protection_domain_free(struct protection_domain *domain) |
2390 | { | |
2391 | if (!domain) | |
2392 | return; | |
2393 | ||
aeb26f55 JR |
2394 | del_domain_from_list(domain); |
2395 | ||
2650815f JR |
2396 | if (domain->id) |
2397 | domain_id_free(domain->id); | |
2398 | ||
2399 | kfree(domain); | |
2400 | } | |
2401 | ||
2402 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2403 | { |
2404 | struct protection_domain *domain; | |
2405 | ||
2406 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2407 | if (!domain) | |
2650815f | 2408 | return NULL; |
c156e347 JR |
2409 | |
2410 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2411 | mutex_init(&domain->api_lock); |
c156e347 JR |
2412 | domain->id = domain_id_alloc(); |
2413 | if (!domain->id) | |
2650815f | 2414 | goto out_err; |
7c392cbe | 2415 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2416 | |
aeb26f55 JR |
2417 | add_domain_to_list(domain); |
2418 | ||
2650815f JR |
2419 | return domain; |
2420 | ||
2421 | out_err: | |
2422 | kfree(domain); | |
2423 | ||
2424 | return NULL; | |
2425 | } | |
2426 | ||
2427 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2428 | { | |
2429 | struct protection_domain *domain; | |
2430 | ||
2431 | domain = protection_domain_alloc(); | |
2432 | if (!domain) | |
c156e347 | 2433 | goto out_free; |
2650815f JR |
2434 | |
2435 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2436 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2437 | if (!domain->pt_root) | |
2438 | goto out_free; | |
2439 | ||
2440 | dom->priv = domain; | |
2441 | ||
2442 | return 0; | |
2443 | ||
2444 | out_free: | |
2650815f | 2445 | protection_domain_free(domain); |
c156e347 JR |
2446 | |
2447 | return -ENOMEM; | |
2448 | } | |
2449 | ||
98383fc3 JR |
2450 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2451 | { | |
2452 | struct protection_domain *domain = dom->priv; | |
2453 | ||
2454 | if (!domain) | |
2455 | return; | |
2456 | ||
2457 | if (domain->dev_cnt > 0) | |
2458 | cleanup_domain(domain); | |
2459 | ||
2460 | BUG_ON(domain->dev_cnt != 0); | |
2461 | ||
2462 | free_pagetable(domain); | |
2463 | ||
8b408fe4 | 2464 | protection_domain_free(domain); |
98383fc3 JR |
2465 | |
2466 | dom->priv = NULL; | |
2467 | } | |
2468 | ||
684f2888 JR |
2469 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2470 | struct device *dev) | |
2471 | { | |
657cbb6b | 2472 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2473 | struct amd_iommu *iommu; |
684f2888 JR |
2474 | u16 devid; |
2475 | ||
98fc5a69 | 2476 | if (!check_device(dev)) |
684f2888 JR |
2477 | return; |
2478 | ||
98fc5a69 | 2479 | devid = get_device_id(dev); |
684f2888 | 2480 | |
657cbb6b | 2481 | if (dev_data->domain != NULL) |
15898bbc | 2482 | detach_device(dev); |
684f2888 JR |
2483 | |
2484 | iommu = amd_iommu_rlookup_table[devid]; | |
2485 | if (!iommu) | |
2486 | return; | |
2487 | ||
3fa43655 | 2488 | iommu_flush_device(dev); |
684f2888 JR |
2489 | iommu_completion_wait(iommu); |
2490 | } | |
2491 | ||
01106066 JR |
2492 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2493 | struct device *dev) | |
2494 | { | |
2495 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2496 | struct iommu_dev_data *dev_data; |
01106066 | 2497 | struct amd_iommu *iommu; |
15898bbc | 2498 | int ret; |
01106066 JR |
2499 | u16 devid; |
2500 | ||
98fc5a69 | 2501 | if (!check_device(dev)) |
01106066 JR |
2502 | return -EINVAL; |
2503 | ||
657cbb6b JR |
2504 | dev_data = dev->archdata.iommu; |
2505 | ||
98fc5a69 | 2506 | devid = get_device_id(dev); |
01106066 JR |
2507 | |
2508 | iommu = amd_iommu_rlookup_table[devid]; | |
2509 | if (!iommu) | |
2510 | return -EINVAL; | |
2511 | ||
657cbb6b | 2512 | if (dev_data->domain) |
15898bbc | 2513 | detach_device(dev); |
01106066 | 2514 | |
15898bbc | 2515 | ret = attach_device(dev, domain); |
01106066 JR |
2516 | |
2517 | iommu_completion_wait(iommu); | |
2518 | ||
15898bbc | 2519 | return ret; |
01106066 JR |
2520 | } |
2521 | ||
468e2366 JR |
2522 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2523 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2524 | { |
468e2366 | 2525 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2526 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2527 | int prot = 0; |
2528 | int ret; | |
2529 | ||
2530 | if (iommu_prot & IOMMU_READ) | |
2531 | prot |= IOMMU_PROT_IR; | |
2532 | if (iommu_prot & IOMMU_WRITE) | |
2533 | prot |= IOMMU_PROT_IW; | |
2534 | ||
5d214fe6 | 2535 | mutex_lock(&domain->api_lock); |
795e74f7 | 2536 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2537 | mutex_unlock(&domain->api_lock); |
2538 | ||
795e74f7 | 2539 | return ret; |
c6229ca6 JR |
2540 | } |
2541 | ||
468e2366 JR |
2542 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2543 | int gfp_order) | |
eb74ff6c | 2544 | { |
eb74ff6c | 2545 | struct protection_domain *domain = dom->priv; |
468e2366 | 2546 | unsigned long page_size, unmap_size; |
eb74ff6c | 2547 | |
468e2366 | 2548 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2549 | |
5d214fe6 | 2550 | mutex_lock(&domain->api_lock); |
468e2366 | 2551 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2552 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2553 | |
601367d7 | 2554 | iommu_flush_tlb_pde(domain); |
5d214fe6 | 2555 | |
468e2366 | 2556 | return get_order(unmap_size); |
eb74ff6c JR |
2557 | } |
2558 | ||
645c4c8d JR |
2559 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2560 | unsigned long iova) | |
2561 | { | |
2562 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2563 | unsigned long offset_mask; |
645c4c8d | 2564 | phys_addr_t paddr; |
f03152bb | 2565 | u64 *pte, __pte; |
645c4c8d | 2566 | |
24cd7723 | 2567 | pte = fetch_pte(domain, iova); |
645c4c8d | 2568 | |
a6d41a40 | 2569 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2570 | return 0; |
2571 | ||
f03152bb JR |
2572 | if (PM_PTE_LEVEL(*pte) == 0) |
2573 | offset_mask = PAGE_SIZE - 1; | |
2574 | else | |
2575 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2576 | ||
2577 | __pte = *pte & PM_ADDR_MASK; | |
2578 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2579 | |
2580 | return paddr; | |
2581 | } | |
2582 | ||
dbb9fd86 SY |
2583 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2584 | unsigned long cap) | |
2585 | { | |
80a506b8 JR |
2586 | switch (cap) { |
2587 | case IOMMU_CAP_CACHE_COHERENCY: | |
2588 | return 1; | |
2589 | } | |
2590 | ||
dbb9fd86 SY |
2591 | return 0; |
2592 | } | |
2593 | ||
26961efe JR |
2594 | static struct iommu_ops amd_iommu_ops = { |
2595 | .domain_init = amd_iommu_domain_init, | |
2596 | .domain_destroy = amd_iommu_domain_destroy, | |
2597 | .attach_dev = amd_iommu_attach_device, | |
2598 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2599 | .map = amd_iommu_map, |
2600 | .unmap = amd_iommu_unmap, | |
26961efe | 2601 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2602 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2603 | }; |
2604 | ||
0feae533 JR |
2605 | /***************************************************************************** |
2606 | * | |
2607 | * The next functions do a basic initialization of IOMMU for pass through | |
2608 | * mode | |
2609 | * | |
2610 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2611 | * DMA-API translation. | |
2612 | * | |
2613 | *****************************************************************************/ | |
2614 | ||
2615 | int __init amd_iommu_init_passthrough(void) | |
2616 | { | |
15898bbc | 2617 | struct amd_iommu *iommu; |
0feae533 | 2618 | struct pci_dev *dev = NULL; |
15898bbc | 2619 | u16 devid; |
0feae533 | 2620 | |
af901ca1 | 2621 | /* allocate passthrough domain */ |
0feae533 JR |
2622 | pt_domain = protection_domain_alloc(); |
2623 | if (!pt_domain) | |
2624 | return -ENOMEM; | |
2625 | ||
2626 | pt_domain->mode |= PAGE_MODE_NONE; | |
2627 | ||
6c54aabd | 2628 | for_each_pci_dev(dev) { |
98fc5a69 | 2629 | if (!check_device(&dev->dev)) |
0feae533 JR |
2630 | continue; |
2631 | ||
98fc5a69 JR |
2632 | devid = get_device_id(&dev->dev); |
2633 | ||
15898bbc | 2634 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2635 | if (!iommu) |
2636 | continue; | |
2637 | ||
15898bbc | 2638 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2639 | } |
2640 | ||
2641 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2642 | ||
2643 | return 0; | |
2644 | } |