Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
a66022c4 | 21 | #include <linux/bitmap.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
815b33fd | 28 | #include <linux/delay.h> |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
6a9401a7 | 32 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 33 | #include <asm/amd_iommu_types.h> |
c6da992e | 34 | #include <asm/amd_iommu.h> |
b6c02715 JR |
35 | |
36 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
37 | ||
815b33fd | 38 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 39 | |
b6c02715 JR |
40 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
41 | ||
bd60b735 JR |
42 | /* A list of preallocated protection domains */ |
43 | static LIST_HEAD(iommu_pd_list); | |
44 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
45 | ||
0feae533 JR |
46 | /* |
47 | * Domain for untranslated devices - only allocated | |
48 | * if iommu=pt passed on kernel cmd line. | |
49 | */ | |
50 | static struct protection_domain *pt_domain; | |
51 | ||
26961efe | 52 | static struct iommu_ops amd_iommu_ops; |
26961efe | 53 | |
431b2a20 JR |
54 | /* |
55 | * general struct to manage commands send to an IOMMU | |
56 | */ | |
d6449536 | 57 | struct iommu_cmd { |
b6c02715 JR |
58 | u32 data[4]; |
59 | }; | |
60 | ||
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
657cbb6b JR |
76 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
77 | { | |
78 | return dev->archdata.iommu; | |
79 | } | |
80 | ||
71c70984 JR |
81 | /* |
82 | * In this function the list of preallocated protection domains is traversed to | |
83 | * find the domain for a specific device | |
84 | */ | |
85 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
86 | { | |
87 | struct dma_ops_domain *entry, *ret = NULL; | |
88 | unsigned long flags; | |
89 | u16 alias = amd_iommu_alias_table[devid]; | |
90 | ||
91 | if (list_empty(&iommu_pd_list)) | |
92 | return NULL; | |
93 | ||
94 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
95 | ||
96 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
97 | if (entry->target_dev == devid || | |
98 | entry->target_dev == alias) { | |
99 | ret = entry; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
98fc5a69 JR |
109 | /* |
110 | * This function checks if the driver got a valid device from the caller to | |
111 | * avoid dereferencing invalid pointers. | |
112 | */ | |
113 | static bool check_device(struct device *dev) | |
114 | { | |
115 | u16 devid; | |
116 | ||
117 | if (!dev || !dev->dma_mask) | |
118 | return false; | |
119 | ||
120 | /* No device or no PCI device */ | |
339d3261 | 121 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
122 | return false; |
123 | ||
124 | devid = get_device_id(dev); | |
125 | ||
126 | /* Out of our scope? */ | |
127 | if (devid > amd_iommu_last_bdf) | |
128 | return false; | |
129 | ||
130 | if (amd_iommu_rlookup_table[devid] == NULL) | |
131 | return false; | |
132 | ||
133 | return true; | |
134 | } | |
135 | ||
657cbb6b JR |
136 | static int iommu_init_device(struct device *dev) |
137 | { | |
138 | struct iommu_dev_data *dev_data; | |
139 | struct pci_dev *pdev; | |
140 | u16 devid, alias; | |
141 | ||
142 | if (dev->archdata.iommu) | |
143 | return 0; | |
144 | ||
145 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
146 | if (!dev_data) | |
147 | return -ENOMEM; | |
148 | ||
b00d3bcf JR |
149 | dev_data->dev = dev; |
150 | ||
657cbb6b JR |
151 | devid = get_device_id(dev); |
152 | alias = amd_iommu_alias_table[devid]; | |
153 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
154 | if (pdev) | |
155 | dev_data->alias = &pdev->dev; | |
156 | ||
24100055 JR |
157 | atomic_set(&dev_data->bind, 0); |
158 | ||
657cbb6b JR |
159 | dev->archdata.iommu = dev_data; |
160 | ||
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static void iommu_uninit_device(struct device *dev) | |
166 | { | |
167 | kfree(dev->archdata.iommu); | |
168 | } | |
b7cc9554 JR |
169 | |
170 | void __init amd_iommu_uninit_devices(void) | |
171 | { | |
172 | struct pci_dev *pdev = NULL; | |
173 | ||
174 | for_each_pci_dev(pdev) { | |
175 | ||
176 | if (!check_device(&pdev->dev)) | |
177 | continue; | |
178 | ||
179 | iommu_uninit_device(&pdev->dev); | |
180 | } | |
181 | } | |
182 | ||
183 | int __init amd_iommu_init_devices(void) | |
184 | { | |
185 | struct pci_dev *pdev = NULL; | |
186 | int ret = 0; | |
187 | ||
188 | for_each_pci_dev(pdev) { | |
189 | ||
190 | if (!check_device(&pdev->dev)) | |
191 | continue; | |
192 | ||
193 | ret = iommu_init_device(&pdev->dev); | |
194 | if (ret) | |
195 | goto out_free; | |
196 | } | |
197 | ||
198 | return 0; | |
199 | ||
200 | out_free: | |
201 | ||
202 | amd_iommu_uninit_devices(); | |
203 | ||
204 | return ret; | |
205 | } | |
7f26508b JR |
206 | #ifdef CONFIG_AMD_IOMMU_STATS |
207 | ||
208 | /* | |
209 | * Initialization code for statistics collection | |
210 | */ | |
211 | ||
da49f6df | 212 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 213 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 214 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 215 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 216 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 217 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 218 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 219 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 220 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 221 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 222 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 223 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 224 | |
7f26508b | 225 | static struct dentry *stats_dir; |
7f26508b JR |
226 | static struct dentry *de_fflush; |
227 | ||
228 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
229 | { | |
230 | if (stats_dir == NULL) | |
231 | return; | |
232 | ||
233 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
234 | &cnt->value); | |
235 | } | |
236 | ||
237 | static void amd_iommu_stats_init(void) | |
238 | { | |
239 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
240 | if (stats_dir == NULL) | |
241 | return; | |
242 | ||
7f26508b JR |
243 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
244 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
245 | |
246 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 247 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 248 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 249 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 250 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 251 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 252 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 253 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 254 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 255 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 256 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 257 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
258 | } |
259 | ||
260 | #endif | |
261 | ||
a80dc3e0 JR |
262 | /**************************************************************************** |
263 | * | |
264 | * Interrupt handling functions | |
265 | * | |
266 | ****************************************************************************/ | |
267 | ||
e3e59876 JR |
268 | static void dump_dte_entry(u16 devid) |
269 | { | |
270 | int i; | |
271 | ||
272 | for (i = 0; i < 8; ++i) | |
273 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
274 | amd_iommu_dev_table[devid].data[i]); | |
275 | } | |
276 | ||
945b4ac4 JR |
277 | static void dump_command(unsigned long phys_addr) |
278 | { | |
279 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < 4; ++i) | |
283 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
284 | } | |
285 | ||
a345b23b | 286 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
287 | { |
288 | u32 *event = __evt; | |
289 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
290 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
291 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
292 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
293 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
294 | ||
4c6f40d4 | 295 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
296 | |
297 | switch (type) { | |
298 | case EVENT_TYPE_ILL_DEV: | |
299 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
300 | "address=0x%016llx flags=0x%04x]\n", | |
301 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
302 | address, flags); | |
e3e59876 | 303 | dump_dte_entry(devid); |
90008ee4 JR |
304 | break; |
305 | case EVENT_TYPE_IO_FAULT: | |
306 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
307 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
308 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
309 | domid, address, flags); | |
310 | break; | |
311 | case EVENT_TYPE_DEV_TAB_ERR: | |
312 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
313 | "address=0x%016llx flags=0x%04x]\n", | |
314 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
315 | address, flags); | |
316 | break; | |
317 | case EVENT_TYPE_PAGE_TAB_ERR: | |
318 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
319 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
320 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
321 | domid, address, flags); | |
322 | break; | |
323 | case EVENT_TYPE_ILL_CMD: | |
324 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 325 | dump_command(address); |
90008ee4 JR |
326 | break; |
327 | case EVENT_TYPE_CMD_HARD_ERR: | |
328 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
329 | "flags=0x%04x]\n", address, flags); | |
330 | break; | |
331 | case EVENT_TYPE_IOTLB_INV_TO: | |
332 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
333 | "address=0x%016llx]\n", | |
334 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
335 | address); | |
336 | break; | |
337 | case EVENT_TYPE_INV_DEV_REQ: | |
338 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
339 | "address=0x%016llx flags=0x%04x]\n", | |
340 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
341 | address, flags); | |
342 | break; | |
343 | default: | |
344 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
345 | } | |
346 | } | |
347 | ||
348 | static void iommu_poll_events(struct amd_iommu *iommu) | |
349 | { | |
350 | u32 head, tail; | |
351 | unsigned long flags; | |
352 | ||
353 | spin_lock_irqsave(&iommu->lock, flags); | |
354 | ||
355 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
356 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
357 | ||
358 | while (head != tail) { | |
a345b23b | 359 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
360 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
361 | } | |
362 | ||
363 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
364 | ||
365 | spin_unlock_irqrestore(&iommu->lock, flags); | |
366 | } | |
367 | ||
a80dc3e0 JR |
368 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
369 | { | |
90008ee4 JR |
370 | struct amd_iommu *iommu; |
371 | ||
3bd22172 | 372 | for_each_iommu(iommu) |
90008ee4 JR |
373 | iommu_poll_events(iommu); |
374 | ||
375 | return IRQ_HANDLED; | |
a80dc3e0 JR |
376 | } |
377 | ||
431b2a20 JR |
378 | /**************************************************************************** |
379 | * | |
380 | * IOMMU command queuing functions | |
381 | * | |
382 | ****************************************************************************/ | |
383 | ||
ac0ea6e9 JR |
384 | static int wait_on_sem(volatile u64 *sem) |
385 | { | |
386 | int i = 0; | |
387 | ||
388 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
389 | udelay(1); | |
390 | i += 1; | |
391 | } | |
392 | ||
393 | if (i == LOOP_TIMEOUT) { | |
394 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
395 | return -EIO; | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
402 | struct iommu_cmd *cmd, | |
403 | u32 tail) | |
404 | { | |
405 | u8 *target; | |
406 | ||
407 | target = iommu->cmd_buf + tail; | |
408 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
409 | ||
410 | /* Copy command to buffer */ | |
411 | memcpy(target, cmd, sizeof(*cmd)); | |
412 | ||
413 | /* Tell the IOMMU about it */ | |
414 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
415 | } | |
416 | ||
815b33fd | 417 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 418 | { |
815b33fd JR |
419 | WARN_ON(address & 0x7ULL); |
420 | ||
ded46737 | 421 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
422 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
423 | cmd->data[1] = upper_32_bits(__pa(address)); | |
424 | cmd->data[2] = 1; | |
ded46737 JR |
425 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
426 | } | |
427 | ||
94fe79e2 JR |
428 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
429 | { | |
430 | memset(cmd, 0, sizeof(*cmd)); | |
431 | cmd->data[0] = devid; | |
432 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
433 | } | |
434 | ||
11b6402c JR |
435 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
436 | size_t size, u16 domid, int pde) | |
437 | { | |
438 | u64 pages; | |
439 | int s; | |
440 | ||
441 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
442 | s = 0; | |
443 | ||
444 | if (pages > 1) { | |
445 | /* | |
446 | * If we have to flush more than one page, flush all | |
447 | * TLB entries for this domain | |
448 | */ | |
449 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
450 | s = 1; | |
451 | } | |
452 | ||
453 | address &= PAGE_MASK; | |
454 | ||
455 | memset(cmd, 0, sizeof(*cmd)); | |
456 | cmd->data[1] |= domid; | |
457 | cmd->data[2] = lower_32_bits(address); | |
458 | cmd->data[3] = upper_32_bits(address); | |
459 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
460 | if (s) /* size bit - we flush more than one 4kb page */ | |
461 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
462 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
463 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
464 | } | |
465 | ||
431b2a20 JR |
466 | /* |
467 | * Writes the command to the IOMMUs command buffer and informs the | |
ac0ea6e9 | 468 | * hardware about the new command. |
431b2a20 | 469 | */ |
815b33fd | 470 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 471 | { |
ac0ea6e9 | 472 | u32 left, tail, head, next_tail; |
815b33fd | 473 | unsigned long flags; |
a19ae1ec | 474 | |
549c90dc | 475 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
476 | |
477 | again: | |
815b33fd | 478 | spin_lock_irqsave(&iommu->lock, flags); |
ac0ea6e9 JR |
479 | |
480 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
481 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
482 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
483 | left = (head - next_tail) % iommu->cmd_buf_size; | |
484 | ||
485 | if (left <= 2) { | |
486 | struct iommu_cmd sync_cmd; | |
487 | volatile u64 sem = 0; | |
488 | int ret; | |
489 | ||
490 | build_completion_wait(&sync_cmd, (u64)&sem); | |
491 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
492 | ||
493 | spin_unlock_irqrestore(&iommu->lock, flags); | |
494 | ||
495 | if ((ret = wait_on_sem(&sem)) != 0) | |
496 | return ret; | |
497 | ||
498 | goto again; | |
499 | } | |
500 | ||
501 | copy_cmd_to_buffer(iommu, cmd, tail); | |
502 | ||
503 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 504 | iommu->need_sync = true; |
ac0ea6e9 | 505 | |
a19ae1ec JR |
506 | spin_unlock_irqrestore(&iommu->lock, flags); |
507 | ||
815b33fd | 508 | return 0; |
8d201968 JR |
509 | } |
510 | ||
511 | /* | |
512 | * This function queues a completion wait command into the command | |
513 | * buffer of an IOMMU | |
514 | */ | |
a19ae1ec JR |
515 | static int iommu_completion_wait(struct amd_iommu *iommu) |
516 | { | |
815b33fd JR |
517 | struct iommu_cmd cmd; |
518 | volatile u64 sem = 0; | |
ac0ea6e9 | 519 | int ret; |
7e4f88da | 520 | |
09ee17eb | 521 | if (!iommu->need_sync) |
815b33fd | 522 | return 0; |
09ee17eb | 523 | |
815b33fd | 524 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 525 | |
815b33fd | 526 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 527 | if (ret) |
815b33fd | 528 | return ret; |
84df8175 | 529 | |
ac0ea6e9 | 530 | return wait_on_sem(&sem); |
a19ae1ec JR |
531 | } |
532 | ||
d8c13085 JR |
533 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
534 | { | |
535 | struct iommu_cmd cmd; | |
536 | ||
537 | build_inv_dte(&cmd, devid); | |
538 | ||
539 | return iommu_queue_command(iommu, &cmd); | |
540 | } | |
541 | ||
7d0c5cc5 JR |
542 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
543 | { | |
544 | u32 devid; | |
545 | ||
546 | for (devid = 0; devid <= 0xffff; ++devid) | |
547 | iommu_flush_dte(iommu, devid); | |
548 | ||
549 | iommu_completion_wait(iommu); | |
550 | } | |
551 | ||
552 | /* | |
553 | * This function uses heavy locking and may disable irqs for some time. But | |
554 | * this is no issue because it is only called during resume. | |
555 | */ | |
556 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
557 | { | |
558 | u32 dom_id; | |
559 | ||
560 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { | |
561 | struct iommu_cmd cmd; | |
562 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
563 | dom_id, 1); | |
564 | iommu_queue_command(iommu, &cmd); | |
565 | } | |
566 | ||
567 | iommu_completion_wait(iommu); | |
568 | } | |
569 | ||
570 | void iommu_flush_all_caches(struct amd_iommu *iommu) | |
571 | { | |
572 | iommu_flush_dte_all(iommu); | |
573 | iommu_flush_tlb_all(iommu); | |
574 | } | |
575 | ||
431b2a20 JR |
576 | /* |
577 | * Command send function for invalidating a device table entry | |
578 | */ | |
d8c13085 | 579 | static int device_flush_dte(struct device *dev) |
3fa43655 JR |
580 | { |
581 | struct amd_iommu *iommu; | |
582 | u16 devid; | |
583 | ||
584 | devid = get_device_id(dev); | |
585 | iommu = amd_iommu_rlookup_table[devid]; | |
586 | ||
d8c13085 | 587 | return iommu_flush_dte(iommu, devid); |
3fa43655 JR |
588 | } |
589 | ||
431b2a20 JR |
590 | /* |
591 | * TLB invalidation function which is called from the mapping functions. | |
592 | * It invalidates a single PTE if the range to flush is within a single | |
593 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
594 | */ | |
17b124bf JR |
595 | static void __domain_flush_pages(struct protection_domain *domain, |
596 | u64 address, size_t size, int pde) | |
a19ae1ec | 597 | { |
11b6402c JR |
598 | struct iommu_cmd cmd; |
599 | int ret = 0, i; | |
a19ae1ec | 600 | |
11b6402c | 601 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 602 | |
6de8ad9b JR |
603 | for (i = 0; i < amd_iommus_present; ++i) { |
604 | if (!domain->dev_iommu[i]) | |
605 | continue; | |
606 | ||
607 | /* | |
608 | * Devices of this domain are behind this IOMMU | |
609 | * We need a TLB flush | |
610 | */ | |
11b6402c | 611 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
612 | } |
613 | ||
11b6402c | 614 | WARN_ON(ret); |
6de8ad9b JR |
615 | } |
616 | ||
17b124bf JR |
617 | static void domain_flush_pages(struct protection_domain *domain, |
618 | u64 address, size_t size) | |
6de8ad9b | 619 | { |
17b124bf | 620 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 621 | } |
b6c02715 | 622 | |
1c655773 | 623 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 624 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 625 | { |
17b124bf | 626 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
627 | } |
628 | ||
42a49f96 | 629 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 630 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 631 | { |
17b124bf JR |
632 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
633 | } | |
634 | ||
635 | static void domain_flush_complete(struct protection_domain *domain) | |
636 | { | |
637 | int i; | |
638 | ||
639 | for (i = 0; i < amd_iommus_present; ++i) { | |
640 | if (!domain->dev_iommu[i]) | |
641 | continue; | |
642 | ||
643 | /* | |
644 | * Devices of this domain are behind this IOMMU | |
645 | * We need to wait for completion of all commands. | |
646 | */ | |
647 | iommu_completion_wait(amd_iommus[i]); | |
648 | } | |
42a49f96 CW |
649 | } |
650 | ||
b00d3bcf | 651 | |
43f49609 | 652 | /* |
b00d3bcf | 653 | * This function flushes the DTEs for all devices in domain |
43f49609 | 654 | */ |
17b124bf | 655 | static void domain_flush_devices(struct protection_domain *domain) |
b00d3bcf JR |
656 | { |
657 | struct iommu_dev_data *dev_data; | |
658 | unsigned long flags; | |
659 | ||
660 | spin_lock_irqsave(&domain->lock, flags); | |
661 | ||
662 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
d8c13085 | 663 | device_flush_dte(dev_data->dev); |
b00d3bcf JR |
664 | |
665 | spin_unlock_irqrestore(&domain->lock, flags); | |
666 | } | |
667 | ||
431b2a20 JR |
668 | /**************************************************************************** |
669 | * | |
670 | * The functions below are used the create the page table mappings for | |
671 | * unity mapped regions. | |
672 | * | |
673 | ****************************************************************************/ | |
674 | ||
308973d3 JR |
675 | /* |
676 | * This function is used to add another level to an IO page table. Adding | |
677 | * another level increases the size of the address space by 9 bits to a size up | |
678 | * to 64 bits. | |
679 | */ | |
680 | static bool increase_address_space(struct protection_domain *domain, | |
681 | gfp_t gfp) | |
682 | { | |
683 | u64 *pte; | |
684 | ||
685 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
686 | /* address space already 64 bit large */ | |
687 | return false; | |
688 | ||
689 | pte = (void *)get_zeroed_page(gfp); | |
690 | if (!pte) | |
691 | return false; | |
692 | ||
693 | *pte = PM_LEVEL_PDE(domain->mode, | |
694 | virt_to_phys(domain->pt_root)); | |
695 | domain->pt_root = pte; | |
696 | domain->mode += 1; | |
697 | domain->updated = true; | |
698 | ||
699 | return true; | |
700 | } | |
701 | ||
702 | static u64 *alloc_pte(struct protection_domain *domain, | |
703 | unsigned long address, | |
cbb9d729 | 704 | unsigned long page_size, |
308973d3 JR |
705 | u64 **pte_page, |
706 | gfp_t gfp) | |
707 | { | |
cbb9d729 | 708 | int level, end_lvl; |
308973d3 | 709 | u64 *pte, *page; |
cbb9d729 JR |
710 | |
711 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
712 | |
713 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
714 | increase_address_space(domain, gfp); | |
715 | ||
cbb9d729 JR |
716 | level = domain->mode - 1; |
717 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
718 | address = PAGE_SIZE_ALIGN(address, page_size); | |
719 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
720 | |
721 | while (level > end_lvl) { | |
722 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
723 | page = (u64 *)get_zeroed_page(gfp); | |
724 | if (!page) | |
725 | return NULL; | |
726 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
727 | } | |
728 | ||
cbb9d729 JR |
729 | /* No level skipping support yet */ |
730 | if (PM_PTE_LEVEL(*pte) != level) | |
731 | return NULL; | |
732 | ||
308973d3 JR |
733 | level -= 1; |
734 | ||
735 | pte = IOMMU_PTE_PAGE(*pte); | |
736 | ||
737 | if (pte_page && level == end_lvl) | |
738 | *pte_page = pte; | |
739 | ||
740 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
741 | } | |
742 | ||
743 | return pte; | |
744 | } | |
745 | ||
746 | /* | |
747 | * This function checks if there is a PTE for a given dma address. If | |
748 | * there is one, it returns the pointer to it. | |
749 | */ | |
24cd7723 | 750 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
751 | { |
752 | int level; | |
753 | u64 *pte; | |
754 | ||
24cd7723 JR |
755 | if (address > PM_LEVEL_SIZE(domain->mode)) |
756 | return NULL; | |
757 | ||
758 | level = domain->mode - 1; | |
759 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 760 | |
24cd7723 JR |
761 | while (level > 0) { |
762 | ||
763 | /* Not Present */ | |
308973d3 JR |
764 | if (!IOMMU_PTE_PRESENT(*pte)) |
765 | return NULL; | |
766 | ||
24cd7723 JR |
767 | /* Large PTE */ |
768 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
769 | unsigned long pte_mask, __pte; | |
770 | ||
771 | /* | |
772 | * If we have a series of large PTEs, make | |
773 | * sure to return a pointer to the first one. | |
774 | */ | |
775 | pte_mask = PTE_PAGE_SIZE(*pte); | |
776 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
777 | __pte = ((unsigned long)pte) & pte_mask; | |
778 | ||
779 | return (u64 *)__pte; | |
780 | } | |
781 | ||
782 | /* No level skipping support yet */ | |
783 | if (PM_PTE_LEVEL(*pte) != level) | |
784 | return NULL; | |
785 | ||
308973d3 JR |
786 | level -= 1; |
787 | ||
24cd7723 | 788 | /* Walk to the next level */ |
308973d3 JR |
789 | pte = IOMMU_PTE_PAGE(*pte); |
790 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
791 | } |
792 | ||
793 | return pte; | |
794 | } | |
795 | ||
431b2a20 JR |
796 | /* |
797 | * Generic mapping functions. It maps a physical address into a DMA | |
798 | * address space. It allocates the page table pages if necessary. | |
799 | * In the future it can be extended to a generic mapping function | |
800 | * supporting all features of AMD IOMMU page tables like level skipping | |
801 | * and full 64 bit address spaces. | |
802 | */ | |
38e817fe JR |
803 | static int iommu_map_page(struct protection_domain *dom, |
804 | unsigned long bus_addr, | |
805 | unsigned long phys_addr, | |
abdc5eb3 | 806 | int prot, |
cbb9d729 | 807 | unsigned long page_size) |
bd0e5211 | 808 | { |
8bda3092 | 809 | u64 __pte, *pte; |
cbb9d729 | 810 | int i, count; |
abdc5eb3 | 811 | |
bad1cac2 | 812 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
813 | return -EINVAL; |
814 | ||
cbb9d729 JR |
815 | bus_addr = PAGE_ALIGN(bus_addr); |
816 | phys_addr = PAGE_ALIGN(phys_addr); | |
817 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
818 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
819 | ||
820 | for (i = 0; i < count; ++i) | |
821 | if (IOMMU_PTE_PRESENT(pte[i])) | |
822 | return -EBUSY; | |
bd0e5211 | 823 | |
cbb9d729 JR |
824 | if (page_size > PAGE_SIZE) { |
825 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
826 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
827 | } else | |
828 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 829 | |
bd0e5211 JR |
830 | if (prot & IOMMU_PROT_IR) |
831 | __pte |= IOMMU_PTE_IR; | |
832 | if (prot & IOMMU_PROT_IW) | |
833 | __pte |= IOMMU_PTE_IW; | |
834 | ||
cbb9d729 JR |
835 | for (i = 0; i < count; ++i) |
836 | pte[i] = __pte; | |
bd0e5211 | 837 | |
04bfdd84 JR |
838 | update_domain(dom); |
839 | ||
bd0e5211 JR |
840 | return 0; |
841 | } | |
842 | ||
24cd7723 JR |
843 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
844 | unsigned long bus_addr, | |
845 | unsigned long page_size) | |
eb74ff6c | 846 | { |
24cd7723 JR |
847 | unsigned long long unmap_size, unmapped; |
848 | u64 *pte; | |
849 | ||
850 | BUG_ON(!is_power_of_2(page_size)); | |
851 | ||
852 | unmapped = 0; | |
eb74ff6c | 853 | |
24cd7723 JR |
854 | while (unmapped < page_size) { |
855 | ||
856 | pte = fetch_pte(dom, bus_addr); | |
857 | ||
858 | if (!pte) { | |
859 | /* | |
860 | * No PTE for this address | |
861 | * move forward in 4kb steps | |
862 | */ | |
863 | unmap_size = PAGE_SIZE; | |
864 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
865 | /* 4kb PTE found for this address */ | |
866 | unmap_size = PAGE_SIZE; | |
867 | *pte = 0ULL; | |
868 | } else { | |
869 | int count, i; | |
870 | ||
871 | /* Large PTE found which maps this address */ | |
872 | unmap_size = PTE_PAGE_SIZE(*pte); | |
873 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
874 | for (i = 0; i < count; i++) | |
875 | pte[i] = 0ULL; | |
876 | } | |
877 | ||
878 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
879 | unmapped += unmap_size; | |
880 | } | |
881 | ||
882 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 883 | |
24cd7723 | 884 | return unmapped; |
eb74ff6c | 885 | } |
eb74ff6c | 886 | |
431b2a20 JR |
887 | /* |
888 | * This function checks if a specific unity mapping entry is needed for | |
889 | * this specific IOMMU. | |
890 | */ | |
bd0e5211 JR |
891 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
892 | struct unity_map_entry *entry) | |
893 | { | |
894 | u16 bdf, i; | |
895 | ||
896 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
897 | bdf = amd_iommu_alias_table[i]; | |
898 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
899 | return 1; | |
900 | } | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
431b2a20 JR |
905 | /* |
906 | * This function actually applies the mapping to the page table of the | |
907 | * dma_ops domain. | |
908 | */ | |
bd0e5211 JR |
909 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
910 | struct unity_map_entry *e) | |
911 | { | |
912 | u64 addr; | |
913 | int ret; | |
914 | ||
915 | for (addr = e->address_start; addr < e->address_end; | |
916 | addr += PAGE_SIZE) { | |
abdc5eb3 | 917 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 918 | PAGE_SIZE); |
bd0e5211 JR |
919 | if (ret) |
920 | return ret; | |
921 | /* | |
922 | * if unity mapping is in aperture range mark the page | |
923 | * as allocated in the aperture | |
924 | */ | |
925 | if (addr < dma_dom->aperture_size) | |
c3239567 | 926 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 927 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
928 | } |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
171e7b37 JR |
933 | /* |
934 | * Init the unity mappings for a specific IOMMU in the system | |
935 | * | |
936 | * Basically iterates over all unity mapping entries and applies them to | |
937 | * the default domain DMA of that IOMMU if necessary. | |
938 | */ | |
939 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
940 | { | |
941 | struct unity_map_entry *entry; | |
942 | int ret; | |
943 | ||
944 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
945 | if (!iommu_for_unity_map(iommu, entry)) | |
946 | continue; | |
947 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
948 | if (ret) | |
949 | return ret; | |
950 | } | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
431b2a20 JR |
955 | /* |
956 | * Inits the unity mappings required for a specific device | |
957 | */ | |
bd0e5211 JR |
958 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
959 | u16 devid) | |
960 | { | |
961 | struct unity_map_entry *e; | |
962 | int ret; | |
963 | ||
964 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
965 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
966 | continue; | |
967 | ret = dma_ops_unity_map(dma_dom, e); | |
968 | if (ret) | |
969 | return ret; | |
970 | } | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
431b2a20 JR |
975 | /**************************************************************************** |
976 | * | |
977 | * The next functions belong to the address allocator for the dma_ops | |
978 | * interface functions. They work like the allocators in the other IOMMU | |
979 | * drivers. Its basically a bitmap which marks the allocated pages in | |
980 | * the aperture. Maybe it could be enhanced in the future to a more | |
981 | * efficient allocator. | |
982 | * | |
983 | ****************************************************************************/ | |
d3086444 | 984 | |
431b2a20 | 985 | /* |
384de729 | 986 | * The address allocator core functions. |
431b2a20 JR |
987 | * |
988 | * called with domain->lock held | |
989 | */ | |
384de729 | 990 | |
171e7b37 JR |
991 | /* |
992 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
993 | * ranges. | |
994 | */ | |
995 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
996 | unsigned long start_page, | |
997 | unsigned int pages) | |
998 | { | |
999 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1000 | ||
1001 | if (start_page + pages > last_page) | |
1002 | pages = last_page - start_page; | |
1003 | ||
1004 | for (i = start_page; i < start_page + pages; ++i) { | |
1005 | int index = i / APERTURE_RANGE_PAGES; | |
1006 | int page = i % APERTURE_RANGE_PAGES; | |
1007 | __set_bit(page, dom->aperture[index]->bitmap); | |
1008 | } | |
1009 | } | |
1010 | ||
9cabe89b JR |
1011 | /* |
1012 | * This function is used to add a new aperture range to an existing | |
1013 | * aperture in case of dma_ops domain allocation or address allocation | |
1014 | * failure. | |
1015 | */ | |
576175c2 | 1016 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1017 | bool populate, gfp_t gfp) |
1018 | { | |
1019 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1020 | struct amd_iommu *iommu; |
d91afd15 | 1021 | unsigned long i; |
9cabe89b | 1022 | |
f5e9705c JR |
1023 | #ifdef CONFIG_IOMMU_STRESS |
1024 | populate = false; | |
1025 | #endif | |
1026 | ||
9cabe89b JR |
1027 | if (index >= APERTURE_MAX_RANGES) |
1028 | return -ENOMEM; | |
1029 | ||
1030 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1031 | if (!dma_dom->aperture[index]) | |
1032 | return -ENOMEM; | |
1033 | ||
1034 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1035 | if (!dma_dom->aperture[index]->bitmap) | |
1036 | goto out_free; | |
1037 | ||
1038 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1039 | ||
1040 | if (populate) { | |
1041 | unsigned long address = dma_dom->aperture_size; | |
1042 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1043 | u64 *pte, *pte_page; | |
1044 | ||
1045 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1046 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1047 | &pte_page, gfp); |
1048 | if (!pte) | |
1049 | goto out_free; | |
1050 | ||
1051 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1052 | ||
1053 | address += APERTURE_RANGE_SIZE / 64; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1058 | ||
b595076a | 1059 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1060 | for_each_iommu(iommu) { |
1061 | if (iommu->exclusion_start && | |
1062 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1063 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1064 | unsigned long startpage; | |
1065 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1066 | iommu->exclusion_length, | |
1067 | PAGE_SIZE); | |
1068 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1069 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1070 | } | |
00cd122a JR |
1071 | } |
1072 | ||
1073 | /* | |
1074 | * Check for areas already mapped as present in the new aperture | |
1075 | * range and mark those pages as reserved in the allocator. Such | |
1076 | * mappings may already exist as a result of requested unity | |
1077 | * mappings for devices. | |
1078 | */ | |
1079 | for (i = dma_dom->aperture[index]->offset; | |
1080 | i < dma_dom->aperture_size; | |
1081 | i += PAGE_SIZE) { | |
24cd7723 | 1082 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1083 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1084 | continue; | |
1085 | ||
1086 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1087 | } | |
1088 | ||
04bfdd84 JR |
1089 | update_domain(&dma_dom->domain); |
1090 | ||
9cabe89b JR |
1091 | return 0; |
1092 | ||
1093 | out_free: | |
04bfdd84 JR |
1094 | update_domain(&dma_dom->domain); |
1095 | ||
9cabe89b JR |
1096 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1097 | ||
1098 | kfree(dma_dom->aperture[index]); | |
1099 | dma_dom->aperture[index] = NULL; | |
1100 | ||
1101 | return -ENOMEM; | |
1102 | } | |
1103 | ||
384de729 JR |
1104 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1105 | struct dma_ops_domain *dom, | |
1106 | unsigned int pages, | |
1107 | unsigned long align_mask, | |
1108 | u64 dma_mask, | |
1109 | unsigned long start) | |
1110 | { | |
803b8cb4 | 1111 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1112 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1113 | int i = start >> APERTURE_RANGE_SHIFT; | |
1114 | unsigned long boundary_size; | |
1115 | unsigned long address = -1; | |
1116 | unsigned long limit; | |
1117 | ||
803b8cb4 JR |
1118 | next_bit >>= PAGE_SHIFT; |
1119 | ||
384de729 JR |
1120 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1121 | PAGE_SIZE) >> PAGE_SHIFT; | |
1122 | ||
1123 | for (;i < max_index; ++i) { | |
1124 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1125 | ||
1126 | if (dom->aperture[i]->offset >= dma_mask) | |
1127 | break; | |
1128 | ||
1129 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1130 | dma_mask >> PAGE_SHIFT); | |
1131 | ||
1132 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1133 | limit, next_bit, pages, 0, | |
1134 | boundary_size, align_mask); | |
1135 | if (address != -1) { | |
1136 | address = dom->aperture[i]->offset + | |
1137 | (address << PAGE_SHIFT); | |
803b8cb4 | 1138 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1139 | break; |
1140 | } | |
1141 | ||
1142 | next_bit = 0; | |
1143 | } | |
1144 | ||
1145 | return address; | |
1146 | } | |
1147 | ||
d3086444 JR |
1148 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1149 | struct dma_ops_domain *dom, | |
6d4f343f | 1150 | unsigned int pages, |
832a90c3 JR |
1151 | unsigned long align_mask, |
1152 | u64 dma_mask) | |
d3086444 | 1153 | { |
d3086444 | 1154 | unsigned long address; |
d3086444 | 1155 | |
fe16f088 JR |
1156 | #ifdef CONFIG_IOMMU_STRESS |
1157 | dom->next_address = 0; | |
1158 | dom->need_flush = true; | |
1159 | #endif | |
d3086444 | 1160 | |
384de729 | 1161 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1162 | dma_mask, dom->next_address); |
d3086444 | 1163 | |
1c655773 | 1164 | if (address == -1) { |
803b8cb4 | 1165 | dom->next_address = 0; |
384de729 JR |
1166 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1167 | dma_mask, 0); | |
1c655773 JR |
1168 | dom->need_flush = true; |
1169 | } | |
d3086444 | 1170 | |
384de729 | 1171 | if (unlikely(address == -1)) |
8fd524b3 | 1172 | address = DMA_ERROR_CODE; |
d3086444 JR |
1173 | |
1174 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1175 | ||
1176 | return address; | |
1177 | } | |
1178 | ||
431b2a20 JR |
1179 | /* |
1180 | * The address free function. | |
1181 | * | |
1182 | * called with domain->lock held | |
1183 | */ | |
d3086444 JR |
1184 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1185 | unsigned long address, | |
1186 | unsigned int pages) | |
1187 | { | |
384de729 JR |
1188 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1189 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1190 | |
384de729 JR |
1191 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1192 | ||
47bccd6b JR |
1193 | #ifdef CONFIG_IOMMU_STRESS |
1194 | if (i < 4) | |
1195 | return; | |
1196 | #endif | |
80be308d | 1197 | |
803b8cb4 | 1198 | if (address >= dom->next_address) |
80be308d | 1199 | dom->need_flush = true; |
384de729 JR |
1200 | |
1201 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1202 | |
a66022c4 | 1203 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1204 | |
d3086444 JR |
1205 | } |
1206 | ||
431b2a20 JR |
1207 | /**************************************************************************** |
1208 | * | |
1209 | * The next functions belong to the domain allocation. A domain is | |
1210 | * allocated for every IOMMU as the default domain. If device isolation | |
1211 | * is enabled, every device get its own domain. The most important thing | |
1212 | * about domains is the page table mapping the DMA address space they | |
1213 | * contain. | |
1214 | * | |
1215 | ****************************************************************************/ | |
1216 | ||
aeb26f55 JR |
1217 | /* |
1218 | * This function adds a protection domain to the global protection domain list | |
1219 | */ | |
1220 | static void add_domain_to_list(struct protection_domain *domain) | |
1221 | { | |
1222 | unsigned long flags; | |
1223 | ||
1224 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1225 | list_add(&domain->list, &amd_iommu_pd_list); | |
1226 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1227 | } | |
1228 | ||
1229 | /* | |
1230 | * This function removes a protection domain to the global | |
1231 | * protection domain list | |
1232 | */ | |
1233 | static void del_domain_from_list(struct protection_domain *domain) | |
1234 | { | |
1235 | unsigned long flags; | |
1236 | ||
1237 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1238 | list_del(&domain->list); | |
1239 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1240 | } | |
1241 | ||
ec487d1a JR |
1242 | static u16 domain_id_alloc(void) |
1243 | { | |
1244 | unsigned long flags; | |
1245 | int id; | |
1246 | ||
1247 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1248 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1249 | BUG_ON(id == 0); | |
1250 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1251 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1252 | else | |
1253 | id = 0; | |
1254 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1255 | ||
1256 | return id; | |
1257 | } | |
1258 | ||
a2acfb75 JR |
1259 | static void domain_id_free(int id) |
1260 | { | |
1261 | unsigned long flags; | |
1262 | ||
1263 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1264 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1265 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1266 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1267 | } | |
a2acfb75 | 1268 | |
86db2e5d | 1269 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1270 | { |
1271 | int i, j; | |
1272 | u64 *p1, *p2, *p3; | |
1273 | ||
86db2e5d | 1274 | p1 = domain->pt_root; |
ec487d1a JR |
1275 | |
1276 | if (!p1) | |
1277 | return; | |
1278 | ||
1279 | for (i = 0; i < 512; ++i) { | |
1280 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1281 | continue; | |
1282 | ||
1283 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1284 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1285 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1286 | continue; | |
1287 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1288 | free_page((unsigned long)p3); | |
1289 | } | |
1290 | ||
1291 | free_page((unsigned long)p2); | |
1292 | } | |
1293 | ||
1294 | free_page((unsigned long)p1); | |
86db2e5d JR |
1295 | |
1296 | domain->pt_root = NULL; | |
ec487d1a JR |
1297 | } |
1298 | ||
431b2a20 JR |
1299 | /* |
1300 | * Free a domain, only used if something went wrong in the | |
1301 | * allocation path and we need to free an already allocated page table | |
1302 | */ | |
ec487d1a JR |
1303 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1304 | { | |
384de729 JR |
1305 | int i; |
1306 | ||
ec487d1a JR |
1307 | if (!dom) |
1308 | return; | |
1309 | ||
aeb26f55 JR |
1310 | del_domain_from_list(&dom->domain); |
1311 | ||
86db2e5d | 1312 | free_pagetable(&dom->domain); |
ec487d1a | 1313 | |
384de729 JR |
1314 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1315 | if (!dom->aperture[i]) | |
1316 | continue; | |
1317 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1318 | kfree(dom->aperture[i]); | |
1319 | } | |
ec487d1a JR |
1320 | |
1321 | kfree(dom); | |
1322 | } | |
1323 | ||
431b2a20 JR |
1324 | /* |
1325 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1326 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1327 | * structures required for the dma_ops interface |
1328 | */ | |
87a64d52 | 1329 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1330 | { |
1331 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1332 | |
1333 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1334 | if (!dma_dom) | |
1335 | return NULL; | |
1336 | ||
1337 | spin_lock_init(&dma_dom->domain.lock); | |
1338 | ||
1339 | dma_dom->domain.id = domain_id_alloc(); | |
1340 | if (dma_dom->domain.id == 0) | |
1341 | goto free_dma_dom; | |
7c392cbe | 1342 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1343 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1344 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1345 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1346 | dma_dom->domain.priv = dma_dom; |
1347 | if (!dma_dom->domain.pt_root) | |
1348 | goto free_dma_dom; | |
ec487d1a | 1349 | |
1c655773 | 1350 | dma_dom->need_flush = false; |
bd60b735 | 1351 | dma_dom->target_dev = 0xffff; |
1c655773 | 1352 | |
aeb26f55 JR |
1353 | add_domain_to_list(&dma_dom->domain); |
1354 | ||
576175c2 | 1355 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1356 | goto free_dma_dom; |
ec487d1a | 1357 | |
431b2a20 | 1358 | /* |
ec487d1a JR |
1359 | * mark the first page as allocated so we never return 0 as |
1360 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1361 | */ |
384de729 | 1362 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1363 | dma_dom->next_address = 0; |
ec487d1a | 1364 | |
ec487d1a JR |
1365 | |
1366 | return dma_dom; | |
1367 | ||
1368 | free_dma_dom: | |
1369 | dma_ops_domain_free(dma_dom); | |
1370 | ||
1371 | return NULL; | |
1372 | } | |
1373 | ||
5b28df6f JR |
1374 | /* |
1375 | * little helper function to check whether a given protection domain is a | |
1376 | * dma_ops domain | |
1377 | */ | |
1378 | static bool dma_ops_domain(struct protection_domain *domain) | |
1379 | { | |
1380 | return domain->flags & PD_DMA_OPS_MASK; | |
1381 | } | |
1382 | ||
407d733e | 1383 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1384 | { |
b20ac0d4 | 1385 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1386 | |
38ddf41b JR |
1387 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1388 | << DEV_ENTRY_MODE_SHIFT; | |
1389 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1390 | |
b20ac0d4 | 1391 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1392 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1393 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1394 | } |
1395 | ||
1396 | static void clear_dte_entry(u16 devid) | |
1397 | { | |
15898bbc JR |
1398 | /* remove entry from the device table seen by the hardware */ |
1399 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1400 | amd_iommu_dev_table[devid].data[1] = 0; | |
1401 | amd_iommu_dev_table[devid].data[2] = 0; | |
1402 | ||
1403 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1404 | } |
1405 | ||
1406 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1407 | { | |
1408 | struct iommu_dev_data *dev_data; | |
1409 | struct amd_iommu *iommu; | |
1410 | u16 devid; | |
1411 | ||
1412 | devid = get_device_id(dev); | |
1413 | iommu = amd_iommu_rlookup_table[devid]; | |
1414 | dev_data = get_dev_data(dev); | |
1415 | ||
1416 | /* Update data structures */ | |
1417 | dev_data->domain = domain; | |
1418 | list_add(&dev_data->list, &domain->dev_list); | |
1419 | set_dte_entry(devid, domain); | |
1420 | ||
1421 | /* Do reference counting */ | |
1422 | domain->dev_iommu[iommu->index] += 1; | |
1423 | domain->dev_cnt += 1; | |
1424 | ||
1425 | /* Flush the DTE entry */ | |
d8c13085 | 1426 | device_flush_dte(dev); |
7f760ddd JR |
1427 | } |
1428 | ||
1429 | static void do_detach(struct device *dev) | |
1430 | { | |
1431 | struct iommu_dev_data *dev_data; | |
1432 | struct amd_iommu *iommu; | |
1433 | u16 devid; | |
1434 | ||
1435 | devid = get_device_id(dev); | |
1436 | iommu = amd_iommu_rlookup_table[devid]; | |
1437 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1438 | |
1439 | /* decrease reference counters */ | |
7f760ddd JR |
1440 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1441 | dev_data->domain->dev_cnt -= 1; | |
1442 | ||
1443 | /* Update data structures */ | |
1444 | dev_data->domain = NULL; | |
1445 | list_del(&dev_data->list); | |
1446 | clear_dte_entry(devid); | |
15898bbc | 1447 | |
7f760ddd | 1448 | /* Flush the DTE entry */ |
d8c13085 | 1449 | device_flush_dte(dev); |
2b681faf JR |
1450 | } |
1451 | ||
1452 | /* | |
1453 | * If a device is not yet associated with a domain, this function does | |
1454 | * assigns it visible for the hardware | |
1455 | */ | |
15898bbc JR |
1456 | static int __attach_device(struct device *dev, |
1457 | struct protection_domain *domain) | |
2b681faf | 1458 | { |
657cbb6b | 1459 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1460 | int ret; |
657cbb6b | 1461 | |
657cbb6b JR |
1462 | dev_data = get_dev_data(dev); |
1463 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1464 | |
657cbb6b JR |
1465 | if (!alias_data) |
1466 | return -EINVAL; | |
15898bbc | 1467 | |
2b681faf JR |
1468 | /* lock domain */ |
1469 | spin_lock(&domain->lock); | |
1470 | ||
15898bbc | 1471 | /* Some sanity checks */ |
84fe6c19 | 1472 | ret = -EBUSY; |
657cbb6b JR |
1473 | if (alias_data->domain != NULL && |
1474 | alias_data->domain != domain) | |
84fe6c19 | 1475 | goto out_unlock; |
eba6ac60 | 1476 | |
657cbb6b JR |
1477 | if (dev_data->domain != NULL && |
1478 | dev_data->domain != domain) | |
84fe6c19 | 1479 | goto out_unlock; |
15898bbc JR |
1480 | |
1481 | /* Do real assignment */ | |
7f760ddd JR |
1482 | if (dev_data->alias != dev) { |
1483 | alias_data = get_dev_data(dev_data->alias); | |
1484 | if (alias_data->domain == NULL) | |
1485 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1486 | |
1487 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1488 | } |
15898bbc | 1489 | |
7f760ddd JR |
1490 | if (dev_data->domain == NULL) |
1491 | do_attach(dev, domain); | |
eba6ac60 | 1492 | |
24100055 JR |
1493 | atomic_inc(&dev_data->bind); |
1494 | ||
84fe6c19 JL |
1495 | ret = 0; |
1496 | ||
1497 | out_unlock: | |
1498 | ||
eba6ac60 JR |
1499 | /* ready */ |
1500 | spin_unlock(&domain->lock); | |
15898bbc | 1501 | |
84fe6c19 | 1502 | return ret; |
0feae533 | 1503 | } |
b20ac0d4 | 1504 | |
407d733e JR |
1505 | /* |
1506 | * If a device is not yet associated with a domain, this function does | |
1507 | * assigns it visible for the hardware | |
1508 | */ | |
15898bbc JR |
1509 | static int attach_device(struct device *dev, |
1510 | struct protection_domain *domain) | |
0feae533 | 1511 | { |
eba6ac60 | 1512 | unsigned long flags; |
15898bbc | 1513 | int ret; |
eba6ac60 JR |
1514 | |
1515 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1516 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1517 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1518 | ||
0feae533 JR |
1519 | /* |
1520 | * We might boot into a crash-kernel here. The crashed kernel | |
1521 | * left the caches in the IOMMU dirty. So we have to flush | |
1522 | * here to evict all dirty stuff. | |
1523 | */ | |
17b124bf | 1524 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1525 | |
1526 | return ret; | |
b20ac0d4 JR |
1527 | } |
1528 | ||
355bf553 JR |
1529 | /* |
1530 | * Removes a device from a protection domain (unlocked) | |
1531 | */ | |
15898bbc | 1532 | static void __detach_device(struct device *dev) |
355bf553 | 1533 | { |
657cbb6b | 1534 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1535 | struct iommu_dev_data *alias_data; |
2ca76279 | 1536 | struct protection_domain *domain; |
7c392cbe | 1537 | unsigned long flags; |
c4596114 | 1538 | |
7f760ddd | 1539 | BUG_ON(!dev_data->domain); |
355bf553 | 1540 | |
2ca76279 JR |
1541 | domain = dev_data->domain; |
1542 | ||
1543 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1544 | |
7f760ddd | 1545 | if (dev_data->alias != dev) { |
24100055 | 1546 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1547 | if (atomic_dec_and_test(&alias_data->bind)) |
1548 | do_detach(dev_data->alias); | |
24100055 JR |
1549 | } |
1550 | ||
7f760ddd JR |
1551 | if (atomic_dec_and_test(&dev_data->bind)) |
1552 | do_detach(dev); | |
1553 | ||
2ca76279 | 1554 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1555 | |
1556 | /* | |
1557 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1558 | * passthrough domain if it is detached from any other domain. |
1559 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1560 | */ |
d3ad9373 JR |
1561 | if (iommu_pass_through && |
1562 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1563 | __attach_device(dev, pt_domain); |
355bf553 JR |
1564 | } |
1565 | ||
1566 | /* | |
1567 | * Removes a device from a protection domain (with devtable_lock held) | |
1568 | */ | |
15898bbc | 1569 | static void detach_device(struct device *dev) |
355bf553 JR |
1570 | { |
1571 | unsigned long flags; | |
1572 | ||
1573 | /* lock device table */ | |
1574 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1575 | __detach_device(dev); |
355bf553 JR |
1576 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1577 | } | |
e275a2a0 | 1578 | |
15898bbc JR |
1579 | /* |
1580 | * Find out the protection domain structure for a given PCI device. This | |
1581 | * will give us the pointer to the page table root for example. | |
1582 | */ | |
1583 | static struct protection_domain *domain_for_device(struct device *dev) | |
1584 | { | |
1585 | struct protection_domain *dom; | |
657cbb6b | 1586 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1587 | unsigned long flags; |
1588 | u16 devid, alias; | |
1589 | ||
657cbb6b JR |
1590 | devid = get_device_id(dev); |
1591 | alias = amd_iommu_alias_table[devid]; | |
1592 | dev_data = get_dev_data(dev); | |
1593 | alias_data = get_dev_data(dev_data->alias); | |
1594 | if (!alias_data) | |
1595 | return NULL; | |
15898bbc JR |
1596 | |
1597 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1598 | dom = dev_data->domain; |
15898bbc | 1599 | if (dom == NULL && |
657cbb6b JR |
1600 | alias_data->domain != NULL) { |
1601 | __attach_device(dev, alias_data->domain); | |
1602 | dom = alias_data->domain; | |
15898bbc JR |
1603 | } |
1604 | ||
1605 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1606 | ||
1607 | return dom; | |
1608 | } | |
1609 | ||
e275a2a0 JR |
1610 | static int device_change_notifier(struct notifier_block *nb, |
1611 | unsigned long action, void *data) | |
1612 | { | |
1613 | struct device *dev = data; | |
98fc5a69 | 1614 | u16 devid; |
e275a2a0 JR |
1615 | struct protection_domain *domain; |
1616 | struct dma_ops_domain *dma_domain; | |
1617 | struct amd_iommu *iommu; | |
1ac4cbbc | 1618 | unsigned long flags; |
e275a2a0 | 1619 | |
98fc5a69 JR |
1620 | if (!check_device(dev)) |
1621 | return 0; | |
e275a2a0 | 1622 | |
98fc5a69 JR |
1623 | devid = get_device_id(dev); |
1624 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1625 | |
1626 | switch (action) { | |
c1eee67b | 1627 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1628 | |
1629 | domain = domain_for_device(dev); | |
1630 | ||
e275a2a0 JR |
1631 | if (!domain) |
1632 | goto out; | |
a1ca331c JR |
1633 | if (iommu_pass_through) |
1634 | break; | |
15898bbc | 1635 | detach_device(dev); |
1ac4cbbc JR |
1636 | break; |
1637 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1638 | |
1639 | iommu_init_device(dev); | |
1640 | ||
1641 | domain = domain_for_device(dev); | |
1642 | ||
1ac4cbbc JR |
1643 | /* allocate a protection domain if a device is added */ |
1644 | dma_domain = find_protection_domain(devid); | |
1645 | if (dma_domain) | |
1646 | goto out; | |
87a64d52 | 1647 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1648 | if (!dma_domain) |
1649 | goto out; | |
1650 | dma_domain->target_dev = devid; | |
1651 | ||
1652 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1653 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1654 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1655 | ||
e275a2a0 | 1656 | break; |
657cbb6b JR |
1657 | case BUS_NOTIFY_DEL_DEVICE: |
1658 | ||
1659 | iommu_uninit_device(dev); | |
1660 | ||
e275a2a0 JR |
1661 | default: |
1662 | goto out; | |
1663 | } | |
1664 | ||
d8c13085 | 1665 | device_flush_dte(dev); |
e275a2a0 JR |
1666 | iommu_completion_wait(iommu); |
1667 | ||
1668 | out: | |
1669 | return 0; | |
1670 | } | |
1671 | ||
b25ae679 | 1672 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1673 | .notifier_call = device_change_notifier, |
1674 | }; | |
355bf553 | 1675 | |
8638c491 JR |
1676 | void amd_iommu_init_notifier(void) |
1677 | { | |
1678 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1679 | } | |
1680 | ||
431b2a20 JR |
1681 | /***************************************************************************** |
1682 | * | |
1683 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1684 | * | |
1685 | *****************************************************************************/ | |
1686 | ||
1687 | /* | |
1688 | * In the dma_ops path we only have the struct device. This function | |
1689 | * finds the corresponding IOMMU, the protection domain and the | |
1690 | * requestor id for a given device. | |
1691 | * If the device is not yet associated with a domain this is also done | |
1692 | * in this function. | |
1693 | */ | |
94f6d190 | 1694 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1695 | { |
94f6d190 | 1696 | struct protection_domain *domain; |
b20ac0d4 | 1697 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1698 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1699 | |
f99c0f1c | 1700 | if (!check_device(dev)) |
94f6d190 | 1701 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1702 | |
94f6d190 JR |
1703 | domain = domain_for_device(dev); |
1704 | if (domain != NULL && !dma_ops_domain(domain)) | |
1705 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1706 | |
94f6d190 JR |
1707 | if (domain != NULL) |
1708 | return domain; | |
b20ac0d4 | 1709 | |
15898bbc | 1710 | /* Device not bount yet - bind it */ |
94f6d190 | 1711 | dma_dom = find_protection_domain(devid); |
15898bbc | 1712 | if (!dma_dom) |
94f6d190 JR |
1713 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1714 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1715 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1716 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1717 | |
94f6d190 | 1718 | return &dma_dom->domain; |
b20ac0d4 JR |
1719 | } |
1720 | ||
04bfdd84 JR |
1721 | static void update_device_table(struct protection_domain *domain) |
1722 | { | |
492667da | 1723 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1724 | |
492667da JR |
1725 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
1726 | u16 devid = get_device_id(dev_data->dev); | |
1727 | set_dte_entry(devid, domain); | |
04bfdd84 JR |
1728 | } |
1729 | } | |
1730 | ||
1731 | static void update_domain(struct protection_domain *domain) | |
1732 | { | |
1733 | if (!domain->updated) | |
1734 | return; | |
1735 | ||
1736 | update_device_table(domain); | |
17b124bf JR |
1737 | |
1738 | domain_flush_devices(domain); | |
1739 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1740 | |
1741 | domain->updated = false; | |
1742 | } | |
1743 | ||
8bda3092 JR |
1744 | /* |
1745 | * This function fetches the PTE for a given address in the aperture | |
1746 | */ | |
1747 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1748 | unsigned long address) | |
1749 | { | |
384de729 | 1750 | struct aperture_range *aperture; |
8bda3092 JR |
1751 | u64 *pte, *pte_page; |
1752 | ||
384de729 JR |
1753 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1754 | if (!aperture) | |
1755 | return NULL; | |
1756 | ||
1757 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1758 | if (!pte) { |
cbb9d729 | 1759 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1760 | GFP_ATOMIC); |
384de729 JR |
1761 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1762 | } else | |
8c8c143c | 1763 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1764 | |
04bfdd84 | 1765 | update_domain(&dom->domain); |
8bda3092 JR |
1766 | |
1767 | return pte; | |
1768 | } | |
1769 | ||
431b2a20 JR |
1770 | /* |
1771 | * This is the generic map function. It maps one 4kb page at paddr to | |
1772 | * the given address in the DMA address space for the domain. | |
1773 | */ | |
680525e0 | 1774 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1775 | unsigned long address, |
1776 | phys_addr_t paddr, | |
1777 | int direction) | |
1778 | { | |
1779 | u64 *pte, __pte; | |
1780 | ||
1781 | WARN_ON(address > dom->aperture_size); | |
1782 | ||
1783 | paddr &= PAGE_MASK; | |
1784 | ||
8bda3092 | 1785 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1786 | if (!pte) |
8fd524b3 | 1787 | return DMA_ERROR_CODE; |
cb76c322 JR |
1788 | |
1789 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1790 | ||
1791 | if (direction == DMA_TO_DEVICE) | |
1792 | __pte |= IOMMU_PTE_IR; | |
1793 | else if (direction == DMA_FROM_DEVICE) | |
1794 | __pte |= IOMMU_PTE_IW; | |
1795 | else if (direction == DMA_BIDIRECTIONAL) | |
1796 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1797 | ||
1798 | WARN_ON(*pte); | |
1799 | ||
1800 | *pte = __pte; | |
1801 | ||
1802 | return (dma_addr_t)address; | |
1803 | } | |
1804 | ||
431b2a20 JR |
1805 | /* |
1806 | * The generic unmapping function for on page in the DMA address space. | |
1807 | */ | |
680525e0 | 1808 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1809 | unsigned long address) |
1810 | { | |
384de729 | 1811 | struct aperture_range *aperture; |
cb76c322 JR |
1812 | u64 *pte; |
1813 | ||
1814 | if (address >= dom->aperture_size) | |
1815 | return; | |
1816 | ||
384de729 JR |
1817 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1818 | if (!aperture) | |
1819 | return; | |
1820 | ||
1821 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1822 | if (!pte) | |
1823 | return; | |
cb76c322 | 1824 | |
8c8c143c | 1825 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1826 | |
1827 | WARN_ON(!*pte); | |
1828 | ||
1829 | *pte = 0ULL; | |
1830 | } | |
1831 | ||
431b2a20 JR |
1832 | /* |
1833 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1834 | * contiguous memory region into DMA address space. It is used by all |
1835 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1836 | * Must be called with the domain lock held. |
1837 | */ | |
cb76c322 | 1838 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1839 | struct dma_ops_domain *dma_dom, |
1840 | phys_addr_t paddr, | |
1841 | size_t size, | |
6d4f343f | 1842 | int dir, |
832a90c3 JR |
1843 | bool align, |
1844 | u64 dma_mask) | |
cb76c322 JR |
1845 | { |
1846 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1847 | dma_addr_t address, start, ret; |
cb76c322 | 1848 | unsigned int pages; |
6d4f343f | 1849 | unsigned long align_mask = 0; |
cb76c322 JR |
1850 | int i; |
1851 | ||
e3c449f5 | 1852 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1853 | paddr &= PAGE_MASK; |
1854 | ||
8ecaf8f1 JR |
1855 | INC_STATS_COUNTER(total_map_requests); |
1856 | ||
c1858976 JR |
1857 | if (pages > 1) |
1858 | INC_STATS_COUNTER(cross_page); | |
1859 | ||
6d4f343f JR |
1860 | if (align) |
1861 | align_mask = (1UL << get_order(size)) - 1; | |
1862 | ||
11b83888 | 1863 | retry: |
832a90c3 JR |
1864 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1865 | dma_mask); | |
8fd524b3 | 1866 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1867 | /* |
1868 | * setting next_address here will let the address | |
1869 | * allocator only scan the new allocated range in the | |
1870 | * first run. This is a small optimization. | |
1871 | */ | |
1872 | dma_dom->next_address = dma_dom->aperture_size; | |
1873 | ||
576175c2 | 1874 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1875 | goto out; |
1876 | ||
1877 | /* | |
af901ca1 | 1878 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1879 | * allocation again |
1880 | */ | |
1881 | goto retry; | |
1882 | } | |
cb76c322 JR |
1883 | |
1884 | start = address; | |
1885 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1886 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1887 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1888 | goto out_unmap; |
1889 | ||
cb76c322 JR |
1890 | paddr += PAGE_SIZE; |
1891 | start += PAGE_SIZE; | |
1892 | } | |
1893 | address += offset; | |
1894 | ||
5774f7c5 JR |
1895 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1896 | ||
afa9fdc2 | 1897 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 1898 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 1899 | dma_dom->need_flush = false; |
318afd41 | 1900 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 1901 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1902 | |
cb76c322 JR |
1903 | out: |
1904 | return address; | |
53812c11 JR |
1905 | |
1906 | out_unmap: | |
1907 | ||
1908 | for (--i; i >= 0; --i) { | |
1909 | start -= PAGE_SIZE; | |
680525e0 | 1910 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1911 | } |
1912 | ||
1913 | dma_ops_free_addresses(dma_dom, address, pages); | |
1914 | ||
8fd524b3 | 1915 | return DMA_ERROR_CODE; |
cb76c322 JR |
1916 | } |
1917 | ||
431b2a20 JR |
1918 | /* |
1919 | * Does the reverse of the __map_single function. Must be called with | |
1920 | * the domain lock held too | |
1921 | */ | |
cd8c82e8 | 1922 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1923 | dma_addr_t dma_addr, |
1924 | size_t size, | |
1925 | int dir) | |
1926 | { | |
04e0463e | 1927 | dma_addr_t flush_addr; |
cb76c322 JR |
1928 | dma_addr_t i, start; |
1929 | unsigned int pages; | |
1930 | ||
8fd524b3 | 1931 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1932 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1933 | return; |
1934 | ||
04e0463e | 1935 | flush_addr = dma_addr; |
e3c449f5 | 1936 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1937 | dma_addr &= PAGE_MASK; |
1938 | start = dma_addr; | |
1939 | ||
1940 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1941 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1942 | start += PAGE_SIZE; |
1943 | } | |
1944 | ||
5774f7c5 JR |
1945 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1946 | ||
cb76c322 | 1947 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1948 | |
80be308d | 1949 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 1950 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
1951 | dma_dom->need_flush = false; |
1952 | } | |
cb76c322 JR |
1953 | } |
1954 | ||
431b2a20 JR |
1955 | /* |
1956 | * The exported map_single function for dma_ops. | |
1957 | */ | |
51491367 FT |
1958 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1959 | unsigned long offset, size_t size, | |
1960 | enum dma_data_direction dir, | |
1961 | struct dma_attrs *attrs) | |
4da70b9e JR |
1962 | { |
1963 | unsigned long flags; | |
4da70b9e | 1964 | struct protection_domain *domain; |
4da70b9e | 1965 | dma_addr_t addr; |
832a90c3 | 1966 | u64 dma_mask; |
51491367 | 1967 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1968 | |
0f2a86f2 JR |
1969 | INC_STATS_COUNTER(cnt_map_single); |
1970 | ||
94f6d190 JR |
1971 | domain = get_domain(dev); |
1972 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 1973 | return (dma_addr_t)paddr; |
94f6d190 JR |
1974 | else if (IS_ERR(domain)) |
1975 | return DMA_ERROR_CODE; | |
4da70b9e | 1976 | |
f99c0f1c JR |
1977 | dma_mask = *dev->dma_mask; |
1978 | ||
4da70b9e | 1979 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 1980 | |
cd8c82e8 | 1981 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 1982 | dma_mask); |
8fd524b3 | 1983 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1984 | goto out; |
1985 | ||
17b124bf | 1986 | domain_flush_complete(domain); |
4da70b9e JR |
1987 | |
1988 | out: | |
1989 | spin_unlock_irqrestore(&domain->lock, flags); | |
1990 | ||
1991 | return addr; | |
1992 | } | |
1993 | ||
431b2a20 JR |
1994 | /* |
1995 | * The exported unmap_single function for dma_ops. | |
1996 | */ | |
51491367 FT |
1997 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1998 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1999 | { |
2000 | unsigned long flags; | |
4da70b9e | 2001 | struct protection_domain *domain; |
4da70b9e | 2002 | |
146a6917 JR |
2003 | INC_STATS_COUNTER(cnt_unmap_single); |
2004 | ||
94f6d190 JR |
2005 | domain = get_domain(dev); |
2006 | if (IS_ERR(domain)) | |
5b28df6f JR |
2007 | return; |
2008 | ||
4da70b9e JR |
2009 | spin_lock_irqsave(&domain->lock, flags); |
2010 | ||
cd8c82e8 | 2011 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2012 | |
17b124bf | 2013 | domain_flush_complete(domain); |
4da70b9e JR |
2014 | |
2015 | spin_unlock_irqrestore(&domain->lock, flags); | |
2016 | } | |
2017 | ||
431b2a20 JR |
2018 | /* |
2019 | * This is a special map_sg function which is used if we should map a | |
2020 | * device which is not handled by an AMD IOMMU in the system. | |
2021 | */ | |
65b050ad JR |
2022 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2023 | int nelems, int dir) | |
2024 | { | |
2025 | struct scatterlist *s; | |
2026 | int i; | |
2027 | ||
2028 | for_each_sg(sglist, s, nelems, i) { | |
2029 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2030 | s->dma_length = s->length; | |
2031 | } | |
2032 | ||
2033 | return nelems; | |
2034 | } | |
2035 | ||
431b2a20 JR |
2036 | /* |
2037 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2038 | * lists). | |
2039 | */ | |
65b050ad | 2040 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2041 | int nelems, enum dma_data_direction dir, |
2042 | struct dma_attrs *attrs) | |
65b050ad JR |
2043 | { |
2044 | unsigned long flags; | |
65b050ad | 2045 | struct protection_domain *domain; |
65b050ad JR |
2046 | int i; |
2047 | struct scatterlist *s; | |
2048 | phys_addr_t paddr; | |
2049 | int mapped_elems = 0; | |
832a90c3 | 2050 | u64 dma_mask; |
65b050ad | 2051 | |
d03f067a JR |
2052 | INC_STATS_COUNTER(cnt_map_sg); |
2053 | ||
94f6d190 JR |
2054 | domain = get_domain(dev); |
2055 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2056 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2057 | else if (IS_ERR(domain)) |
2058 | return 0; | |
dbcc112e | 2059 | |
832a90c3 | 2060 | dma_mask = *dev->dma_mask; |
65b050ad | 2061 | |
65b050ad JR |
2062 | spin_lock_irqsave(&domain->lock, flags); |
2063 | ||
2064 | for_each_sg(sglist, s, nelems, i) { | |
2065 | paddr = sg_phys(s); | |
2066 | ||
cd8c82e8 | 2067 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2068 | paddr, s->length, dir, false, |
2069 | dma_mask); | |
65b050ad JR |
2070 | |
2071 | if (s->dma_address) { | |
2072 | s->dma_length = s->length; | |
2073 | mapped_elems++; | |
2074 | } else | |
2075 | goto unmap; | |
65b050ad JR |
2076 | } |
2077 | ||
17b124bf | 2078 | domain_flush_complete(domain); |
65b050ad JR |
2079 | |
2080 | out: | |
2081 | spin_unlock_irqrestore(&domain->lock, flags); | |
2082 | ||
2083 | return mapped_elems; | |
2084 | unmap: | |
2085 | for_each_sg(sglist, s, mapped_elems, i) { | |
2086 | if (s->dma_address) | |
cd8c82e8 | 2087 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2088 | s->dma_length, dir); |
2089 | s->dma_address = s->dma_length = 0; | |
2090 | } | |
2091 | ||
2092 | mapped_elems = 0; | |
2093 | ||
2094 | goto out; | |
2095 | } | |
2096 | ||
431b2a20 JR |
2097 | /* |
2098 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2099 | * lists). | |
2100 | */ | |
65b050ad | 2101 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2102 | int nelems, enum dma_data_direction dir, |
2103 | struct dma_attrs *attrs) | |
65b050ad JR |
2104 | { |
2105 | unsigned long flags; | |
65b050ad JR |
2106 | struct protection_domain *domain; |
2107 | struct scatterlist *s; | |
65b050ad JR |
2108 | int i; |
2109 | ||
55877a6b JR |
2110 | INC_STATS_COUNTER(cnt_unmap_sg); |
2111 | ||
94f6d190 JR |
2112 | domain = get_domain(dev); |
2113 | if (IS_ERR(domain)) | |
5b28df6f JR |
2114 | return; |
2115 | ||
65b050ad JR |
2116 | spin_lock_irqsave(&domain->lock, flags); |
2117 | ||
2118 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2119 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2120 | s->dma_length, dir); |
65b050ad JR |
2121 | s->dma_address = s->dma_length = 0; |
2122 | } | |
2123 | ||
17b124bf | 2124 | domain_flush_complete(domain); |
65b050ad JR |
2125 | |
2126 | spin_unlock_irqrestore(&domain->lock, flags); | |
2127 | } | |
2128 | ||
431b2a20 JR |
2129 | /* |
2130 | * The exported alloc_coherent function for dma_ops. | |
2131 | */ | |
5d8b53cf JR |
2132 | static void *alloc_coherent(struct device *dev, size_t size, |
2133 | dma_addr_t *dma_addr, gfp_t flag) | |
2134 | { | |
2135 | unsigned long flags; | |
2136 | void *virt_addr; | |
5d8b53cf | 2137 | struct protection_domain *domain; |
5d8b53cf | 2138 | phys_addr_t paddr; |
832a90c3 | 2139 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2140 | |
c8f0fb36 JR |
2141 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2142 | ||
94f6d190 JR |
2143 | domain = get_domain(dev); |
2144 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2145 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2146 | *dma_addr = __pa(virt_addr); | |
2147 | return virt_addr; | |
94f6d190 JR |
2148 | } else if (IS_ERR(domain)) |
2149 | return NULL; | |
5d8b53cf | 2150 | |
f99c0f1c JR |
2151 | dma_mask = dev->coherent_dma_mask; |
2152 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2153 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2154 | |
2155 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2156 | if (!virt_addr) | |
b25ae679 | 2157 | return NULL; |
5d8b53cf | 2158 | |
5d8b53cf JR |
2159 | paddr = virt_to_phys(virt_addr); |
2160 | ||
832a90c3 JR |
2161 | if (!dma_mask) |
2162 | dma_mask = *dev->dma_mask; | |
2163 | ||
5d8b53cf JR |
2164 | spin_lock_irqsave(&domain->lock, flags); |
2165 | ||
cd8c82e8 | 2166 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2167 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2168 | |
8fd524b3 | 2169 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2170 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2171 | goto out_free; |
367d04c4 | 2172 | } |
5d8b53cf | 2173 | |
17b124bf | 2174 | domain_flush_complete(domain); |
5d8b53cf | 2175 | |
5d8b53cf JR |
2176 | spin_unlock_irqrestore(&domain->lock, flags); |
2177 | ||
2178 | return virt_addr; | |
5b28df6f JR |
2179 | |
2180 | out_free: | |
2181 | ||
2182 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2183 | ||
2184 | return NULL; | |
5d8b53cf JR |
2185 | } |
2186 | ||
431b2a20 JR |
2187 | /* |
2188 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2189 | */ |
5d8b53cf JR |
2190 | static void free_coherent(struct device *dev, size_t size, |
2191 | void *virt_addr, dma_addr_t dma_addr) | |
2192 | { | |
2193 | unsigned long flags; | |
5d8b53cf | 2194 | struct protection_domain *domain; |
5d8b53cf | 2195 | |
5d31ee7e JR |
2196 | INC_STATS_COUNTER(cnt_free_coherent); |
2197 | ||
94f6d190 JR |
2198 | domain = get_domain(dev); |
2199 | if (IS_ERR(domain)) | |
5b28df6f JR |
2200 | goto free_mem; |
2201 | ||
5d8b53cf JR |
2202 | spin_lock_irqsave(&domain->lock, flags); |
2203 | ||
cd8c82e8 | 2204 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2205 | |
17b124bf | 2206 | domain_flush_complete(domain); |
5d8b53cf JR |
2207 | |
2208 | spin_unlock_irqrestore(&domain->lock, flags); | |
2209 | ||
2210 | free_mem: | |
2211 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2212 | } | |
2213 | ||
b39ba6ad JR |
2214 | /* |
2215 | * This function is called by the DMA layer to find out if we can handle a | |
2216 | * particular device. It is part of the dma_ops. | |
2217 | */ | |
2218 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2219 | { | |
420aef8a | 2220 | return check_device(dev); |
b39ba6ad JR |
2221 | } |
2222 | ||
c432f3df | 2223 | /* |
431b2a20 JR |
2224 | * The function for pre-allocating protection domains. |
2225 | * | |
c432f3df JR |
2226 | * If the driver core informs the DMA layer if a driver grabs a device |
2227 | * we don't need to preallocate the protection domains anymore. | |
2228 | * For now we have to. | |
2229 | */ | |
0e93dd88 | 2230 | static void prealloc_protection_domains(void) |
c432f3df JR |
2231 | { |
2232 | struct pci_dev *dev = NULL; | |
2233 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2234 | u16 devid; |
c432f3df | 2235 | |
d18c69d3 | 2236 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2237 | |
2238 | /* Do we handle this device? */ | |
2239 | if (!check_device(&dev->dev)) | |
c432f3df | 2240 | continue; |
98fc5a69 JR |
2241 | |
2242 | /* Is there already any domain for it? */ | |
15898bbc | 2243 | if (domain_for_device(&dev->dev)) |
c432f3df | 2244 | continue; |
98fc5a69 JR |
2245 | |
2246 | devid = get_device_id(&dev->dev); | |
2247 | ||
87a64d52 | 2248 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2249 | if (!dma_dom) |
2250 | continue; | |
2251 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2252 | dma_dom->target_dev = devid; |
2253 | ||
15898bbc | 2254 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2255 | |
bd60b735 | 2256 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2257 | } |
2258 | } | |
2259 | ||
160c1d8e | 2260 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2261 | .alloc_coherent = alloc_coherent, |
2262 | .free_coherent = free_coherent, | |
51491367 FT |
2263 | .map_page = map_page, |
2264 | .unmap_page = unmap_page, | |
6631ee9d JR |
2265 | .map_sg = map_sg, |
2266 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2267 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2268 | }; |
2269 | ||
431b2a20 JR |
2270 | /* |
2271 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2272 | */ | |
f5325094 JR |
2273 | |
2274 | void __init amd_iommu_init_api(void) | |
2275 | { | |
2276 | register_iommu(&amd_iommu_ops); | |
2277 | } | |
2278 | ||
6631ee9d JR |
2279 | int __init amd_iommu_init_dma_ops(void) |
2280 | { | |
2281 | struct amd_iommu *iommu; | |
6631ee9d JR |
2282 | int ret; |
2283 | ||
431b2a20 JR |
2284 | /* |
2285 | * first allocate a default protection domain for every IOMMU we | |
2286 | * found in the system. Devices not assigned to any other | |
2287 | * protection domain will be assigned to the default one. | |
2288 | */ | |
3bd22172 | 2289 | for_each_iommu(iommu) { |
87a64d52 | 2290 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2291 | if (iommu->default_dom == NULL) |
2292 | return -ENOMEM; | |
e2dc14a2 | 2293 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2294 | ret = iommu_init_unity_mappings(iommu); |
2295 | if (ret) | |
2296 | goto free_domains; | |
2297 | } | |
2298 | ||
431b2a20 | 2299 | /* |
8793abeb | 2300 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2301 | */ |
8793abeb | 2302 | prealloc_protection_domains(); |
6631ee9d JR |
2303 | |
2304 | iommu_detected = 1; | |
75f1cdf1 | 2305 | swiotlb = 0; |
6631ee9d | 2306 | |
431b2a20 | 2307 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2308 | dma_ops = &amd_iommu_dma_ops; |
2309 | ||
7f26508b JR |
2310 | amd_iommu_stats_init(); |
2311 | ||
6631ee9d JR |
2312 | return 0; |
2313 | ||
2314 | free_domains: | |
2315 | ||
3bd22172 | 2316 | for_each_iommu(iommu) { |
6631ee9d JR |
2317 | if (iommu->default_dom) |
2318 | dma_ops_domain_free(iommu->default_dom); | |
2319 | } | |
2320 | ||
2321 | return ret; | |
2322 | } | |
6d98cd80 JR |
2323 | |
2324 | /***************************************************************************** | |
2325 | * | |
2326 | * The following functions belong to the exported interface of AMD IOMMU | |
2327 | * | |
2328 | * This interface allows access to lower level functions of the IOMMU | |
2329 | * like protection domain handling and assignement of devices to domains | |
2330 | * which is not possible with the dma_ops interface. | |
2331 | * | |
2332 | *****************************************************************************/ | |
2333 | ||
6d98cd80 JR |
2334 | static void cleanup_domain(struct protection_domain *domain) |
2335 | { | |
492667da | 2336 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2337 | unsigned long flags; |
6d98cd80 JR |
2338 | |
2339 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2340 | ||
492667da JR |
2341 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2342 | struct device *dev = dev_data->dev; | |
2343 | ||
04e856c0 | 2344 | __detach_device(dev); |
492667da JR |
2345 | atomic_set(&dev_data->bind, 0); |
2346 | } | |
6d98cd80 JR |
2347 | |
2348 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2349 | } | |
2350 | ||
2650815f JR |
2351 | static void protection_domain_free(struct protection_domain *domain) |
2352 | { | |
2353 | if (!domain) | |
2354 | return; | |
2355 | ||
aeb26f55 JR |
2356 | del_domain_from_list(domain); |
2357 | ||
2650815f JR |
2358 | if (domain->id) |
2359 | domain_id_free(domain->id); | |
2360 | ||
2361 | kfree(domain); | |
2362 | } | |
2363 | ||
2364 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2365 | { |
2366 | struct protection_domain *domain; | |
2367 | ||
2368 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2369 | if (!domain) | |
2650815f | 2370 | return NULL; |
c156e347 JR |
2371 | |
2372 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2373 | mutex_init(&domain->api_lock); |
c156e347 JR |
2374 | domain->id = domain_id_alloc(); |
2375 | if (!domain->id) | |
2650815f | 2376 | goto out_err; |
7c392cbe | 2377 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2378 | |
aeb26f55 JR |
2379 | add_domain_to_list(domain); |
2380 | ||
2650815f JR |
2381 | return domain; |
2382 | ||
2383 | out_err: | |
2384 | kfree(domain); | |
2385 | ||
2386 | return NULL; | |
2387 | } | |
2388 | ||
2389 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2390 | { | |
2391 | struct protection_domain *domain; | |
2392 | ||
2393 | domain = protection_domain_alloc(); | |
2394 | if (!domain) | |
c156e347 | 2395 | goto out_free; |
2650815f JR |
2396 | |
2397 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2398 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2399 | if (!domain->pt_root) | |
2400 | goto out_free; | |
2401 | ||
2402 | dom->priv = domain; | |
2403 | ||
2404 | return 0; | |
2405 | ||
2406 | out_free: | |
2650815f | 2407 | protection_domain_free(domain); |
c156e347 JR |
2408 | |
2409 | return -ENOMEM; | |
2410 | } | |
2411 | ||
98383fc3 JR |
2412 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2413 | { | |
2414 | struct protection_domain *domain = dom->priv; | |
2415 | ||
2416 | if (!domain) | |
2417 | return; | |
2418 | ||
2419 | if (domain->dev_cnt > 0) | |
2420 | cleanup_domain(domain); | |
2421 | ||
2422 | BUG_ON(domain->dev_cnt != 0); | |
2423 | ||
2424 | free_pagetable(domain); | |
2425 | ||
8b408fe4 | 2426 | protection_domain_free(domain); |
98383fc3 JR |
2427 | |
2428 | dom->priv = NULL; | |
2429 | } | |
2430 | ||
684f2888 JR |
2431 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2432 | struct device *dev) | |
2433 | { | |
657cbb6b | 2434 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2435 | struct amd_iommu *iommu; |
684f2888 JR |
2436 | u16 devid; |
2437 | ||
98fc5a69 | 2438 | if (!check_device(dev)) |
684f2888 JR |
2439 | return; |
2440 | ||
98fc5a69 | 2441 | devid = get_device_id(dev); |
684f2888 | 2442 | |
657cbb6b | 2443 | if (dev_data->domain != NULL) |
15898bbc | 2444 | detach_device(dev); |
684f2888 JR |
2445 | |
2446 | iommu = amd_iommu_rlookup_table[devid]; | |
2447 | if (!iommu) | |
2448 | return; | |
2449 | ||
d8c13085 | 2450 | device_flush_dte(dev); |
684f2888 JR |
2451 | iommu_completion_wait(iommu); |
2452 | } | |
2453 | ||
01106066 JR |
2454 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2455 | struct device *dev) | |
2456 | { | |
2457 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2458 | struct iommu_dev_data *dev_data; |
01106066 | 2459 | struct amd_iommu *iommu; |
15898bbc | 2460 | int ret; |
01106066 JR |
2461 | u16 devid; |
2462 | ||
98fc5a69 | 2463 | if (!check_device(dev)) |
01106066 JR |
2464 | return -EINVAL; |
2465 | ||
657cbb6b JR |
2466 | dev_data = dev->archdata.iommu; |
2467 | ||
98fc5a69 | 2468 | devid = get_device_id(dev); |
01106066 JR |
2469 | |
2470 | iommu = amd_iommu_rlookup_table[devid]; | |
2471 | if (!iommu) | |
2472 | return -EINVAL; | |
2473 | ||
657cbb6b | 2474 | if (dev_data->domain) |
15898bbc | 2475 | detach_device(dev); |
01106066 | 2476 | |
15898bbc | 2477 | ret = attach_device(dev, domain); |
01106066 JR |
2478 | |
2479 | iommu_completion_wait(iommu); | |
2480 | ||
15898bbc | 2481 | return ret; |
01106066 JR |
2482 | } |
2483 | ||
468e2366 JR |
2484 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2485 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2486 | { |
468e2366 | 2487 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2488 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2489 | int prot = 0; |
2490 | int ret; | |
2491 | ||
2492 | if (iommu_prot & IOMMU_READ) | |
2493 | prot |= IOMMU_PROT_IR; | |
2494 | if (iommu_prot & IOMMU_WRITE) | |
2495 | prot |= IOMMU_PROT_IW; | |
2496 | ||
5d214fe6 | 2497 | mutex_lock(&domain->api_lock); |
795e74f7 | 2498 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2499 | mutex_unlock(&domain->api_lock); |
2500 | ||
795e74f7 | 2501 | return ret; |
c6229ca6 JR |
2502 | } |
2503 | ||
468e2366 JR |
2504 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2505 | int gfp_order) | |
eb74ff6c | 2506 | { |
eb74ff6c | 2507 | struct protection_domain *domain = dom->priv; |
468e2366 | 2508 | unsigned long page_size, unmap_size; |
eb74ff6c | 2509 | |
468e2366 | 2510 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2511 | |
5d214fe6 | 2512 | mutex_lock(&domain->api_lock); |
468e2366 | 2513 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2514 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2515 | |
17b124bf | 2516 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2517 | |
468e2366 | 2518 | return get_order(unmap_size); |
eb74ff6c JR |
2519 | } |
2520 | ||
645c4c8d JR |
2521 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2522 | unsigned long iova) | |
2523 | { | |
2524 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2525 | unsigned long offset_mask; |
645c4c8d | 2526 | phys_addr_t paddr; |
f03152bb | 2527 | u64 *pte, __pte; |
645c4c8d | 2528 | |
24cd7723 | 2529 | pte = fetch_pte(domain, iova); |
645c4c8d | 2530 | |
a6d41a40 | 2531 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2532 | return 0; |
2533 | ||
f03152bb JR |
2534 | if (PM_PTE_LEVEL(*pte) == 0) |
2535 | offset_mask = PAGE_SIZE - 1; | |
2536 | else | |
2537 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2538 | ||
2539 | __pte = *pte & PM_ADDR_MASK; | |
2540 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2541 | |
2542 | return paddr; | |
2543 | } | |
2544 | ||
dbb9fd86 SY |
2545 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2546 | unsigned long cap) | |
2547 | { | |
80a506b8 JR |
2548 | switch (cap) { |
2549 | case IOMMU_CAP_CACHE_COHERENCY: | |
2550 | return 1; | |
2551 | } | |
2552 | ||
dbb9fd86 SY |
2553 | return 0; |
2554 | } | |
2555 | ||
26961efe JR |
2556 | static struct iommu_ops amd_iommu_ops = { |
2557 | .domain_init = amd_iommu_domain_init, | |
2558 | .domain_destroy = amd_iommu_domain_destroy, | |
2559 | .attach_dev = amd_iommu_attach_device, | |
2560 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2561 | .map = amd_iommu_map, |
2562 | .unmap = amd_iommu_unmap, | |
26961efe | 2563 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2564 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2565 | }; |
2566 | ||
0feae533 JR |
2567 | /***************************************************************************** |
2568 | * | |
2569 | * The next functions do a basic initialization of IOMMU for pass through | |
2570 | * mode | |
2571 | * | |
2572 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2573 | * DMA-API translation. | |
2574 | * | |
2575 | *****************************************************************************/ | |
2576 | ||
2577 | int __init amd_iommu_init_passthrough(void) | |
2578 | { | |
15898bbc | 2579 | struct amd_iommu *iommu; |
0feae533 | 2580 | struct pci_dev *dev = NULL; |
15898bbc | 2581 | u16 devid; |
0feae533 | 2582 | |
af901ca1 | 2583 | /* allocate passthrough domain */ |
0feae533 JR |
2584 | pt_domain = protection_domain_alloc(); |
2585 | if (!pt_domain) | |
2586 | return -ENOMEM; | |
2587 | ||
2588 | pt_domain->mode |= PAGE_MODE_NONE; | |
2589 | ||
6c54aabd | 2590 | for_each_pci_dev(dev) { |
98fc5a69 | 2591 | if (!check_device(&dev->dev)) |
0feae533 JR |
2592 | continue; |
2593 | ||
98fc5a69 JR |
2594 | devid = get_device_id(&dev->dev); |
2595 | ||
15898bbc | 2596 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2597 | if (!iommu) |
2598 | continue; | |
2599 | ||
15898bbc | 2600 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2601 | } |
2602 | ||
2603 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2604 | ||
2605 | return 0; | |
2606 | } |