Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
26 | #include <asm/gart.h> | |
27 | #include <asm/amd_iommu_types.h> | |
c6da992e | 28 | #include <asm/amd_iommu.h> |
b6c02715 JR |
29 | |
30 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
31 | ||
32 | #define to_pages(addr, size) \ | |
33 | (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT) | |
34 | ||
136f78a1 JR |
35 | #define EXIT_LOOP_COUNT 10000000 |
36 | ||
b6c02715 JR |
37 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
38 | ||
431b2a20 JR |
39 | /* |
40 | * general struct to manage commands send to an IOMMU | |
41 | */ | |
d6449536 | 42 | struct iommu_cmd { |
b6c02715 JR |
43 | u32 data[4]; |
44 | }; | |
45 | ||
bd0e5211 JR |
46 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
47 | struct unity_map_entry *e); | |
48 | ||
431b2a20 | 49 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
50 | static int iommu_has_npcache(struct amd_iommu *iommu) |
51 | { | |
52 | return iommu->cap & IOMMU_CAP_NPCACHE; | |
53 | } | |
54 | ||
431b2a20 JR |
55 | /**************************************************************************** |
56 | * | |
57 | * IOMMU command queuing functions | |
58 | * | |
59 | ****************************************************************************/ | |
60 | ||
61 | /* | |
62 | * Writes the command to the IOMMUs command buffer and informs the | |
63 | * hardware about the new command. Must be called with iommu->lock held. | |
64 | */ | |
d6449536 | 65 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
66 | { |
67 | u32 tail, head; | |
68 | u8 *target; | |
69 | ||
70 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
71 | target = (iommu->cmd_buf + tail); | |
72 | memcpy_toio(target, cmd, sizeof(*cmd)); | |
73 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
74 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
75 | if (tail == head) | |
76 | return -ENOMEM; | |
77 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
431b2a20 JR |
82 | /* |
83 | * General queuing function for commands. Takes iommu->lock and calls | |
84 | * __iommu_queue_command(). | |
85 | */ | |
d6449536 | 86 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
87 | { |
88 | unsigned long flags; | |
89 | int ret; | |
90 | ||
91 | spin_lock_irqsave(&iommu->lock, flags); | |
92 | ret = __iommu_queue_command(iommu, cmd); | |
93 | spin_unlock_irqrestore(&iommu->lock, flags); | |
94 | ||
95 | return ret; | |
96 | } | |
97 | ||
431b2a20 JR |
98 | /* |
99 | * This function is called whenever we need to ensure that the IOMMU has | |
100 | * completed execution of all commands we sent. It sends a | |
101 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
102 | * us about that by writing a value to a physical address we pass with | |
103 | * the command. | |
104 | */ | |
a19ae1ec JR |
105 | static int iommu_completion_wait(struct amd_iommu *iommu) |
106 | { | |
107 | int ret; | |
d6449536 | 108 | struct iommu_cmd cmd; |
a19ae1ec JR |
109 | volatile u64 ready = 0; |
110 | unsigned long ready_phys = virt_to_phys(&ready); | |
136f78a1 | 111 | unsigned long i = 0; |
a19ae1ec JR |
112 | |
113 | memset(&cmd, 0, sizeof(cmd)); | |
114 | cmd.data[0] = LOW_U32(ready_phys) | CMD_COMPL_WAIT_STORE_MASK; | |
8ea80d78 | 115 | cmd.data[1] = upper_32_bits(ready_phys); |
a19ae1ec JR |
116 | cmd.data[2] = 1; /* value written to 'ready' */ |
117 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
118 | ||
119 | iommu->need_sync = 0; | |
120 | ||
121 | ret = iommu_queue_command(iommu, &cmd); | |
122 | ||
123 | if (ret) | |
124 | return ret; | |
125 | ||
136f78a1 JR |
126 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
127 | ++i; | |
a19ae1ec | 128 | cpu_relax(); |
136f78a1 JR |
129 | } |
130 | ||
131 | if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit())) | |
132 | printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n"); | |
a19ae1ec JR |
133 | |
134 | return 0; | |
135 | } | |
136 | ||
431b2a20 JR |
137 | /* |
138 | * Command send function for invalidating a device table entry | |
139 | */ | |
a19ae1ec JR |
140 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
141 | { | |
d6449536 | 142 | struct iommu_cmd cmd; |
a19ae1ec JR |
143 | |
144 | BUG_ON(iommu == NULL); | |
145 | ||
146 | memset(&cmd, 0, sizeof(cmd)); | |
147 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
148 | cmd.data[0] = devid; | |
149 | ||
150 | iommu->need_sync = 1; | |
151 | ||
152 | return iommu_queue_command(iommu, &cmd); | |
153 | } | |
154 | ||
431b2a20 JR |
155 | /* |
156 | * Generic command send function for invalidaing TLB entries | |
157 | */ | |
a19ae1ec JR |
158 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
159 | u64 address, u16 domid, int pde, int s) | |
160 | { | |
d6449536 | 161 | struct iommu_cmd cmd; |
a19ae1ec JR |
162 | |
163 | memset(&cmd, 0, sizeof(cmd)); | |
164 | address &= PAGE_MASK; | |
165 | CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES); | |
166 | cmd.data[1] |= domid; | |
167 | cmd.data[2] = LOW_U32(address); | |
8ea80d78 | 168 | cmd.data[3] = upper_32_bits(address); |
431b2a20 | 169 | if (s) /* size bit - we flush more than one 4kb page */ |
a19ae1ec | 170 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
431b2a20 | 171 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ |
a19ae1ec JR |
172 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
173 | ||
174 | iommu->need_sync = 1; | |
175 | ||
176 | return iommu_queue_command(iommu, &cmd); | |
177 | } | |
178 | ||
431b2a20 JR |
179 | /* |
180 | * TLB invalidation function which is called from the mapping functions. | |
181 | * It invalidates a single PTE if the range to flush is within a single | |
182 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
183 | */ | |
a19ae1ec JR |
184 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
185 | u64 address, size_t size) | |
186 | { | |
999ba417 | 187 | int s = 0; |
a19ae1ec JR |
188 | unsigned pages = to_pages(address, size); |
189 | ||
190 | address &= PAGE_MASK; | |
191 | ||
999ba417 JR |
192 | if (pages > 1) { |
193 | /* | |
194 | * If we have to flush more than one page, flush all | |
195 | * TLB entries for this domain | |
196 | */ | |
197 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
198 | s = 1; | |
a19ae1ec JR |
199 | } |
200 | ||
999ba417 JR |
201 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
202 | ||
a19ae1ec JR |
203 | return 0; |
204 | } | |
b6c02715 | 205 | |
431b2a20 JR |
206 | /**************************************************************************** |
207 | * | |
208 | * The functions below are used the create the page table mappings for | |
209 | * unity mapped regions. | |
210 | * | |
211 | ****************************************************************************/ | |
212 | ||
213 | /* | |
214 | * Generic mapping functions. It maps a physical address into a DMA | |
215 | * address space. It allocates the page table pages if necessary. | |
216 | * In the future it can be extended to a generic mapping function | |
217 | * supporting all features of AMD IOMMU page tables like level skipping | |
218 | * and full 64 bit address spaces. | |
219 | */ | |
bd0e5211 JR |
220 | static int iommu_map(struct protection_domain *dom, |
221 | unsigned long bus_addr, | |
222 | unsigned long phys_addr, | |
223 | int prot) | |
224 | { | |
225 | u64 __pte, *pte, *page; | |
226 | ||
227 | bus_addr = PAGE_ALIGN(bus_addr); | |
228 | phys_addr = PAGE_ALIGN(bus_addr); | |
229 | ||
230 | /* only support 512GB address spaces for now */ | |
231 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
232 | return -EINVAL; | |
233 | ||
234 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
235 | ||
236 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
237 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
238 | if (!page) | |
239 | return -ENOMEM; | |
240 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
241 | } | |
242 | ||
243 | pte = IOMMU_PTE_PAGE(*pte); | |
244 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
245 | ||
246 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
247 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
248 | if (!page) | |
249 | return -ENOMEM; | |
250 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
251 | } | |
252 | ||
253 | pte = IOMMU_PTE_PAGE(*pte); | |
254 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
255 | ||
256 | if (IOMMU_PTE_PRESENT(*pte)) | |
257 | return -EBUSY; | |
258 | ||
259 | __pte = phys_addr | IOMMU_PTE_P; | |
260 | if (prot & IOMMU_PROT_IR) | |
261 | __pte |= IOMMU_PTE_IR; | |
262 | if (prot & IOMMU_PROT_IW) | |
263 | __pte |= IOMMU_PTE_IW; | |
264 | ||
265 | *pte = __pte; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
431b2a20 JR |
270 | /* |
271 | * This function checks if a specific unity mapping entry is needed for | |
272 | * this specific IOMMU. | |
273 | */ | |
bd0e5211 JR |
274 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
275 | struct unity_map_entry *entry) | |
276 | { | |
277 | u16 bdf, i; | |
278 | ||
279 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
280 | bdf = amd_iommu_alias_table[i]; | |
281 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
282 | return 1; | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
431b2a20 JR |
288 | /* |
289 | * Init the unity mappings for a specific IOMMU in the system | |
290 | * | |
291 | * Basically iterates over all unity mapping entries and applies them to | |
292 | * the default domain DMA of that IOMMU if necessary. | |
293 | */ | |
bd0e5211 JR |
294 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
295 | { | |
296 | struct unity_map_entry *entry; | |
297 | int ret; | |
298 | ||
299 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
300 | if (!iommu_for_unity_map(iommu, entry)) | |
301 | continue; | |
302 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
303 | if (ret) | |
304 | return ret; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
431b2a20 JR |
310 | /* |
311 | * This function actually applies the mapping to the page table of the | |
312 | * dma_ops domain. | |
313 | */ | |
bd0e5211 JR |
314 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
315 | struct unity_map_entry *e) | |
316 | { | |
317 | u64 addr; | |
318 | int ret; | |
319 | ||
320 | for (addr = e->address_start; addr < e->address_end; | |
321 | addr += PAGE_SIZE) { | |
322 | ret = iommu_map(&dma_dom->domain, addr, addr, e->prot); | |
323 | if (ret) | |
324 | return ret; | |
325 | /* | |
326 | * if unity mapping is in aperture range mark the page | |
327 | * as allocated in the aperture | |
328 | */ | |
329 | if (addr < dma_dom->aperture_size) | |
330 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
331 | } | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
431b2a20 JR |
336 | /* |
337 | * Inits the unity mappings required for a specific device | |
338 | */ | |
bd0e5211 JR |
339 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
340 | u16 devid) | |
341 | { | |
342 | struct unity_map_entry *e; | |
343 | int ret; | |
344 | ||
345 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
346 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
347 | continue; | |
348 | ret = dma_ops_unity_map(dma_dom, e); | |
349 | if (ret) | |
350 | return ret; | |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
431b2a20 JR |
356 | /**************************************************************************** |
357 | * | |
358 | * The next functions belong to the address allocator for the dma_ops | |
359 | * interface functions. They work like the allocators in the other IOMMU | |
360 | * drivers. Its basically a bitmap which marks the allocated pages in | |
361 | * the aperture. Maybe it could be enhanced in the future to a more | |
362 | * efficient allocator. | |
363 | * | |
364 | ****************************************************************************/ | |
d3086444 JR |
365 | static unsigned long dma_mask_to_pages(unsigned long mask) |
366 | { | |
367 | return (mask >> PAGE_SHIFT) + | |
368 | (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT); | |
369 | } | |
370 | ||
431b2a20 JR |
371 | /* |
372 | * The address allocator core function. | |
373 | * | |
374 | * called with domain->lock held | |
375 | */ | |
d3086444 JR |
376 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
377 | struct dma_ops_domain *dom, | |
378 | unsigned int pages) | |
379 | { | |
380 | unsigned long limit = dma_mask_to_pages(*dev->dma_mask); | |
381 | unsigned long address; | |
382 | unsigned long size = dom->aperture_size >> PAGE_SHIFT; | |
383 | unsigned long boundary_size; | |
384 | ||
385 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
386 | PAGE_SIZE) >> PAGE_SHIFT; | |
387 | limit = limit < size ? limit : size; | |
388 | ||
389 | if (dom->next_bit >= limit) | |
390 | dom->next_bit = 0; | |
391 | ||
392 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
393 | 0 , boundary_size, 0); | |
394 | if (address == -1) | |
395 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, | |
396 | 0, boundary_size, 0); | |
397 | ||
398 | if (likely(address != -1)) { | |
d3086444 JR |
399 | dom->next_bit = address + pages; |
400 | address <<= PAGE_SHIFT; | |
401 | } else | |
402 | address = bad_dma_address; | |
403 | ||
404 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
405 | ||
406 | return address; | |
407 | } | |
408 | ||
431b2a20 JR |
409 | /* |
410 | * The address free function. | |
411 | * | |
412 | * called with domain->lock held | |
413 | */ | |
d3086444 JR |
414 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
415 | unsigned long address, | |
416 | unsigned int pages) | |
417 | { | |
418 | address >>= PAGE_SHIFT; | |
419 | iommu_area_free(dom->bitmap, address, pages); | |
420 | } | |
421 | ||
431b2a20 JR |
422 | /**************************************************************************** |
423 | * | |
424 | * The next functions belong to the domain allocation. A domain is | |
425 | * allocated for every IOMMU as the default domain. If device isolation | |
426 | * is enabled, every device get its own domain. The most important thing | |
427 | * about domains is the page table mapping the DMA address space they | |
428 | * contain. | |
429 | * | |
430 | ****************************************************************************/ | |
431 | ||
ec487d1a JR |
432 | static u16 domain_id_alloc(void) |
433 | { | |
434 | unsigned long flags; | |
435 | int id; | |
436 | ||
437 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
438 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
439 | BUG_ON(id == 0); | |
440 | if (id > 0 && id < MAX_DOMAIN_ID) | |
441 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
442 | else | |
443 | id = 0; | |
444 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
445 | ||
446 | return id; | |
447 | } | |
448 | ||
431b2a20 JR |
449 | /* |
450 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
451 | * ranges. | |
452 | */ | |
ec487d1a JR |
453 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
454 | unsigned long start_page, | |
455 | unsigned int pages) | |
456 | { | |
457 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
458 | ||
459 | if (start_page + pages > last_page) | |
460 | pages = last_page - start_page; | |
461 | ||
462 | set_bit_string(dom->bitmap, start_page, pages); | |
463 | } | |
464 | ||
465 | static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom) | |
466 | { | |
467 | int i, j; | |
468 | u64 *p1, *p2, *p3; | |
469 | ||
470 | p1 = dma_dom->domain.pt_root; | |
471 | ||
472 | if (!p1) | |
473 | return; | |
474 | ||
475 | for (i = 0; i < 512; ++i) { | |
476 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
477 | continue; | |
478 | ||
479 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
480 | for (j = 0; j < 512; ++i) { | |
481 | if (!IOMMU_PTE_PRESENT(p2[j])) | |
482 | continue; | |
483 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
484 | free_page((unsigned long)p3); | |
485 | } | |
486 | ||
487 | free_page((unsigned long)p2); | |
488 | } | |
489 | ||
490 | free_page((unsigned long)p1); | |
491 | } | |
492 | ||
431b2a20 JR |
493 | /* |
494 | * Free a domain, only used if something went wrong in the | |
495 | * allocation path and we need to free an already allocated page table | |
496 | */ | |
ec487d1a JR |
497 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
498 | { | |
499 | if (!dom) | |
500 | return; | |
501 | ||
502 | dma_ops_free_pagetable(dom); | |
503 | ||
504 | kfree(dom->pte_pages); | |
505 | ||
506 | kfree(dom->bitmap); | |
507 | ||
508 | kfree(dom); | |
509 | } | |
510 | ||
431b2a20 JR |
511 | /* |
512 | * Allocates a new protection domain usable for the dma_ops functions. | |
513 | * It also intializes the page table and the address allocator data | |
514 | * structures required for the dma_ops interface | |
515 | */ | |
ec487d1a JR |
516 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
517 | unsigned order) | |
518 | { | |
519 | struct dma_ops_domain *dma_dom; | |
520 | unsigned i, num_pte_pages; | |
521 | u64 *l2_pde; | |
522 | u64 address; | |
523 | ||
524 | /* | |
525 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
526 | */ | |
527 | if ((order < 25) || (order > 30)) | |
528 | return NULL; | |
529 | ||
530 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
531 | if (!dma_dom) | |
532 | return NULL; | |
533 | ||
534 | spin_lock_init(&dma_dom->domain.lock); | |
535 | ||
536 | dma_dom->domain.id = domain_id_alloc(); | |
537 | if (dma_dom->domain.id == 0) | |
538 | goto free_dma_dom; | |
539 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
540 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
541 | dma_dom->domain.priv = dma_dom; | |
542 | if (!dma_dom->domain.pt_root) | |
543 | goto free_dma_dom; | |
544 | dma_dom->aperture_size = (1ULL << order); | |
545 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
546 | GFP_KERNEL); | |
547 | if (!dma_dom->bitmap) | |
548 | goto free_dma_dom; | |
549 | /* | |
550 | * mark the first page as allocated so we never return 0 as | |
551 | * a valid dma-address. So we can use 0 as error value | |
552 | */ | |
553 | dma_dom->bitmap[0] = 1; | |
554 | dma_dom->next_bit = 0; | |
555 | ||
431b2a20 | 556 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
557 | if (iommu->exclusion_start && |
558 | iommu->exclusion_start < dma_dom->aperture_size) { | |
559 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
560 | int pages = to_pages(iommu->exclusion_start, | |
561 | iommu->exclusion_length); | |
562 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
563 | } | |
564 | ||
431b2a20 JR |
565 | /* |
566 | * At the last step, build the page tables so we don't need to | |
567 | * allocate page table pages in the dma_ops mapping/unmapping | |
568 | * path. | |
569 | */ | |
ec487d1a JR |
570 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
571 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
572 | GFP_KERNEL); | |
573 | if (!dma_dom->pte_pages) | |
574 | goto free_dma_dom; | |
575 | ||
576 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
577 | if (l2_pde == NULL) | |
578 | goto free_dma_dom; | |
579 | ||
580 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
581 | ||
582 | for (i = 0; i < num_pte_pages; ++i) { | |
583 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
584 | if (!dma_dom->pte_pages[i]) | |
585 | goto free_dma_dom; | |
586 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
587 | l2_pde[i] = IOMMU_L1_PDE(address); | |
588 | } | |
589 | ||
590 | return dma_dom; | |
591 | ||
592 | free_dma_dom: | |
593 | dma_ops_domain_free(dma_dom); | |
594 | ||
595 | return NULL; | |
596 | } | |
597 | ||
431b2a20 JR |
598 | /* |
599 | * Find out the protection domain structure for a given PCI device. This | |
600 | * will give us the pointer to the page table root for example. | |
601 | */ | |
b20ac0d4 JR |
602 | static struct protection_domain *domain_for_device(u16 devid) |
603 | { | |
604 | struct protection_domain *dom; | |
605 | unsigned long flags; | |
606 | ||
607 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
608 | dom = amd_iommu_pd_table[devid]; | |
609 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
610 | ||
611 | return dom; | |
612 | } | |
613 | ||
431b2a20 JR |
614 | /* |
615 | * If a device is not yet associated with a domain, this function does | |
616 | * assigns it visible for the hardware | |
617 | */ | |
b20ac0d4 JR |
618 | static void set_device_domain(struct amd_iommu *iommu, |
619 | struct protection_domain *domain, | |
620 | u16 devid) | |
621 | { | |
622 | unsigned long flags; | |
623 | ||
624 | u64 pte_root = virt_to_phys(domain->pt_root); | |
625 | ||
626 | pte_root |= (domain->mode & 0x07) << 9; | |
627 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2; | |
628 | ||
629 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
630 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
631 | amd_iommu_dev_table[devid].data[1] = pte_root >> 32; | |
632 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
633 | ||
634 | amd_iommu_pd_table[devid] = domain; | |
635 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
636 | ||
637 | iommu_queue_inv_dev_entry(iommu, devid); | |
638 | ||
639 | iommu->need_sync = 1; | |
640 | } | |
641 | ||
431b2a20 JR |
642 | /***************************************************************************** |
643 | * | |
644 | * The next functions belong to the dma_ops mapping/unmapping code. | |
645 | * | |
646 | *****************************************************************************/ | |
647 | ||
648 | /* | |
649 | * In the dma_ops path we only have the struct device. This function | |
650 | * finds the corresponding IOMMU, the protection domain and the | |
651 | * requestor id for a given device. | |
652 | * If the device is not yet associated with a domain this is also done | |
653 | * in this function. | |
654 | */ | |
b20ac0d4 JR |
655 | static int get_device_resources(struct device *dev, |
656 | struct amd_iommu **iommu, | |
657 | struct protection_domain **domain, | |
658 | u16 *bdf) | |
659 | { | |
660 | struct dma_ops_domain *dma_dom; | |
661 | struct pci_dev *pcidev; | |
662 | u16 _bdf; | |
663 | ||
664 | BUG_ON(!dev || dev->bus != &pci_bus_type || !dev->dma_mask); | |
665 | ||
666 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 667 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 668 | |
431b2a20 | 669 | /* device not translated by any IOMMU in the system? */ |
b20ac0d4 JR |
670 | if (_bdf >= amd_iommu_last_bdf) { |
671 | *iommu = NULL; | |
672 | *domain = NULL; | |
673 | *bdf = 0xffff; | |
674 | return 0; | |
675 | } | |
676 | ||
677 | *bdf = amd_iommu_alias_table[_bdf]; | |
678 | ||
679 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
680 | if (*iommu == NULL) | |
681 | return 0; | |
682 | dma_dom = (*iommu)->default_dom; | |
683 | *domain = domain_for_device(*bdf); | |
684 | if (*domain == NULL) { | |
685 | *domain = &dma_dom->domain; | |
686 | set_device_domain(*iommu, *domain, *bdf); | |
687 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
688 | "device ", (*domain)->id); | |
689 | print_devid(_bdf, 1); | |
690 | } | |
691 | ||
692 | return 1; | |
693 | } | |
694 | ||
431b2a20 JR |
695 | /* |
696 | * This is the generic map function. It maps one 4kb page at paddr to | |
697 | * the given address in the DMA address space for the domain. | |
698 | */ | |
cb76c322 JR |
699 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
700 | struct dma_ops_domain *dom, | |
701 | unsigned long address, | |
702 | phys_addr_t paddr, | |
703 | int direction) | |
704 | { | |
705 | u64 *pte, __pte; | |
706 | ||
707 | WARN_ON(address > dom->aperture_size); | |
708 | ||
709 | paddr &= PAGE_MASK; | |
710 | ||
711 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
712 | pte += IOMMU_PTE_L0_INDEX(address); | |
713 | ||
714 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
715 | ||
716 | if (direction == DMA_TO_DEVICE) | |
717 | __pte |= IOMMU_PTE_IR; | |
718 | else if (direction == DMA_FROM_DEVICE) | |
719 | __pte |= IOMMU_PTE_IW; | |
720 | else if (direction == DMA_BIDIRECTIONAL) | |
721 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
722 | ||
723 | WARN_ON(*pte); | |
724 | ||
725 | *pte = __pte; | |
726 | ||
727 | return (dma_addr_t)address; | |
728 | } | |
729 | ||
431b2a20 JR |
730 | /* |
731 | * The generic unmapping function for on page in the DMA address space. | |
732 | */ | |
cb76c322 JR |
733 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
734 | struct dma_ops_domain *dom, | |
735 | unsigned long address) | |
736 | { | |
737 | u64 *pte; | |
738 | ||
739 | if (address >= dom->aperture_size) | |
740 | return; | |
741 | ||
742 | WARN_ON(address & 0xfffULL || address > dom->aperture_size); | |
743 | ||
744 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
745 | pte += IOMMU_PTE_L0_INDEX(address); | |
746 | ||
747 | WARN_ON(!*pte); | |
748 | ||
749 | *pte = 0ULL; | |
750 | } | |
751 | ||
431b2a20 JR |
752 | /* |
753 | * This function contains common code for mapping of a physically | |
754 | * contiguous memory region into DMA address space. It is uses by all | |
755 | * mapping functions provided by this IOMMU driver. | |
756 | * Must be called with the domain lock held. | |
757 | */ | |
cb76c322 JR |
758 | static dma_addr_t __map_single(struct device *dev, |
759 | struct amd_iommu *iommu, | |
760 | struct dma_ops_domain *dma_dom, | |
761 | phys_addr_t paddr, | |
762 | size_t size, | |
763 | int dir) | |
764 | { | |
765 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
766 | dma_addr_t address, start; | |
767 | unsigned int pages; | |
768 | int i; | |
769 | ||
770 | pages = to_pages(paddr, size); | |
771 | paddr &= PAGE_MASK; | |
772 | ||
773 | address = dma_ops_alloc_addresses(dev, dma_dom, pages); | |
774 | if (unlikely(address == bad_dma_address)) | |
775 | goto out; | |
776 | ||
777 | start = address; | |
778 | for (i = 0; i < pages; ++i) { | |
779 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
780 | paddr += PAGE_SIZE; | |
781 | start += PAGE_SIZE; | |
782 | } | |
783 | address += offset; | |
784 | ||
785 | out: | |
786 | return address; | |
787 | } | |
788 | ||
431b2a20 JR |
789 | /* |
790 | * Does the reverse of the __map_single function. Must be called with | |
791 | * the domain lock held too | |
792 | */ | |
cb76c322 JR |
793 | static void __unmap_single(struct amd_iommu *iommu, |
794 | struct dma_ops_domain *dma_dom, | |
795 | dma_addr_t dma_addr, | |
796 | size_t size, | |
797 | int dir) | |
798 | { | |
799 | dma_addr_t i, start; | |
800 | unsigned int pages; | |
801 | ||
802 | if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) | |
803 | return; | |
804 | ||
805 | pages = to_pages(dma_addr, size); | |
806 | dma_addr &= PAGE_MASK; | |
807 | start = dma_addr; | |
808 | ||
809 | for (i = 0; i < pages; ++i) { | |
810 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
811 | start += PAGE_SIZE; | |
812 | } | |
813 | ||
814 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
815 | } | |
816 | ||
431b2a20 JR |
817 | /* |
818 | * The exported map_single function for dma_ops. | |
819 | */ | |
4da70b9e JR |
820 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
821 | size_t size, int dir) | |
822 | { | |
823 | unsigned long flags; | |
824 | struct amd_iommu *iommu; | |
825 | struct protection_domain *domain; | |
826 | u16 devid; | |
827 | dma_addr_t addr; | |
828 | ||
829 | get_device_resources(dev, &iommu, &domain, &devid); | |
830 | ||
831 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 832 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
833 | return (dma_addr_t)paddr; |
834 | ||
835 | spin_lock_irqsave(&domain->lock, flags); | |
836 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir); | |
837 | if (addr == bad_dma_address) | |
838 | goto out; | |
839 | ||
840 | if (iommu_has_npcache(iommu)) | |
841 | iommu_flush_pages(iommu, domain->id, addr, size); | |
842 | ||
843 | if (iommu->need_sync) | |
844 | iommu_completion_wait(iommu); | |
845 | ||
846 | out: | |
847 | spin_unlock_irqrestore(&domain->lock, flags); | |
848 | ||
849 | return addr; | |
850 | } | |
851 | ||
431b2a20 JR |
852 | /* |
853 | * The exported unmap_single function for dma_ops. | |
854 | */ | |
4da70b9e JR |
855 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
856 | size_t size, int dir) | |
857 | { | |
858 | unsigned long flags; | |
859 | struct amd_iommu *iommu; | |
860 | struct protection_domain *domain; | |
861 | u16 devid; | |
862 | ||
863 | if (!get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 864 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
865 | return; |
866 | ||
867 | spin_lock_irqsave(&domain->lock, flags); | |
868 | ||
869 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
870 | ||
871 | iommu_flush_pages(iommu, domain->id, dma_addr, size); | |
872 | ||
873 | if (iommu->need_sync) | |
874 | iommu_completion_wait(iommu); | |
875 | ||
876 | spin_unlock_irqrestore(&domain->lock, flags); | |
877 | } | |
878 | ||
431b2a20 JR |
879 | /* |
880 | * This is a special map_sg function which is used if we should map a | |
881 | * device which is not handled by an AMD IOMMU in the system. | |
882 | */ | |
65b050ad JR |
883 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
884 | int nelems, int dir) | |
885 | { | |
886 | struct scatterlist *s; | |
887 | int i; | |
888 | ||
889 | for_each_sg(sglist, s, nelems, i) { | |
890 | s->dma_address = (dma_addr_t)sg_phys(s); | |
891 | s->dma_length = s->length; | |
892 | } | |
893 | ||
894 | return nelems; | |
895 | } | |
896 | ||
431b2a20 JR |
897 | /* |
898 | * The exported map_sg function for dma_ops (handles scatter-gather | |
899 | * lists). | |
900 | */ | |
65b050ad JR |
901 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
902 | int nelems, int dir) | |
903 | { | |
904 | unsigned long flags; | |
905 | struct amd_iommu *iommu; | |
906 | struct protection_domain *domain; | |
907 | u16 devid; | |
908 | int i; | |
909 | struct scatterlist *s; | |
910 | phys_addr_t paddr; | |
911 | int mapped_elems = 0; | |
912 | ||
913 | get_device_resources(dev, &iommu, &domain, &devid); | |
914 | ||
915 | if (!iommu || !domain) | |
916 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
917 | ||
918 | spin_lock_irqsave(&domain->lock, flags); | |
919 | ||
920 | for_each_sg(sglist, s, nelems, i) { | |
921 | paddr = sg_phys(s); | |
922 | ||
923 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
924 | paddr, s->length, dir); | |
925 | ||
926 | if (s->dma_address) { | |
927 | s->dma_length = s->length; | |
928 | mapped_elems++; | |
929 | } else | |
930 | goto unmap; | |
931 | if (iommu_has_npcache(iommu)) | |
932 | iommu_flush_pages(iommu, domain->id, s->dma_address, | |
933 | s->dma_length); | |
934 | } | |
935 | ||
936 | if (iommu->need_sync) | |
937 | iommu_completion_wait(iommu); | |
938 | ||
939 | out: | |
940 | spin_unlock_irqrestore(&domain->lock, flags); | |
941 | ||
942 | return mapped_elems; | |
943 | unmap: | |
944 | for_each_sg(sglist, s, mapped_elems, i) { | |
945 | if (s->dma_address) | |
946 | __unmap_single(iommu, domain->priv, s->dma_address, | |
947 | s->dma_length, dir); | |
948 | s->dma_address = s->dma_length = 0; | |
949 | } | |
950 | ||
951 | mapped_elems = 0; | |
952 | ||
953 | goto out; | |
954 | } | |
955 | ||
431b2a20 JR |
956 | /* |
957 | * The exported map_sg function for dma_ops (handles scatter-gather | |
958 | * lists). | |
959 | */ | |
65b050ad JR |
960 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
961 | int nelems, int dir) | |
962 | { | |
963 | unsigned long flags; | |
964 | struct amd_iommu *iommu; | |
965 | struct protection_domain *domain; | |
966 | struct scatterlist *s; | |
967 | u16 devid; | |
968 | int i; | |
969 | ||
970 | if (!get_device_resources(dev, &iommu, &domain, &devid)) | |
971 | return; | |
972 | ||
973 | spin_lock_irqsave(&domain->lock, flags); | |
974 | ||
975 | for_each_sg(sglist, s, nelems, i) { | |
976 | __unmap_single(iommu, domain->priv, s->dma_address, | |
977 | s->dma_length, dir); | |
978 | iommu_flush_pages(iommu, domain->id, s->dma_address, | |
979 | s->dma_length); | |
980 | s->dma_address = s->dma_length = 0; | |
981 | } | |
982 | ||
983 | if (iommu->need_sync) | |
984 | iommu_completion_wait(iommu); | |
985 | ||
986 | spin_unlock_irqrestore(&domain->lock, flags); | |
987 | } | |
988 | ||
431b2a20 JR |
989 | /* |
990 | * The exported alloc_coherent function for dma_ops. | |
991 | */ | |
5d8b53cf JR |
992 | static void *alloc_coherent(struct device *dev, size_t size, |
993 | dma_addr_t *dma_addr, gfp_t flag) | |
994 | { | |
995 | unsigned long flags; | |
996 | void *virt_addr; | |
997 | struct amd_iommu *iommu; | |
998 | struct protection_domain *domain; | |
999 | u16 devid; | |
1000 | phys_addr_t paddr; | |
1001 | ||
1002 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
1003 | if (!virt_addr) | |
1004 | return 0; | |
1005 | ||
1006 | memset(virt_addr, 0, size); | |
1007 | paddr = virt_to_phys(virt_addr); | |
1008 | ||
1009 | get_device_resources(dev, &iommu, &domain, &devid); | |
1010 | ||
1011 | if (!iommu || !domain) { | |
1012 | *dma_addr = (dma_addr_t)paddr; | |
1013 | return virt_addr; | |
1014 | } | |
1015 | ||
1016 | spin_lock_irqsave(&domain->lock, flags); | |
1017 | ||
1018 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
1019 | size, DMA_BIDIRECTIONAL); | |
1020 | ||
1021 | if (*dma_addr == bad_dma_address) { | |
1022 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1023 | virt_addr = NULL; | |
1024 | goto out; | |
1025 | } | |
1026 | ||
1027 | if (iommu_has_npcache(iommu)) | |
1028 | iommu_flush_pages(iommu, domain->id, *dma_addr, size); | |
1029 | ||
1030 | if (iommu->need_sync) | |
1031 | iommu_completion_wait(iommu); | |
1032 | ||
1033 | out: | |
1034 | spin_unlock_irqrestore(&domain->lock, flags); | |
1035 | ||
1036 | return virt_addr; | |
1037 | } | |
1038 | ||
431b2a20 JR |
1039 | /* |
1040 | * The exported free_coherent function for dma_ops. | |
1041 | * FIXME: fix the generic x86 DMA layer so that it actually calls that | |
1042 | * function. | |
1043 | */ | |
5d8b53cf JR |
1044 | static void free_coherent(struct device *dev, size_t size, |
1045 | void *virt_addr, dma_addr_t dma_addr) | |
1046 | { | |
1047 | unsigned long flags; | |
1048 | struct amd_iommu *iommu; | |
1049 | struct protection_domain *domain; | |
1050 | u16 devid; | |
1051 | ||
1052 | get_device_resources(dev, &iommu, &domain, &devid); | |
1053 | ||
1054 | if (!iommu || !domain) | |
1055 | goto free_mem; | |
1056 | ||
1057 | spin_lock_irqsave(&domain->lock, flags); | |
1058 | ||
1059 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
1060 | iommu_flush_pages(iommu, domain->id, dma_addr, size); | |
1061 | ||
1062 | if (iommu->need_sync) | |
1063 | iommu_completion_wait(iommu); | |
1064 | ||
1065 | spin_unlock_irqrestore(&domain->lock, flags); | |
1066 | ||
1067 | free_mem: | |
1068 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1069 | } | |
1070 | ||
c432f3df | 1071 | /* |
431b2a20 JR |
1072 | * The function for pre-allocating protection domains. |
1073 | * | |
c432f3df JR |
1074 | * If the driver core informs the DMA layer if a driver grabs a device |
1075 | * we don't need to preallocate the protection domains anymore. | |
1076 | * For now we have to. | |
1077 | */ | |
1078 | void prealloc_protection_domains(void) | |
1079 | { | |
1080 | struct pci_dev *dev = NULL; | |
1081 | struct dma_ops_domain *dma_dom; | |
1082 | struct amd_iommu *iommu; | |
1083 | int order = amd_iommu_aperture_order; | |
1084 | u16 devid; | |
1085 | ||
1086 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1087 | devid = (dev->bus->number << 8) | dev->devfn; | |
1088 | if (devid >= amd_iommu_last_bdf) | |
1089 | continue; | |
1090 | devid = amd_iommu_alias_table[devid]; | |
1091 | if (domain_for_device(devid)) | |
1092 | continue; | |
1093 | iommu = amd_iommu_rlookup_table[devid]; | |
1094 | if (!iommu) | |
1095 | continue; | |
1096 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1097 | if (!dma_dom) | |
1098 | continue; | |
1099 | init_unity_mappings_for_device(dma_dom, devid); | |
1100 | set_device_domain(iommu, &dma_dom->domain, devid); | |
1101 | printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ", | |
1102 | dma_dom->domain.id); | |
1103 | print_devid(devid, 1); | |
1104 | } | |
1105 | } | |
1106 | ||
6631ee9d JR |
1107 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1108 | .alloc_coherent = alloc_coherent, | |
1109 | .free_coherent = free_coherent, | |
1110 | .map_single = map_single, | |
1111 | .unmap_single = unmap_single, | |
1112 | .map_sg = map_sg, | |
1113 | .unmap_sg = unmap_sg, | |
1114 | }; | |
1115 | ||
431b2a20 JR |
1116 | /* |
1117 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1118 | */ | |
6631ee9d JR |
1119 | int __init amd_iommu_init_dma_ops(void) |
1120 | { | |
1121 | struct amd_iommu *iommu; | |
1122 | int order = amd_iommu_aperture_order; | |
1123 | int ret; | |
1124 | ||
431b2a20 JR |
1125 | /* |
1126 | * first allocate a default protection domain for every IOMMU we | |
1127 | * found in the system. Devices not assigned to any other | |
1128 | * protection domain will be assigned to the default one. | |
1129 | */ | |
6631ee9d JR |
1130 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1131 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1132 | if (iommu->default_dom == NULL) | |
1133 | return -ENOMEM; | |
1134 | ret = iommu_init_unity_mappings(iommu); | |
1135 | if (ret) | |
1136 | goto free_domains; | |
1137 | } | |
1138 | ||
431b2a20 JR |
1139 | /* |
1140 | * If device isolation is enabled, pre-allocate the protection | |
1141 | * domains for each device. | |
1142 | */ | |
6631ee9d JR |
1143 | if (amd_iommu_isolate) |
1144 | prealloc_protection_domains(); | |
1145 | ||
1146 | iommu_detected = 1; | |
1147 | force_iommu = 1; | |
1148 | bad_dma_address = 0; | |
92af4e29 | 1149 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1150 | gart_iommu_aperture_disabled = 1; |
1151 | gart_iommu_aperture = 0; | |
92af4e29 | 1152 | #endif |
6631ee9d | 1153 | |
431b2a20 | 1154 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1155 | dma_ops = &amd_iommu_dma_ops; |
1156 | ||
1157 | return 0; | |
1158 | ||
1159 | free_domains: | |
1160 | ||
1161 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1162 | if (iommu->default_dom) | |
1163 | dma_ops_domain_free(iommu->default_dom); | |
1164 | } | |
1165 | ||
1166 | return ret; | |
1167 | } |