Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
bd0e5211 JR |
60 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
61 | struct unity_map_entry *e); | |
e275a2a0 | 62 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bc3e127 | 63 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
64 | unsigned long address, int end_lvl, |
65 | u64 **pte_page, gfp_t gfp); | |
00cd122a JR |
66 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
67 | unsigned long start_page, | |
68 | unsigned int pages); | |
a345b23b | 69 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
9355a081 | 70 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 71 | unsigned long address, int map_size); |
04bfdd84 | 72 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 73 | |
7f26508b JR |
74 | #ifdef CONFIG_AMD_IOMMU_STATS |
75 | ||
76 | /* | |
77 | * Initialization code for statistics collection | |
78 | */ | |
79 | ||
da49f6df | 80 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 81 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 82 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 83 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 84 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 85 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 86 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 87 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 88 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 89 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 90 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 91 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 92 | |
7f26508b JR |
93 | static struct dentry *stats_dir; |
94 | static struct dentry *de_isolate; | |
95 | static struct dentry *de_fflush; | |
96 | ||
97 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
98 | { | |
99 | if (stats_dir == NULL) | |
100 | return; | |
101 | ||
102 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
103 | &cnt->value); | |
104 | } | |
105 | ||
106 | static void amd_iommu_stats_init(void) | |
107 | { | |
108 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
109 | if (stats_dir == NULL) | |
110 | return; | |
111 | ||
112 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
113 | (u32 *)&amd_iommu_isolate); | |
114 | ||
115 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
116 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
117 | |
118 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 119 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 120 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 121 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 122 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 123 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 124 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 125 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 126 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 127 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 128 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 129 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
130 | } |
131 | ||
132 | #endif | |
133 | ||
431b2a20 | 134 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
135 | static int iommu_has_npcache(struct amd_iommu *iommu) |
136 | { | |
ae9b9403 | 137 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
138 | } |
139 | ||
a80dc3e0 JR |
140 | /**************************************************************************** |
141 | * | |
142 | * Interrupt handling functions | |
143 | * | |
144 | ****************************************************************************/ | |
145 | ||
e3e59876 JR |
146 | static void dump_dte_entry(u16 devid) |
147 | { | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < 8; ++i) | |
151 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
152 | amd_iommu_dev_table[devid].data[i]); | |
153 | } | |
154 | ||
945b4ac4 JR |
155 | static void dump_command(unsigned long phys_addr) |
156 | { | |
157 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
158 | int i; | |
159 | ||
160 | for (i = 0; i < 4; ++i) | |
161 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
162 | } | |
163 | ||
a345b23b | 164 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
165 | { |
166 | u32 *event = __evt; | |
167 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
168 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
169 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
170 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
171 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
172 | ||
4c6f40d4 | 173 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
174 | |
175 | switch (type) { | |
176 | case EVENT_TYPE_ILL_DEV: | |
177 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
178 | "address=0x%016llx flags=0x%04x]\n", | |
179 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
180 | address, flags); | |
e3e59876 | 181 | dump_dte_entry(devid); |
90008ee4 JR |
182 | break; |
183 | case EVENT_TYPE_IO_FAULT: | |
184 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
185 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
186 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
187 | domid, address, flags); | |
188 | break; | |
189 | case EVENT_TYPE_DEV_TAB_ERR: | |
190 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
191 | "address=0x%016llx flags=0x%04x]\n", | |
192 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
193 | address, flags); | |
194 | break; | |
195 | case EVENT_TYPE_PAGE_TAB_ERR: | |
196 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
197 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
198 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
199 | domid, address, flags); | |
200 | break; | |
201 | case EVENT_TYPE_ILL_CMD: | |
202 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 203 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 204 | dump_command(address); |
90008ee4 JR |
205 | break; |
206 | case EVENT_TYPE_CMD_HARD_ERR: | |
207 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
208 | "flags=0x%04x]\n", address, flags); | |
209 | break; | |
210 | case EVENT_TYPE_IOTLB_INV_TO: | |
211 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
212 | "address=0x%016llx]\n", | |
213 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
214 | address); | |
215 | break; | |
216 | case EVENT_TYPE_INV_DEV_REQ: | |
217 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
218 | "address=0x%016llx flags=0x%04x]\n", | |
219 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
220 | address, flags); | |
221 | break; | |
222 | default: | |
223 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
224 | } | |
225 | } | |
226 | ||
227 | static void iommu_poll_events(struct amd_iommu *iommu) | |
228 | { | |
229 | u32 head, tail; | |
230 | unsigned long flags; | |
231 | ||
232 | spin_lock_irqsave(&iommu->lock, flags); | |
233 | ||
234 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
235 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
236 | ||
237 | while (head != tail) { | |
a345b23b | 238 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
239 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
240 | } | |
241 | ||
242 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
243 | ||
244 | spin_unlock_irqrestore(&iommu->lock, flags); | |
245 | } | |
246 | ||
a80dc3e0 JR |
247 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
248 | { | |
90008ee4 JR |
249 | struct amd_iommu *iommu; |
250 | ||
3bd22172 | 251 | for_each_iommu(iommu) |
90008ee4 JR |
252 | iommu_poll_events(iommu); |
253 | ||
254 | return IRQ_HANDLED; | |
a80dc3e0 JR |
255 | } |
256 | ||
431b2a20 JR |
257 | /**************************************************************************** |
258 | * | |
259 | * IOMMU command queuing functions | |
260 | * | |
261 | ****************************************************************************/ | |
262 | ||
263 | /* | |
264 | * Writes the command to the IOMMUs command buffer and informs the | |
265 | * hardware about the new command. Must be called with iommu->lock held. | |
266 | */ | |
d6449536 | 267 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
268 | { |
269 | u32 tail, head; | |
270 | u8 *target; | |
271 | ||
272 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 273 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
274 | memcpy_toio(target, cmd, sizeof(*cmd)); |
275 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
276 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
277 | if (tail == head) | |
278 | return -ENOMEM; | |
279 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
431b2a20 JR |
284 | /* |
285 | * General queuing function for commands. Takes iommu->lock and calls | |
286 | * __iommu_queue_command(). | |
287 | */ | |
d6449536 | 288 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
289 | { |
290 | unsigned long flags; | |
291 | int ret; | |
292 | ||
293 | spin_lock_irqsave(&iommu->lock, flags); | |
294 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 295 | if (!ret) |
0cfd7aa9 | 296 | iommu->need_sync = true; |
a19ae1ec JR |
297 | spin_unlock_irqrestore(&iommu->lock, flags); |
298 | ||
299 | return ret; | |
300 | } | |
301 | ||
8d201968 JR |
302 | /* |
303 | * This function waits until an IOMMU has completed a completion | |
304 | * wait command | |
305 | */ | |
306 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
307 | { | |
308 | int ready = 0; | |
309 | unsigned status = 0; | |
310 | unsigned long i = 0; | |
311 | ||
da49f6df JR |
312 | INC_STATS_COUNTER(compl_wait); |
313 | ||
8d201968 JR |
314 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
315 | ++i; | |
316 | /* wait for the bit to become one */ | |
317 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
318 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
319 | } | |
320 | ||
321 | /* set bit back to zero */ | |
322 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
323 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
324 | ||
6a1eddd2 JR |
325 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
326 | spin_unlock(&iommu->lock); | |
327 | reset_iommu_command_buffer(iommu); | |
328 | spin_lock(&iommu->lock); | |
329 | } | |
8d201968 JR |
330 | } |
331 | ||
332 | /* | |
333 | * This function queues a completion wait command into the command | |
334 | * buffer of an IOMMU | |
335 | */ | |
336 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
337 | { | |
338 | struct iommu_cmd cmd; | |
339 | ||
340 | memset(&cmd, 0, sizeof(cmd)); | |
341 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
342 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
343 | ||
344 | return __iommu_queue_command(iommu, &cmd); | |
345 | } | |
346 | ||
431b2a20 JR |
347 | /* |
348 | * This function is called whenever we need to ensure that the IOMMU has | |
349 | * completed execution of all commands we sent. It sends a | |
350 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
351 | * us about that by writing a value to a physical address we pass with | |
352 | * the command. | |
353 | */ | |
a19ae1ec JR |
354 | static int iommu_completion_wait(struct amd_iommu *iommu) |
355 | { | |
8d201968 JR |
356 | int ret = 0; |
357 | unsigned long flags; | |
a19ae1ec | 358 | |
7e4f88da JR |
359 | spin_lock_irqsave(&iommu->lock, flags); |
360 | ||
09ee17eb JR |
361 | if (!iommu->need_sync) |
362 | goto out; | |
363 | ||
8d201968 | 364 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 365 | |
0cfd7aa9 | 366 | iommu->need_sync = false; |
a19ae1ec JR |
367 | |
368 | if (ret) | |
7e4f88da | 369 | goto out; |
a19ae1ec | 370 | |
8d201968 | 371 | __iommu_wait_for_completion(iommu); |
84df8175 | 372 | |
7e4f88da JR |
373 | out: |
374 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
0518a3a4 JR |
379 | static void iommu_flush_complete(struct protection_domain *domain) |
380 | { | |
381 | int i; | |
382 | ||
383 | for (i = 0; i < amd_iommus_present; ++i) { | |
384 | if (!domain->dev_iommu[i]) | |
385 | continue; | |
386 | ||
387 | /* | |
388 | * Devices of this domain are behind this IOMMU | |
389 | * We need to wait for completion of all commands. | |
390 | */ | |
391 | iommu_completion_wait(amd_iommus[i]); | |
392 | } | |
393 | } | |
394 | ||
431b2a20 JR |
395 | /* |
396 | * Command send function for invalidating a device table entry | |
397 | */ | |
a19ae1ec JR |
398 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
399 | { | |
d6449536 | 400 | struct iommu_cmd cmd; |
ee2fa743 | 401 | int ret; |
a19ae1ec JR |
402 | |
403 | BUG_ON(iommu == NULL); | |
404 | ||
405 | memset(&cmd, 0, sizeof(cmd)); | |
406 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
407 | cmd.data[0] = devid; | |
408 | ||
ee2fa743 JR |
409 | ret = iommu_queue_command(iommu, &cmd); |
410 | ||
ee2fa743 | 411 | return ret; |
a19ae1ec JR |
412 | } |
413 | ||
237b6f33 JR |
414 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
415 | u16 domid, int pde, int s) | |
416 | { | |
417 | memset(cmd, 0, sizeof(*cmd)); | |
418 | address &= PAGE_MASK; | |
419 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
420 | cmd->data[1] |= domid; | |
421 | cmd->data[2] = lower_32_bits(address); | |
422 | cmd->data[3] = upper_32_bits(address); | |
423 | if (s) /* size bit - we flush more than one 4kb page */ | |
424 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
425 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
426 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
427 | } | |
428 | ||
431b2a20 JR |
429 | /* |
430 | * Generic command send function for invalidaing TLB entries | |
431 | */ | |
a19ae1ec JR |
432 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
433 | u64 address, u16 domid, int pde, int s) | |
434 | { | |
d6449536 | 435 | struct iommu_cmd cmd; |
ee2fa743 | 436 | int ret; |
a19ae1ec | 437 | |
237b6f33 | 438 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 439 | |
ee2fa743 JR |
440 | ret = iommu_queue_command(iommu, &cmd); |
441 | ||
ee2fa743 | 442 | return ret; |
a19ae1ec JR |
443 | } |
444 | ||
431b2a20 JR |
445 | /* |
446 | * TLB invalidation function which is called from the mapping functions. | |
447 | * It invalidates a single PTE if the range to flush is within a single | |
448 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
449 | */ | |
6de8ad9b JR |
450 | static void __iommu_flush_pages(struct protection_domain *domain, |
451 | u64 address, size_t size, int pde) | |
a19ae1ec | 452 | { |
6de8ad9b | 453 | int s = 0, i; |
dcd1e92e | 454 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
455 | |
456 | address &= PAGE_MASK; | |
457 | ||
999ba417 JR |
458 | if (pages > 1) { |
459 | /* | |
460 | * If we have to flush more than one page, flush all | |
461 | * TLB entries for this domain | |
462 | */ | |
463 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
464 | s = 1; | |
a19ae1ec JR |
465 | } |
466 | ||
999ba417 | 467 | |
6de8ad9b JR |
468 | for (i = 0; i < amd_iommus_present; ++i) { |
469 | if (!domain->dev_iommu[i]) | |
470 | continue; | |
471 | ||
472 | /* | |
473 | * Devices of this domain are behind this IOMMU | |
474 | * We need a TLB flush | |
475 | */ | |
476 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
477 | domain->id, pde, s); | |
478 | } | |
479 | ||
480 | return; | |
481 | } | |
482 | ||
483 | static void iommu_flush_pages(struct protection_domain *domain, | |
484 | u64 address, size_t size) | |
485 | { | |
486 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 487 | } |
b6c02715 | 488 | |
1c655773 | 489 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 490 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 491 | { |
dcd1e92e | 492 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
493 | } |
494 | ||
42a49f96 | 495 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 496 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 497 | { |
dcd1e92e | 498 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
499 | } |
500 | ||
43f49609 | 501 | /* |
e394d72a | 502 | * This function flushes one domain on one IOMMU |
43f49609 | 503 | */ |
e394d72a | 504 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 505 | { |
43f49609 | 506 | struct iommu_cmd cmd; |
e394d72a | 507 | unsigned long flags; |
18811f55 | 508 | |
43f49609 JR |
509 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
510 | domid, 1, 1); | |
511 | ||
e394d72a JR |
512 | spin_lock_irqsave(&iommu->lock, flags); |
513 | __iommu_queue_command(iommu, &cmd); | |
514 | __iommu_completion_wait(iommu); | |
515 | __iommu_wait_for_completion(iommu); | |
516 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 517 | } |
43f49609 | 518 | |
e394d72a | 519 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
520 | { |
521 | int i; | |
522 | ||
523 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
524 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
525 | continue; | |
e394d72a | 526 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 527 | } |
e394d72a JR |
528 | |
529 | } | |
530 | ||
bfd1be18 | 531 | void amd_iommu_flush_all_domains(void) |
e394d72a | 532 | { |
e3306664 | 533 | struct protection_domain *domain; |
e394d72a | 534 | |
e3306664 JR |
535 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
536 | iommu_flush_tlb_pde(domain); | |
537 | iommu_flush_complete(domain); | |
538 | } | |
bfd1be18 JR |
539 | } |
540 | ||
d586d785 | 541 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
542 | { |
543 | int i; | |
544 | ||
d586d785 JR |
545 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
546 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 547 | continue; |
d586d785 JR |
548 | |
549 | iommu_queue_inv_dev_entry(iommu, i); | |
550 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
551 | } |
552 | } | |
553 | ||
6a0dbcbe | 554 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
555 | { |
556 | struct amd_iommu *iommu; | |
557 | int i; | |
558 | ||
559 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
560 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
561 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
562 | continue; |
563 | ||
564 | iommu = amd_iommu_rlookup_table[i]; | |
565 | if (!iommu) | |
566 | continue; | |
567 | ||
568 | iommu_queue_inv_dev_entry(iommu, i); | |
569 | iommu_completion_wait(iommu); | |
570 | } | |
571 | } | |
572 | ||
a345b23b JR |
573 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
574 | { | |
575 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
576 | ||
b26e81b8 JR |
577 | if (iommu->reset_in_progress) |
578 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
579 | ||
580 | iommu->reset_in_progress = true; | |
581 | ||
a345b23b JR |
582 | amd_iommu_reset_cmd_buffer(iommu); |
583 | flush_all_devices_for_iommu(iommu); | |
584 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
585 | |
586 | iommu->reset_in_progress = false; | |
a345b23b JR |
587 | } |
588 | ||
6a0dbcbe JR |
589 | void amd_iommu_flush_all_devices(void) |
590 | { | |
591 | flush_devices_by_domain(NULL); | |
592 | } | |
593 | ||
431b2a20 JR |
594 | /**************************************************************************** |
595 | * | |
596 | * The functions below are used the create the page table mappings for | |
597 | * unity mapped regions. | |
598 | * | |
599 | ****************************************************************************/ | |
600 | ||
601 | /* | |
602 | * Generic mapping functions. It maps a physical address into a DMA | |
603 | * address space. It allocates the page table pages if necessary. | |
604 | * In the future it can be extended to a generic mapping function | |
605 | * supporting all features of AMD IOMMU page tables like level skipping | |
606 | * and full 64 bit address spaces. | |
607 | */ | |
38e817fe JR |
608 | static int iommu_map_page(struct protection_domain *dom, |
609 | unsigned long bus_addr, | |
610 | unsigned long phys_addr, | |
abdc5eb3 JR |
611 | int prot, |
612 | int map_size) | |
bd0e5211 | 613 | { |
8bda3092 | 614 | u64 __pte, *pte; |
bd0e5211 JR |
615 | |
616 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 617 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 618 | |
abdc5eb3 JR |
619 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
620 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
621 | ||
bad1cac2 | 622 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
623 | return -EINVAL; |
624 | ||
abdc5eb3 | 625 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
626 | |
627 | if (IOMMU_PTE_PRESENT(*pte)) | |
628 | return -EBUSY; | |
629 | ||
630 | __pte = phys_addr | IOMMU_PTE_P; | |
631 | if (prot & IOMMU_PROT_IR) | |
632 | __pte |= IOMMU_PTE_IR; | |
633 | if (prot & IOMMU_PROT_IW) | |
634 | __pte |= IOMMU_PTE_IW; | |
635 | ||
636 | *pte = __pte; | |
637 | ||
04bfdd84 JR |
638 | update_domain(dom); |
639 | ||
bd0e5211 JR |
640 | return 0; |
641 | } | |
642 | ||
eb74ff6c | 643 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 644 | unsigned long bus_addr, int map_size) |
eb74ff6c | 645 | { |
a6b256b4 | 646 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 647 | |
38a76eee JR |
648 | if (pte) |
649 | *pte = 0; | |
eb74ff6c | 650 | } |
eb74ff6c | 651 | |
431b2a20 JR |
652 | /* |
653 | * This function checks if a specific unity mapping entry is needed for | |
654 | * this specific IOMMU. | |
655 | */ | |
bd0e5211 JR |
656 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
657 | struct unity_map_entry *entry) | |
658 | { | |
659 | u16 bdf, i; | |
660 | ||
661 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
662 | bdf = amd_iommu_alias_table[i]; | |
663 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
664 | return 1; | |
665 | } | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
431b2a20 JR |
670 | /* |
671 | * Init the unity mappings for a specific IOMMU in the system | |
672 | * | |
673 | * Basically iterates over all unity mapping entries and applies them to | |
674 | * the default domain DMA of that IOMMU if necessary. | |
675 | */ | |
bd0e5211 JR |
676 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
677 | { | |
678 | struct unity_map_entry *entry; | |
679 | int ret; | |
680 | ||
681 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
682 | if (!iommu_for_unity_map(iommu, entry)) | |
683 | continue; | |
684 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
685 | if (ret) | |
686 | return ret; | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
431b2a20 JR |
692 | /* |
693 | * This function actually applies the mapping to the page table of the | |
694 | * dma_ops domain. | |
695 | */ | |
bd0e5211 JR |
696 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
697 | struct unity_map_entry *e) | |
698 | { | |
699 | u64 addr; | |
700 | int ret; | |
701 | ||
702 | for (addr = e->address_start; addr < e->address_end; | |
703 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
704 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
705 | PM_MAP_4k); | |
bd0e5211 JR |
706 | if (ret) |
707 | return ret; | |
708 | /* | |
709 | * if unity mapping is in aperture range mark the page | |
710 | * as allocated in the aperture | |
711 | */ | |
712 | if (addr < dma_dom->aperture_size) | |
c3239567 | 713 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 714 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
715 | } |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
431b2a20 JR |
720 | /* |
721 | * Inits the unity mappings required for a specific device | |
722 | */ | |
bd0e5211 JR |
723 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
724 | u16 devid) | |
725 | { | |
726 | struct unity_map_entry *e; | |
727 | int ret; | |
728 | ||
729 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
730 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
731 | continue; | |
732 | ret = dma_ops_unity_map(dma_dom, e); | |
733 | if (ret) | |
734 | return ret; | |
735 | } | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
431b2a20 JR |
740 | /**************************************************************************** |
741 | * | |
742 | * The next functions belong to the address allocator for the dma_ops | |
743 | * interface functions. They work like the allocators in the other IOMMU | |
744 | * drivers. Its basically a bitmap which marks the allocated pages in | |
745 | * the aperture. Maybe it could be enhanced in the future to a more | |
746 | * efficient allocator. | |
747 | * | |
748 | ****************************************************************************/ | |
d3086444 | 749 | |
431b2a20 | 750 | /* |
384de729 | 751 | * The address allocator core functions. |
431b2a20 JR |
752 | * |
753 | * called with domain->lock held | |
754 | */ | |
384de729 | 755 | |
00cd122a JR |
756 | /* |
757 | * This function checks if there is a PTE for a given dma address. If | |
758 | * there is one, it returns the pointer to it. | |
759 | */ | |
9355a081 | 760 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 761 | unsigned long address, int map_size) |
00cd122a | 762 | { |
9355a081 | 763 | int level; |
00cd122a JR |
764 | u64 *pte; |
765 | ||
9355a081 JR |
766 | level = domain->mode - 1; |
767 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 768 | |
a6b256b4 | 769 | while (level > map_size) { |
9355a081 JR |
770 | if (!IOMMU_PTE_PRESENT(*pte)) |
771 | return NULL; | |
00cd122a | 772 | |
9355a081 | 773 | level -= 1; |
00cd122a | 774 | |
9355a081 JR |
775 | pte = IOMMU_PTE_PAGE(*pte); |
776 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 777 | |
a6b256b4 JR |
778 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { |
779 | pte = NULL; | |
780 | break; | |
781 | } | |
9355a081 | 782 | } |
00cd122a JR |
783 | |
784 | return pte; | |
785 | } | |
786 | ||
9cabe89b JR |
787 | /* |
788 | * This function is used to add a new aperture range to an existing | |
789 | * aperture in case of dma_ops domain allocation or address allocation | |
790 | * failure. | |
791 | */ | |
00cd122a JR |
792 | static int alloc_new_range(struct amd_iommu *iommu, |
793 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
794 | bool populate, gfp_t gfp) |
795 | { | |
796 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 797 | int i; |
9cabe89b | 798 | |
f5e9705c JR |
799 | #ifdef CONFIG_IOMMU_STRESS |
800 | populate = false; | |
801 | #endif | |
802 | ||
9cabe89b JR |
803 | if (index >= APERTURE_MAX_RANGES) |
804 | return -ENOMEM; | |
805 | ||
806 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
807 | if (!dma_dom->aperture[index]) | |
808 | return -ENOMEM; | |
809 | ||
810 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
811 | if (!dma_dom->aperture[index]->bitmap) | |
812 | goto out_free; | |
813 | ||
814 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
815 | ||
816 | if (populate) { | |
817 | unsigned long address = dma_dom->aperture_size; | |
818 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
819 | u64 *pte, *pte_page; | |
820 | ||
821 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 822 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
823 | &pte_page, gfp); |
824 | if (!pte) | |
825 | goto out_free; | |
826 | ||
827 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
828 | ||
829 | address += APERTURE_RANGE_SIZE / 64; | |
830 | } | |
831 | } | |
832 | ||
833 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
834 | ||
00cd122a JR |
835 | /* Intialize the exclusion range if necessary */ |
836 | if (iommu->exclusion_start && | |
837 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
838 | iommu->exclusion_start < dma_dom->aperture_size) { | |
839 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
840 | int pages = iommu_num_pages(iommu->exclusion_start, | |
841 | iommu->exclusion_length, | |
842 | PAGE_SIZE); | |
843 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
844 | } | |
845 | ||
846 | /* | |
847 | * Check for areas already mapped as present in the new aperture | |
848 | * range and mark those pages as reserved in the allocator. Such | |
849 | * mappings may already exist as a result of requested unity | |
850 | * mappings for devices. | |
851 | */ | |
852 | for (i = dma_dom->aperture[index]->offset; | |
853 | i < dma_dom->aperture_size; | |
854 | i += PAGE_SIZE) { | |
a6b256b4 | 855 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
856 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
857 | continue; | |
858 | ||
859 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
860 | } | |
861 | ||
04bfdd84 JR |
862 | update_domain(&dma_dom->domain); |
863 | ||
9cabe89b JR |
864 | return 0; |
865 | ||
866 | out_free: | |
04bfdd84 JR |
867 | update_domain(&dma_dom->domain); |
868 | ||
9cabe89b JR |
869 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
870 | ||
871 | kfree(dma_dom->aperture[index]); | |
872 | dma_dom->aperture[index] = NULL; | |
873 | ||
874 | return -ENOMEM; | |
875 | } | |
876 | ||
384de729 JR |
877 | static unsigned long dma_ops_area_alloc(struct device *dev, |
878 | struct dma_ops_domain *dom, | |
879 | unsigned int pages, | |
880 | unsigned long align_mask, | |
881 | u64 dma_mask, | |
882 | unsigned long start) | |
883 | { | |
803b8cb4 | 884 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
885 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
886 | int i = start >> APERTURE_RANGE_SHIFT; | |
887 | unsigned long boundary_size; | |
888 | unsigned long address = -1; | |
889 | unsigned long limit; | |
890 | ||
803b8cb4 JR |
891 | next_bit >>= PAGE_SHIFT; |
892 | ||
384de729 JR |
893 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
894 | PAGE_SIZE) >> PAGE_SHIFT; | |
895 | ||
896 | for (;i < max_index; ++i) { | |
897 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
898 | ||
899 | if (dom->aperture[i]->offset >= dma_mask) | |
900 | break; | |
901 | ||
902 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
903 | dma_mask >> PAGE_SHIFT); | |
904 | ||
905 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
906 | limit, next_bit, pages, 0, | |
907 | boundary_size, align_mask); | |
908 | if (address != -1) { | |
909 | address = dom->aperture[i]->offset + | |
910 | (address << PAGE_SHIFT); | |
803b8cb4 | 911 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
912 | break; |
913 | } | |
914 | ||
915 | next_bit = 0; | |
916 | } | |
917 | ||
918 | return address; | |
919 | } | |
920 | ||
d3086444 JR |
921 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
922 | struct dma_ops_domain *dom, | |
6d4f343f | 923 | unsigned int pages, |
832a90c3 JR |
924 | unsigned long align_mask, |
925 | u64 dma_mask) | |
d3086444 | 926 | { |
d3086444 | 927 | unsigned long address; |
d3086444 | 928 | |
fe16f088 JR |
929 | #ifdef CONFIG_IOMMU_STRESS |
930 | dom->next_address = 0; | |
931 | dom->need_flush = true; | |
932 | #endif | |
d3086444 | 933 | |
384de729 | 934 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 935 | dma_mask, dom->next_address); |
d3086444 | 936 | |
1c655773 | 937 | if (address == -1) { |
803b8cb4 | 938 | dom->next_address = 0; |
384de729 JR |
939 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
940 | dma_mask, 0); | |
1c655773 JR |
941 | dom->need_flush = true; |
942 | } | |
d3086444 | 943 | |
384de729 | 944 | if (unlikely(address == -1)) |
8fd524b3 | 945 | address = DMA_ERROR_CODE; |
d3086444 JR |
946 | |
947 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
948 | ||
949 | return address; | |
950 | } | |
951 | ||
431b2a20 JR |
952 | /* |
953 | * The address free function. | |
954 | * | |
955 | * called with domain->lock held | |
956 | */ | |
d3086444 JR |
957 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
958 | unsigned long address, | |
959 | unsigned int pages) | |
960 | { | |
384de729 JR |
961 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
962 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 963 | |
384de729 JR |
964 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
965 | ||
47bccd6b JR |
966 | #ifdef CONFIG_IOMMU_STRESS |
967 | if (i < 4) | |
968 | return; | |
969 | #endif | |
80be308d | 970 | |
803b8cb4 | 971 | if (address >= dom->next_address) |
80be308d | 972 | dom->need_flush = true; |
384de729 JR |
973 | |
974 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 975 | |
384de729 JR |
976 | iommu_area_free(range->bitmap, address, pages); |
977 | ||
d3086444 JR |
978 | } |
979 | ||
431b2a20 JR |
980 | /**************************************************************************** |
981 | * | |
982 | * The next functions belong to the domain allocation. A domain is | |
983 | * allocated for every IOMMU as the default domain. If device isolation | |
984 | * is enabled, every device get its own domain. The most important thing | |
985 | * about domains is the page table mapping the DMA address space they | |
986 | * contain. | |
987 | * | |
988 | ****************************************************************************/ | |
989 | ||
aeb26f55 JR |
990 | /* |
991 | * This function adds a protection domain to the global protection domain list | |
992 | */ | |
993 | static void add_domain_to_list(struct protection_domain *domain) | |
994 | { | |
995 | unsigned long flags; | |
996 | ||
997 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
998 | list_add(&domain->list, &amd_iommu_pd_list); | |
999 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * This function removes a protection domain to the global | |
1004 | * protection domain list | |
1005 | */ | |
1006 | static void del_domain_from_list(struct protection_domain *domain) | |
1007 | { | |
1008 | unsigned long flags; | |
1009 | ||
1010 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1011 | list_del(&domain->list); | |
1012 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1013 | } | |
1014 | ||
ec487d1a JR |
1015 | static u16 domain_id_alloc(void) |
1016 | { | |
1017 | unsigned long flags; | |
1018 | int id; | |
1019 | ||
1020 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1021 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1022 | BUG_ON(id == 0); | |
1023 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1024 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1025 | else | |
1026 | id = 0; | |
1027 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1028 | ||
1029 | return id; | |
1030 | } | |
1031 | ||
a2acfb75 JR |
1032 | static void domain_id_free(int id) |
1033 | { | |
1034 | unsigned long flags; | |
1035 | ||
1036 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1037 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1038 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1039 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1040 | } | |
a2acfb75 | 1041 | |
431b2a20 JR |
1042 | /* |
1043 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1044 | * ranges. | |
1045 | */ | |
ec487d1a JR |
1046 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
1047 | unsigned long start_page, | |
1048 | unsigned int pages) | |
1049 | { | |
384de729 | 1050 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
1051 | |
1052 | if (start_page + pages > last_page) | |
1053 | pages = last_page - start_page; | |
1054 | ||
384de729 JR |
1055 | for (i = start_page; i < start_page + pages; ++i) { |
1056 | int index = i / APERTURE_RANGE_PAGES; | |
1057 | int page = i % APERTURE_RANGE_PAGES; | |
1058 | __set_bit(page, dom->aperture[index]->bitmap); | |
1059 | } | |
ec487d1a JR |
1060 | } |
1061 | ||
86db2e5d | 1062 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1063 | { |
1064 | int i, j; | |
1065 | u64 *p1, *p2, *p3; | |
1066 | ||
86db2e5d | 1067 | p1 = domain->pt_root; |
ec487d1a JR |
1068 | |
1069 | if (!p1) | |
1070 | return; | |
1071 | ||
1072 | for (i = 0; i < 512; ++i) { | |
1073 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1074 | continue; | |
1075 | ||
1076 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1077 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1078 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1079 | continue; | |
1080 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1081 | free_page((unsigned long)p3); | |
1082 | } | |
1083 | ||
1084 | free_page((unsigned long)p2); | |
1085 | } | |
1086 | ||
1087 | free_page((unsigned long)p1); | |
86db2e5d JR |
1088 | |
1089 | domain->pt_root = NULL; | |
ec487d1a JR |
1090 | } |
1091 | ||
431b2a20 JR |
1092 | /* |
1093 | * Free a domain, only used if something went wrong in the | |
1094 | * allocation path and we need to free an already allocated page table | |
1095 | */ | |
ec487d1a JR |
1096 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1097 | { | |
384de729 JR |
1098 | int i; |
1099 | ||
ec487d1a JR |
1100 | if (!dom) |
1101 | return; | |
1102 | ||
aeb26f55 JR |
1103 | del_domain_from_list(&dom->domain); |
1104 | ||
86db2e5d | 1105 | free_pagetable(&dom->domain); |
ec487d1a | 1106 | |
384de729 JR |
1107 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1108 | if (!dom->aperture[i]) | |
1109 | continue; | |
1110 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1111 | kfree(dom->aperture[i]); | |
1112 | } | |
ec487d1a JR |
1113 | |
1114 | kfree(dom); | |
1115 | } | |
1116 | ||
431b2a20 JR |
1117 | /* |
1118 | * Allocates a new protection domain usable for the dma_ops functions. | |
1119 | * It also intializes the page table and the address allocator data | |
1120 | * structures required for the dma_ops interface | |
1121 | */ | |
d9cfed92 | 1122 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1123 | { |
1124 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1125 | |
1126 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1127 | if (!dma_dom) | |
1128 | return NULL; | |
1129 | ||
1130 | spin_lock_init(&dma_dom->domain.lock); | |
1131 | ||
1132 | dma_dom->domain.id = domain_id_alloc(); | |
1133 | if (dma_dom->domain.id == 0) | |
1134 | goto free_dma_dom; | |
8f7a017c | 1135 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1136 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1137 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1138 | dma_dom->domain.priv = dma_dom; |
1139 | if (!dma_dom->domain.pt_root) | |
1140 | goto free_dma_dom; | |
ec487d1a | 1141 | |
1c655773 | 1142 | dma_dom->need_flush = false; |
bd60b735 | 1143 | dma_dom->target_dev = 0xffff; |
1c655773 | 1144 | |
aeb26f55 JR |
1145 | add_domain_to_list(&dma_dom->domain); |
1146 | ||
00cd122a | 1147 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1148 | goto free_dma_dom; |
ec487d1a | 1149 | |
431b2a20 | 1150 | /* |
ec487d1a JR |
1151 | * mark the first page as allocated so we never return 0 as |
1152 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1153 | */ |
384de729 | 1154 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1155 | dma_dom->next_address = 0; |
ec487d1a | 1156 | |
ec487d1a JR |
1157 | |
1158 | return dma_dom; | |
1159 | ||
1160 | free_dma_dom: | |
1161 | dma_ops_domain_free(dma_dom); | |
1162 | ||
1163 | return NULL; | |
1164 | } | |
1165 | ||
5b28df6f JR |
1166 | /* |
1167 | * little helper function to check whether a given protection domain is a | |
1168 | * dma_ops domain | |
1169 | */ | |
1170 | static bool dma_ops_domain(struct protection_domain *domain) | |
1171 | { | |
1172 | return domain->flags & PD_DMA_OPS_MASK; | |
1173 | } | |
1174 | ||
431b2a20 JR |
1175 | /* |
1176 | * Find out the protection domain structure for a given PCI device. This | |
1177 | * will give us the pointer to the page table root for example. | |
1178 | */ | |
b20ac0d4 JR |
1179 | static struct protection_domain *domain_for_device(u16 devid) |
1180 | { | |
1181 | struct protection_domain *dom; | |
1182 | unsigned long flags; | |
1183 | ||
1184 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1185 | dom = amd_iommu_pd_table[devid]; | |
1186 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1187 | ||
1188 | return dom; | |
1189 | } | |
1190 | ||
407d733e | 1191 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1192 | { |
b20ac0d4 | 1193 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1194 | |
38ddf41b JR |
1195 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1196 | << DEV_ENTRY_MODE_SHIFT; | |
1197 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1198 | |
b20ac0d4 | 1199 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1200 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1201 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1202 | |
1203 | amd_iommu_pd_table[devid] = domain; | |
2b681faf JR |
1204 | } |
1205 | ||
1206 | /* | |
1207 | * If a device is not yet associated with a domain, this function does | |
1208 | * assigns it visible for the hardware | |
1209 | */ | |
1210 | static void __attach_device(struct amd_iommu *iommu, | |
1211 | struct protection_domain *domain, | |
1212 | u16 devid) | |
1213 | { | |
1214 | /* lock domain */ | |
1215 | spin_lock(&domain->lock); | |
1216 | ||
1217 | /* update DTE entry */ | |
1218 | set_dte_entry(devid, domain); | |
eba6ac60 | 1219 | |
c4596114 JR |
1220 | /* Do reference counting */ |
1221 | domain->dev_iommu[iommu->index] += 1; | |
1222 | domain->dev_cnt += 1; | |
eba6ac60 JR |
1223 | |
1224 | /* ready */ | |
1225 | spin_unlock(&domain->lock); | |
0feae533 | 1226 | } |
b20ac0d4 | 1227 | |
407d733e JR |
1228 | /* |
1229 | * If a device is not yet associated with a domain, this function does | |
1230 | * assigns it visible for the hardware | |
1231 | */ | |
0feae533 JR |
1232 | static void attach_device(struct amd_iommu *iommu, |
1233 | struct protection_domain *domain, | |
1234 | u16 devid) | |
1235 | { | |
eba6ac60 JR |
1236 | unsigned long flags; |
1237 | ||
1238 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
0feae533 | 1239 | __attach_device(iommu, domain, devid); |
b20ac0d4 JR |
1240 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1241 | ||
0feae533 JR |
1242 | /* |
1243 | * We might boot into a crash-kernel here. The crashed kernel | |
1244 | * left the caches in the IOMMU dirty. So we have to flush | |
1245 | * here to evict all dirty stuff. | |
1246 | */ | |
b20ac0d4 | 1247 | iommu_queue_inv_dev_entry(iommu, devid); |
dcd1e92e | 1248 | iommu_flush_tlb_pde(domain); |
b20ac0d4 JR |
1249 | } |
1250 | ||
355bf553 JR |
1251 | /* |
1252 | * Removes a device from a protection domain (unlocked) | |
1253 | */ | |
1254 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1255 | { | |
c4596114 JR |
1256 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
1257 | ||
1258 | BUG_ON(!iommu); | |
355bf553 JR |
1259 | |
1260 | /* lock domain */ | |
1261 | spin_lock(&domain->lock); | |
1262 | ||
1263 | /* remove domain from the lookup table */ | |
1264 | amd_iommu_pd_table[devid] = NULL; | |
1265 | ||
1266 | /* remove entry from the device table seen by the hardware */ | |
1267 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1268 | amd_iommu_dev_table[devid].data[1] = 0; | |
1269 | amd_iommu_dev_table[devid].data[2] = 0; | |
1270 | ||
c5cca146 JR |
1271 | amd_iommu_apply_erratum_63(devid); |
1272 | ||
c4596114 JR |
1273 | /* decrease reference counters */ |
1274 | domain->dev_iommu[iommu->index] -= 1; | |
1275 | domain->dev_cnt -= 1; | |
355bf553 JR |
1276 | |
1277 | /* ready */ | |
1278 | spin_unlock(&domain->lock); | |
21129f78 JR |
1279 | |
1280 | /* | |
1281 | * If we run in passthrough mode the device must be assigned to the | |
1282 | * passthrough domain if it is detached from any other domain | |
1283 | */ | |
1284 | if (iommu_pass_through) { | |
1285 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1286 | __attach_device(iommu, pt_domain, devid); | |
1287 | } | |
355bf553 JR |
1288 | } |
1289 | ||
1290 | /* | |
1291 | * Removes a device from a protection domain (with devtable_lock held) | |
1292 | */ | |
1293 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1294 | { | |
1295 | unsigned long flags; | |
1296 | ||
1297 | /* lock device table */ | |
1298 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1299 | __detach_device(domain, devid); | |
1300 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1301 | } | |
e275a2a0 JR |
1302 | |
1303 | static int device_change_notifier(struct notifier_block *nb, | |
1304 | unsigned long action, void *data) | |
1305 | { | |
1306 | struct device *dev = data; | |
1307 | struct pci_dev *pdev = to_pci_dev(dev); | |
1308 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1309 | struct protection_domain *domain; | |
1310 | struct dma_ops_domain *dma_domain; | |
1311 | struct amd_iommu *iommu; | |
1ac4cbbc | 1312 | unsigned long flags; |
e275a2a0 JR |
1313 | |
1314 | if (devid > amd_iommu_last_bdf) | |
1315 | goto out; | |
1316 | ||
1317 | devid = amd_iommu_alias_table[devid]; | |
1318 | ||
1319 | iommu = amd_iommu_rlookup_table[devid]; | |
1320 | if (iommu == NULL) | |
1321 | goto out; | |
1322 | ||
1323 | domain = domain_for_device(devid); | |
1324 | ||
1325 | if (domain && !dma_ops_domain(domain)) | |
1326 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1327 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1328 | ||
1329 | switch (action) { | |
c1eee67b | 1330 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1331 | if (!domain) |
1332 | goto out; | |
a1ca331c JR |
1333 | if (iommu_pass_through) |
1334 | break; | |
e275a2a0 | 1335 | detach_device(domain, devid); |
1ac4cbbc JR |
1336 | break; |
1337 | case BUS_NOTIFY_ADD_DEVICE: | |
1338 | /* allocate a protection domain if a device is added */ | |
1339 | dma_domain = find_protection_domain(devid); | |
1340 | if (dma_domain) | |
1341 | goto out; | |
d9cfed92 | 1342 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1343 | if (!dma_domain) |
1344 | goto out; | |
1345 | dma_domain->target_dev = devid; | |
1346 | ||
1347 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1348 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1349 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1350 | ||
e275a2a0 JR |
1351 | break; |
1352 | default: | |
1353 | goto out; | |
1354 | } | |
1355 | ||
1356 | iommu_queue_inv_dev_entry(iommu, devid); | |
1357 | iommu_completion_wait(iommu); | |
1358 | ||
1359 | out: | |
1360 | return 0; | |
1361 | } | |
1362 | ||
b25ae679 | 1363 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1364 | .notifier_call = device_change_notifier, |
1365 | }; | |
355bf553 | 1366 | |
431b2a20 JR |
1367 | /***************************************************************************** |
1368 | * | |
1369 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1370 | * | |
1371 | *****************************************************************************/ | |
1372 | ||
dbcc112e JR |
1373 | /* |
1374 | * This function checks if the driver got a valid device from the caller to | |
1375 | * avoid dereferencing invalid pointers. | |
1376 | */ | |
1377 | static bool check_device(struct device *dev) | |
1378 | { | |
1379 | if (!dev || !dev->dma_mask) | |
1380 | return false; | |
1381 | ||
1382 | return true; | |
1383 | } | |
1384 | ||
bd60b735 JR |
1385 | /* |
1386 | * In this function the list of preallocated protection domains is traversed to | |
1387 | * find the domain for a specific device | |
1388 | */ | |
1389 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1390 | { | |
1391 | struct dma_ops_domain *entry, *ret = NULL; | |
1392 | unsigned long flags; | |
1393 | ||
1394 | if (list_empty(&iommu_pd_list)) | |
1395 | return NULL; | |
1396 | ||
1397 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1398 | ||
1399 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1400 | if (entry->target_dev == devid) { | |
1401 | ret = entry; | |
bd60b735 JR |
1402 | break; |
1403 | } | |
1404 | } | |
1405 | ||
1406 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1407 | ||
1408 | return ret; | |
1409 | } | |
1410 | ||
431b2a20 JR |
1411 | /* |
1412 | * In the dma_ops path we only have the struct device. This function | |
1413 | * finds the corresponding IOMMU, the protection domain and the | |
1414 | * requestor id for a given device. | |
1415 | * If the device is not yet associated with a domain this is also done | |
1416 | * in this function. | |
1417 | */ | |
b20ac0d4 JR |
1418 | static int get_device_resources(struct device *dev, |
1419 | struct amd_iommu **iommu, | |
1420 | struct protection_domain **domain, | |
1421 | u16 *bdf) | |
1422 | { | |
1423 | struct dma_ops_domain *dma_dom; | |
1424 | struct pci_dev *pcidev; | |
1425 | u16 _bdf; | |
1426 | ||
dbcc112e JR |
1427 | *iommu = NULL; |
1428 | *domain = NULL; | |
1429 | *bdf = 0xffff; | |
1430 | ||
1431 | if (dev->bus != &pci_bus_type) | |
1432 | return 0; | |
b20ac0d4 JR |
1433 | |
1434 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1435 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1436 | |
431b2a20 | 1437 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1438 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1439 | return 0; |
b20ac0d4 JR |
1440 | |
1441 | *bdf = amd_iommu_alias_table[_bdf]; | |
1442 | ||
1443 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1444 | if (*iommu == NULL) | |
1445 | return 0; | |
b20ac0d4 JR |
1446 | *domain = domain_for_device(*bdf); |
1447 | if (*domain == NULL) { | |
bd60b735 JR |
1448 | dma_dom = find_protection_domain(*bdf); |
1449 | if (!dma_dom) | |
1450 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1451 | *domain = &dma_dom->domain; |
f1179dc0 | 1452 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1453 | DUMP_printk("Using protection domain %d for device %s\n", |
1454 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1455 | } |
1456 | ||
f91ba190 | 1457 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1458 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1459 | |
b20ac0d4 JR |
1460 | return 1; |
1461 | } | |
1462 | ||
04bfdd84 JR |
1463 | static void update_device_table(struct protection_domain *domain) |
1464 | { | |
2b681faf | 1465 | unsigned long flags; |
04bfdd84 JR |
1466 | int i; |
1467 | ||
1468 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1469 | if (amd_iommu_pd_table[i] != domain) | |
1470 | continue; | |
2b681faf | 1471 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1472 | set_dte_entry(i, domain); |
2b681faf | 1473 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1474 | } |
1475 | } | |
1476 | ||
1477 | static void update_domain(struct protection_domain *domain) | |
1478 | { | |
1479 | if (!domain->updated) | |
1480 | return; | |
1481 | ||
1482 | update_device_table(domain); | |
1483 | flush_devices_by_domain(domain); | |
601367d7 | 1484 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1485 | |
1486 | domain->updated = false; | |
1487 | } | |
1488 | ||
8bda3092 | 1489 | /* |
50020fb6 JR |
1490 | * This function is used to add another level to an IO page table. Adding |
1491 | * another level increases the size of the address space by 9 bits to a size up | |
1492 | * to 64 bits. | |
8bda3092 | 1493 | */ |
50020fb6 JR |
1494 | static bool increase_address_space(struct protection_domain *domain, |
1495 | gfp_t gfp) | |
1496 | { | |
1497 | u64 *pte; | |
1498 | ||
1499 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1500 | /* address space already 64 bit large */ | |
1501 | return false; | |
1502 | ||
1503 | pte = (void *)get_zeroed_page(gfp); | |
1504 | if (!pte) | |
1505 | return false; | |
1506 | ||
1507 | *pte = PM_LEVEL_PDE(domain->mode, | |
1508 | virt_to_phys(domain->pt_root)); | |
1509 | domain->pt_root = pte; | |
1510 | domain->mode += 1; | |
1511 | domain->updated = true; | |
1512 | ||
1513 | return true; | |
1514 | } | |
1515 | ||
8bc3e127 | 1516 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
1517 | unsigned long address, |
1518 | int end_lvl, | |
1519 | u64 **pte_page, | |
1520 | gfp_t gfp) | |
8bda3092 JR |
1521 | { |
1522 | u64 *pte, *page; | |
8bc3e127 | 1523 | int level; |
8bda3092 | 1524 | |
8bc3e127 JR |
1525 | while (address > PM_LEVEL_SIZE(domain->mode)) |
1526 | increase_address_space(domain, gfp); | |
8bda3092 | 1527 | |
8bc3e127 JR |
1528 | level = domain->mode - 1; |
1529 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
8bda3092 | 1530 | |
abdc5eb3 | 1531 | while (level > end_lvl) { |
8bc3e127 JR |
1532 | if (!IOMMU_PTE_PRESENT(*pte)) { |
1533 | page = (u64 *)get_zeroed_page(gfp); | |
1534 | if (!page) | |
1535 | return NULL; | |
1536 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1537 | } | |
8bda3092 | 1538 | |
8bc3e127 | 1539 | level -= 1; |
8bda3092 | 1540 | |
8bc3e127 | 1541 | pte = IOMMU_PTE_PAGE(*pte); |
8bda3092 | 1542 | |
abdc5eb3 | 1543 | if (pte_page && level == end_lvl) |
8bc3e127 | 1544 | *pte_page = pte; |
8bda3092 | 1545 | |
8bc3e127 JR |
1546 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
1547 | } | |
8bda3092 JR |
1548 | |
1549 | return pte; | |
1550 | } | |
1551 | ||
1552 | /* | |
1553 | * This function fetches the PTE for a given address in the aperture | |
1554 | */ | |
1555 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1556 | unsigned long address) | |
1557 | { | |
384de729 | 1558 | struct aperture_range *aperture; |
8bda3092 JR |
1559 | u64 *pte, *pte_page; |
1560 | ||
384de729 JR |
1561 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1562 | if (!aperture) | |
1563 | return NULL; | |
1564 | ||
1565 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1566 | if (!pte) { |
abdc5eb3 JR |
1567 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1568 | GFP_ATOMIC); | |
384de729 JR |
1569 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1570 | } else | |
8c8c143c | 1571 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1572 | |
04bfdd84 | 1573 | update_domain(&dom->domain); |
8bda3092 JR |
1574 | |
1575 | return pte; | |
1576 | } | |
1577 | ||
431b2a20 JR |
1578 | /* |
1579 | * This is the generic map function. It maps one 4kb page at paddr to | |
1580 | * the given address in the DMA address space for the domain. | |
1581 | */ | |
cb76c322 JR |
1582 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1583 | struct dma_ops_domain *dom, | |
1584 | unsigned long address, | |
1585 | phys_addr_t paddr, | |
1586 | int direction) | |
1587 | { | |
1588 | u64 *pte, __pte; | |
1589 | ||
1590 | WARN_ON(address > dom->aperture_size); | |
1591 | ||
1592 | paddr &= PAGE_MASK; | |
1593 | ||
8bda3092 | 1594 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1595 | if (!pte) |
8fd524b3 | 1596 | return DMA_ERROR_CODE; |
cb76c322 JR |
1597 | |
1598 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1599 | ||
1600 | if (direction == DMA_TO_DEVICE) | |
1601 | __pte |= IOMMU_PTE_IR; | |
1602 | else if (direction == DMA_FROM_DEVICE) | |
1603 | __pte |= IOMMU_PTE_IW; | |
1604 | else if (direction == DMA_BIDIRECTIONAL) | |
1605 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1606 | ||
1607 | WARN_ON(*pte); | |
1608 | ||
1609 | *pte = __pte; | |
1610 | ||
1611 | return (dma_addr_t)address; | |
1612 | } | |
1613 | ||
431b2a20 JR |
1614 | /* |
1615 | * The generic unmapping function for on page in the DMA address space. | |
1616 | */ | |
cb76c322 JR |
1617 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1618 | struct dma_ops_domain *dom, | |
1619 | unsigned long address) | |
1620 | { | |
384de729 | 1621 | struct aperture_range *aperture; |
cb76c322 JR |
1622 | u64 *pte; |
1623 | ||
1624 | if (address >= dom->aperture_size) | |
1625 | return; | |
1626 | ||
384de729 JR |
1627 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1628 | if (!aperture) | |
1629 | return; | |
1630 | ||
1631 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1632 | if (!pte) | |
1633 | return; | |
cb76c322 | 1634 | |
8c8c143c | 1635 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1636 | |
1637 | WARN_ON(!*pte); | |
1638 | ||
1639 | *pte = 0ULL; | |
1640 | } | |
1641 | ||
431b2a20 JR |
1642 | /* |
1643 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1644 | * contiguous memory region into DMA address space. It is used by all |
1645 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1646 | * Must be called with the domain lock held. |
1647 | */ | |
cb76c322 JR |
1648 | static dma_addr_t __map_single(struct device *dev, |
1649 | struct amd_iommu *iommu, | |
1650 | struct dma_ops_domain *dma_dom, | |
1651 | phys_addr_t paddr, | |
1652 | size_t size, | |
6d4f343f | 1653 | int dir, |
832a90c3 JR |
1654 | bool align, |
1655 | u64 dma_mask) | |
cb76c322 JR |
1656 | { |
1657 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1658 | dma_addr_t address, start, ret; |
cb76c322 | 1659 | unsigned int pages; |
6d4f343f | 1660 | unsigned long align_mask = 0; |
cb76c322 JR |
1661 | int i; |
1662 | ||
e3c449f5 | 1663 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1664 | paddr &= PAGE_MASK; |
1665 | ||
8ecaf8f1 JR |
1666 | INC_STATS_COUNTER(total_map_requests); |
1667 | ||
c1858976 JR |
1668 | if (pages > 1) |
1669 | INC_STATS_COUNTER(cross_page); | |
1670 | ||
6d4f343f JR |
1671 | if (align) |
1672 | align_mask = (1UL << get_order(size)) - 1; | |
1673 | ||
11b83888 | 1674 | retry: |
832a90c3 JR |
1675 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1676 | dma_mask); | |
8fd524b3 | 1677 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1678 | /* |
1679 | * setting next_address here will let the address | |
1680 | * allocator only scan the new allocated range in the | |
1681 | * first run. This is a small optimization. | |
1682 | */ | |
1683 | dma_dom->next_address = dma_dom->aperture_size; | |
1684 | ||
1685 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1686 | goto out; | |
1687 | ||
1688 | /* | |
1689 | * aperture was sucessfully enlarged by 128 MB, try | |
1690 | * allocation again | |
1691 | */ | |
1692 | goto retry; | |
1693 | } | |
cb76c322 JR |
1694 | |
1695 | start = address; | |
1696 | for (i = 0; i < pages; ++i) { | |
53812c11 | 1697 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
8fd524b3 | 1698 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1699 | goto out_unmap; |
1700 | ||
cb76c322 JR |
1701 | paddr += PAGE_SIZE; |
1702 | start += PAGE_SIZE; | |
1703 | } | |
1704 | address += offset; | |
1705 | ||
5774f7c5 JR |
1706 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1707 | ||
afa9fdc2 | 1708 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1709 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 JR |
1710 | dma_dom->need_flush = false; |
1711 | } else if (unlikely(iommu_has_npcache(iommu))) | |
6de8ad9b | 1712 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1713 | |
cb76c322 JR |
1714 | out: |
1715 | return address; | |
53812c11 JR |
1716 | |
1717 | out_unmap: | |
1718 | ||
1719 | for (--i; i >= 0; --i) { | |
1720 | start -= PAGE_SIZE; | |
1721 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1722 | } | |
1723 | ||
1724 | dma_ops_free_addresses(dma_dom, address, pages); | |
1725 | ||
8fd524b3 | 1726 | return DMA_ERROR_CODE; |
cb76c322 JR |
1727 | } |
1728 | ||
431b2a20 JR |
1729 | /* |
1730 | * Does the reverse of the __map_single function. Must be called with | |
1731 | * the domain lock held too | |
1732 | */ | |
cb76c322 JR |
1733 | static void __unmap_single(struct amd_iommu *iommu, |
1734 | struct dma_ops_domain *dma_dom, | |
1735 | dma_addr_t dma_addr, | |
1736 | size_t size, | |
1737 | int dir) | |
1738 | { | |
1739 | dma_addr_t i, start; | |
1740 | unsigned int pages; | |
1741 | ||
8fd524b3 | 1742 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1743 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1744 | return; |
1745 | ||
e3c449f5 | 1746 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1747 | dma_addr &= PAGE_MASK; |
1748 | start = dma_addr; | |
1749 | ||
1750 | for (i = 0; i < pages; ++i) { | |
1751 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1752 | start += PAGE_SIZE; | |
1753 | } | |
1754 | ||
5774f7c5 JR |
1755 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1756 | ||
cb76c322 | 1757 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1758 | |
80be308d | 1759 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
6de8ad9b | 1760 | iommu_flush_pages(&dma_dom->domain, dma_addr, size); |
80be308d JR |
1761 | dma_dom->need_flush = false; |
1762 | } | |
cb76c322 JR |
1763 | } |
1764 | ||
431b2a20 JR |
1765 | /* |
1766 | * The exported map_single function for dma_ops. | |
1767 | */ | |
51491367 FT |
1768 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1769 | unsigned long offset, size_t size, | |
1770 | enum dma_data_direction dir, | |
1771 | struct dma_attrs *attrs) | |
4da70b9e JR |
1772 | { |
1773 | unsigned long flags; | |
1774 | struct amd_iommu *iommu; | |
1775 | struct protection_domain *domain; | |
1776 | u16 devid; | |
1777 | dma_addr_t addr; | |
832a90c3 | 1778 | u64 dma_mask; |
51491367 | 1779 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1780 | |
0f2a86f2 JR |
1781 | INC_STATS_COUNTER(cnt_map_single); |
1782 | ||
dbcc112e | 1783 | if (!check_device(dev)) |
8fd524b3 | 1784 | return DMA_ERROR_CODE; |
dbcc112e | 1785 | |
832a90c3 | 1786 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1787 | |
1788 | get_device_resources(dev, &iommu, &domain, &devid); | |
1789 | ||
1790 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1791 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1792 | return (dma_addr_t)paddr; |
1793 | ||
5b28df6f | 1794 | if (!dma_ops_domain(domain)) |
8fd524b3 | 1795 | return DMA_ERROR_CODE; |
5b28df6f | 1796 | |
4da70b9e | 1797 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1798 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1799 | dma_mask); | |
8fd524b3 | 1800 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1801 | goto out; |
1802 | ||
0518a3a4 | 1803 | iommu_flush_complete(domain); |
4da70b9e JR |
1804 | |
1805 | out: | |
1806 | spin_unlock_irqrestore(&domain->lock, flags); | |
1807 | ||
1808 | return addr; | |
1809 | } | |
1810 | ||
431b2a20 JR |
1811 | /* |
1812 | * The exported unmap_single function for dma_ops. | |
1813 | */ | |
51491367 FT |
1814 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1815 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1816 | { |
1817 | unsigned long flags; | |
1818 | struct amd_iommu *iommu; | |
1819 | struct protection_domain *domain; | |
1820 | u16 devid; | |
1821 | ||
146a6917 JR |
1822 | INC_STATS_COUNTER(cnt_unmap_single); |
1823 | ||
dbcc112e JR |
1824 | if (!check_device(dev) || |
1825 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1826 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1827 | return; |
1828 | ||
5b28df6f JR |
1829 | if (!dma_ops_domain(domain)) |
1830 | return; | |
1831 | ||
4da70b9e JR |
1832 | spin_lock_irqsave(&domain->lock, flags); |
1833 | ||
1834 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1835 | ||
0518a3a4 | 1836 | iommu_flush_complete(domain); |
4da70b9e JR |
1837 | |
1838 | spin_unlock_irqrestore(&domain->lock, flags); | |
1839 | } | |
1840 | ||
431b2a20 JR |
1841 | /* |
1842 | * This is a special map_sg function which is used if we should map a | |
1843 | * device which is not handled by an AMD IOMMU in the system. | |
1844 | */ | |
65b050ad JR |
1845 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1846 | int nelems, int dir) | |
1847 | { | |
1848 | struct scatterlist *s; | |
1849 | int i; | |
1850 | ||
1851 | for_each_sg(sglist, s, nelems, i) { | |
1852 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1853 | s->dma_length = s->length; | |
1854 | } | |
1855 | ||
1856 | return nelems; | |
1857 | } | |
1858 | ||
431b2a20 JR |
1859 | /* |
1860 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1861 | * lists). | |
1862 | */ | |
65b050ad | 1863 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1864 | int nelems, enum dma_data_direction dir, |
1865 | struct dma_attrs *attrs) | |
65b050ad JR |
1866 | { |
1867 | unsigned long flags; | |
1868 | struct amd_iommu *iommu; | |
1869 | struct protection_domain *domain; | |
1870 | u16 devid; | |
1871 | int i; | |
1872 | struct scatterlist *s; | |
1873 | phys_addr_t paddr; | |
1874 | int mapped_elems = 0; | |
832a90c3 | 1875 | u64 dma_mask; |
65b050ad | 1876 | |
d03f067a JR |
1877 | INC_STATS_COUNTER(cnt_map_sg); |
1878 | ||
dbcc112e JR |
1879 | if (!check_device(dev)) |
1880 | return 0; | |
1881 | ||
832a90c3 | 1882 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1883 | |
1884 | get_device_resources(dev, &iommu, &domain, &devid); | |
1885 | ||
1886 | if (!iommu || !domain) | |
1887 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1888 | ||
5b28df6f JR |
1889 | if (!dma_ops_domain(domain)) |
1890 | return 0; | |
1891 | ||
65b050ad JR |
1892 | spin_lock_irqsave(&domain->lock, flags); |
1893 | ||
1894 | for_each_sg(sglist, s, nelems, i) { | |
1895 | paddr = sg_phys(s); | |
1896 | ||
1897 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1898 | paddr, s->length, dir, false, |
1899 | dma_mask); | |
65b050ad JR |
1900 | |
1901 | if (s->dma_address) { | |
1902 | s->dma_length = s->length; | |
1903 | mapped_elems++; | |
1904 | } else | |
1905 | goto unmap; | |
65b050ad JR |
1906 | } |
1907 | ||
0518a3a4 | 1908 | iommu_flush_complete(domain); |
65b050ad JR |
1909 | |
1910 | out: | |
1911 | spin_unlock_irqrestore(&domain->lock, flags); | |
1912 | ||
1913 | return mapped_elems; | |
1914 | unmap: | |
1915 | for_each_sg(sglist, s, mapped_elems, i) { | |
1916 | if (s->dma_address) | |
1917 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1918 | s->dma_length, dir); | |
1919 | s->dma_address = s->dma_length = 0; | |
1920 | } | |
1921 | ||
1922 | mapped_elems = 0; | |
1923 | ||
1924 | goto out; | |
1925 | } | |
1926 | ||
431b2a20 JR |
1927 | /* |
1928 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1929 | * lists). | |
1930 | */ | |
65b050ad | 1931 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1932 | int nelems, enum dma_data_direction dir, |
1933 | struct dma_attrs *attrs) | |
65b050ad JR |
1934 | { |
1935 | unsigned long flags; | |
1936 | struct amd_iommu *iommu; | |
1937 | struct protection_domain *domain; | |
1938 | struct scatterlist *s; | |
1939 | u16 devid; | |
1940 | int i; | |
1941 | ||
55877a6b JR |
1942 | INC_STATS_COUNTER(cnt_unmap_sg); |
1943 | ||
dbcc112e JR |
1944 | if (!check_device(dev) || |
1945 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1946 | return; |
1947 | ||
5b28df6f JR |
1948 | if (!dma_ops_domain(domain)) |
1949 | return; | |
1950 | ||
65b050ad JR |
1951 | spin_lock_irqsave(&domain->lock, flags); |
1952 | ||
1953 | for_each_sg(sglist, s, nelems, i) { | |
1954 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1955 | s->dma_length, dir); | |
65b050ad JR |
1956 | s->dma_address = s->dma_length = 0; |
1957 | } | |
1958 | ||
0518a3a4 | 1959 | iommu_flush_complete(domain); |
65b050ad JR |
1960 | |
1961 | spin_unlock_irqrestore(&domain->lock, flags); | |
1962 | } | |
1963 | ||
431b2a20 JR |
1964 | /* |
1965 | * The exported alloc_coherent function for dma_ops. | |
1966 | */ | |
5d8b53cf JR |
1967 | static void *alloc_coherent(struct device *dev, size_t size, |
1968 | dma_addr_t *dma_addr, gfp_t flag) | |
1969 | { | |
1970 | unsigned long flags; | |
1971 | void *virt_addr; | |
1972 | struct amd_iommu *iommu; | |
1973 | struct protection_domain *domain; | |
1974 | u16 devid; | |
1975 | phys_addr_t paddr; | |
832a90c3 | 1976 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1977 | |
c8f0fb36 JR |
1978 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1979 | ||
dbcc112e JR |
1980 | if (!check_device(dev)) |
1981 | return NULL; | |
5d8b53cf | 1982 | |
13d9fead FT |
1983 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1984 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1985 | |
c97ac535 | 1986 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1987 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1988 | if (!virt_addr) | |
b25ae679 | 1989 | return NULL; |
5d8b53cf | 1990 | |
5d8b53cf JR |
1991 | paddr = virt_to_phys(virt_addr); |
1992 | ||
5d8b53cf JR |
1993 | if (!iommu || !domain) { |
1994 | *dma_addr = (dma_addr_t)paddr; | |
1995 | return virt_addr; | |
1996 | } | |
1997 | ||
5b28df6f JR |
1998 | if (!dma_ops_domain(domain)) |
1999 | goto out_free; | |
2000 | ||
832a90c3 JR |
2001 | if (!dma_mask) |
2002 | dma_mask = *dev->dma_mask; | |
2003 | ||
5d8b53cf JR |
2004 | spin_lock_irqsave(&domain->lock, flags); |
2005 | ||
2006 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 2007 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2008 | |
8fd524b3 | 2009 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2010 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2011 | goto out_free; |
367d04c4 | 2012 | } |
5d8b53cf | 2013 | |
0518a3a4 | 2014 | iommu_flush_complete(domain); |
5d8b53cf | 2015 | |
5d8b53cf JR |
2016 | spin_unlock_irqrestore(&domain->lock, flags); |
2017 | ||
2018 | return virt_addr; | |
5b28df6f JR |
2019 | |
2020 | out_free: | |
2021 | ||
2022 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2023 | ||
2024 | return NULL; | |
5d8b53cf JR |
2025 | } |
2026 | ||
431b2a20 JR |
2027 | /* |
2028 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2029 | */ |
5d8b53cf JR |
2030 | static void free_coherent(struct device *dev, size_t size, |
2031 | void *virt_addr, dma_addr_t dma_addr) | |
2032 | { | |
2033 | unsigned long flags; | |
2034 | struct amd_iommu *iommu; | |
2035 | struct protection_domain *domain; | |
2036 | u16 devid; | |
2037 | ||
5d31ee7e JR |
2038 | INC_STATS_COUNTER(cnt_free_coherent); |
2039 | ||
dbcc112e JR |
2040 | if (!check_device(dev)) |
2041 | return; | |
2042 | ||
5d8b53cf JR |
2043 | get_device_resources(dev, &iommu, &domain, &devid); |
2044 | ||
2045 | if (!iommu || !domain) | |
2046 | goto free_mem; | |
2047 | ||
5b28df6f JR |
2048 | if (!dma_ops_domain(domain)) |
2049 | goto free_mem; | |
2050 | ||
5d8b53cf JR |
2051 | spin_lock_irqsave(&domain->lock, flags); |
2052 | ||
2053 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2054 | |
0518a3a4 | 2055 | iommu_flush_complete(domain); |
5d8b53cf JR |
2056 | |
2057 | spin_unlock_irqrestore(&domain->lock, flags); | |
2058 | ||
2059 | free_mem: | |
2060 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2061 | } | |
2062 | ||
b39ba6ad JR |
2063 | /* |
2064 | * This function is called by the DMA layer to find out if we can handle a | |
2065 | * particular device. It is part of the dma_ops. | |
2066 | */ | |
2067 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2068 | { | |
2069 | u16 bdf; | |
2070 | struct pci_dev *pcidev; | |
2071 | ||
2072 | /* No device or no PCI device */ | |
2073 | if (!dev || dev->bus != &pci_bus_type) | |
2074 | return 0; | |
2075 | ||
2076 | pcidev = to_pci_dev(dev); | |
2077 | ||
2078 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
2079 | ||
2080 | /* Out of our scope? */ | |
2081 | if (bdf > amd_iommu_last_bdf) | |
2082 | return 0; | |
2083 | ||
2084 | return 1; | |
2085 | } | |
2086 | ||
c432f3df | 2087 | /* |
431b2a20 JR |
2088 | * The function for pre-allocating protection domains. |
2089 | * | |
c432f3df JR |
2090 | * If the driver core informs the DMA layer if a driver grabs a device |
2091 | * we don't need to preallocate the protection domains anymore. | |
2092 | * For now we have to. | |
2093 | */ | |
0e93dd88 | 2094 | static void prealloc_protection_domains(void) |
c432f3df JR |
2095 | { |
2096 | struct pci_dev *dev = NULL; | |
2097 | struct dma_ops_domain *dma_dom; | |
2098 | struct amd_iommu *iommu; | |
be831297 | 2099 | u16 devid, __devid; |
c432f3df JR |
2100 | |
2101 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
be831297 | 2102 | __devid = devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 2103 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
2104 | continue; |
2105 | devid = amd_iommu_alias_table[devid]; | |
2106 | if (domain_for_device(devid)) | |
2107 | continue; | |
2108 | iommu = amd_iommu_rlookup_table[devid]; | |
2109 | if (!iommu) | |
2110 | continue; | |
d9cfed92 | 2111 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
2112 | if (!dma_dom) |
2113 | continue; | |
2114 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2115 | dma_dom->target_dev = devid; |
2116 | ||
be831297 JR |
2117 | attach_device(iommu, &dma_dom->domain, devid); |
2118 | if (__devid != devid) | |
2119 | attach_device(iommu, &dma_dom->domain, __devid); | |
2120 | ||
bd60b735 | 2121 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2122 | } |
2123 | } | |
2124 | ||
160c1d8e | 2125 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2126 | .alloc_coherent = alloc_coherent, |
2127 | .free_coherent = free_coherent, | |
51491367 FT |
2128 | .map_page = map_page, |
2129 | .unmap_page = unmap_page, | |
6631ee9d JR |
2130 | .map_sg = map_sg, |
2131 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2132 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2133 | }; |
2134 | ||
431b2a20 JR |
2135 | /* |
2136 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2137 | */ | |
6631ee9d JR |
2138 | int __init amd_iommu_init_dma_ops(void) |
2139 | { | |
2140 | struct amd_iommu *iommu; | |
6631ee9d JR |
2141 | int ret; |
2142 | ||
431b2a20 JR |
2143 | /* |
2144 | * first allocate a default protection domain for every IOMMU we | |
2145 | * found in the system. Devices not assigned to any other | |
2146 | * protection domain will be assigned to the default one. | |
2147 | */ | |
3bd22172 | 2148 | for_each_iommu(iommu) { |
d9cfed92 | 2149 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
2150 | if (iommu->default_dom == NULL) |
2151 | return -ENOMEM; | |
e2dc14a2 | 2152 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2153 | ret = iommu_init_unity_mappings(iommu); |
2154 | if (ret) | |
2155 | goto free_domains; | |
2156 | } | |
2157 | ||
431b2a20 JR |
2158 | /* |
2159 | * If device isolation is enabled, pre-allocate the protection | |
2160 | * domains for each device. | |
2161 | */ | |
6631ee9d JR |
2162 | if (amd_iommu_isolate) |
2163 | prealloc_protection_domains(); | |
2164 | ||
2165 | iommu_detected = 1; | |
75f1cdf1 | 2166 | swiotlb = 0; |
92af4e29 | 2167 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2168 | gart_iommu_aperture_disabled = 1; |
2169 | gart_iommu_aperture = 0; | |
92af4e29 | 2170 | #endif |
6631ee9d | 2171 | |
431b2a20 | 2172 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2173 | dma_ops = &amd_iommu_dma_ops; |
2174 | ||
26961efe | 2175 | register_iommu(&amd_iommu_ops); |
26961efe | 2176 | |
e275a2a0 JR |
2177 | bus_register_notifier(&pci_bus_type, &device_nb); |
2178 | ||
7f26508b JR |
2179 | amd_iommu_stats_init(); |
2180 | ||
6631ee9d JR |
2181 | return 0; |
2182 | ||
2183 | free_domains: | |
2184 | ||
3bd22172 | 2185 | for_each_iommu(iommu) { |
6631ee9d JR |
2186 | if (iommu->default_dom) |
2187 | dma_ops_domain_free(iommu->default_dom); | |
2188 | } | |
2189 | ||
2190 | return ret; | |
2191 | } | |
6d98cd80 JR |
2192 | |
2193 | /***************************************************************************** | |
2194 | * | |
2195 | * The following functions belong to the exported interface of AMD IOMMU | |
2196 | * | |
2197 | * This interface allows access to lower level functions of the IOMMU | |
2198 | * like protection domain handling and assignement of devices to domains | |
2199 | * which is not possible with the dma_ops interface. | |
2200 | * | |
2201 | *****************************************************************************/ | |
2202 | ||
6d98cd80 JR |
2203 | static void cleanup_domain(struct protection_domain *domain) |
2204 | { | |
2205 | unsigned long flags; | |
2206 | u16 devid; | |
2207 | ||
2208 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2209 | ||
2210 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2211 | if (amd_iommu_pd_table[devid] == domain) | |
2212 | __detach_device(domain, devid); | |
2213 | ||
2214 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2215 | } | |
2216 | ||
2650815f JR |
2217 | static void protection_domain_free(struct protection_domain *domain) |
2218 | { | |
2219 | if (!domain) | |
2220 | return; | |
2221 | ||
aeb26f55 JR |
2222 | del_domain_from_list(domain); |
2223 | ||
2650815f JR |
2224 | if (domain->id) |
2225 | domain_id_free(domain->id); | |
2226 | ||
2227 | kfree(domain); | |
2228 | } | |
2229 | ||
2230 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2231 | { |
2232 | struct protection_domain *domain; | |
2233 | ||
2234 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2235 | if (!domain) | |
2650815f | 2236 | return NULL; |
c156e347 JR |
2237 | |
2238 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2239 | domain->id = domain_id_alloc(); |
2240 | if (!domain->id) | |
2650815f JR |
2241 | goto out_err; |
2242 | ||
aeb26f55 JR |
2243 | add_domain_to_list(domain); |
2244 | ||
2650815f JR |
2245 | return domain; |
2246 | ||
2247 | out_err: | |
2248 | kfree(domain); | |
2249 | ||
2250 | return NULL; | |
2251 | } | |
2252 | ||
2253 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2254 | { | |
2255 | struct protection_domain *domain; | |
2256 | ||
2257 | domain = protection_domain_alloc(); | |
2258 | if (!domain) | |
c156e347 | 2259 | goto out_free; |
2650815f JR |
2260 | |
2261 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2262 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2263 | if (!domain->pt_root) | |
2264 | goto out_free; | |
2265 | ||
2266 | dom->priv = domain; | |
2267 | ||
2268 | return 0; | |
2269 | ||
2270 | out_free: | |
2650815f | 2271 | protection_domain_free(domain); |
c156e347 JR |
2272 | |
2273 | return -ENOMEM; | |
2274 | } | |
2275 | ||
98383fc3 JR |
2276 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2277 | { | |
2278 | struct protection_domain *domain = dom->priv; | |
2279 | ||
2280 | if (!domain) | |
2281 | return; | |
2282 | ||
2283 | if (domain->dev_cnt > 0) | |
2284 | cleanup_domain(domain); | |
2285 | ||
2286 | BUG_ON(domain->dev_cnt != 0); | |
2287 | ||
2288 | free_pagetable(domain); | |
2289 | ||
2290 | domain_id_free(domain->id); | |
2291 | ||
2292 | kfree(domain); | |
2293 | ||
2294 | dom->priv = NULL; | |
2295 | } | |
2296 | ||
684f2888 JR |
2297 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2298 | struct device *dev) | |
2299 | { | |
2300 | struct protection_domain *domain = dom->priv; | |
2301 | struct amd_iommu *iommu; | |
2302 | struct pci_dev *pdev; | |
2303 | u16 devid; | |
2304 | ||
2305 | if (dev->bus != &pci_bus_type) | |
2306 | return; | |
2307 | ||
2308 | pdev = to_pci_dev(dev); | |
2309 | ||
2310 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2311 | ||
2312 | if (devid > 0) | |
2313 | detach_device(domain, devid); | |
2314 | ||
2315 | iommu = amd_iommu_rlookup_table[devid]; | |
2316 | if (!iommu) | |
2317 | return; | |
2318 | ||
2319 | iommu_queue_inv_dev_entry(iommu, devid); | |
2320 | iommu_completion_wait(iommu); | |
2321 | } | |
2322 | ||
01106066 JR |
2323 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2324 | struct device *dev) | |
2325 | { | |
2326 | struct protection_domain *domain = dom->priv; | |
2327 | struct protection_domain *old_domain; | |
2328 | struct amd_iommu *iommu; | |
2329 | struct pci_dev *pdev; | |
2330 | u16 devid; | |
2331 | ||
2332 | if (dev->bus != &pci_bus_type) | |
2333 | return -EINVAL; | |
2334 | ||
2335 | pdev = to_pci_dev(dev); | |
2336 | ||
2337 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2338 | ||
2339 | if (devid >= amd_iommu_last_bdf || | |
2340 | devid != amd_iommu_alias_table[devid]) | |
2341 | return -EINVAL; | |
2342 | ||
2343 | iommu = amd_iommu_rlookup_table[devid]; | |
2344 | if (!iommu) | |
2345 | return -EINVAL; | |
2346 | ||
2347 | old_domain = domain_for_device(devid); | |
2348 | if (old_domain) | |
71ff3bca | 2349 | detach_device(old_domain, devid); |
01106066 JR |
2350 | |
2351 | attach_device(iommu, domain, devid); | |
2352 | ||
2353 | iommu_completion_wait(iommu); | |
2354 | ||
2355 | return 0; | |
2356 | } | |
2357 | ||
c6229ca6 JR |
2358 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2359 | unsigned long iova, phys_addr_t paddr, | |
2360 | size_t size, int iommu_prot) | |
2361 | { | |
2362 | struct protection_domain *domain = dom->priv; | |
2363 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2364 | int prot = 0; | |
2365 | int ret; | |
2366 | ||
2367 | if (iommu_prot & IOMMU_READ) | |
2368 | prot |= IOMMU_PROT_IR; | |
2369 | if (iommu_prot & IOMMU_WRITE) | |
2370 | prot |= IOMMU_PROT_IW; | |
2371 | ||
2372 | iova &= PAGE_MASK; | |
2373 | paddr &= PAGE_MASK; | |
2374 | ||
2375 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2376 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2377 | if (ret) |
2378 | return ret; | |
2379 | ||
2380 | iova += PAGE_SIZE; | |
2381 | paddr += PAGE_SIZE; | |
2382 | } | |
2383 | ||
2384 | return 0; | |
2385 | } | |
2386 | ||
eb74ff6c JR |
2387 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2388 | unsigned long iova, size_t size) | |
2389 | { | |
2390 | ||
2391 | struct protection_domain *domain = dom->priv; | |
2392 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2393 | ||
2394 | iova &= PAGE_MASK; | |
2395 | ||
2396 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2397 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2398 | iova += PAGE_SIZE; |
2399 | } | |
2400 | ||
601367d7 | 2401 | iommu_flush_tlb_pde(domain); |
eb74ff6c JR |
2402 | } |
2403 | ||
645c4c8d JR |
2404 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2405 | unsigned long iova) | |
2406 | { | |
2407 | struct protection_domain *domain = dom->priv; | |
2408 | unsigned long offset = iova & ~PAGE_MASK; | |
2409 | phys_addr_t paddr; | |
2410 | u64 *pte; | |
2411 | ||
a6b256b4 | 2412 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2413 | |
a6d41a40 | 2414 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2415 | return 0; |
2416 | ||
2417 | paddr = *pte & IOMMU_PAGE_MASK; | |
2418 | paddr |= offset; | |
2419 | ||
2420 | return paddr; | |
2421 | } | |
2422 | ||
dbb9fd86 SY |
2423 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2424 | unsigned long cap) | |
2425 | { | |
2426 | return 0; | |
2427 | } | |
2428 | ||
26961efe JR |
2429 | static struct iommu_ops amd_iommu_ops = { |
2430 | .domain_init = amd_iommu_domain_init, | |
2431 | .domain_destroy = amd_iommu_domain_destroy, | |
2432 | .attach_dev = amd_iommu_attach_device, | |
2433 | .detach_dev = amd_iommu_detach_device, | |
2434 | .map = amd_iommu_map_range, | |
2435 | .unmap = amd_iommu_unmap_range, | |
2436 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2437 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2438 | }; |
2439 | ||
0feae533 JR |
2440 | /***************************************************************************** |
2441 | * | |
2442 | * The next functions do a basic initialization of IOMMU for pass through | |
2443 | * mode | |
2444 | * | |
2445 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2446 | * DMA-API translation. | |
2447 | * | |
2448 | *****************************************************************************/ | |
2449 | ||
2450 | int __init amd_iommu_init_passthrough(void) | |
2451 | { | |
2452 | struct pci_dev *dev = NULL; | |
2453 | u16 devid, devid2; | |
2454 | ||
2455 | /* allocate passthroug domain */ | |
2456 | pt_domain = protection_domain_alloc(); | |
2457 | if (!pt_domain) | |
2458 | return -ENOMEM; | |
2459 | ||
2460 | pt_domain->mode |= PAGE_MODE_NONE; | |
2461 | ||
2462 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2463 | struct amd_iommu *iommu; | |
2464 | ||
2465 | devid = calc_devid(dev->bus->number, dev->devfn); | |
2466 | if (devid > amd_iommu_last_bdf) | |
2467 | continue; | |
2468 | ||
2469 | devid2 = amd_iommu_alias_table[devid]; | |
2470 | ||
2471 | iommu = amd_iommu_rlookup_table[devid2]; | |
2472 | if (!iommu) | |
2473 | continue; | |
2474 | ||
2475 | __attach_device(iommu, pt_domain, devid); | |
2476 | __attach_device(iommu, pt_domain, devid2); | |
2477 | } | |
2478 | ||
2479 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2480 | ||
2481 | return 0; | |
2482 | } |