Commit | Line | Data |
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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
f6e2e6b6 JR |
32 | |
33 | /* | |
34 | * definitions for the ACPI scanning code | |
35 | */ | |
f6e2e6b6 | 36 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
37 | |
38 | #define ACPI_IVHD_TYPE 0x10 | |
39 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
40 | #define ACPI_IVMD_TYPE 0x21 | |
41 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
42 | ||
43 | #define IVHD_DEV_ALL 0x01 | |
44 | #define IVHD_DEV_SELECT 0x02 | |
45 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
46 | #define IVHD_DEV_RANGE_END 0x04 | |
47 | #define IVHD_DEV_ALIAS 0x42 | |
48 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
49 | #define IVHD_DEV_EXT_SELECT 0x46 | |
50 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
51 | ||
6da7342f JR |
52 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
53 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
54 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
55 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
56 | |
57 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
58 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
59 | ||
60 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
61 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
62 | #define ACPI_DEVFLAG_NMI 0x04 | |
63 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
64 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
65 | #define ACPI_DEVFLAG_LINT0 0x40 | |
66 | #define ACPI_DEVFLAG_LINT1 0x80 | |
67 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
68 | ||
b65233a9 JR |
69 | /* |
70 | * ACPI table definitions | |
71 | * | |
72 | * These data structures are laid over the table to parse the important values | |
73 | * out of it. | |
74 | */ | |
75 | ||
76 | /* | |
77 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
78 | * or more ivhd_entrys. | |
79 | */ | |
f6e2e6b6 JR |
80 | struct ivhd_header { |
81 | u8 type; | |
82 | u8 flags; | |
83 | u16 length; | |
84 | u16 devid; | |
85 | u16 cap_ptr; | |
86 | u64 mmio_phys; | |
87 | u16 pci_seg; | |
88 | u16 info; | |
89 | u32 reserved; | |
90 | } __attribute__((packed)); | |
91 | ||
b65233a9 JR |
92 | /* |
93 | * A device entry describing which devices a specific IOMMU translates and | |
94 | * which requestor ids they use. | |
95 | */ | |
f6e2e6b6 JR |
96 | struct ivhd_entry { |
97 | u8 type; | |
98 | u16 devid; | |
99 | u8 flags; | |
100 | u32 ext; | |
101 | } __attribute__((packed)); | |
102 | ||
b65233a9 JR |
103 | /* |
104 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
105 | * ranges for devices and regions that should be unity mapped. | |
106 | */ | |
f6e2e6b6 JR |
107 | struct ivmd_header { |
108 | u8 type; | |
109 | u8 flags; | |
110 | u16 length; | |
111 | u16 devid; | |
112 | u16 aux; | |
113 | u64 resv; | |
114 | u64 range_start; | |
115 | u64 range_length; | |
116 | } __attribute__((packed)); | |
117 | ||
c1cbebee JR |
118 | static int __initdata amd_iommu_detected; |
119 | ||
b65233a9 JR |
120 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
121 | to handle */ | |
2e22847f | 122 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 JR |
123 | we find in ACPI */ |
124 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
c226f853 JR |
125 | bool amd_iommu_isolate = true; /* if true, device isolation is |
126 | enabled */ | |
afa9fdc2 | 127 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 128 | |
2e22847f | 129 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 130 | system */ |
928abd25 | 131 | |
b65233a9 JR |
132 | /* |
133 | * Pointer to the device table which is shared by all AMD IOMMUs | |
134 | * it is indexed by the PCI device id or the HT unit id and contains | |
135 | * information about the domain the device belongs to as well as the | |
136 | * page table root pointer. | |
137 | */ | |
928abd25 | 138 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
139 | |
140 | /* | |
141 | * The alias table is a driver specific data structure which contains the | |
142 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
143 | * More than one device can share the same requestor id. | |
144 | */ | |
928abd25 | 145 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
146 | |
147 | /* | |
148 | * The rlookup table is used to find the IOMMU which is responsible | |
149 | * for a specific device. It is also indexed by the PCI device id. | |
150 | */ | |
928abd25 | 151 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
152 | |
153 | /* | |
154 | * The pd table (protection domain table) is used to find the protection domain | |
155 | * data structure a device belongs to. Indexed with the PCI device id too. | |
156 | */ | |
928abd25 | 157 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
158 | |
159 | /* | |
160 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
161 | * to know which ones are already in use. | |
162 | */ | |
928abd25 JR |
163 | unsigned long *amd_iommu_pd_alloc_bitmap; |
164 | ||
b65233a9 JR |
165 | static u32 dev_table_size; /* size of the device table */ |
166 | static u32 alias_table_size; /* size of the alias table */ | |
167 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 168 | |
208ec8c9 JR |
169 | static inline void update_last_devid(u16 devid) |
170 | { | |
171 | if (devid > amd_iommu_last_bdf) | |
172 | amd_iommu_last_bdf = devid; | |
173 | } | |
174 | ||
c571484e JR |
175 | static inline unsigned long tbl_size(int entry_size) |
176 | { | |
177 | unsigned shift = PAGE_SHIFT + | |
178 | get_order(amd_iommu_last_bdf * entry_size); | |
179 | ||
180 | return 1UL << shift; | |
181 | } | |
182 | ||
b65233a9 JR |
183 | /**************************************************************************** |
184 | * | |
185 | * AMD IOMMU MMIO register space handling functions | |
186 | * | |
187 | * These functions are used to program the IOMMU device registers in | |
188 | * MMIO space required for that driver. | |
189 | * | |
190 | ****************************************************************************/ | |
3e8064ba | 191 | |
b65233a9 JR |
192 | /* |
193 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
194 | * exclusion range are passed through untranslated | |
195 | */ | |
05f92db9 | 196 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
197 | { |
198 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
199 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
200 | u64 entry; | |
201 | ||
202 | if (!iommu->exclusion_start) | |
203 | return; | |
204 | ||
205 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
206 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
207 | &entry, sizeof(entry)); | |
208 | ||
209 | entry = limit; | |
210 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
211 | &entry, sizeof(entry)); | |
212 | } | |
213 | ||
b65233a9 | 214 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
215 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
216 | { | |
f609891f | 217 | u64 entry; |
b2026aa2 JR |
218 | |
219 | BUG_ON(iommu->mmio_base == NULL); | |
220 | ||
221 | entry = virt_to_phys(amd_iommu_dev_table); | |
222 | entry |= (dev_table_size >> 12) - 1; | |
223 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
224 | &entry, sizeof(entry)); | |
225 | } | |
226 | ||
b65233a9 | 227 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 228 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
229 | { |
230 | u32 ctrl; | |
231 | ||
232 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
233 | ctrl |= (1 << bit); | |
234 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
235 | } | |
236 | ||
237 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
238 | { | |
239 | u32 ctrl; | |
240 | ||
199d0d50 | 241 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
242 | ctrl &= ~(1 << bit); |
243 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
244 | } | |
245 | ||
b65233a9 | 246 | /* Function to enable the hardware */ |
05f92db9 | 247 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 248 | { |
a4e267c8 JR |
249 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n", |
250 | dev_name(&iommu->dev->dev), iommu->cap_ptr); | |
b2026aa2 JR |
251 | |
252 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
253 | } |
254 | ||
92ac4320 JR |
255 | static void iommu_disable(struct amd_iommu *iommu) |
256 | { | |
257 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); | |
258 | } | |
259 | ||
b65233a9 JR |
260 | /* |
261 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
262 | * the system has one. | |
263 | */ | |
6c56747b JR |
264 | static u8 * __init iommu_map_mmio_space(u64 address) |
265 | { | |
266 | u8 *ret; | |
267 | ||
268 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
269 | return NULL; | |
270 | ||
271 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
272 | if (ret != NULL) | |
273 | return ret; | |
274 | ||
275 | release_mem_region(address, MMIO_REGION_LENGTH); | |
276 | ||
277 | return NULL; | |
278 | } | |
279 | ||
280 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
281 | { | |
282 | if (iommu->mmio_base) | |
283 | iounmap(iommu->mmio_base); | |
284 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
285 | } | |
286 | ||
b65233a9 JR |
287 | /**************************************************************************** |
288 | * | |
289 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
290 | * parsing. In this pass we try to find out the highest device id this | |
291 | * code has to handle. Upon this information the size of the shared data | |
292 | * structures is determined later. | |
293 | * | |
294 | ****************************************************************************/ | |
295 | ||
b514e555 JR |
296 | /* |
297 | * This function calculates the length of a given IVHD entry | |
298 | */ | |
299 | static inline int ivhd_entry_length(u8 *ivhd) | |
300 | { | |
301 | return 0x04 << (*ivhd >> 6); | |
302 | } | |
303 | ||
b65233a9 JR |
304 | /* |
305 | * This function reads the last device id the IOMMU has to handle from the PCI | |
306 | * capability header for this IOMMU | |
307 | */ | |
3e8064ba JR |
308 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
309 | { | |
310 | u32 cap; | |
311 | ||
312 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 313 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
314 | |
315 | return 0; | |
316 | } | |
317 | ||
b65233a9 JR |
318 | /* |
319 | * After reading the highest device id from the IOMMU PCI capability header | |
320 | * this function looks if there is a higher device id defined in the ACPI table | |
321 | */ | |
3e8064ba JR |
322 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
323 | { | |
324 | u8 *p = (void *)h, *end = (void *)h; | |
325 | struct ivhd_entry *dev; | |
326 | ||
327 | p += sizeof(*h); | |
328 | end += h->length; | |
329 | ||
330 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
331 | PCI_SLOT(h->devid), | |
332 | PCI_FUNC(h->devid), | |
333 | h->cap_ptr); | |
334 | ||
335 | while (p < end) { | |
336 | dev = (struct ivhd_entry *)p; | |
337 | switch (dev->type) { | |
338 | case IVHD_DEV_SELECT: | |
339 | case IVHD_DEV_RANGE_END: | |
340 | case IVHD_DEV_ALIAS: | |
341 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 342 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 343 | update_last_devid(dev->devid); |
3e8064ba JR |
344 | break; |
345 | default: | |
346 | break; | |
347 | } | |
b514e555 | 348 | p += ivhd_entry_length(p); |
3e8064ba JR |
349 | } |
350 | ||
351 | WARN_ON(p != end); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
b65233a9 JR |
356 | /* |
357 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
358 | * id which we need to handle. This is the first of three functions which parse | |
359 | * the ACPI table. So we check the checksum here. | |
360 | */ | |
3e8064ba JR |
361 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
362 | { | |
363 | int i; | |
364 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
365 | struct ivhd_header *h; | |
366 | ||
367 | /* | |
368 | * Validate checksum here so we don't need to do it when | |
369 | * we actually parse the table | |
370 | */ | |
371 | for (i = 0; i < table->length; ++i) | |
372 | checksum += p[i]; | |
373 | if (checksum != 0) | |
374 | /* ACPI table corrupt */ | |
375 | return -ENODEV; | |
376 | ||
377 | p += IVRS_HEADER_LENGTH; | |
378 | ||
379 | end += table->length; | |
380 | while (p < end) { | |
381 | h = (struct ivhd_header *)p; | |
382 | switch (h->type) { | |
383 | case ACPI_IVHD_TYPE: | |
384 | find_last_devid_from_ivhd(h); | |
385 | break; | |
386 | default: | |
387 | break; | |
388 | } | |
389 | p += h->length; | |
390 | } | |
391 | WARN_ON(p != end); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
b65233a9 JR |
396 | /**************************************************************************** |
397 | * | |
398 | * The following functions belong the the code path which parses the ACPI table | |
399 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
400 | * data structures, initialize the device/alias/rlookup table and also | |
401 | * basically initialize the hardware. | |
402 | * | |
403 | ****************************************************************************/ | |
404 | ||
405 | /* | |
406 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
407 | * write commands to that buffer later and the IOMMU will execute them | |
408 | * asynchronously | |
409 | */ | |
b36ca91e JR |
410 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
411 | { | |
d0312b21 | 412 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 413 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
414 | |
415 | if (cmd_buf == NULL) | |
416 | return NULL; | |
417 | ||
418 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
419 | ||
58492e12 JR |
420 | return cmd_buf; |
421 | } | |
422 | ||
423 | /* | |
424 | * This function writes the command buffer address to the hardware and | |
425 | * enables it. | |
426 | */ | |
427 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
428 | { | |
429 | u64 entry; | |
430 | ||
431 | BUG_ON(iommu->cmd_buf == NULL); | |
432 | ||
433 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 434 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 435 | |
b36ca91e | 436 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 437 | &entry, sizeof(entry)); |
b36ca91e | 438 | |
cf558d25 JR |
439 | /* set head and tail to zero manually */ |
440 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
441 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
442 | ||
b36ca91e | 443 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); |
b36ca91e JR |
444 | } |
445 | ||
446 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
447 | { | |
23c1713f JR |
448 | free_pages((unsigned long)iommu->cmd_buf, |
449 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
450 | } |
451 | ||
335503e5 JR |
452 | /* allocates the memory where the IOMMU will log its events to */ |
453 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
454 | { | |
335503e5 JR |
455 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
456 | get_order(EVT_BUFFER_SIZE)); | |
457 | ||
458 | if (iommu->evt_buf == NULL) | |
459 | return NULL; | |
460 | ||
58492e12 JR |
461 | return iommu->evt_buf; |
462 | } | |
463 | ||
464 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
465 | { | |
466 | u64 entry; | |
467 | ||
468 | BUG_ON(iommu->evt_buf == NULL); | |
469 | ||
335503e5 | 470 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 471 | |
335503e5 JR |
472 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
473 | &entry, sizeof(entry)); | |
474 | ||
58492e12 | 475 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
476 | } |
477 | ||
478 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
479 | { | |
480 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
481 | } | |
482 | ||
b65233a9 | 483 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
484 | static void set_dev_entry_bit(u16 devid, u8 bit) |
485 | { | |
486 | int i = (bit >> 5) & 0x07; | |
487 | int _bit = bit & 0x1f; | |
488 | ||
489 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
490 | } | |
491 | ||
5ff4789d JR |
492 | /* Writes the specific IOMMU for a device into the rlookup table */ |
493 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
494 | { | |
495 | amd_iommu_rlookup_table[devid] = iommu; | |
496 | } | |
497 | ||
b65233a9 JR |
498 | /* |
499 | * This function takes the device specific flags read from the ACPI | |
500 | * table and sets up the device table entry with that information | |
501 | */ | |
5ff4789d JR |
502 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
503 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
504 | { |
505 | if (flags & ACPI_DEVFLAG_INITPASS) | |
506 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
507 | if (flags & ACPI_DEVFLAG_EXTINT) | |
508 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
509 | if (flags & ACPI_DEVFLAG_NMI) | |
510 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
511 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
512 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
513 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
514 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
515 | if (flags & ACPI_DEVFLAG_LINT0) | |
516 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
517 | if (flags & ACPI_DEVFLAG_LINT1) | |
518 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 519 | |
5ff4789d | 520 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
521 | } |
522 | ||
b65233a9 JR |
523 | /* |
524 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
525 | * it | |
526 | */ | |
3566b778 JR |
527 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
528 | { | |
529 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
530 | ||
531 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
532 | return; | |
533 | ||
534 | if (iommu) { | |
b65233a9 JR |
535 | /* |
536 | * We only can configure exclusion ranges per IOMMU, not | |
537 | * per device. But we can enable the exclusion range per | |
538 | * device. This is done here | |
539 | */ | |
3566b778 JR |
540 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
541 | iommu->exclusion_start = m->range_start; | |
542 | iommu->exclusion_length = m->range_length; | |
543 | } | |
544 | } | |
545 | ||
b65233a9 JR |
546 | /* |
547 | * This function reads some important data from the IOMMU PCI space and | |
548 | * initializes the driver data structure with it. It reads the hardware | |
549 | * capabilities and the first/last device entries | |
550 | */ | |
5d0c8e49 JR |
551 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
552 | { | |
5d0c8e49 | 553 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 554 | u32 range, misc; |
5d0c8e49 | 555 | |
3eaf28a1 JR |
556 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
557 | &iommu->cap); | |
558 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
559 | &range); | |
a80dc3e0 JR |
560 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
561 | &misc); | |
5d0c8e49 | 562 | |
d591b0a3 JR |
563 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
564 | MMIO_GET_FD(range)); | |
565 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
566 | MMIO_GET_LD(range)); | |
a80dc3e0 | 567 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
568 | } |
569 | ||
b65233a9 JR |
570 | /* |
571 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
572 | * initializes the hardware and our data structures with it. | |
573 | */ | |
5d0c8e49 JR |
574 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
575 | struct ivhd_header *h) | |
576 | { | |
577 | u8 *p = (u8 *)h; | |
578 | u8 *end = p, flags = 0; | |
579 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
580 | u32 ext_flags = 0; | |
58a3bee5 | 581 | bool alias = false; |
5d0c8e49 JR |
582 | struct ivhd_entry *e; |
583 | ||
584 | /* | |
585 | * First set the recommended feature enable bits from ACPI | |
586 | * into the IOMMU control registers | |
587 | */ | |
6da7342f | 588 | h->flags & IVHD_FLAG_HT_TUN_EN_MASK ? |
5d0c8e49 JR |
589 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : |
590 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
591 | ||
6da7342f | 592 | h->flags & IVHD_FLAG_PASSPW_EN_MASK ? |
5d0c8e49 JR |
593 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : |
594 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
595 | ||
6da7342f | 596 | h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ? |
5d0c8e49 JR |
597 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : |
598 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
599 | ||
6da7342f | 600 | h->flags & IVHD_FLAG_ISOC_EN_MASK ? |
5d0c8e49 JR |
601 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : |
602 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
603 | ||
604 | /* | |
605 | * make IOMMU memory accesses cache coherent | |
606 | */ | |
607 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
608 | ||
609 | /* | |
610 | * Done. Now parse the device entries | |
611 | */ | |
612 | p += sizeof(struct ivhd_header); | |
613 | end += h->length; | |
614 | ||
615 | while (p < end) { | |
616 | e = (struct ivhd_entry *)p; | |
617 | switch (e->type) { | |
618 | case IVHD_DEV_ALL: | |
619 | for (dev_i = iommu->first_device; | |
620 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
621 | set_dev_entry_from_acpi(iommu, dev_i, |
622 | e->flags, 0); | |
5d0c8e49 JR |
623 | break; |
624 | case IVHD_DEV_SELECT: | |
625 | devid = e->devid; | |
5ff4789d | 626 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
627 | break; |
628 | case IVHD_DEV_SELECT_RANGE_START: | |
629 | devid_start = e->devid; | |
630 | flags = e->flags; | |
631 | ext_flags = 0; | |
58a3bee5 | 632 | alias = false; |
5d0c8e49 JR |
633 | break; |
634 | case IVHD_DEV_ALIAS: | |
635 | devid = e->devid; | |
636 | devid_to = e->ext >> 8; | |
5ff4789d | 637 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
638 | amd_iommu_alias_table[devid] = devid_to; |
639 | break; | |
640 | case IVHD_DEV_ALIAS_RANGE: | |
641 | devid_start = e->devid; | |
642 | flags = e->flags; | |
643 | devid_to = e->ext >> 8; | |
644 | ext_flags = 0; | |
58a3bee5 | 645 | alias = true; |
5d0c8e49 JR |
646 | break; |
647 | case IVHD_DEV_EXT_SELECT: | |
648 | devid = e->devid; | |
5ff4789d JR |
649 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
650 | e->ext); | |
5d0c8e49 JR |
651 | break; |
652 | case IVHD_DEV_EXT_SELECT_RANGE: | |
653 | devid_start = e->devid; | |
654 | flags = e->flags; | |
655 | ext_flags = e->ext; | |
58a3bee5 | 656 | alias = false; |
5d0c8e49 JR |
657 | break; |
658 | case IVHD_DEV_RANGE_END: | |
659 | devid = e->devid; | |
660 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
661 | if (alias) | |
662 | amd_iommu_alias_table[dev_i] = devid_to; | |
5ff4789d | 663 | set_dev_entry_from_acpi(iommu, |
5d0c8e49 JR |
664 | amd_iommu_alias_table[dev_i], |
665 | flags, ext_flags); | |
666 | } | |
667 | break; | |
668 | default: | |
669 | break; | |
670 | } | |
671 | ||
b514e555 | 672 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
673 | } |
674 | } | |
675 | ||
b65233a9 | 676 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
677 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
678 | { | |
679 | u16 i; | |
680 | ||
681 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
682 | set_iommu_for_device(iommu, i); | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
e47d402d JR |
687 | static void __init free_iommu_one(struct amd_iommu *iommu) |
688 | { | |
689 | free_command_buffer(iommu); | |
335503e5 | 690 | free_event_buffer(iommu); |
e47d402d JR |
691 | iommu_unmap_mmio_space(iommu); |
692 | } | |
693 | ||
694 | static void __init free_iommu_all(void) | |
695 | { | |
696 | struct amd_iommu *iommu, *next; | |
697 | ||
3bd22172 | 698 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
699 | list_del(&iommu->list); |
700 | free_iommu_one(iommu); | |
701 | kfree(iommu); | |
702 | } | |
703 | } | |
704 | ||
b65233a9 JR |
705 | /* |
706 | * This function clues the initialization function for one IOMMU | |
707 | * together and also allocates the command buffer and programs the | |
708 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
709 | */ | |
e47d402d JR |
710 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
711 | { | |
712 | spin_lock_init(&iommu->lock); | |
713 | list_add_tail(&iommu->list, &amd_iommu_list); | |
714 | ||
715 | /* | |
716 | * Copy data from ACPI table entry to the iommu struct | |
717 | */ | |
3eaf28a1 JR |
718 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
719 | if (!iommu->dev) | |
720 | return 1; | |
721 | ||
e47d402d | 722 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 723 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
724 | iommu->mmio_phys = h->mmio_phys; |
725 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
726 | if (!iommu->mmio_base) | |
727 | return -ENOMEM; | |
728 | ||
e47d402d JR |
729 | iommu->cmd_buf = alloc_command_buffer(iommu); |
730 | if (!iommu->cmd_buf) | |
731 | return -ENOMEM; | |
732 | ||
335503e5 JR |
733 | iommu->evt_buf = alloc_event_buffer(iommu); |
734 | if (!iommu->evt_buf) | |
735 | return -ENOMEM; | |
736 | ||
a80dc3e0 JR |
737 | iommu->int_enabled = false; |
738 | ||
e47d402d JR |
739 | init_iommu_from_pci(iommu); |
740 | init_iommu_from_acpi(iommu, h); | |
741 | init_iommu_devices(iommu); | |
742 | ||
8a66712b | 743 | return pci_enable_device(iommu->dev); |
e47d402d JR |
744 | } |
745 | ||
b65233a9 JR |
746 | /* |
747 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
748 | * IOMMU structure and initializes it with init_iommu_one() | |
749 | */ | |
e47d402d JR |
750 | static int __init init_iommu_all(struct acpi_table_header *table) |
751 | { | |
752 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
753 | struct ivhd_header *h; | |
754 | struct amd_iommu *iommu; | |
755 | int ret; | |
756 | ||
e47d402d JR |
757 | end += table->length; |
758 | p += IVRS_HEADER_LENGTH; | |
759 | ||
760 | while (p < end) { | |
761 | h = (struct ivhd_header *)p; | |
762 | switch (*p) { | |
763 | case ACPI_IVHD_TYPE: | |
764 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
765 | if (iommu == NULL) | |
766 | return -ENOMEM; | |
767 | ret = init_iommu_one(iommu, h); | |
768 | if (ret) | |
769 | return ret; | |
770 | break; | |
771 | default: | |
772 | break; | |
773 | } | |
774 | p += h->length; | |
775 | ||
776 | } | |
777 | WARN_ON(p != end); | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
a80dc3e0 JR |
782 | /**************************************************************************** |
783 | * | |
784 | * The following functions initialize the MSI interrupts for all IOMMUs | |
785 | * in the system. Its a bit challenging because there could be multiple | |
786 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
787 | * pci_dev. | |
788 | * | |
789 | ****************************************************************************/ | |
790 | ||
a80dc3e0 JR |
791 | static int __init iommu_setup_msi(struct amd_iommu *iommu) |
792 | { | |
793 | int r; | |
a80dc3e0 JR |
794 | |
795 | if (pci_enable_msi(iommu->dev)) | |
796 | return 1; | |
797 | ||
798 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
799 | IRQF_SAMPLE_RANDOM, | |
800 | "AMD IOMMU", | |
801 | NULL); | |
802 | ||
803 | if (r) { | |
804 | pci_disable_msi(iommu->dev); | |
805 | return 1; | |
806 | } | |
807 | ||
fab6afa3 | 808 | iommu->int_enabled = true; |
58492e12 JR |
809 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
810 | ||
a80dc3e0 JR |
811 | return 0; |
812 | } | |
813 | ||
05f92db9 | 814 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
815 | { |
816 | if (iommu->int_enabled) | |
817 | return 0; | |
818 | ||
d91cecdd | 819 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
820 | return iommu_setup_msi(iommu); |
821 | ||
822 | return 1; | |
823 | } | |
824 | ||
b65233a9 JR |
825 | /**************************************************************************** |
826 | * | |
827 | * The next functions belong to the third pass of parsing the ACPI | |
828 | * table. In this last pass the memory mapping requirements are | |
829 | * gathered (like exclusion and unity mapping reanges). | |
830 | * | |
831 | ****************************************************************************/ | |
832 | ||
be2a022c JR |
833 | static void __init free_unity_maps(void) |
834 | { | |
835 | struct unity_map_entry *entry, *next; | |
836 | ||
837 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
838 | list_del(&entry->list); | |
839 | kfree(entry); | |
840 | } | |
841 | } | |
842 | ||
b65233a9 | 843 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
844 | static int __init init_exclusion_range(struct ivmd_header *m) |
845 | { | |
846 | int i; | |
847 | ||
848 | switch (m->type) { | |
849 | case ACPI_IVMD_TYPE: | |
850 | set_device_exclusion_range(m->devid, m); | |
851 | break; | |
852 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 853 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
854 | set_device_exclusion_range(i, m); |
855 | break; | |
856 | case ACPI_IVMD_TYPE_RANGE: | |
857 | for (i = m->devid; i <= m->aux; ++i) | |
858 | set_device_exclusion_range(i, m); | |
859 | break; | |
860 | default: | |
861 | break; | |
862 | } | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
b65233a9 | 867 | /* called for unity map ACPI definition */ |
be2a022c JR |
868 | static int __init init_unity_map_range(struct ivmd_header *m) |
869 | { | |
870 | struct unity_map_entry *e = 0; | |
871 | ||
872 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
873 | if (e == NULL) | |
874 | return -ENOMEM; | |
875 | ||
876 | switch (m->type) { | |
877 | default: | |
878 | case ACPI_IVMD_TYPE: | |
879 | e->devid_start = e->devid_end = m->devid; | |
880 | break; | |
881 | case ACPI_IVMD_TYPE_ALL: | |
882 | e->devid_start = 0; | |
883 | e->devid_end = amd_iommu_last_bdf; | |
884 | break; | |
885 | case ACPI_IVMD_TYPE_RANGE: | |
886 | e->devid_start = m->devid; | |
887 | e->devid_end = m->aux; | |
888 | break; | |
889 | } | |
890 | e->address_start = PAGE_ALIGN(m->range_start); | |
891 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
892 | e->prot = m->flags >> 1; | |
893 | ||
894 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
b65233a9 | 899 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
900 | static int __init init_memory_definitions(struct acpi_table_header *table) |
901 | { | |
902 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
903 | struct ivmd_header *m; | |
904 | ||
be2a022c JR |
905 | end += table->length; |
906 | p += IVRS_HEADER_LENGTH; | |
907 | ||
908 | while (p < end) { | |
909 | m = (struct ivmd_header *)p; | |
910 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
911 | init_exclusion_range(m); | |
912 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
913 | init_unity_map_range(m); | |
914 | ||
915 | p += m->length; | |
916 | } | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
9f5f5fb3 JR |
921 | /* |
922 | * Init the device table to not allow DMA access for devices and | |
923 | * suppress all page faults | |
924 | */ | |
925 | static void init_device_table(void) | |
926 | { | |
927 | u16 devid; | |
928 | ||
929 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
930 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
931 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
932 | } |
933 | } | |
934 | ||
b65233a9 JR |
935 | /* |
936 | * This function finally enables all IOMMUs found in the system after | |
937 | * they have been initialized | |
938 | */ | |
05f92db9 | 939 | static void enable_iommus(void) |
8736197b JR |
940 | { |
941 | struct amd_iommu *iommu; | |
942 | ||
3bd22172 | 943 | for_each_iommu(iommu) { |
58492e12 JR |
944 | iommu_set_device_table(iommu); |
945 | iommu_enable_command_buffer(iommu); | |
946 | iommu_enable_event_buffer(iommu); | |
8736197b | 947 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 948 | iommu_init_msi(iommu); |
8736197b JR |
949 | iommu_enable(iommu); |
950 | } | |
951 | } | |
952 | ||
92ac4320 JR |
953 | static void disable_iommus(void) |
954 | { | |
955 | struct amd_iommu *iommu; | |
956 | ||
957 | for_each_iommu(iommu) | |
958 | iommu_disable(iommu); | |
959 | } | |
960 | ||
7441e9cb JR |
961 | /* |
962 | * Suspend/Resume support | |
963 | * disable suspend until real resume implemented | |
964 | */ | |
965 | ||
966 | static int amd_iommu_resume(struct sys_device *dev) | |
967 | { | |
968 | return 0; | |
969 | } | |
970 | ||
971 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
972 | { | |
973 | return -EINVAL; | |
974 | } | |
975 | ||
976 | static struct sysdev_class amd_iommu_sysdev_class = { | |
977 | .name = "amd_iommu", | |
978 | .suspend = amd_iommu_suspend, | |
979 | .resume = amd_iommu_resume, | |
980 | }; | |
981 | ||
982 | static struct sys_device device_amd_iommu = { | |
983 | .id = 0, | |
984 | .cls = &amd_iommu_sysdev_class, | |
985 | }; | |
986 | ||
b65233a9 JR |
987 | /* |
988 | * This is the core init function for AMD IOMMU hardware in the system. | |
989 | * This function is called from the generic x86 DMA layer initialization | |
990 | * code. | |
991 | * | |
992 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
993 | * three times: | |
994 | * | |
995 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
996 | * Upon this information the size of the data structures is | |
997 | * determined that needs to be allocated. | |
998 | * | |
999 | * 2 pass) Initialize the data structures just allocated with the | |
1000 | * information in the ACPI table about available AMD IOMMUs | |
1001 | * in the system. It also maps the PCI devices in the | |
1002 | * system to specific IOMMUs | |
1003 | * | |
1004 | * 3 pass) After the basic data structures are allocated and | |
1005 | * initialized we update them with information about memory | |
1006 | * remapping requirements parsed out of the ACPI table in | |
1007 | * this last pass. | |
1008 | * | |
1009 | * After that the hardware is initialized and ready to go. In the last | |
1010 | * step we do some Linux specific things like registering the driver in | |
1011 | * the dma_ops interface and initializing the suspend/resume support | |
1012 | * functions. Finally it prints some information about AMD IOMMUs and | |
1013 | * the driver state and enables the hardware. | |
1014 | */ | |
fe74c9cf JR |
1015 | int __init amd_iommu_init(void) |
1016 | { | |
1017 | int i, ret = 0; | |
1018 | ||
1019 | ||
8b14518f | 1020 | if (no_iommu) { |
fe74c9cf JR |
1021 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
1022 | return 0; | |
1023 | } | |
1024 | ||
c1cbebee JR |
1025 | if (!amd_iommu_detected) |
1026 | return -ENODEV; | |
1027 | ||
fe74c9cf JR |
1028 | /* |
1029 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1030 | * we need to handle. Upon this information the shared data | |
1031 | * structures for the IOMMUs in the system will be allocated | |
1032 | */ | |
1033 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1034 | return -ENODEV; | |
1035 | ||
c571484e JR |
1036 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1037 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1038 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1039 | |
1040 | ret = -ENOMEM; | |
1041 | ||
1042 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1043 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1044 | get_order(dev_table_size)); |
1045 | if (amd_iommu_dev_table == NULL) | |
1046 | goto out; | |
1047 | ||
1048 | /* | |
1049 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1050 | * IOMMU see for that device | |
1051 | */ | |
1052 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1053 | get_order(alias_table_size)); | |
1054 | if (amd_iommu_alias_table == NULL) | |
1055 | goto free; | |
1056 | ||
1057 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1058 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1059 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1060 | get_order(rlookup_table_size)); |
1061 | if (amd_iommu_rlookup_table == NULL) | |
1062 | goto free; | |
1063 | ||
1064 | /* | |
1065 | * Protection Domain table - maps devices to protection domains | |
1066 | * This table has the same size as the rlookup_table | |
1067 | */ | |
5dc8bff0 | 1068 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1069 | get_order(rlookup_table_size)); |
1070 | if (amd_iommu_pd_table == NULL) | |
1071 | goto free; | |
1072 | ||
5dc8bff0 JR |
1073 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1074 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1075 | get_order(MAX_DOMAIN_ID/8)); |
1076 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1077 | goto free; | |
1078 | ||
9f5f5fb3 JR |
1079 | /* init the device table */ |
1080 | init_device_table(); | |
1081 | ||
fe74c9cf | 1082 | /* |
5dc8bff0 | 1083 | * let all alias entries point to itself |
fe74c9cf | 1084 | */ |
3a61ec38 | 1085 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1086 | amd_iommu_alias_table[i] = i; |
1087 | ||
fe74c9cf JR |
1088 | /* |
1089 | * never allocate domain 0 because its used as the non-allocated and | |
1090 | * error value placeholder | |
1091 | */ | |
1092 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1093 | ||
1094 | /* | |
1095 | * now the data structures are allocated and basically initialized | |
1096 | * start the real acpi table scan | |
1097 | */ | |
1098 | ret = -ENODEV; | |
1099 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1100 | goto free; | |
1101 | ||
1102 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1103 | goto free; | |
1104 | ||
129d6aba | 1105 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1106 | if (ret) |
1107 | goto free; | |
1108 | ||
129d6aba | 1109 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1110 | if (ret) |
1111 | goto free; | |
1112 | ||
129d6aba | 1113 | ret = amd_iommu_init_dma_ops(); |
7441e9cb JR |
1114 | if (ret) |
1115 | goto free; | |
1116 | ||
8736197b JR |
1117 | enable_iommus(); |
1118 | ||
fe74c9cf JR |
1119 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
1120 | (1 << (amd_iommu_aperture_order-20))); | |
1121 | ||
1122 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
1123 | if (amd_iommu_isolate) | |
1124 | printk("enabled\n"); | |
1125 | else | |
1126 | printk("disabled\n"); | |
1127 | ||
afa9fdc2 | 1128 | if (amd_iommu_unmap_flush) |
1c655773 JR |
1129 | printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n"); |
1130 | else | |
1131 | printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n"); | |
1132 | ||
fe74c9cf JR |
1133 | out: |
1134 | return ret; | |
1135 | ||
1136 | free: | |
d58befd3 JR |
1137 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1138 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1139 | |
9a836de0 JR |
1140 | free_pages((unsigned long)amd_iommu_pd_table, |
1141 | get_order(rlookup_table_size)); | |
fe74c9cf | 1142 | |
9a836de0 JR |
1143 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1144 | get_order(rlookup_table_size)); | |
fe74c9cf | 1145 | |
9a836de0 JR |
1146 | free_pages((unsigned long)amd_iommu_alias_table, |
1147 | get_order(alias_table_size)); | |
fe74c9cf | 1148 | |
9a836de0 JR |
1149 | free_pages((unsigned long)amd_iommu_dev_table, |
1150 | get_order(dev_table_size)); | |
fe74c9cf JR |
1151 | |
1152 | free_iommu_all(); | |
1153 | ||
1154 | free_unity_maps(); | |
1155 | ||
1156 | goto out; | |
1157 | } | |
1158 | ||
b65233a9 JR |
1159 | /**************************************************************************** |
1160 | * | |
1161 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1162 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1163 | * IOMMUs | |
1164 | * | |
1165 | ****************************************************************************/ | |
ae7877de JR |
1166 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1167 | { | |
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | void __init amd_iommu_detect(void) | |
1172 | { | |
299a140d | 1173 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1174 | return; |
1175 | ||
ae7877de JR |
1176 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1177 | iommu_detected = 1; | |
c1cbebee | 1178 | amd_iommu_detected = 1; |
92af4e29 | 1179 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1180 | gart_iommu_aperture_disabled = 1; |
1181 | gart_iommu_aperture = 0; | |
92af4e29 | 1182 | #endif |
ae7877de JR |
1183 | } |
1184 | } | |
1185 | ||
b65233a9 JR |
1186 | /**************************************************************************** |
1187 | * | |
1188 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1189 | * options. | |
1190 | * | |
1191 | ****************************************************************************/ | |
1192 | ||
918ad6c5 JR |
1193 | static int __init parse_amd_iommu_options(char *str) |
1194 | { | |
1195 | for (; *str; ++str) { | |
1c655773 | 1196 | if (strncmp(str, "isolate", 7) == 0) |
c226f853 | 1197 | amd_iommu_isolate = true; |
e5e1f606 | 1198 | if (strncmp(str, "share", 5) == 0) |
c226f853 | 1199 | amd_iommu_isolate = false; |
695b5676 | 1200 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1201 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1202 | } |
1203 | ||
1204 | return 1; | |
1205 | } | |
1206 | ||
1207 | static int __init parse_amd_iommu_size_options(char *str) | |
1208 | { | |
0906372e JR |
1209 | unsigned order = PAGE_SHIFT + get_order(memparse(str, &str)); |
1210 | ||
1211 | if ((order > 24) && (order < 31)) | |
1212 | amd_iommu_aperture_order = order; | |
918ad6c5 JR |
1213 | |
1214 | return 1; | |
1215 | } | |
1216 | ||
1217 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1218 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |