Commit | Line | Data |
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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
f6e2e6b6 JR |
32 | |
33 | /* | |
34 | * definitions for the ACPI scanning code | |
35 | */ | |
f6e2e6b6 | 36 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
37 | |
38 | #define ACPI_IVHD_TYPE 0x10 | |
39 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
40 | #define ACPI_IVMD_TYPE 0x21 | |
41 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
42 | ||
43 | #define IVHD_DEV_ALL 0x01 | |
44 | #define IVHD_DEV_SELECT 0x02 | |
45 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
46 | #define IVHD_DEV_RANGE_END 0x04 | |
47 | #define IVHD_DEV_ALIAS 0x42 | |
48 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
49 | #define IVHD_DEV_EXT_SELECT 0x46 | |
50 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
51 | ||
52 | #define IVHD_FLAG_HT_TUN_EN 0x00 | |
53 | #define IVHD_FLAG_PASSPW_EN 0x01 | |
54 | #define IVHD_FLAG_RESPASSPW_EN 0x02 | |
55 | #define IVHD_FLAG_ISOC_EN 0x03 | |
56 | ||
57 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
58 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
59 | ||
60 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
61 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
62 | #define ACPI_DEVFLAG_NMI 0x04 | |
63 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
64 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
65 | #define ACPI_DEVFLAG_LINT0 0x40 | |
66 | #define ACPI_DEVFLAG_LINT1 0x80 | |
67 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
68 | ||
b65233a9 JR |
69 | /* |
70 | * ACPI table definitions | |
71 | * | |
72 | * These data structures are laid over the table to parse the important values | |
73 | * out of it. | |
74 | */ | |
75 | ||
76 | /* | |
77 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
78 | * or more ivhd_entrys. | |
79 | */ | |
f6e2e6b6 JR |
80 | struct ivhd_header { |
81 | u8 type; | |
82 | u8 flags; | |
83 | u16 length; | |
84 | u16 devid; | |
85 | u16 cap_ptr; | |
86 | u64 mmio_phys; | |
87 | u16 pci_seg; | |
88 | u16 info; | |
89 | u32 reserved; | |
90 | } __attribute__((packed)); | |
91 | ||
b65233a9 JR |
92 | /* |
93 | * A device entry describing which devices a specific IOMMU translates and | |
94 | * which requestor ids they use. | |
95 | */ | |
f6e2e6b6 JR |
96 | struct ivhd_entry { |
97 | u8 type; | |
98 | u16 devid; | |
99 | u8 flags; | |
100 | u32 ext; | |
101 | } __attribute__((packed)); | |
102 | ||
b65233a9 JR |
103 | /* |
104 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
105 | * ranges for devices and regions that should be unity mapped. | |
106 | */ | |
f6e2e6b6 JR |
107 | struct ivmd_header { |
108 | u8 type; | |
109 | u8 flags; | |
110 | u16 length; | |
111 | u16 devid; | |
112 | u16 aux; | |
113 | u64 resv; | |
114 | u64 range_start; | |
115 | u64 range_length; | |
116 | } __attribute__((packed)); | |
117 | ||
c1cbebee JR |
118 | static int __initdata amd_iommu_detected; |
119 | ||
b65233a9 JR |
120 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
121 | to handle */ | |
2e22847f | 122 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 JR |
123 | we find in ACPI */ |
124 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
3ce1f93c | 125 | int amd_iommu_isolate = 1; /* if 1, device isolation is enabled */ |
afa9fdc2 | 126 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 127 | |
2e22847f | 128 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 129 | system */ |
928abd25 | 130 | |
b65233a9 JR |
131 | /* |
132 | * Pointer to the device table which is shared by all AMD IOMMUs | |
133 | * it is indexed by the PCI device id or the HT unit id and contains | |
134 | * information about the domain the device belongs to as well as the | |
135 | * page table root pointer. | |
136 | */ | |
928abd25 | 137 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
138 | |
139 | /* | |
140 | * The alias table is a driver specific data structure which contains the | |
141 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
142 | * More than one device can share the same requestor id. | |
143 | */ | |
928abd25 | 144 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
145 | |
146 | /* | |
147 | * The rlookup table is used to find the IOMMU which is responsible | |
148 | * for a specific device. It is also indexed by the PCI device id. | |
149 | */ | |
928abd25 | 150 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
151 | |
152 | /* | |
153 | * The pd table (protection domain table) is used to find the protection domain | |
154 | * data structure a device belongs to. Indexed with the PCI device id too. | |
155 | */ | |
928abd25 | 156 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
157 | |
158 | /* | |
159 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
160 | * to know which ones are already in use. | |
161 | */ | |
928abd25 JR |
162 | unsigned long *amd_iommu_pd_alloc_bitmap; |
163 | ||
b65233a9 JR |
164 | static u32 dev_table_size; /* size of the device table */ |
165 | static u32 alias_table_size; /* size of the alias table */ | |
166 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 167 | |
208ec8c9 JR |
168 | static inline void update_last_devid(u16 devid) |
169 | { | |
170 | if (devid > amd_iommu_last_bdf) | |
171 | amd_iommu_last_bdf = devid; | |
172 | } | |
173 | ||
c571484e JR |
174 | static inline unsigned long tbl_size(int entry_size) |
175 | { | |
176 | unsigned shift = PAGE_SHIFT + | |
177 | get_order(amd_iommu_last_bdf * entry_size); | |
178 | ||
179 | return 1UL << shift; | |
180 | } | |
181 | ||
b65233a9 JR |
182 | /**************************************************************************** |
183 | * | |
184 | * AMD IOMMU MMIO register space handling functions | |
185 | * | |
186 | * These functions are used to program the IOMMU device registers in | |
187 | * MMIO space required for that driver. | |
188 | * | |
189 | ****************************************************************************/ | |
3e8064ba | 190 | |
b65233a9 JR |
191 | /* |
192 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
193 | * exclusion range are passed through untranslated | |
194 | */ | |
b2026aa2 JR |
195 | static void __init iommu_set_exclusion_range(struct amd_iommu *iommu) |
196 | { | |
197 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
198 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
199 | u64 entry; | |
200 | ||
201 | if (!iommu->exclusion_start) | |
202 | return; | |
203 | ||
204 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
205 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
206 | &entry, sizeof(entry)); | |
207 | ||
208 | entry = limit; | |
209 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
210 | &entry, sizeof(entry)); | |
211 | } | |
212 | ||
b65233a9 | 213 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
214 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
215 | { | |
f609891f | 216 | u64 entry; |
b2026aa2 JR |
217 | |
218 | BUG_ON(iommu->mmio_base == NULL); | |
219 | ||
220 | entry = virt_to_phys(amd_iommu_dev_table); | |
221 | entry |= (dev_table_size >> 12) - 1; | |
222 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
223 | &entry, sizeof(entry)); | |
224 | } | |
225 | ||
b65233a9 | 226 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
b2026aa2 JR |
227 | static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
228 | { | |
229 | u32 ctrl; | |
230 | ||
231 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
232 | ctrl |= (1 << bit); | |
233 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
234 | } | |
235 | ||
236 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
237 | { | |
238 | u32 ctrl; | |
239 | ||
199d0d50 | 240 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
241 | ctrl &= ~(1 << bit); |
242 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
243 | } | |
244 | ||
b65233a9 | 245 | /* Function to enable the hardware */ |
b2026aa2 JR |
246 | void __init iommu_enable(struct amd_iommu *iommu) |
247 | { | |
3eaf28a1 JR |
248 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU " |
249 | "at %02x:%02x.%x cap 0x%hx\n", | |
250 | iommu->dev->bus->number, | |
251 | PCI_SLOT(iommu->dev->devfn), | |
252 | PCI_FUNC(iommu->dev->devfn), | |
253 | iommu->cap_ptr); | |
b2026aa2 JR |
254 | |
255 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
256 | } |
257 | ||
126c52be JR |
258 | /* Function to enable IOMMU event logging and event interrupts */ |
259 | void __init iommu_enable_event_logging(struct amd_iommu *iommu) | |
260 | { | |
261 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); | |
262 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
263 | } | |
264 | ||
b65233a9 JR |
265 | /* |
266 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
267 | * the system has one. | |
268 | */ | |
6c56747b JR |
269 | static u8 * __init iommu_map_mmio_space(u64 address) |
270 | { | |
271 | u8 *ret; | |
272 | ||
273 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
274 | return NULL; | |
275 | ||
276 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
277 | if (ret != NULL) | |
278 | return ret; | |
279 | ||
280 | release_mem_region(address, MMIO_REGION_LENGTH); | |
281 | ||
282 | return NULL; | |
283 | } | |
284 | ||
285 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
286 | { | |
287 | if (iommu->mmio_base) | |
288 | iounmap(iommu->mmio_base); | |
289 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
290 | } | |
291 | ||
b65233a9 JR |
292 | /**************************************************************************** |
293 | * | |
294 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
295 | * parsing. In this pass we try to find out the highest device id this | |
296 | * code has to handle. Upon this information the size of the shared data | |
297 | * structures is determined later. | |
298 | * | |
299 | ****************************************************************************/ | |
300 | ||
b514e555 JR |
301 | /* |
302 | * This function calculates the length of a given IVHD entry | |
303 | */ | |
304 | static inline int ivhd_entry_length(u8 *ivhd) | |
305 | { | |
306 | return 0x04 << (*ivhd >> 6); | |
307 | } | |
308 | ||
b65233a9 JR |
309 | /* |
310 | * This function reads the last device id the IOMMU has to handle from the PCI | |
311 | * capability header for this IOMMU | |
312 | */ | |
3e8064ba JR |
313 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
314 | { | |
315 | u32 cap; | |
316 | ||
317 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 318 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
319 | |
320 | return 0; | |
321 | } | |
322 | ||
b65233a9 JR |
323 | /* |
324 | * After reading the highest device id from the IOMMU PCI capability header | |
325 | * this function looks if there is a higher device id defined in the ACPI table | |
326 | */ | |
3e8064ba JR |
327 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
328 | { | |
329 | u8 *p = (void *)h, *end = (void *)h; | |
330 | struct ivhd_entry *dev; | |
331 | ||
332 | p += sizeof(*h); | |
333 | end += h->length; | |
334 | ||
335 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
336 | PCI_SLOT(h->devid), | |
337 | PCI_FUNC(h->devid), | |
338 | h->cap_ptr); | |
339 | ||
340 | while (p < end) { | |
341 | dev = (struct ivhd_entry *)p; | |
342 | switch (dev->type) { | |
343 | case IVHD_DEV_SELECT: | |
344 | case IVHD_DEV_RANGE_END: | |
345 | case IVHD_DEV_ALIAS: | |
346 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 347 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 348 | update_last_devid(dev->devid); |
3e8064ba JR |
349 | break; |
350 | default: | |
351 | break; | |
352 | } | |
b514e555 | 353 | p += ivhd_entry_length(p); |
3e8064ba JR |
354 | } |
355 | ||
356 | WARN_ON(p != end); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
b65233a9 JR |
361 | /* |
362 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
363 | * id which we need to handle. This is the first of three functions which parse | |
364 | * the ACPI table. So we check the checksum here. | |
365 | */ | |
3e8064ba JR |
366 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
367 | { | |
368 | int i; | |
369 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
370 | struct ivhd_header *h; | |
371 | ||
372 | /* | |
373 | * Validate checksum here so we don't need to do it when | |
374 | * we actually parse the table | |
375 | */ | |
376 | for (i = 0; i < table->length; ++i) | |
377 | checksum += p[i]; | |
378 | if (checksum != 0) | |
379 | /* ACPI table corrupt */ | |
380 | return -ENODEV; | |
381 | ||
382 | p += IVRS_HEADER_LENGTH; | |
383 | ||
384 | end += table->length; | |
385 | while (p < end) { | |
386 | h = (struct ivhd_header *)p; | |
387 | switch (h->type) { | |
388 | case ACPI_IVHD_TYPE: | |
389 | find_last_devid_from_ivhd(h); | |
390 | break; | |
391 | default: | |
392 | break; | |
393 | } | |
394 | p += h->length; | |
395 | } | |
396 | WARN_ON(p != end); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
b65233a9 JR |
401 | /**************************************************************************** |
402 | * | |
403 | * The following functions belong the the code path which parses the ACPI table | |
404 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
405 | * data structures, initialize the device/alias/rlookup table and also | |
406 | * basically initialize the hardware. | |
407 | * | |
408 | ****************************************************************************/ | |
409 | ||
410 | /* | |
411 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
412 | * write commands to that buffer later and the IOMMU will execute them | |
413 | * asynchronously | |
414 | */ | |
b36ca91e JR |
415 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
416 | { | |
d0312b21 | 417 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 418 | get_order(CMD_BUFFER_SIZE)); |
d0312b21 | 419 | u64 entry; |
b36ca91e JR |
420 | |
421 | if (cmd_buf == NULL) | |
422 | return NULL; | |
423 | ||
424 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
425 | ||
b36ca91e JR |
426 | entry = (u64)virt_to_phys(cmd_buf); |
427 | entry |= MMIO_CMD_SIZE_512; | |
428 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, | |
429 | &entry, sizeof(entry)); | |
430 | ||
cf558d25 JR |
431 | /* set head and tail to zero manually */ |
432 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
433 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
434 | ||
b36ca91e JR |
435 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); |
436 | ||
437 | return cmd_buf; | |
438 | } | |
439 | ||
440 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
441 | { | |
23c1713f JR |
442 | free_pages((unsigned long)iommu->cmd_buf, |
443 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
444 | } |
445 | ||
335503e5 JR |
446 | /* allocates the memory where the IOMMU will log its events to */ |
447 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
448 | { | |
449 | u64 entry; | |
450 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
451 | get_order(EVT_BUFFER_SIZE)); | |
452 | ||
453 | if (iommu->evt_buf == NULL) | |
454 | return NULL; | |
455 | ||
456 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; | |
457 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, | |
458 | &entry, sizeof(entry)); | |
459 | ||
460 | iommu->evt_buf_size = EVT_BUFFER_SIZE; | |
461 | ||
462 | return iommu->evt_buf; | |
463 | } | |
464 | ||
465 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
466 | { | |
467 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
468 | } | |
469 | ||
b65233a9 | 470 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
471 | static void set_dev_entry_bit(u16 devid, u8 bit) |
472 | { | |
473 | int i = (bit >> 5) & 0x07; | |
474 | int _bit = bit & 0x1f; | |
475 | ||
476 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
477 | } | |
478 | ||
5ff4789d JR |
479 | /* Writes the specific IOMMU for a device into the rlookup table */ |
480 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
481 | { | |
482 | amd_iommu_rlookup_table[devid] = iommu; | |
483 | } | |
484 | ||
b65233a9 JR |
485 | /* |
486 | * This function takes the device specific flags read from the ACPI | |
487 | * table and sets up the device table entry with that information | |
488 | */ | |
5ff4789d JR |
489 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
490 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
491 | { |
492 | if (flags & ACPI_DEVFLAG_INITPASS) | |
493 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
494 | if (flags & ACPI_DEVFLAG_EXTINT) | |
495 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
496 | if (flags & ACPI_DEVFLAG_NMI) | |
497 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
498 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
499 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
500 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
501 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
502 | if (flags & ACPI_DEVFLAG_LINT0) | |
503 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
504 | if (flags & ACPI_DEVFLAG_LINT1) | |
505 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 506 | |
5ff4789d | 507 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
508 | } |
509 | ||
b65233a9 JR |
510 | /* |
511 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
512 | * it | |
513 | */ | |
3566b778 JR |
514 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
515 | { | |
516 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
517 | ||
518 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
519 | return; | |
520 | ||
521 | if (iommu) { | |
b65233a9 JR |
522 | /* |
523 | * We only can configure exclusion ranges per IOMMU, not | |
524 | * per device. But we can enable the exclusion range per | |
525 | * device. This is done here | |
526 | */ | |
3566b778 JR |
527 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
528 | iommu->exclusion_start = m->range_start; | |
529 | iommu->exclusion_length = m->range_length; | |
530 | } | |
531 | } | |
532 | ||
b65233a9 JR |
533 | /* |
534 | * This function reads some important data from the IOMMU PCI space and | |
535 | * initializes the driver data structure with it. It reads the hardware | |
536 | * capabilities and the first/last device entries | |
537 | */ | |
5d0c8e49 JR |
538 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
539 | { | |
5d0c8e49 | 540 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 541 | u32 range, misc; |
5d0c8e49 | 542 | |
3eaf28a1 JR |
543 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
544 | &iommu->cap); | |
545 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
546 | &range); | |
a80dc3e0 JR |
547 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
548 | &misc); | |
5d0c8e49 | 549 | |
d591b0a3 JR |
550 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
551 | MMIO_GET_FD(range)); | |
552 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
553 | MMIO_GET_LD(range)); | |
a80dc3e0 | 554 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
555 | } |
556 | ||
b65233a9 JR |
557 | /* |
558 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
559 | * initializes the hardware and our data structures with it. | |
560 | */ | |
5d0c8e49 JR |
561 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
562 | struct ivhd_header *h) | |
563 | { | |
564 | u8 *p = (u8 *)h; | |
565 | u8 *end = p, flags = 0; | |
566 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
567 | u32 ext_flags = 0; | |
58a3bee5 | 568 | bool alias = false; |
5d0c8e49 JR |
569 | struct ivhd_entry *e; |
570 | ||
571 | /* | |
572 | * First set the recommended feature enable bits from ACPI | |
573 | * into the IOMMU control registers | |
574 | */ | |
575 | h->flags & IVHD_FLAG_HT_TUN_EN ? | |
576 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
577 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
578 | ||
579 | h->flags & IVHD_FLAG_PASSPW_EN ? | |
580 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
581 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
582 | ||
583 | h->flags & IVHD_FLAG_RESPASSPW_EN ? | |
584 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
585 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
586 | ||
587 | h->flags & IVHD_FLAG_ISOC_EN ? | |
588 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
589 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
590 | ||
591 | /* | |
592 | * make IOMMU memory accesses cache coherent | |
593 | */ | |
594 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
595 | ||
596 | /* | |
597 | * Done. Now parse the device entries | |
598 | */ | |
599 | p += sizeof(struct ivhd_header); | |
600 | end += h->length; | |
601 | ||
602 | while (p < end) { | |
603 | e = (struct ivhd_entry *)p; | |
604 | switch (e->type) { | |
605 | case IVHD_DEV_ALL: | |
606 | for (dev_i = iommu->first_device; | |
607 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
608 | set_dev_entry_from_acpi(iommu, dev_i, |
609 | e->flags, 0); | |
5d0c8e49 JR |
610 | break; |
611 | case IVHD_DEV_SELECT: | |
612 | devid = e->devid; | |
5ff4789d | 613 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
614 | break; |
615 | case IVHD_DEV_SELECT_RANGE_START: | |
616 | devid_start = e->devid; | |
617 | flags = e->flags; | |
618 | ext_flags = 0; | |
58a3bee5 | 619 | alias = false; |
5d0c8e49 JR |
620 | break; |
621 | case IVHD_DEV_ALIAS: | |
622 | devid = e->devid; | |
623 | devid_to = e->ext >> 8; | |
5ff4789d | 624 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
625 | amd_iommu_alias_table[devid] = devid_to; |
626 | break; | |
627 | case IVHD_DEV_ALIAS_RANGE: | |
628 | devid_start = e->devid; | |
629 | flags = e->flags; | |
630 | devid_to = e->ext >> 8; | |
631 | ext_flags = 0; | |
58a3bee5 | 632 | alias = true; |
5d0c8e49 JR |
633 | break; |
634 | case IVHD_DEV_EXT_SELECT: | |
635 | devid = e->devid; | |
5ff4789d JR |
636 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
637 | e->ext); | |
5d0c8e49 JR |
638 | break; |
639 | case IVHD_DEV_EXT_SELECT_RANGE: | |
640 | devid_start = e->devid; | |
641 | flags = e->flags; | |
642 | ext_flags = e->ext; | |
58a3bee5 | 643 | alias = false; |
5d0c8e49 JR |
644 | break; |
645 | case IVHD_DEV_RANGE_END: | |
646 | devid = e->devid; | |
647 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
648 | if (alias) | |
649 | amd_iommu_alias_table[dev_i] = devid_to; | |
5ff4789d | 650 | set_dev_entry_from_acpi(iommu, |
5d0c8e49 JR |
651 | amd_iommu_alias_table[dev_i], |
652 | flags, ext_flags); | |
653 | } | |
654 | break; | |
655 | default: | |
656 | break; | |
657 | } | |
658 | ||
b514e555 | 659 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
660 | } |
661 | } | |
662 | ||
b65233a9 | 663 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
664 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
665 | { | |
666 | u16 i; | |
667 | ||
668 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
669 | set_iommu_for_device(iommu, i); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
e47d402d JR |
674 | static void __init free_iommu_one(struct amd_iommu *iommu) |
675 | { | |
676 | free_command_buffer(iommu); | |
335503e5 | 677 | free_event_buffer(iommu); |
e47d402d JR |
678 | iommu_unmap_mmio_space(iommu); |
679 | } | |
680 | ||
681 | static void __init free_iommu_all(void) | |
682 | { | |
683 | struct amd_iommu *iommu, *next; | |
684 | ||
685 | list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) { | |
686 | list_del(&iommu->list); | |
687 | free_iommu_one(iommu); | |
688 | kfree(iommu); | |
689 | } | |
690 | } | |
691 | ||
b65233a9 JR |
692 | /* |
693 | * This function clues the initialization function for one IOMMU | |
694 | * together and also allocates the command buffer and programs the | |
695 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
696 | */ | |
e47d402d JR |
697 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
698 | { | |
699 | spin_lock_init(&iommu->lock); | |
700 | list_add_tail(&iommu->list, &amd_iommu_list); | |
701 | ||
702 | /* | |
703 | * Copy data from ACPI table entry to the iommu struct | |
704 | */ | |
3eaf28a1 JR |
705 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
706 | if (!iommu->dev) | |
707 | return 1; | |
708 | ||
e47d402d | 709 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 710 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
711 | iommu->mmio_phys = h->mmio_phys; |
712 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
713 | if (!iommu->mmio_base) | |
714 | return -ENOMEM; | |
715 | ||
716 | iommu_set_device_table(iommu); | |
717 | iommu->cmd_buf = alloc_command_buffer(iommu); | |
718 | if (!iommu->cmd_buf) | |
719 | return -ENOMEM; | |
720 | ||
335503e5 JR |
721 | iommu->evt_buf = alloc_event_buffer(iommu); |
722 | if (!iommu->evt_buf) | |
723 | return -ENOMEM; | |
724 | ||
a80dc3e0 JR |
725 | iommu->int_enabled = false; |
726 | ||
e47d402d JR |
727 | init_iommu_from_pci(iommu); |
728 | init_iommu_from_acpi(iommu, h); | |
729 | init_iommu_devices(iommu); | |
730 | ||
8a66712b | 731 | return pci_enable_device(iommu->dev); |
e47d402d JR |
732 | } |
733 | ||
b65233a9 JR |
734 | /* |
735 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
736 | * IOMMU structure and initializes it with init_iommu_one() | |
737 | */ | |
e47d402d JR |
738 | static int __init init_iommu_all(struct acpi_table_header *table) |
739 | { | |
740 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
741 | struct ivhd_header *h; | |
742 | struct amd_iommu *iommu; | |
743 | int ret; | |
744 | ||
e47d402d JR |
745 | end += table->length; |
746 | p += IVRS_HEADER_LENGTH; | |
747 | ||
748 | while (p < end) { | |
749 | h = (struct ivhd_header *)p; | |
750 | switch (*p) { | |
751 | case ACPI_IVHD_TYPE: | |
752 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
753 | if (iommu == NULL) | |
754 | return -ENOMEM; | |
755 | ret = init_iommu_one(iommu, h); | |
756 | if (ret) | |
757 | return ret; | |
758 | break; | |
759 | default: | |
760 | break; | |
761 | } | |
762 | p += h->length; | |
763 | ||
764 | } | |
765 | WARN_ON(p != end); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
a80dc3e0 JR |
770 | /**************************************************************************** |
771 | * | |
772 | * The following functions initialize the MSI interrupts for all IOMMUs | |
773 | * in the system. Its a bit challenging because there could be multiple | |
774 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
775 | * pci_dev. | |
776 | * | |
777 | ****************************************************************************/ | |
778 | ||
779 | static int __init iommu_setup_msix(struct amd_iommu *iommu) | |
780 | { | |
781 | struct amd_iommu *curr; | |
782 | struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */ | |
783 | int nvec = 0, i; | |
784 | ||
785 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
786 | if (curr->dev == iommu->dev) { | |
787 | entries[nvec].entry = curr->evt_msi_num; | |
788 | entries[nvec].vector = 0; | |
789 | curr->int_enabled = true; | |
790 | nvec++; | |
791 | } | |
792 | } | |
793 | ||
794 | if (pci_enable_msix(iommu->dev, entries, nvec)) { | |
795 | pci_disable_msix(iommu->dev); | |
796 | return 1; | |
797 | } | |
798 | ||
799 | for (i = 0; i < nvec; ++i) { | |
800 | int r = request_irq(entries->vector, amd_iommu_int_handler, | |
801 | IRQF_SAMPLE_RANDOM, | |
802 | "AMD IOMMU", | |
803 | NULL); | |
804 | if (r) | |
805 | goto out_free; | |
806 | } | |
807 | ||
808 | return 0; | |
809 | ||
810 | out_free: | |
811 | for (i -= 1; i >= 0; --i) | |
812 | free_irq(entries->vector, NULL); | |
813 | ||
814 | pci_disable_msix(iommu->dev); | |
815 | ||
816 | return 1; | |
817 | } | |
818 | ||
819 | static int __init iommu_setup_msi(struct amd_iommu *iommu) | |
820 | { | |
821 | int r; | |
822 | struct amd_iommu *curr; | |
823 | ||
824 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
825 | if (curr->dev == iommu->dev) | |
826 | curr->int_enabled = true; | |
827 | } | |
828 | ||
829 | ||
830 | if (pci_enable_msi(iommu->dev)) | |
831 | return 1; | |
832 | ||
833 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
834 | IRQF_SAMPLE_RANDOM, | |
835 | "AMD IOMMU", | |
836 | NULL); | |
837 | ||
838 | if (r) { | |
839 | pci_disable_msi(iommu->dev); | |
840 | return 1; | |
841 | } | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static int __init iommu_init_msi(struct amd_iommu *iommu) | |
847 | { | |
848 | if (iommu->int_enabled) | |
849 | return 0; | |
850 | ||
851 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX)) | |
852 | return iommu_setup_msix(iommu); | |
853 | else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) | |
854 | return iommu_setup_msi(iommu); | |
855 | ||
856 | return 1; | |
857 | } | |
858 | ||
b65233a9 JR |
859 | /**************************************************************************** |
860 | * | |
861 | * The next functions belong to the third pass of parsing the ACPI | |
862 | * table. In this last pass the memory mapping requirements are | |
863 | * gathered (like exclusion and unity mapping reanges). | |
864 | * | |
865 | ****************************************************************************/ | |
866 | ||
be2a022c JR |
867 | static void __init free_unity_maps(void) |
868 | { | |
869 | struct unity_map_entry *entry, *next; | |
870 | ||
871 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
872 | list_del(&entry->list); | |
873 | kfree(entry); | |
874 | } | |
875 | } | |
876 | ||
b65233a9 | 877 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
878 | static int __init init_exclusion_range(struct ivmd_header *m) |
879 | { | |
880 | int i; | |
881 | ||
882 | switch (m->type) { | |
883 | case ACPI_IVMD_TYPE: | |
884 | set_device_exclusion_range(m->devid, m); | |
885 | break; | |
886 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 887 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
888 | set_device_exclusion_range(i, m); |
889 | break; | |
890 | case ACPI_IVMD_TYPE_RANGE: | |
891 | for (i = m->devid; i <= m->aux; ++i) | |
892 | set_device_exclusion_range(i, m); | |
893 | break; | |
894 | default: | |
895 | break; | |
896 | } | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
b65233a9 | 901 | /* called for unity map ACPI definition */ |
be2a022c JR |
902 | static int __init init_unity_map_range(struct ivmd_header *m) |
903 | { | |
904 | struct unity_map_entry *e = 0; | |
905 | ||
906 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
907 | if (e == NULL) | |
908 | return -ENOMEM; | |
909 | ||
910 | switch (m->type) { | |
911 | default: | |
912 | case ACPI_IVMD_TYPE: | |
913 | e->devid_start = e->devid_end = m->devid; | |
914 | break; | |
915 | case ACPI_IVMD_TYPE_ALL: | |
916 | e->devid_start = 0; | |
917 | e->devid_end = amd_iommu_last_bdf; | |
918 | break; | |
919 | case ACPI_IVMD_TYPE_RANGE: | |
920 | e->devid_start = m->devid; | |
921 | e->devid_end = m->aux; | |
922 | break; | |
923 | } | |
924 | e->address_start = PAGE_ALIGN(m->range_start); | |
925 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
926 | e->prot = m->flags >> 1; | |
927 | ||
928 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
b65233a9 | 933 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
934 | static int __init init_memory_definitions(struct acpi_table_header *table) |
935 | { | |
936 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
937 | struct ivmd_header *m; | |
938 | ||
be2a022c JR |
939 | end += table->length; |
940 | p += IVRS_HEADER_LENGTH; | |
941 | ||
942 | while (p < end) { | |
943 | m = (struct ivmd_header *)p; | |
944 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
945 | init_exclusion_range(m); | |
946 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
947 | init_unity_map_range(m); | |
948 | ||
949 | p += m->length; | |
950 | } | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
9f5f5fb3 JR |
955 | /* |
956 | * Init the device table to not allow DMA access for devices and | |
957 | * suppress all page faults | |
958 | */ | |
959 | static void init_device_table(void) | |
960 | { | |
961 | u16 devid; | |
962 | ||
963 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
964 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
965 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
966 | } |
967 | } | |
968 | ||
b65233a9 JR |
969 | /* |
970 | * This function finally enables all IOMMUs found in the system after | |
971 | * they have been initialized | |
972 | */ | |
8736197b JR |
973 | static void __init enable_iommus(void) |
974 | { | |
975 | struct amd_iommu *iommu; | |
976 | ||
977 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
978 | iommu_set_exclusion_range(iommu); | |
a80dc3e0 | 979 | iommu_init_msi(iommu); |
126c52be | 980 | iommu_enable_event_logging(iommu); |
8736197b JR |
981 | iommu_enable(iommu); |
982 | } | |
983 | } | |
984 | ||
7441e9cb JR |
985 | /* |
986 | * Suspend/Resume support | |
987 | * disable suspend until real resume implemented | |
988 | */ | |
989 | ||
990 | static int amd_iommu_resume(struct sys_device *dev) | |
991 | { | |
992 | return 0; | |
993 | } | |
994 | ||
995 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
996 | { | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
1000 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1001 | .name = "amd_iommu", | |
1002 | .suspend = amd_iommu_suspend, | |
1003 | .resume = amd_iommu_resume, | |
1004 | }; | |
1005 | ||
1006 | static struct sys_device device_amd_iommu = { | |
1007 | .id = 0, | |
1008 | .cls = &amd_iommu_sysdev_class, | |
1009 | }; | |
1010 | ||
b65233a9 JR |
1011 | /* |
1012 | * This is the core init function for AMD IOMMU hardware in the system. | |
1013 | * This function is called from the generic x86 DMA layer initialization | |
1014 | * code. | |
1015 | * | |
1016 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1017 | * three times: | |
1018 | * | |
1019 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1020 | * Upon this information the size of the data structures is | |
1021 | * determined that needs to be allocated. | |
1022 | * | |
1023 | * 2 pass) Initialize the data structures just allocated with the | |
1024 | * information in the ACPI table about available AMD IOMMUs | |
1025 | * in the system. It also maps the PCI devices in the | |
1026 | * system to specific IOMMUs | |
1027 | * | |
1028 | * 3 pass) After the basic data structures are allocated and | |
1029 | * initialized we update them with information about memory | |
1030 | * remapping requirements parsed out of the ACPI table in | |
1031 | * this last pass. | |
1032 | * | |
1033 | * After that the hardware is initialized and ready to go. In the last | |
1034 | * step we do some Linux specific things like registering the driver in | |
1035 | * the dma_ops interface and initializing the suspend/resume support | |
1036 | * functions. Finally it prints some information about AMD IOMMUs and | |
1037 | * the driver state and enables the hardware. | |
1038 | */ | |
fe74c9cf JR |
1039 | int __init amd_iommu_init(void) |
1040 | { | |
1041 | int i, ret = 0; | |
1042 | ||
1043 | ||
8b14518f | 1044 | if (no_iommu) { |
fe74c9cf JR |
1045 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
1046 | return 0; | |
1047 | } | |
1048 | ||
c1cbebee JR |
1049 | if (!amd_iommu_detected) |
1050 | return -ENODEV; | |
1051 | ||
fe74c9cf JR |
1052 | /* |
1053 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1054 | * we need to handle. Upon this information the shared data | |
1055 | * structures for the IOMMUs in the system will be allocated | |
1056 | */ | |
1057 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1058 | return -ENODEV; | |
1059 | ||
c571484e JR |
1060 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1061 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1062 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1063 | |
1064 | ret = -ENOMEM; | |
1065 | ||
1066 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1067 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1068 | get_order(dev_table_size)); |
1069 | if (amd_iommu_dev_table == NULL) | |
1070 | goto out; | |
1071 | ||
1072 | /* | |
1073 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1074 | * IOMMU see for that device | |
1075 | */ | |
1076 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1077 | get_order(alias_table_size)); | |
1078 | if (amd_iommu_alias_table == NULL) | |
1079 | goto free; | |
1080 | ||
1081 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1082 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1083 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1084 | get_order(rlookup_table_size)); |
1085 | if (amd_iommu_rlookup_table == NULL) | |
1086 | goto free; | |
1087 | ||
1088 | /* | |
1089 | * Protection Domain table - maps devices to protection domains | |
1090 | * This table has the same size as the rlookup_table | |
1091 | */ | |
5dc8bff0 | 1092 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1093 | get_order(rlookup_table_size)); |
1094 | if (amd_iommu_pd_table == NULL) | |
1095 | goto free; | |
1096 | ||
5dc8bff0 JR |
1097 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1098 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1099 | get_order(MAX_DOMAIN_ID/8)); |
1100 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1101 | goto free; | |
1102 | ||
9f5f5fb3 JR |
1103 | /* init the device table */ |
1104 | init_device_table(); | |
1105 | ||
fe74c9cf | 1106 | /* |
5dc8bff0 | 1107 | * let all alias entries point to itself |
fe74c9cf | 1108 | */ |
3a61ec38 | 1109 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1110 | amd_iommu_alias_table[i] = i; |
1111 | ||
fe74c9cf JR |
1112 | /* |
1113 | * never allocate domain 0 because its used as the non-allocated and | |
1114 | * error value placeholder | |
1115 | */ | |
1116 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1117 | ||
1118 | /* | |
1119 | * now the data structures are allocated and basically initialized | |
1120 | * start the real acpi table scan | |
1121 | */ | |
1122 | ret = -ENODEV; | |
1123 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1124 | goto free; | |
1125 | ||
1126 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1127 | goto free; | |
1128 | ||
129d6aba | 1129 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1130 | if (ret) |
1131 | goto free; | |
1132 | ||
129d6aba | 1133 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1134 | if (ret) |
1135 | goto free; | |
1136 | ||
129d6aba | 1137 | ret = amd_iommu_init_dma_ops(); |
7441e9cb JR |
1138 | if (ret) |
1139 | goto free; | |
1140 | ||
8736197b JR |
1141 | enable_iommus(); |
1142 | ||
fe74c9cf JR |
1143 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
1144 | (1 << (amd_iommu_aperture_order-20))); | |
1145 | ||
1146 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
1147 | if (amd_iommu_isolate) | |
1148 | printk("enabled\n"); | |
1149 | else | |
1150 | printk("disabled\n"); | |
1151 | ||
afa9fdc2 | 1152 | if (amd_iommu_unmap_flush) |
1c655773 JR |
1153 | printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n"); |
1154 | else | |
1155 | printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n"); | |
1156 | ||
fe74c9cf JR |
1157 | out: |
1158 | return ret; | |
1159 | ||
1160 | free: | |
d58befd3 JR |
1161 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1162 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1163 | |
9a836de0 JR |
1164 | free_pages((unsigned long)amd_iommu_pd_table, |
1165 | get_order(rlookup_table_size)); | |
fe74c9cf | 1166 | |
9a836de0 JR |
1167 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1168 | get_order(rlookup_table_size)); | |
fe74c9cf | 1169 | |
9a836de0 JR |
1170 | free_pages((unsigned long)amd_iommu_alias_table, |
1171 | get_order(alias_table_size)); | |
fe74c9cf | 1172 | |
9a836de0 JR |
1173 | free_pages((unsigned long)amd_iommu_dev_table, |
1174 | get_order(dev_table_size)); | |
fe74c9cf JR |
1175 | |
1176 | free_iommu_all(); | |
1177 | ||
1178 | free_unity_maps(); | |
1179 | ||
1180 | goto out; | |
1181 | } | |
1182 | ||
b65233a9 JR |
1183 | /**************************************************************************** |
1184 | * | |
1185 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1186 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1187 | * IOMMUs | |
1188 | * | |
1189 | ****************************************************************************/ | |
ae7877de JR |
1190 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1191 | { | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | void __init amd_iommu_detect(void) | |
1196 | { | |
299a140d | 1197 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1198 | return; |
1199 | ||
ae7877de JR |
1200 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1201 | iommu_detected = 1; | |
c1cbebee | 1202 | amd_iommu_detected = 1; |
92af4e29 | 1203 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1204 | gart_iommu_aperture_disabled = 1; |
1205 | gart_iommu_aperture = 0; | |
92af4e29 | 1206 | #endif |
ae7877de JR |
1207 | } |
1208 | } | |
1209 | ||
b65233a9 JR |
1210 | /**************************************************************************** |
1211 | * | |
1212 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1213 | * options. | |
1214 | * | |
1215 | ****************************************************************************/ | |
1216 | ||
918ad6c5 JR |
1217 | static int __init parse_amd_iommu_options(char *str) |
1218 | { | |
1219 | for (; *str; ++str) { | |
1c655773 | 1220 | if (strncmp(str, "isolate", 7) == 0) |
918ad6c5 | 1221 | amd_iommu_isolate = 1; |
e5e1f606 JR |
1222 | if (strncmp(str, "share", 5) == 0) |
1223 | amd_iommu_isolate = 0; | |
695b5676 | 1224 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1225 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1226 | } |
1227 | ||
1228 | return 1; | |
1229 | } | |
1230 | ||
1231 | static int __init parse_amd_iommu_size_options(char *str) | |
1232 | { | |
0906372e JR |
1233 | unsigned order = PAGE_SHIFT + get_order(memparse(str, &str)); |
1234 | ||
1235 | if ((order > 24) && (order < 31)) | |
1236 | amd_iommu_aperture_order = order; | |
918ad6c5 JR |
1237 | |
1238 | return 1; | |
1239 | } | |
1240 | ||
1241 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1242 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |