Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
e83a5fdc | 26 | #include <linux/module.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
83ab8514 | 38 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 39 | #include <asm/irq_remapping.h> |
cdd6c482 | 40 | #include <asm/perf_event.h> |
736decac | 41 | #include <asm/x86_init.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
60063497 | 43 | #include <linux/atomic.h> |
1da177e4 | 44 | #include <asm/mpspec.h> |
d1de36f5 | 45 | #include <asm/i8259.h> |
73dea47f | 46 | #include <asm/proto.h> |
2c8c0e6b | 47 | #include <asm/apic.h> |
7167d08e | 48 | #include <asm/io_apic.h> |
d1de36f5 IM |
49 | #include <asm/desc.h> |
50 | #include <asm/hpet.h> | |
51 | #include <asm/idle.h> | |
52 | #include <asm/mtrr.h> | |
16f871bc | 53 | #include <asm/time.h> |
2bc13797 | 54 | #include <asm/smp.h> |
be71b855 | 55 | #include <asm/mce.h> |
8c3ba8d0 | 56 | #include <asm/tsc.h> |
2904ed8d | 57 | #include <asm/hypervisor.h> |
1da177e4 | 58 | |
ec70de8b | 59 | unsigned int num_processors; |
fdbecd9f | 60 | |
148f9bb8 | 61 | unsigned disabled_cpus; |
fdbecd9f | 62 | |
ec70de8b BG |
63 | /* Processor that is doing the boot up */ |
64 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 65 | |
80e5609c | 66 | /* |
fdbecd9f | 67 | * The highest APIC ID seen during enumeration. |
80e5609c | 68 | */ |
ec70de8b | 69 | unsigned int max_physical_apicid; |
5af5573e | 70 | |
80e5609c | 71 | /* |
fdbecd9f | 72 | * Bitmask of physically existing CPUs: |
80e5609c | 73 | */ |
ec70de8b BG |
74 | physid_mask_t phys_cpu_present_map; |
75 | ||
76 | /* | |
77 | * Map cpu index to physical APIC ID | |
78 | */ | |
0816b0f0 VZ |
79 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
80 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); | |
ec70de8b BG |
81 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
82 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 83 | |
b3c51170 | 84 | #ifdef CONFIG_X86_32 |
4c321ff8 | 85 | |
4c321ff8 TH |
86 | /* |
87 | * On x86_32, the mapping between cpu and logical apicid may vary | |
88 | * depending on apic in use. The following early percpu variable is | |
89 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
90 | * actually diverge. Let's keep it ugly for now. | |
91 | */ | |
0816b0f0 | 92 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 93 | |
f28c0ae2 YL |
94 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
95 | static int enabled_via_apicbase; | |
96 | ||
c0eaa453 CG |
97 | /* |
98 | * Handle interrupt mode configuration register (IMCR). | |
99 | * This register controls whether the interrupt signals | |
100 | * that reach the BSP come from the master PIC or from the | |
101 | * local APIC. Before entering Symmetric I/O Mode, either | |
102 | * the BIOS or the operating system must switch out of | |
103 | * PIC Mode by changing the IMCR. | |
104 | */ | |
5cda395f | 105 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
106 | { |
107 | /* select IMCR register */ | |
108 | outb(0x70, 0x22); | |
109 | /* NMI and 8259 INTR go through APIC */ | |
110 | outb(0x01, 0x23); | |
111 | } | |
112 | ||
5cda395f | 113 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
114 | { |
115 | /* select IMCR register */ | |
116 | outb(0x70, 0x22); | |
117 | /* NMI and 8259 INTR go directly to BSP */ | |
118 | outb(0x00, 0x23); | |
119 | } | |
b3c51170 YL |
120 | #endif |
121 | ||
279f1461 SS |
122 | /* |
123 | * Knob to control our willingness to enable the local APIC. | |
124 | * | |
125 | * +1=force-enable | |
126 | */ | |
127 | static int force_enable_local_apic __initdata; | |
128 | /* | |
129 | * APIC command line parameters | |
130 | */ | |
131 | static int __init parse_lapic(char *arg) | |
132 | { | |
133 | if (config_enabled(CONFIG_X86_32) && !arg) | |
134 | force_enable_local_apic = 1; | |
27cf9298 | 135 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
136 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
137 | return 0; | |
138 | } | |
139 | early_param("lapic", parse_lapic); | |
140 | ||
b3c51170 | 141 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 142 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
143 | static __init int setup_apicpmtimer(char *s) |
144 | { | |
145 | apic_calibrate_pmtmr = 1; | |
146 | notsc_setup(NULL); | |
147 | return 0; | |
148 | } | |
149 | __setup("apicpmtimer", setup_apicpmtimer); | |
150 | #endif | |
151 | ||
fc1edaf9 | 152 | int x2apic_mode; |
06cd9a7d | 153 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a | 154 | /* x2apic enabled before OS handover */ |
fb209bd8 YL |
155 | int x2apic_preenabled; |
156 | static int x2apic_disabled; | |
a31bc327 | 157 | static int nox2apic; |
49899eac YL |
158 | static __init int setup_nox2apic(char *str) |
159 | { | |
39d83a5d | 160 | if (x2apic_enabled()) { |
a31bc327 YL |
161 | int apicid = native_apic_msr_read(APIC_ID); |
162 | ||
163 | if (apicid >= 255) { | |
164 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
165 | apicid); | |
166 | return 0; | |
167 | } | |
168 | ||
169 | pr_warning("x2apic already enabled. will disable it\n"); | |
170 | } else | |
171 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
172 | ||
173 | nox2apic = 1; | |
39d83a5d | 174 | |
49899eac YL |
175 | return 0; |
176 | } | |
177 | early_param("nox2apic", setup_nox2apic); | |
178 | #endif | |
1da177e4 | 179 | |
b3c51170 YL |
180 | unsigned long mp_lapic_addr; |
181 | int disable_apic; | |
182 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 183 | static int disable_apic_timer __initdata; |
e83a5fdc | 184 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
185 | int local_apic_timer_c2_ok; |
186 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
187 | ||
efa2559f YL |
188 | int first_system_vector = 0xfe; |
189 | ||
e83a5fdc HS |
190 | /* |
191 | * Debug level, exported for io_apic.c | |
192 | */ | |
baa13188 | 193 | unsigned int apic_verbosity; |
e83a5fdc | 194 | |
89c38c28 CG |
195 | int pic_mode; |
196 | ||
bab4b27c AS |
197 | /* Have we found an MP table */ |
198 | int smp_found_config; | |
199 | ||
39928722 AD |
200 | static struct resource lapic_resource = { |
201 | .name = "Local APIC", | |
202 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
203 | }; | |
204 | ||
1ade93ef | 205 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 206 | |
0e078e2f | 207 | static void apic_pm_activate(void); |
ba7eda4c | 208 | |
d3432896 AK |
209 | static unsigned long apic_phys; |
210 | ||
0e078e2f TG |
211 | /* |
212 | * Get the LAPIC version | |
213 | */ | |
214 | static inline int lapic_get_version(void) | |
ba7eda4c | 215 | { |
0e078e2f | 216 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
217 | } |
218 | ||
0e078e2f | 219 | /* |
9c803869 | 220 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
221 | */ |
222 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 223 | { |
9c803869 | 224 | #ifdef CONFIG_X86_64 |
0e078e2f | 225 | return 1; |
9c803869 CG |
226 | #else |
227 | return APIC_INTEGRATED(lapic_get_version()); | |
228 | #endif | |
ba7eda4c TG |
229 | } |
230 | ||
231 | /* | |
0e078e2f | 232 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 233 | */ |
0e078e2f | 234 | static int modern_apic(void) |
ba7eda4c | 235 | { |
0e078e2f TG |
236 | /* AMD systems use old APIC versions, so check the CPU */ |
237 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
238 | boot_cpu_data.x86 >= 0xf) | |
239 | return 1; | |
240 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
241 | } |
242 | ||
08306ce6 | 243 | /* |
a933c618 CG |
244 | * right after this call apic become NOOP driven |
245 | * so apic->write/read doesn't do anything | |
08306ce6 | 246 | */ |
25874a29 | 247 | static void __init apic_disable(void) |
08306ce6 | 248 | { |
f88f2b4f | 249 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 250 | apic = &apic_noop; |
08306ce6 CG |
251 | } |
252 | ||
c1eeb2de | 253 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
254 | { |
255 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
256 | cpu_relax(); | |
257 | } | |
258 | ||
c1eeb2de | 259 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 260 | { |
3c6bb07a | 261 | u32 send_status; |
8339e9fb FLV |
262 | int timeout; |
263 | ||
264 | timeout = 0; | |
265 | do { | |
266 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
267 | if (!send_status) | |
268 | break; | |
b49d7d87 | 269 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
270 | udelay(100); |
271 | } while (timeout++ < 1000); | |
272 | ||
273 | return send_status; | |
274 | } | |
275 | ||
c1eeb2de | 276 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 277 | { |
ed4e5ec1 | 278 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
279 | apic_write(APIC_ICR, low); |
280 | } | |
281 | ||
c1eeb2de | 282 | u64 native_apic_icr_read(void) |
1b374e4d SS |
283 | { |
284 | u32 icr1, icr2; | |
285 | ||
286 | icr2 = apic_read(APIC_ICR2); | |
287 | icr1 = apic_read(APIC_ICR); | |
288 | ||
cf9768d7 | 289 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
290 | } |
291 | ||
7c37e48b CG |
292 | #ifdef CONFIG_X86_32 |
293 | /** | |
294 | * get_physical_broadcast - Get number of physical broadcast IDs | |
295 | */ | |
296 | int get_physical_broadcast(void) | |
297 | { | |
298 | return modern_apic() ? 0xff : 0xf; | |
299 | } | |
300 | #endif | |
301 | ||
0e078e2f TG |
302 | /** |
303 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
304 | */ | |
37e650c7 | 305 | int lapic_get_maxlvt(void) |
1da177e4 | 306 | { |
36a028de | 307 | unsigned int v; |
1da177e4 LT |
308 | |
309 | v = apic_read(APIC_LVR); | |
36a028de CG |
310 | /* |
311 | * - we always have APIC integrated on 64bit mode | |
312 | * - 82489DXs do not report # of LVT entries | |
313 | */ | |
314 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
315 | } |
316 | ||
274cfe59 CG |
317 | /* |
318 | * Local APIC timer | |
319 | */ | |
320 | ||
c40aaec6 | 321 | /* Clock divisor */ |
c40aaec6 | 322 | #define APIC_DIVISOR 16 |
279f1461 | 323 | #define TSC_DIVISOR 32 |
f07f4f90 | 324 | |
0e078e2f TG |
325 | /* |
326 | * This function sets up the local APIC timer, with a timeout of | |
327 | * 'clocks' APIC bus clock. During calibration we actually call | |
328 | * this function twice on the boot CPU, once with a bogus timeout | |
329 | * value, second time for real. The other (noncalibrating) CPUs | |
330 | * call this function only once, with the real, calibrated value. | |
331 | * | |
332 | * We do reads before writes even if unnecessary, to get around the | |
333 | * P5 APIC double write bug. | |
334 | */ | |
0e078e2f | 335 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 336 | { |
0e078e2f | 337 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 338 | |
0e078e2f TG |
339 | lvtt_value = LOCAL_TIMER_VECTOR; |
340 | if (!oneshot) | |
341 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
342 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
343 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
344 | ||
f07f4f90 CG |
345 | if (!lapic_is_integrated()) |
346 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
347 | ||
0e078e2f TG |
348 | if (!irqen) |
349 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 350 | |
0e078e2f | 351 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 352 | |
279f1461 SS |
353 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
354 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); | |
355 | return; | |
356 | } | |
357 | ||
1da177e4 | 358 | /* |
0e078e2f | 359 | * Divide PICLK by 16 |
1da177e4 | 360 | */ |
0e078e2f | 361 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
362 | apic_write(APIC_TDCR, |
363 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
364 | APIC_TDR_DIV_16); | |
0e078e2f TG |
365 | |
366 | if (!oneshot) | |
f07f4f90 | 367 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
368 | } |
369 | ||
0e078e2f | 370 | /* |
a68c439b | 371 | * Setup extended LVT, AMD specific |
7b83dae7 | 372 | * |
a68c439b RR |
373 | * Software should use the LVT offsets the BIOS provides. The offsets |
374 | * are determined by the subsystems using it like those for MCE | |
375 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
376 | * are supported. Beginning with family 10h at least 4 offsets are | |
377 | * available. | |
286f5718 | 378 | * |
a68c439b RR |
379 | * Since the offsets must be consistent for all cores, we keep track |
380 | * of the LVT offsets in software and reserve the offset for the same | |
381 | * vector also to be used on other cores. An offset is freed by | |
382 | * setting the entry to APIC_EILVT_MASKED. | |
383 | * | |
384 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
385 | * "[Firmware Bug]: ..." error message is generated. However, if | |
386 | * software does not properly determines the offsets, it is not | |
387 | * necessarily a BIOS bug. | |
0e078e2f | 388 | */ |
7b83dae7 | 389 | |
a68c439b RR |
390 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
391 | ||
392 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
393 | { | |
394 | return (old & APIC_EILVT_MASKED) | |
395 | || (new == APIC_EILVT_MASKED) | |
396 | || ((new & ~APIC_EILVT_MASKED) == old); | |
397 | } | |
398 | ||
399 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
400 | { | |
8abc3122 | 401 | unsigned int rsvd, vector; |
a68c439b RR |
402 | |
403 | if (offset >= APIC_EILVT_NR_MAX) | |
404 | return ~0; | |
405 | ||
8abc3122 | 406 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 407 | do { |
8abc3122 RR |
408 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
409 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
410 | /* may not change if vectors are different */ |
411 | return rsvd; | |
412 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
413 | } while (rsvd != new); | |
414 | ||
8abc3122 RR |
415 | rsvd &= ~APIC_EILVT_MASKED; |
416 | if (rsvd && rsvd != vector) | |
417 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
418 | offset, rsvd); | |
419 | ||
a68c439b RR |
420 | return new; |
421 | } | |
422 | ||
423 | /* | |
424 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
425 | * enables the vector. See also the BKDGs. Must be called with |
426 | * preemption disabled. | |
a68c439b RR |
427 | */ |
428 | ||
27afdf20 | 429 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 430 | { |
a68c439b RR |
431 | unsigned long reg = APIC_EILVTn(offset); |
432 | unsigned int new, old, reserved; | |
433 | ||
434 | new = (mask << 16) | (msg_type << 8) | vector; | |
435 | old = apic_read(reg); | |
436 | reserved = reserve_eilvt_offset(offset, new); | |
437 | ||
438 | if (reserved != new) { | |
eb48c9cb RR |
439 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
440 | "vector 0x%x, but the register is already in use for " | |
441 | "vector 0x%x on another cpu\n", | |
442 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
443 | return -EINVAL; |
444 | } | |
445 | ||
446 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
447 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
448 | "vector 0x%x, but the register is already in use for " | |
449 | "vector 0x%x on this cpu\n", | |
450 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
451 | return -EBUSY; |
452 | } | |
453 | ||
454 | apic_write(reg, new); | |
a8fcf1a2 | 455 | |
a68c439b | 456 | return 0; |
1da177e4 | 457 | } |
27afdf20 | 458 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 459 | |
0e078e2f TG |
460 | /* |
461 | * Program the next event, relative to now | |
462 | */ | |
463 | static int lapic_next_event(unsigned long delta, | |
464 | struct clock_event_device *evt) | |
1da177e4 | 465 | { |
0e078e2f TG |
466 | apic_write(APIC_TMICT, delta); |
467 | return 0; | |
1da177e4 LT |
468 | } |
469 | ||
279f1461 SS |
470 | static int lapic_next_deadline(unsigned long delta, |
471 | struct clock_event_device *evt) | |
472 | { | |
473 | u64 tsc; | |
474 | ||
475 | rdtscll(tsc); | |
476 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); | |
477 | return 0; | |
478 | } | |
479 | ||
0e078e2f TG |
480 | /* |
481 | * Setup the lapic timer in periodic or oneshot mode | |
482 | */ | |
483 | static void lapic_timer_setup(enum clock_event_mode mode, | |
484 | struct clock_event_device *evt) | |
9b7711f0 HS |
485 | { |
486 | unsigned long flags; | |
0e078e2f | 487 | unsigned int v; |
9b7711f0 | 488 | |
0e078e2f TG |
489 | /* Lapic used as dummy for broadcast ? */ |
490 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
491 | return; |
492 | ||
493 | local_irq_save(flags); | |
494 | ||
0e078e2f TG |
495 | switch (mode) { |
496 | case CLOCK_EVT_MODE_PERIODIC: | |
497 | case CLOCK_EVT_MODE_ONESHOT: | |
1ade93ef | 498 | __setup_APIC_LVTT(lapic_timer_frequency, |
0e078e2f TG |
499 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
500 | break; | |
501 | case CLOCK_EVT_MODE_UNUSED: | |
502 | case CLOCK_EVT_MODE_SHUTDOWN: | |
503 | v = apic_read(APIC_LVTT); | |
504 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
505 | apic_write(APIC_LVTT, v); | |
6f9b4100 | 506 | apic_write(APIC_TMICT, 0); |
0e078e2f TG |
507 | break; |
508 | case CLOCK_EVT_MODE_RESUME: | |
509 | /* Nothing to do here */ | |
510 | break; | |
511 | } | |
9b7711f0 HS |
512 | |
513 | local_irq_restore(flags); | |
514 | } | |
515 | ||
1da177e4 | 516 | /* |
0e078e2f | 517 | * Local APIC timer broadcast function |
1da177e4 | 518 | */ |
9628937d | 519 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 520 | { |
0e078e2f | 521 | #ifdef CONFIG_SMP |
dac5f412 | 522 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
523 | #endif |
524 | } | |
1da177e4 | 525 | |
25874a29 HK |
526 | |
527 | /* | |
528 | * The local apic timer can be used for any function which is CPU local. | |
529 | */ | |
530 | static struct clock_event_device lapic_clockevent = { | |
531 | .name = "lapic", | |
532 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
533 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
534 | .shift = 32, | |
535 | .set_mode = lapic_timer_setup, | |
536 | .set_next_event = lapic_next_event, | |
537 | .broadcast = lapic_timer_broadcast, | |
538 | .rating = 100, | |
539 | .irq = -1, | |
540 | }; | |
541 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
542 | ||
0e078e2f | 543 | /* |
421f91d2 | 544 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
545 | * of the boot CPU and register the clock event in the framework. |
546 | */ | |
148f9bb8 | 547 | static void setup_APIC_timer(void) |
0e078e2f TG |
548 | { |
549 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 550 | |
349c004e | 551 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
552 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
553 | /* Make LAPIC timer preferrable over percpu HPET */ | |
554 | lapic_clockevent.rating = 150; | |
555 | } | |
556 | ||
0e078e2f | 557 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 558 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 559 | |
279f1461 SS |
560 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
561 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | | |
562 | CLOCK_EVT_FEAT_DUMMY); | |
563 | levt->set_next_event = lapic_next_deadline; | |
564 | clockevents_config_and_register(levt, | |
565 | (tsc_khz / TSC_DIVISOR) * 1000, | |
566 | 0xF, ~0UL); | |
567 | } else | |
568 | clockevents_register_device(levt); | |
0e078e2f | 569 | } |
1da177e4 | 570 | |
2f04fa88 YL |
571 | /* |
572 | * In this functions we calibrate APIC bus clocks to the external timer. | |
573 | * | |
574 | * We want to do the calibration only once since we want to have local timer | |
575 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
576 | * frequency. | |
577 | * | |
578 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
579 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
580 | * readout is broken, so it never gets out of the wait loop again. This was | |
581 | * also reported by others. | |
582 | * | |
583 | * Monitoring the jiffies value is inaccurate and the clockevents | |
584 | * infrastructure allows us to do a simple substitution of the interrupt | |
585 | * handler. | |
586 | * | |
587 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
588 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
589 | * back to normal later in the boot process). | |
590 | */ | |
591 | ||
592 | #define LAPIC_CAL_LOOPS (HZ/10) | |
593 | ||
594 | static __initdata int lapic_cal_loops = -1; | |
595 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
596 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
597 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
598 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
599 | ||
600 | /* | |
601 | * Temporary interrupt handler. | |
602 | */ | |
603 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
604 | { | |
605 | unsigned long long tsc = 0; | |
606 | long tapic = apic_read(APIC_TMCCT); | |
607 | unsigned long pm = acpi_pm_read_early(); | |
608 | ||
609 | if (cpu_has_tsc) | |
610 | rdtscll(tsc); | |
611 | ||
612 | switch (lapic_cal_loops++) { | |
613 | case 0: | |
614 | lapic_cal_t1 = tapic; | |
615 | lapic_cal_tsc1 = tsc; | |
616 | lapic_cal_pm1 = pm; | |
617 | lapic_cal_j1 = jiffies; | |
618 | break; | |
619 | ||
620 | case LAPIC_CAL_LOOPS: | |
621 | lapic_cal_t2 = tapic; | |
622 | lapic_cal_tsc2 = tsc; | |
623 | if (pm < lapic_cal_pm1) | |
624 | pm += ACPI_PM_OVRRUN; | |
625 | lapic_cal_pm2 = pm; | |
626 | lapic_cal_j2 = jiffies; | |
627 | break; | |
628 | } | |
629 | } | |
630 | ||
754ef0cd YI |
631 | static int __init |
632 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
633 | { |
634 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
635 | const long pm_thresh = pm_100ms / 100; | |
636 | unsigned long mult; | |
637 | u64 res; | |
638 | ||
639 | #ifndef CONFIG_X86_PM_TIMER | |
640 | return -1; | |
641 | #endif | |
642 | ||
39ba5d43 | 643 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
644 | |
645 | /* Check, if the PM timer is available */ | |
646 | if (!deltapm) | |
647 | return -1; | |
648 | ||
649 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
650 | ||
651 | if (deltapm > (pm_100ms - pm_thresh) && | |
652 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 653 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
654 | return 0; |
655 | } | |
656 | ||
657 | res = (((u64)deltapm) * mult) >> 22; | |
658 | do_div(res, 1000000); | |
659 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 660 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
661 | |
662 | /* Correct the lapic counter value */ | |
663 | res = (((u64)(*delta)) * pm_100ms); | |
664 | do_div(res, deltapm); | |
665 | pr_info("APIC delta adjusted to PM-Timer: " | |
666 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
667 | *delta = (long)res; | |
668 | ||
669 | /* Correct the tsc counter value */ | |
670 | if (cpu_has_tsc) { | |
671 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 672 | do_div(res, deltapm); |
754ef0cd | 673 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 674 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
675 | (unsigned long)res, *deltatsc); |
676 | *deltatsc = (long)res; | |
b189892d CG |
677 | } |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
2f04fa88 YL |
682 | static int __init calibrate_APIC_clock(void) |
683 | { | |
684 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
685 | void (*real_handler)(struct clock_event_device *dev); |
686 | unsigned long deltaj; | |
754ef0cd | 687 | long delta, deltatsc; |
2f04fa88 YL |
688 | int pm_referenced = 0; |
689 | ||
1ade93ef JP |
690 | /** |
691 | * check if lapic timer has already been calibrated by platform | |
692 | * specific routine, such as tsc calibration code. if so, we just fill | |
693 | * in the clockevent structure and return. | |
694 | */ | |
695 | ||
279f1461 SS |
696 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
697 | return 0; | |
698 | } else if (lapic_timer_frequency) { | |
1ade93ef JP |
699 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
700 | lapic_timer_frequency); | |
701 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
702 | TICK_NSEC, lapic_clockevent.shift); | |
703 | lapic_clockevent.max_delta_ns = | |
704 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
705 | lapic_clockevent.min_delta_ns = | |
706 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
707 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
708 | return 0; | |
709 | } | |
710 | ||
279f1461 SS |
711 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
712 | "calibrating APIC timer ...\n"); | |
713 | ||
2f04fa88 YL |
714 | local_irq_disable(); |
715 | ||
716 | /* Replace the global interrupt handler */ | |
717 | real_handler = global_clock_event->event_handler; | |
718 | global_clock_event->event_handler = lapic_cal_handler; | |
719 | ||
720 | /* | |
81608f3c | 721 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
722 | * can underflow in the 100ms detection time frame |
723 | */ | |
81608f3c | 724 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
725 | |
726 | /* Let the interrupts run */ | |
727 | local_irq_enable(); | |
728 | ||
729 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
730 | cpu_relax(); | |
731 | ||
732 | local_irq_disable(); | |
733 | ||
734 | /* Restore the real event handler */ | |
735 | global_clock_event->event_handler = real_handler; | |
736 | ||
737 | /* Build delta t1-t2 as apic timer counts down */ | |
738 | delta = lapic_cal_t1 - lapic_cal_t2; | |
739 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
740 | ||
754ef0cd YI |
741 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
742 | ||
b189892d CG |
743 | /* we trust the PM based calibration if possible */ |
744 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 745 | &delta, &deltatsc); |
2f04fa88 YL |
746 | |
747 | /* Calculate the scaled math multiplication factor */ | |
748 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
749 | lapic_clockevent.shift); | |
750 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 751 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
752 | lapic_clockevent.min_delta_ns = |
753 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
754 | ||
1ade93ef | 755 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
756 | |
757 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 758 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 759 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 760 | lapic_timer_frequency); |
2f04fa88 YL |
761 | |
762 | if (cpu_has_tsc) { | |
2f04fa88 YL |
763 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
764 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
765 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
766 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
767 | } |
768 | ||
769 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
770 | "%u.%04u MHz.\n", | |
1ade93ef JP |
771 | lapic_timer_frequency / (1000000 / HZ), |
772 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
773 | |
774 | /* | |
775 | * Do a sanity check on the APIC calibration result | |
776 | */ | |
1ade93ef | 777 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 778 | local_irq_enable(); |
ba21ebb6 | 779 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
780 | return -1; |
781 | } | |
782 | ||
783 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
784 | ||
b189892d CG |
785 | /* |
786 | * PM timer calibration failed or not turned on | |
787 | * so lets try APIC timer based calibration | |
788 | */ | |
2f04fa88 YL |
789 | if (!pm_referenced) { |
790 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
791 | ||
792 | /* | |
793 | * Setup the apic timer manually | |
794 | */ | |
795 | levt->event_handler = lapic_cal_handler; | |
796 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
797 | lapic_cal_loops = -1; | |
798 | ||
799 | /* Let the interrupts run */ | |
800 | local_irq_enable(); | |
801 | ||
802 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
803 | cpu_relax(); | |
804 | ||
2f04fa88 YL |
805 | /* Stop the lapic timer */ |
806 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
807 | ||
2f04fa88 YL |
808 | /* Jiffies delta */ |
809 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
810 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
811 | ||
812 | /* Check, if the jiffies result is consistent */ | |
813 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
814 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
815 | else | |
816 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
817 | } else | |
818 | local_irq_enable(); | |
819 | ||
820 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 821 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
822 | return -1; |
823 | } | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
e83a5fdc HS |
828 | /* |
829 | * Setup the boot APIC | |
830 | * | |
831 | * Calibrate and verify the result. | |
832 | */ | |
0e078e2f TG |
833 | void __init setup_boot_APIC_clock(void) |
834 | { | |
835 | /* | |
274cfe59 CG |
836 | * The local apic timer can be disabled via the kernel |
837 | * commandline or from the CPU detection code. Register the lapic | |
838 | * timer as a dummy clock event source on SMP systems, so the | |
839 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
840 | */ |
841 | if (disable_apic_timer) { | |
ba21ebb6 | 842 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 843 | /* No broadcast on UP ! */ |
9d09951d TG |
844 | if (num_possible_cpus() > 1) { |
845 | lapic_clockevent.mult = 1; | |
0e078e2f | 846 | setup_APIC_timer(); |
9d09951d | 847 | } |
0e078e2f TG |
848 | return; |
849 | } | |
850 | ||
89b3b1f4 | 851 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
852 | /* No broadcast on UP ! */ |
853 | if (num_possible_cpus() > 1) | |
854 | setup_APIC_timer(); | |
855 | return; | |
856 | } | |
857 | ||
0e078e2f TG |
858 | /* |
859 | * If nmi_watchdog is set to IO_APIC, we need the | |
860 | * PIT/HPET going. Otherwise register lapic as a dummy | |
861 | * device. | |
862 | */ | |
072b198a | 863 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 864 | |
274cfe59 | 865 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
866 | setup_APIC_timer(); |
867 | } | |
868 | ||
148f9bb8 | 869 | void setup_secondary_APIC_clock(void) |
0e078e2f | 870 | { |
0e078e2f TG |
871 | setup_APIC_timer(); |
872 | } | |
873 | ||
874 | /* | |
875 | * The guts of the apic timer interrupt | |
876 | */ | |
877 | static void local_apic_timer_interrupt(void) | |
878 | { | |
879 | int cpu = smp_processor_id(); | |
880 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
881 | ||
882 | /* | |
883 | * Normally we should not be here till LAPIC has been initialized but | |
884 | * in some cases like kdump, its possible that there is a pending LAPIC | |
885 | * timer interrupt from previous kernel's context and is delivered in | |
886 | * new kernel the moment interrupts are enabled. | |
887 | * | |
888 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
889 | * its possible that when we get here evt->event_handler is NULL. | |
890 | * Check for event_handler being NULL and discard the interrupt as | |
891 | * spurious. | |
892 | */ | |
893 | if (!evt->event_handler) { | |
ba21ebb6 | 894 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
895 | /* Switch it off */ |
896 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
897 | return; | |
898 | } | |
899 | ||
900 | /* | |
901 | * the NMI deadlock-detector uses this. | |
902 | */ | |
915b0d01 | 903 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
904 | |
905 | evt->event_handler(evt); | |
906 | } | |
907 | ||
908 | /* | |
909 | * Local APIC timer interrupt. This is the most natural way for doing | |
910 | * local interrupts, but local timer interrupts can be emulated by | |
911 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
912 | * | |
913 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
914 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
915 | */ | |
1d9090e2 | 916 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
917 | { |
918 | struct pt_regs *old_regs = set_irq_regs(regs); | |
919 | ||
920 | /* | |
921 | * NOTE! We'd better ACK the irq immediately, | |
922 | * because timer handling can be slow. | |
eddc0e92 | 923 | * |
0e078e2f TG |
924 | * update_process_times() expects us to have done irq_enter(). |
925 | * Besides, if we don't timer interrupts ignore the global | |
926 | * interrupt lock, which is the WrongThing (tm) to do. | |
0e078e2f | 927 | */ |
eddc0e92 | 928 | entering_ack_irq(); |
0e078e2f | 929 | local_apic_timer_interrupt(); |
eddc0e92 | 930 | exiting_irq(); |
274cfe59 | 931 | |
0e078e2f TG |
932 | set_irq_regs(old_regs); |
933 | } | |
934 | ||
1d9090e2 | 935 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
cf910e83 SA |
936 | { |
937 | struct pt_regs *old_regs = set_irq_regs(regs); | |
938 | ||
0e078e2f | 939 | /* |
cf910e83 SA |
940 | * NOTE! We'd better ACK the irq immediately, |
941 | * because timer handling can be slow. | |
942 | * | |
0e078e2f TG |
943 | * update_process_times() expects us to have done irq_enter(). |
944 | * Besides, if we don't timer interrupts ignore the global | |
945 | * interrupt lock, which is the WrongThing (tm) to do. | |
946 | */ | |
cf910e83 SA |
947 | entering_ack_irq(); |
948 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); | |
0e078e2f | 949 | local_apic_timer_interrupt(); |
cf910e83 SA |
950 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
951 | exiting_irq(); | |
274cfe59 | 952 | |
0e078e2f TG |
953 | set_irq_regs(old_regs); |
954 | } | |
955 | ||
956 | int setup_profiling_timer(unsigned int multiplier) | |
957 | { | |
958 | return -EINVAL; | |
959 | } | |
960 | ||
0e078e2f TG |
961 | /* |
962 | * Local APIC start and shutdown | |
963 | */ | |
964 | ||
965 | /** | |
966 | * clear_local_APIC - shutdown the local APIC | |
967 | * | |
968 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
969 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
970 | * leftovers during boot. | |
971 | */ | |
972 | void clear_local_APIC(void) | |
973 | { | |
2584a82d | 974 | int maxlvt; |
0e078e2f TG |
975 | u32 v; |
976 | ||
d3432896 | 977 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 978 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
979 | return; |
980 | ||
981 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
982 | /* |
983 | * Masking an LVT entry can trigger a local APIC error | |
984 | * if the vector is zero. Mask LVTERR first to prevent this. | |
985 | */ | |
986 | if (maxlvt >= 3) { | |
987 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
988 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
989 | } | |
990 | /* | |
991 | * Careful: we have to set masks only first to deassert | |
992 | * any level-triggered sources. | |
993 | */ | |
994 | v = apic_read(APIC_LVTT); | |
995 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
996 | v = apic_read(APIC_LVT0); | |
997 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
998 | v = apic_read(APIC_LVT1); | |
999 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1000 | if (maxlvt >= 4) { | |
1001 | v = apic_read(APIC_LVTPC); | |
1002 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1003 | } | |
1004 | ||
6764014b | 1005 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1006 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1007 | if (maxlvt >= 5) { |
1008 | v = apic_read(APIC_LVTTHMR); | |
1009 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1010 | } | |
1011 | #endif | |
5ca8681c AK |
1012 | #ifdef CONFIG_X86_MCE_INTEL |
1013 | if (maxlvt >= 6) { | |
1014 | v = apic_read(APIC_LVTCMCI); | |
1015 | if (!(v & APIC_LVT_MASKED)) | |
1016 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1017 | } | |
1018 | #endif | |
1019 | ||
0e078e2f TG |
1020 | /* |
1021 | * Clean APIC state for other OSs: | |
1022 | */ | |
1023 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1024 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1025 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1026 | if (maxlvt >= 3) | |
1027 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1028 | if (maxlvt >= 4) | |
1029 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1030 | |
1031 | /* Integrated APIC (!82489DX) ? */ | |
1032 | if (lapic_is_integrated()) { | |
1033 | if (maxlvt > 3) | |
1034 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1035 | apic_write(APIC_ESR, 0); | |
1036 | apic_read(APIC_ESR); | |
1037 | } | |
0e078e2f TG |
1038 | } |
1039 | ||
1040 | /** | |
1041 | * disable_local_APIC - clear and disable the local APIC | |
1042 | */ | |
1043 | void disable_local_APIC(void) | |
1044 | { | |
1045 | unsigned int value; | |
1046 | ||
4a13ad0b | 1047 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 1048 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
1049 | return; |
1050 | ||
0e078e2f TG |
1051 | clear_local_APIC(); |
1052 | ||
1053 | /* | |
1054 | * Disable APIC (implies clearing of registers | |
1055 | * for 82489DX!). | |
1056 | */ | |
1057 | value = apic_read(APIC_SPIV); | |
1058 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1059 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1060 | |
1061 | #ifdef CONFIG_X86_32 | |
1062 | /* | |
1063 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1064 | * restore the disabled state. | |
1065 | */ | |
1066 | if (enabled_via_apicbase) { | |
1067 | unsigned int l, h; | |
1068 | ||
1069 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1070 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1071 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1072 | } | |
1073 | #endif | |
0e078e2f TG |
1074 | } |
1075 | ||
fe4024dc CG |
1076 | /* |
1077 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1078 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1079 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1080 | * for the case where Linux didn't enable the LAPIC. | |
1081 | */ | |
0e078e2f TG |
1082 | void lapic_shutdown(void) |
1083 | { | |
1084 | unsigned long flags; | |
1085 | ||
8312136f | 1086 | if (!cpu_has_apic && !apic_from_smp_config()) |
0e078e2f TG |
1087 | return; |
1088 | ||
1089 | local_irq_save(flags); | |
1090 | ||
fe4024dc CG |
1091 | #ifdef CONFIG_X86_32 |
1092 | if (!enabled_via_apicbase) | |
1093 | clear_local_APIC(); | |
1094 | else | |
1095 | #endif | |
1096 | disable_local_APIC(); | |
1097 | ||
0e078e2f TG |
1098 | |
1099 | local_irq_restore(flags); | |
1100 | } | |
1101 | ||
1102 | /* | |
1103 | * This is to verify that we're looking at a real local APIC. | |
1104 | * Check these against your board if the CPUs aren't getting | |
1105 | * started for no apparent reason. | |
1106 | */ | |
1107 | int __init verify_local_APIC(void) | |
1108 | { | |
1109 | unsigned int reg0, reg1; | |
1110 | ||
1111 | /* | |
1112 | * The version register is read-only in a real APIC. | |
1113 | */ | |
1114 | reg0 = apic_read(APIC_LVR); | |
1115 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
1116 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
1117 | reg1 = apic_read(APIC_LVR); | |
1118 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
1119 | ||
1120 | /* | |
1121 | * The two version reads above should print the same | |
1122 | * numbers. If the second one is different, then we | |
1123 | * poke at a non-APIC. | |
1124 | */ | |
1125 | if (reg1 != reg0) | |
1126 | return 0; | |
1127 | ||
1128 | /* | |
1129 | * Check if the version looks reasonably. | |
1130 | */ | |
1131 | reg1 = GET_APIC_VERSION(reg0); | |
1132 | if (reg1 == 0x00 || reg1 == 0xff) | |
1133 | return 0; | |
1134 | reg1 = lapic_get_maxlvt(); | |
1135 | if (reg1 < 0x02 || reg1 == 0xff) | |
1136 | return 0; | |
1137 | ||
1138 | /* | |
1139 | * The ID register is read/write in a real APIC. | |
1140 | */ | |
2d7a66d0 | 1141 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1142 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1143 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1144 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1145 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1146 | apic_write(APIC_ID, reg0); | |
5b812727 | 1147 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1148 | return 0; |
1149 | ||
1150 | /* | |
1da177e4 LT |
1151 | * The next two are just to see if we have sane values. |
1152 | * They're only really relevant if we're in Virtual Wire | |
1153 | * compatibility mode, but most boxes are anymore. | |
1154 | */ | |
1155 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1156 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1157 | reg1 = apic_read(APIC_LVT1); |
1158 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1159 | ||
1160 | return 1; | |
1161 | } | |
1162 | ||
0e078e2f TG |
1163 | /** |
1164 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1165 | */ | |
1da177e4 LT |
1166 | void __init sync_Arb_IDs(void) |
1167 | { | |
296cb951 CG |
1168 | /* |
1169 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1170 | * needed on AMD. | |
1171 | */ | |
1172 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1173 | return; |
1174 | ||
1175 | /* | |
1176 | * Wait for idle. | |
1177 | */ | |
1178 | apic_wait_icr_idle(); | |
1179 | ||
1180 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1181 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1182 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1183 | } |
1184 | ||
1da177e4 LT |
1185 | /* |
1186 | * An initial setup of the virtual wire mode. | |
1187 | */ | |
1188 | void __init init_bsp_APIC(void) | |
1189 | { | |
11a8e778 | 1190 | unsigned int value; |
1da177e4 LT |
1191 | |
1192 | /* | |
1193 | * Don't do the setup now if we have a SMP BIOS as the | |
1194 | * through-I/O-APIC virtual wire mode might be active. | |
1195 | */ | |
1196 | if (smp_found_config || !cpu_has_apic) | |
1197 | return; | |
1198 | ||
1da177e4 LT |
1199 | /* |
1200 | * Do not trust the local APIC being empty at bootup. | |
1201 | */ | |
1202 | clear_local_APIC(); | |
1203 | ||
1204 | /* | |
1205 | * Enable APIC. | |
1206 | */ | |
1207 | value = apic_read(APIC_SPIV); | |
1208 | value &= ~APIC_VECTOR_MASK; | |
1209 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1210 | |
1211 | #ifdef CONFIG_X86_32 | |
1212 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1213 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1214 | (boot_cpu_data.x86 == 15)) | |
1215 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1216 | else | |
1217 | #endif | |
1218 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1219 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1220 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1221 | |
1222 | /* | |
1223 | * Set up the virtual wire mode. | |
1224 | */ | |
11a8e778 | 1225 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1226 | value = APIC_DM_NMI; |
638c0411 CG |
1227 | if (!lapic_is_integrated()) /* 82489DX */ |
1228 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1229 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1230 | } |
1231 | ||
148f9bb8 | 1232 | static void lapic_setup_esr(void) |
c43da2f5 | 1233 | { |
9df08f10 CG |
1234 | unsigned int oldvalue, value, maxlvt; |
1235 | ||
1236 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1237 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1238 | return; |
1239 | } | |
c43da2f5 | 1240 | |
08125d3e | 1241 | if (apic->disable_esr) { |
c43da2f5 | 1242 | /* |
9df08f10 CG |
1243 | * Something untraceable is creating bad interrupts on |
1244 | * secondary quads ... for the moment, just leave the | |
1245 | * ESR disabled - we can't do anything useful with the | |
1246 | * errors anyway - mbligh | |
c43da2f5 | 1247 | */ |
ba21ebb6 | 1248 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1249 | return; |
c43da2f5 | 1250 | } |
9df08f10 CG |
1251 | |
1252 | maxlvt = lapic_get_maxlvt(); | |
1253 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1254 | apic_write(APIC_ESR, 0); | |
1255 | oldvalue = apic_read(APIC_ESR); | |
1256 | ||
1257 | /* enables sending errors */ | |
1258 | value = ERROR_APIC_VECTOR; | |
1259 | apic_write(APIC_LVTERR, value); | |
1260 | ||
1261 | /* | |
1262 | * spec says clear errors after enabling vector. | |
1263 | */ | |
1264 | if (maxlvt > 3) | |
1265 | apic_write(APIC_ESR, 0); | |
1266 | value = apic_read(APIC_ESR); | |
1267 | if (value != oldvalue) | |
1268 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1269 | "vector: 0x%08x after: 0x%08x\n", | |
1270 | oldvalue, value); | |
c43da2f5 CG |
1271 | } |
1272 | ||
0e078e2f TG |
1273 | /** |
1274 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1275 | * |
1276 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1277 | * Always called with preemption disabled. | |
0e078e2f | 1278 | */ |
148f9bb8 | 1279 | void setup_local_APIC(void) |
1da177e4 | 1280 | { |
0aa002fe | 1281 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1282 | unsigned int value, queued; |
1283 | int i, j, acked = 0; | |
1284 | unsigned long long tsc = 0, ntsc; | |
1285 | long long max_loops = cpu_khz; | |
1286 | ||
1287 | if (cpu_has_tsc) | |
1288 | rdtscll(tsc); | |
1da177e4 | 1289 | |
f1182638 | 1290 | if (disable_apic) { |
7167d08e | 1291 | disable_ioapic_support(); |
f1182638 JB |
1292 | return; |
1293 | } | |
1294 | ||
89c38c28 CG |
1295 | #ifdef CONFIG_X86_32 |
1296 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1297 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1298 | apic_write(APIC_ESR, 0); |
1299 | apic_write(APIC_ESR, 0); | |
1300 | apic_write(APIC_ESR, 0); | |
1301 | apic_write(APIC_ESR, 0); | |
1302 | } | |
1303 | #endif | |
cdd6c482 | 1304 | perf_events_lapic_init(); |
89c38c28 | 1305 | |
1da177e4 LT |
1306 | /* |
1307 | * Double-check whether this APIC is really registered. | |
1308 | * This is meaningless in clustered apic mode, so we skip it. | |
1309 | */ | |
c2777f98 | 1310 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1311 | |
1312 | /* | |
1313 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1314 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1315 | * document number 292116). So here it goes... | |
1316 | */ | |
a5c43296 | 1317 | apic->init_apic_ldr(); |
1da177e4 | 1318 | |
6f802c4b TH |
1319 | #ifdef CONFIG_X86_32 |
1320 | /* | |
acb8bc09 TH |
1321 | * APIC LDR is initialized. If logical_apicid mapping was |
1322 | * initialized during get_smp_config(), make sure it matches the | |
1323 | * actual value. | |
6f802c4b | 1324 | */ |
acb8bc09 TH |
1325 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1326 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1327 | /* always use the value from LDR */ | |
6f802c4b TH |
1328 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1329 | logical_smp_processor_id(); | |
c4b90c11 TH |
1330 | |
1331 | /* | |
1332 | * Some NUMA implementations (NUMAQ) don't initialize apicid to | |
1333 | * node mapping during NUMA init. Now that logical apicid is | |
1334 | * guaranteed to be known, give it another chance. This is already | |
1335 | * a bit too late - percpu allocation has already happened without | |
1336 | * proper NUMA affinity. | |
1337 | */ | |
84914ed0 TH |
1338 | if (apic->x86_32_numa_cpu_node) |
1339 | set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), | |
1340 | apic->x86_32_numa_cpu_node(cpu)); | |
6f802c4b TH |
1341 | #endif |
1342 | ||
1da177e4 LT |
1343 | /* |
1344 | * Set Task Priority to 'accept all'. We never change this | |
1345 | * later on. | |
1346 | */ | |
1347 | value = apic_read(APIC_TASKPRI); | |
1348 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1349 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1350 | |
da7ed9f9 VG |
1351 | /* |
1352 | * After a crash, we no longer service the interrupts and a pending | |
1353 | * interrupt from previous kernel might still have ISR bit set. | |
1354 | * | |
1355 | * Most probably by now CPU has serviced that pending interrupt and | |
1356 | * it might not have done the ack_APIC_irq() because it thought, | |
1357 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1358 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1359 | * the interrupt. Hence a vector might get locked. It was noticed | |
1360 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1361 | */ | |
8c3ba8d0 KJ |
1362 | do { |
1363 | queued = 0; | |
1364 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1365 | queued |= apic_read(APIC_IRR + i*0x10); | |
1366 | ||
1367 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1368 | value = apic_read(APIC_ISR + i*0x10); | |
1369 | for (j = 31; j >= 0; j--) { | |
1370 | if (value & (1<<j)) { | |
1371 | ack_APIC_irq(); | |
1372 | acked++; | |
1373 | } | |
1374 | } | |
da7ed9f9 | 1375 | } |
8c3ba8d0 KJ |
1376 | if (acked > 256) { |
1377 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1378 | acked); | |
1379 | break; | |
1380 | } | |
42fa4250 SF |
1381 | if (queued) { |
1382 | if (cpu_has_tsc) { | |
1383 | rdtscll(ntsc); | |
1384 | max_loops = (cpu_khz << 10) - (ntsc - tsc); | |
1385 | } else | |
1386 | max_loops--; | |
1387 | } | |
8c3ba8d0 KJ |
1388 | } while (queued && max_loops > 0); |
1389 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1390 | |
1da177e4 LT |
1391 | /* |
1392 | * Now that we are all set up, enable the APIC | |
1393 | */ | |
1394 | value = apic_read(APIC_SPIV); | |
1395 | value &= ~APIC_VECTOR_MASK; | |
1396 | /* | |
1397 | * Enable APIC | |
1398 | */ | |
1399 | value |= APIC_SPIV_APIC_ENABLED; | |
1400 | ||
89c38c28 CG |
1401 | #ifdef CONFIG_X86_32 |
1402 | /* | |
1403 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1404 | * certain networking cards. If high frequency interrupts are | |
1405 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1406 | * entry is masked/unmasked at a high rate as well then sooner or | |
1407 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1408 | * from the device. If focus CPU is disabled then the hang goes | |
1409 | * away, oh well :-( | |
1410 | * | |
1411 | * [ This bug can be reproduced easily with a level-triggered | |
1412 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1413 | * BX chipset. ] | |
1414 | */ | |
1415 | /* | |
1416 | * Actually disabling the focus CPU check just makes the hang less | |
1417 | * frequent as it makes the interrupt distributon model be more | |
1418 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1419 | * See also the comment in end_level_ioapic_irq(). --macro | |
1420 | */ | |
1421 | ||
1422 | /* | |
1423 | * - enable focus processor (bit==0) | |
1424 | * - 64bit mode always use processor focus | |
1425 | * so no need to set it | |
1426 | */ | |
1427 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1428 | #endif | |
3f14c746 | 1429 | |
1da177e4 LT |
1430 | /* |
1431 | * Set spurious IRQ vector | |
1432 | */ | |
1433 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1434 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1435 | |
1436 | /* | |
1437 | * Set up LVT0, LVT1: | |
1438 | * | |
1439 | * set up through-local-APIC on the BP's LINT0. This is not | |
1440 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1441 | * we delegate interrupts to the 8259A. | |
1442 | */ | |
1443 | /* | |
1444 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1445 | */ | |
1446 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1447 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1448 | value = APIC_DM_EXTINT; |
0aa002fe | 1449 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1450 | } else { |
1451 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1452 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1453 | } |
11a8e778 | 1454 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1455 | |
1456 | /* | |
1457 | * only the BP should see the LINT1 NMI signal, obviously. | |
1458 | */ | |
0aa002fe | 1459 | if (!cpu) |
1da177e4 LT |
1460 | value = APIC_DM_NMI; |
1461 | else | |
1462 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1463 | if (!lapic_is_integrated()) /* 82489DX */ |
1464 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1465 | apic_write(APIC_LVT1, value); |
89c38c28 | 1466 | |
be71b855 AK |
1467 | #ifdef CONFIG_X86_MCE_INTEL |
1468 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1469 | if (!cpu) |
be71b855 AK |
1470 | cmci_recheck(); |
1471 | #endif | |
739f33b3 | 1472 | } |
1da177e4 | 1473 | |
148f9bb8 | 1474 | void end_local_APIC_setup(void) |
739f33b3 AK |
1475 | { |
1476 | lapic_setup_esr(); | |
fa6b95fc CG |
1477 | |
1478 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1479 | { |
1480 | unsigned int value; | |
1481 | /* Disable the local apic timer */ | |
1482 | value = apic_read(APIC_LVTT); | |
1483 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1484 | apic_write(APIC_LVTT, value); | |
1485 | } | |
fa6b95fc CG |
1486 | #endif |
1487 | ||
0e078e2f | 1488 | apic_pm_activate(); |
2fb270f3 JB |
1489 | } |
1490 | ||
1491 | void __init bsp_end_local_APIC_setup(void) | |
1492 | { | |
1493 | end_local_APIC_setup(); | |
7f7fbf45 KK |
1494 | |
1495 | /* | |
1496 | * Now that local APIC setup is completed for BP, configure the fault | |
1497 | * handling for interrupt remapping. | |
1498 | */ | |
70733e0c | 1499 | irq_remap_enable_fault_handling(); |
7f7fbf45 | 1500 | |
1da177e4 | 1501 | } |
1da177e4 | 1502 | |
06cd9a7d | 1503 | #ifdef CONFIG_X86_X2APIC |
fb209bd8 YL |
1504 | /* |
1505 | * Need to disable xapic and x2apic at the same time and then enable xapic mode | |
1506 | */ | |
1507 | static inline void __disable_x2apic(u64 msr) | |
1508 | { | |
1509 | wrmsrl(MSR_IA32_APICBASE, | |
1510 | msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1511 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1512 | } | |
1513 | ||
a31bc327 | 1514 | static __init void disable_x2apic(void) |
fb209bd8 YL |
1515 | { |
1516 | u64 msr; | |
1517 | ||
1518 | if (!cpu_has_x2apic) | |
1519 | return; | |
1520 | ||
1521 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1522 | if (msr & X2APIC_ENABLE) { | |
1523 | u32 x2apic_id = read_apic_id(); | |
1524 | ||
1525 | if (x2apic_id >= 255) | |
1526 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
1527 | ||
1528 | pr_info("Disabling x2apic\n"); | |
1529 | __disable_x2apic(msr); | |
1530 | ||
a31bc327 YL |
1531 | if (nox2apic) { |
1532 | clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); | |
1533 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
1534 | } | |
1535 | ||
fb209bd8 YL |
1536 | x2apic_disabled = 1; |
1537 | x2apic_mode = 0; | |
1538 | ||
1539 | register_lapic_address(mp_lapic_addr); | |
1540 | } | |
1541 | } | |
1542 | ||
6e1cb38a SS |
1543 | void check_x2apic(void) |
1544 | { | |
ef1f87aa | 1545 | if (x2apic_enabled()) { |
ba21ebb6 | 1546 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
fc1edaf9 | 1547 | x2apic_preenabled = x2apic_mode = 1; |
6e1cb38a SS |
1548 | } |
1549 | } | |
1550 | ||
1551 | void enable_x2apic(void) | |
1552 | { | |
fb209bd8 YL |
1553 | u64 msr; |
1554 | ||
1555 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1556 | if (x2apic_disabled) { | |
1557 | __disable_x2apic(msr); | |
1558 | return; | |
1559 | } | |
6e1cb38a | 1560 | |
fc1edaf9 | 1561 | if (!x2apic_mode) |
06cd9a7d YL |
1562 | return; |
1563 | ||
6e1cb38a | 1564 | if (!(msr & X2APIC_ENABLE)) { |
450b1e8d | 1565 | printk_once(KERN_INFO "Enabling x2apic\n"); |
fb209bd8 | 1566 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); |
6e1cb38a SS |
1567 | } |
1568 | } | |
93758238 | 1569 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1570 | |
ce69a784 | 1571 | int __init enable_IR(void) |
6e1cb38a | 1572 | { |
d3f13810 | 1573 | #ifdef CONFIG_IRQ_REMAP |
95a02e97 | 1574 | if (!irq_remapping_supported()) { |
93758238 | 1575 | pr_debug("intr-remapping not supported\n"); |
41750d31 | 1576 | return -1; |
6e1cb38a SS |
1577 | } |
1578 | ||
93758238 WH |
1579 | if (!x2apic_preenabled && skip_ioapic_setup) { |
1580 | pr_info("Skipped enabling intr-remap because of skipping " | |
1581 | "io-apic setup\n"); | |
41750d31 | 1582 | return -1; |
6e1cb38a SS |
1583 | } |
1584 | ||
95a02e97 | 1585 | return irq_remapping_enable(); |
ce69a784 | 1586 | #endif |
41750d31 | 1587 | return -1; |
ce69a784 GN |
1588 | } |
1589 | ||
1590 | void __init enable_IR_x2apic(void) | |
1591 | { | |
1592 | unsigned long flags; | |
ce69a784 | 1593 | int ret, x2apic_enabled = 0; |
736baef4 | 1594 | int hardware_init_ret; |
b7f42ab2 | 1595 | |
736baef4 | 1596 | /* Make sure irq_remap_ops are initialized */ |
95a02e97 | 1597 | setup_irq_remapping_ops(); |
736baef4 | 1598 | |
95a02e97 | 1599 | hardware_init_ret = irq_remapping_prepare(); |
736baef4 | 1600 | if (hardware_init_ret && !x2apic_supported()) |
e670761f | 1601 | return; |
ce69a784 | 1602 | |
31dce14a | 1603 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1604 | if (ret) { |
ba21ebb6 | 1605 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1606 | return; |
5ffa4eb2 | 1607 | } |
6e1cb38a | 1608 | |
05c3dc2c | 1609 | local_irq_save(flags); |
b81bb373 | 1610 | legacy_pic->mask_all(); |
31dce14a | 1611 | mask_ioapic_entries(); |
05c3dc2c | 1612 | |
a31bc327 YL |
1613 | if (x2apic_preenabled && nox2apic) |
1614 | disable_x2apic(); | |
1615 | ||
736baef4 | 1616 | if (hardware_init_ret) |
41750d31 | 1617 | ret = -1; |
b7f42ab2 YL |
1618 | else |
1619 | ret = enable_IR(); | |
1620 | ||
fb209bd8 | 1621 | if (!x2apic_supported()) |
a31bc327 | 1622 | goto skip_x2apic; |
fb209bd8 | 1623 | |
41750d31 | 1624 | if (ret < 0) { |
ce69a784 GN |
1625 | /* IR is required if there is APIC ID > 255 even when running |
1626 | * under KVM | |
1627 | */ | |
2904ed8d | 1628 | if (max_physical_apicid > 255 || |
fb209bd8 YL |
1629 | !hypervisor_x2apic_available()) { |
1630 | if (x2apic_preenabled) | |
1631 | disable_x2apic(); | |
a31bc327 | 1632 | goto skip_x2apic; |
fb209bd8 | 1633 | } |
ce69a784 GN |
1634 | /* |
1635 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1636 | * only in physical mode | |
1637 | */ | |
1638 | x2apic_force_phys(); | |
1639 | } | |
6e1cb38a | 1640 | |
fb209bd8 YL |
1641 | if (ret == IRQ_REMAP_XAPIC_MODE) { |
1642 | pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); | |
a31bc327 | 1643 | goto skip_x2apic; |
fb209bd8 | 1644 | } |
41750d31 | 1645 | |
ce69a784 | 1646 | x2apic_enabled = 1; |
93758238 | 1647 | |
fc1edaf9 SS |
1648 | if (x2apic_supported() && !x2apic_mode) { |
1649 | x2apic_mode = 1; | |
6e1cb38a | 1650 | enable_x2apic(); |
93758238 | 1651 | pr_info("Enabled x2apic\n"); |
6e1cb38a | 1652 | } |
5ffa4eb2 | 1653 | |
a31bc327 | 1654 | skip_x2apic: |
41750d31 | 1655 | if (ret < 0) /* IR enabling failed */ |
31dce14a | 1656 | restore_ioapic_entries(); |
b81bb373 | 1657 | legacy_pic->restore_mask(); |
6e1cb38a | 1658 | local_irq_restore(flags); |
6e1cb38a | 1659 | } |
93758238 | 1660 | |
be7a656f | 1661 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1662 | /* |
1663 | * Detect and enable local APICs on non-SMP boards. | |
1664 | * Original code written by Keir Fraser. | |
1665 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1666 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1667 | */ |
0e078e2f | 1668 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1669 | { |
1670 | if (!cpu_has_apic) { | |
ba21ebb6 | 1671 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1672 | return -1; |
1673 | } | |
1674 | ||
1675 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1676 | return 0; |
1677 | } | |
be7a656f | 1678 | #else |
5a7ae78f | 1679 | |
25874a29 | 1680 | static int __init apic_verify(void) |
5a7ae78f TG |
1681 | { |
1682 | u32 features, h, l; | |
1683 | ||
1684 | /* | |
1685 | * The APIC feature bit should now be enabled | |
1686 | * in `cpuid' | |
1687 | */ | |
1688 | features = cpuid_edx(1); | |
1689 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1690 | pr_warning("Could not enable APIC!\n"); | |
1691 | return -1; | |
1692 | } | |
1693 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1694 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1695 | ||
1696 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1697 | if (boot_cpu_data.x86 >= 6) { |
1698 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1699 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1700 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1701 | } | |
5a7ae78f TG |
1702 | |
1703 | pr_info("Found and enabled local APIC!\n"); | |
1704 | return 0; | |
1705 | } | |
1706 | ||
25874a29 | 1707 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1708 | { |
1709 | u32 h, l; | |
1710 | ||
1711 | if (disable_apic) | |
1712 | return -1; | |
1713 | ||
1714 | /* | |
1715 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1716 | * MSR. This can only be done in software for Intel P6 or later | |
1717 | * and AMD K7 (Model > 1) or later. | |
1718 | */ | |
cbf2829b BD |
1719 | if (boot_cpu_data.x86 >= 6) { |
1720 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1721 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1722 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1723 | l &= ~MSR_IA32_APICBASE_BASE; | |
1724 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1725 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1726 | enabled_via_apicbase = 1; | |
1727 | } | |
5a7ae78f TG |
1728 | } |
1729 | return apic_verify(); | |
1730 | } | |
1731 | ||
be7a656f YL |
1732 | /* |
1733 | * Detect and initialize APIC | |
1734 | */ | |
1735 | static int __init detect_init_APIC(void) | |
1736 | { | |
be7a656f YL |
1737 | /* Disabled by kernel option? */ |
1738 | if (disable_apic) | |
1739 | return -1; | |
1740 | ||
1741 | switch (boot_cpu_data.x86_vendor) { | |
1742 | case X86_VENDOR_AMD: | |
1743 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1744 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1745 | break; |
1746 | goto no_apic; | |
1747 | case X86_VENDOR_INTEL: | |
1748 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1749 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1750 | break; | |
1751 | goto no_apic; | |
1752 | default: | |
1753 | goto no_apic; | |
1754 | } | |
1755 | ||
1756 | if (!cpu_has_apic) { | |
1757 | /* | |
1758 | * Over-ride BIOS and try to enable the local APIC only if | |
1759 | * "lapic" specified. | |
1760 | */ | |
1761 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1762 | pr_info("Local APIC disabled by BIOS -- " |
1763 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1764 | return -1; |
1765 | } | |
a906fdaa | 1766 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1767 | return -1; |
1768 | } else { | |
1769 | if (apic_verify()) | |
1770 | return -1; | |
be7a656f | 1771 | } |
be7a656f YL |
1772 | |
1773 | apic_pm_activate(); | |
1774 | ||
1775 | return 0; | |
1776 | ||
1777 | no_apic: | |
ba21ebb6 | 1778 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1779 | return -1; |
1780 | } | |
1781 | #endif | |
1da177e4 | 1782 | |
0e078e2f TG |
1783 | /** |
1784 | * init_apic_mappings - initialize APIC mappings | |
1785 | */ | |
1da177e4 LT |
1786 | void __init init_apic_mappings(void) |
1787 | { | |
4401da61 YL |
1788 | unsigned int new_apicid; |
1789 | ||
fc1edaf9 | 1790 | if (x2apic_mode) { |
4c9961d5 | 1791 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1792 | return; |
1793 | } | |
1794 | ||
4797f6b0 | 1795 | /* If no local APIC can be found return early */ |
1da177e4 | 1796 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1797 | /* lets NOP'ify apic operations */ |
1798 | pr_info("APIC: disable apic facility\n"); | |
1799 | apic_disable(); | |
1800 | } else { | |
1da177e4 LT |
1801 | apic_phys = mp_lapic_addr; |
1802 | ||
4797f6b0 YL |
1803 | /* |
1804 | * acpi lapic path already maps that address in | |
1805 | * acpi_register_lapic_address() | |
1806 | */ | |
5989cd6a | 1807 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1808 | register_lapic_address(apic_phys); |
cec6be6d | 1809 | } |
1da177e4 LT |
1810 | |
1811 | /* | |
1812 | * Fetch the APIC ID of the BSP in case we have a | |
1813 | * default configuration (or the MP table is broken). | |
1814 | */ | |
4401da61 YL |
1815 | new_apicid = read_apic_id(); |
1816 | if (boot_cpu_physical_apicid != new_apicid) { | |
1817 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1818 | /* |
1819 | * yeah -- we lie about apic_version | |
1820 | * in case if apic was disabled via boot option | |
1821 | * but it's not a problem for SMP compiled kernel | |
1822 | * since smp_sanity_check is prepared for such a case | |
1823 | * and disable smp mode | |
1824 | */ | |
4401da61 YL |
1825 | apic_version[new_apicid] = |
1826 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1827 | } |
1da177e4 LT |
1828 | } |
1829 | ||
c0104d38 YL |
1830 | void __init register_lapic_address(unsigned long address) |
1831 | { | |
1832 | mp_lapic_addr = address; | |
1833 | ||
0450193b YL |
1834 | if (!x2apic_mode) { |
1835 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1836 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1837 | APIC_BASE, mp_lapic_addr); | |
1838 | } | |
c0104d38 YL |
1839 | if (boot_cpu_physical_apicid == -1U) { |
1840 | boot_cpu_physical_apicid = read_apic_id(); | |
1841 | apic_version[boot_cpu_physical_apicid] = | |
1842 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1843 | } | |
1844 | } | |
1845 | ||
1da177e4 | 1846 | /* |
0e078e2f TG |
1847 | * This initializes the IO-APIC and APIC hardware if this is |
1848 | * a UP kernel. | |
1da177e4 | 1849 | */ |
56d91f13 | 1850 | int apic_version[MAX_LOCAL_APIC]; |
1b313f4a | 1851 | |
0e078e2f | 1852 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1853 | { |
0e078e2f | 1854 | if (disable_apic) { |
ba21ebb6 | 1855 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1856 | return -1; |
1857 | } | |
f1182638 | 1858 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1859 | if (!cpu_has_apic) { |
1860 | disable_apic = 1; | |
ba21ebb6 | 1861 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1862 | return -1; |
1863 | } | |
fa2bd35a YL |
1864 | #else |
1865 | if (!smp_found_config && !cpu_has_apic) | |
1866 | return -1; | |
1867 | ||
1868 | /* | |
1869 | * Complain if the BIOS pretends there is one. | |
1870 | */ | |
1871 | if (!cpu_has_apic && | |
1872 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1873 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1874 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1875 | return -1; |
1876 | } | |
1877 | #endif | |
1878 | ||
72ce0165 | 1879 | default_setup_apic_routing(); |
6e1cb38a | 1880 | |
0e078e2f | 1881 | verify_local_APIC(); |
b5841765 GC |
1882 | connect_bsp_APIC(); |
1883 | ||
fa2bd35a | 1884 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1885 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1886 | #else |
1887 | /* | |
1888 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1889 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1890 | * might be zero if read from MP tables. Get it from LAPIC. | |
1891 | */ | |
1892 | # ifdef CONFIG_CRASH_DUMP | |
1893 | boot_cpu_physical_apicid = read_apic_id(); | |
1894 | # endif | |
1895 | #endif | |
1896 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1897 | setup_local_APIC(); |
1da177e4 | 1898 | |
88d0f550 | 1899 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1900 | /* |
1901 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1902 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1903 | */ |
1904 | if (!skip_ioapic_setup && nr_ioapics) | |
1905 | enable_IO_APIC(); | |
fa2bd35a | 1906 | #endif |
739f33b3 | 1907 | |
2fb270f3 | 1908 | bsp_end_local_APIC_setup(); |
739f33b3 | 1909 | |
fa2bd35a | 1910 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1911 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1912 | setup_IO_APIC(); | |
98c061b6 | 1913 | else { |
0e078e2f | 1914 | nr_ioapics = 0; |
98c061b6 | 1915 | } |
fa2bd35a YL |
1916 | #endif |
1917 | ||
736decac | 1918 | x86_init.timers.setup_percpu_clockev(); |
0e078e2f | 1919 | return 0; |
1da177e4 LT |
1920 | } |
1921 | ||
1922 | /* | |
0e078e2f | 1923 | * Local APIC interrupts |
1da177e4 LT |
1924 | */ |
1925 | ||
0e078e2f TG |
1926 | /* |
1927 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1928 | */ | |
eddc0e92 | 1929 | static inline void __smp_spurious_interrupt(void) |
1da177e4 | 1930 | { |
dc1528dd YL |
1931 | u32 v; |
1932 | ||
1da177e4 | 1933 | /* |
0e078e2f TG |
1934 | * Check if this really is a spurious interrupt and ACK it |
1935 | * if it is a vectored one. Just in case... | |
1936 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1937 | */ |
0e078e2f TG |
1938 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1939 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1940 | ack_APIC_irq(); | |
c4d58cbd | 1941 | |
915b0d01 HS |
1942 | inc_irq_stat(irq_spurious_count); |
1943 | ||
dc1528dd | 1944 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1945 | pr_info("spurious APIC interrupt on CPU#%d, " |
1946 | "should never happen.\n", smp_processor_id()); | |
eddc0e92 SA |
1947 | } |
1948 | ||
1d9090e2 | 1949 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1950 | { |
1951 | entering_irq(); | |
1952 | __smp_spurious_interrupt(); | |
1953 | exiting_irq(); | |
0e078e2f | 1954 | } |
1da177e4 | 1955 | |
1d9090e2 | 1956 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
cf910e83 SA |
1957 | { |
1958 | entering_irq(); | |
1959 | trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR); | |
1960 | __smp_spurious_interrupt(); | |
1961 | trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR); | |
1962 | exiting_irq(); | |
0e078e2f | 1963 | } |
1da177e4 | 1964 | |
0e078e2f TG |
1965 | /* |
1966 | * This interrupt should never happen with our APIC/SMP architecture | |
1967 | */ | |
eddc0e92 | 1968 | static inline void __smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1969 | { |
2b398bd9 YS |
1970 | u32 v0, v1; |
1971 | u32 i = 0; | |
1972 | static const char * const error_interrupt_reason[] = { | |
1973 | "Send CS error", /* APIC Error Bit 0 */ | |
1974 | "Receive CS error", /* APIC Error Bit 1 */ | |
1975 | "Send accept error", /* APIC Error Bit 2 */ | |
1976 | "Receive accept error", /* APIC Error Bit 3 */ | |
1977 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1978 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1979 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1980 | "Illegal register address", /* APIC Error Bit 7 */ | |
1981 | }; | |
1da177e4 | 1982 | |
0e078e2f | 1983 | /* First tickle the hardware, only then report what went on. -- REW */ |
2b398bd9 | 1984 | v0 = apic_read(APIC_ESR); |
0e078e2f TG |
1985 | apic_write(APIC_ESR, 0); |
1986 | v1 = apic_read(APIC_ESR); | |
1987 | ack_APIC_irq(); | |
1988 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1989 | |
2b398bd9 YS |
1990 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", |
1991 | smp_processor_id(), v0 , v1); | |
1992 | ||
1993 | v1 = v1 & 0xff; | |
1994 | while (v1) { | |
1995 | if (v1 & 0x1) | |
1996 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); | |
1997 | i++; | |
1998 | v1 >>= 1; | |
4b8073e4 | 1999 | } |
2b398bd9 YS |
2000 | |
2001 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
2002 | ||
eddc0e92 SA |
2003 | } |
2004 | ||
1d9090e2 | 2005 | __visible void smp_error_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
2006 | { |
2007 | entering_irq(); | |
2008 | __smp_error_interrupt(regs); | |
2009 | exiting_irq(); | |
1da177e4 LT |
2010 | } |
2011 | ||
1d9090e2 | 2012 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
cf910e83 SA |
2013 | { |
2014 | entering_irq(); | |
2015 | trace_error_apic_entry(ERROR_APIC_VECTOR); | |
2016 | __smp_error_interrupt(regs); | |
2017 | trace_error_apic_exit(ERROR_APIC_VECTOR); | |
2018 | exiting_irq(); | |
1da177e4 LT |
2019 | } |
2020 | ||
b5841765 | 2021 | /** |
36c9d674 CG |
2022 | * connect_bsp_APIC - attach the APIC to the interrupt system |
2023 | */ | |
b5841765 GC |
2024 | void __init connect_bsp_APIC(void) |
2025 | { | |
36c9d674 CG |
2026 | #ifdef CONFIG_X86_32 |
2027 | if (pic_mode) { | |
2028 | /* | |
2029 | * Do not trust the local APIC being empty at bootup. | |
2030 | */ | |
2031 | clear_local_APIC(); | |
2032 | /* | |
2033 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
2034 | * local APIC to INT and NMI lines. | |
2035 | */ | |
2036 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
2037 | "enabling APIC mode.\n"); | |
c0eaa453 | 2038 | imcr_pic_to_apic(); |
36c9d674 CG |
2039 | } |
2040 | #endif | |
49040333 IM |
2041 | if (apic->enable_apic_mode) |
2042 | apic->enable_apic_mode(); | |
b5841765 GC |
2043 | } |
2044 | ||
274cfe59 CG |
2045 | /** |
2046 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
2047 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
2048 | * | |
2049 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
2050 | * APIC is disabled. | |
2051 | */ | |
0e078e2f | 2052 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 2053 | { |
1b4ee4e4 CG |
2054 | unsigned int value; |
2055 | ||
c177b0bc CG |
2056 | #ifdef CONFIG_X86_32 |
2057 | if (pic_mode) { | |
2058 | /* | |
2059 | * Put the board back into PIC mode (has an effect only on | |
2060 | * certain older boards). Note that APIC interrupts, including | |
2061 | * IPIs, won't work beyond this point! The only exception are | |
2062 | * INIT IPIs. | |
2063 | */ | |
2064 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
2065 | "entering PIC mode.\n"); | |
c0eaa453 | 2066 | imcr_apic_to_pic(); |
c177b0bc CG |
2067 | return; |
2068 | } | |
2069 | #endif | |
2070 | ||
0e078e2f | 2071 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 2072 | |
0e078e2f TG |
2073 | /* For the spurious interrupt use vector F, and enable it */ |
2074 | value = apic_read(APIC_SPIV); | |
2075 | value &= ~APIC_VECTOR_MASK; | |
2076 | value |= APIC_SPIV_APIC_ENABLED; | |
2077 | value |= 0xf; | |
2078 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 2079 | |
0e078e2f TG |
2080 | if (!virt_wire_setup) { |
2081 | /* | |
2082 | * For LVT0 make it edge triggered, active high, | |
2083 | * external and enabled | |
2084 | */ | |
2085 | value = apic_read(APIC_LVT0); | |
2086 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2087 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2088 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2089 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2090 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2091 | apic_write(APIC_LVT0, value); | |
2092 | } else { | |
2093 | /* Disable LVT0 */ | |
2094 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2095 | } | |
b8ce3359 | 2096 | |
c177b0bc CG |
2097 | /* |
2098 | * For LVT1 make it edge triggered, active high, | |
2099 | * nmi and enabled | |
2100 | */ | |
0e078e2f TG |
2101 | value = apic_read(APIC_LVT1); |
2102 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2103 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2104 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2105 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2106 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2107 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2108 | } |
2109 | ||
148f9bb8 | 2110 | void generic_processor_info(int apicid, int version) |
be8a5685 | 2111 | { |
14cb6dcf VG |
2112 | int cpu, max = nr_cpu_ids; |
2113 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2114 | phys_cpu_present_map); | |
2115 | ||
2116 | /* | |
2117 | * If boot cpu has not been detected yet, then only allow upto | |
2118 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2119 | */ | |
2120 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2121 | apicid != boot_cpu_physical_apicid) { | |
2122 | int thiscpu = max + disabled_cpus - 1; | |
2123 | ||
2124 | pr_warning( | |
2125 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" | |
2126 | " reached. Keeping one slot for boot cpu." | |
2127 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2128 | ||
2129 | disabled_cpus++; | |
2130 | return; | |
2131 | } | |
be8a5685 | 2132 | |
3b11ce7f | 2133 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2134 | int thiscpu = max + disabled_cpus; |
2135 | ||
2136 | pr_warning( | |
2137 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
2138 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2139 | ||
2140 | disabled_cpus++; | |
be8a5685 AS |
2141 | return; |
2142 | } | |
2143 | ||
2144 | num_processors++; | |
be8a5685 AS |
2145 | if (apicid == boot_cpu_physical_apicid) { |
2146 | /* | |
2147 | * x86_bios_cpu_apicid is required to have processors listed | |
2148 | * in same order as logical cpu numbers. Hence the first | |
2149 | * entry is BSP, and so on. | |
e5fea868 YL |
2150 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2151 | * for BSP. | |
be8a5685 AS |
2152 | */ |
2153 | cpu = 0; | |
e5fea868 YL |
2154 | } else |
2155 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2156 | ||
2157 | /* | |
2158 | * Validate version | |
2159 | */ | |
2160 | if (version == 0x0) { | |
2161 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2162 | cpu, apicid); | |
2163 | version = 0x10; | |
be8a5685 | 2164 | } |
e5fea868 YL |
2165 | apic_version[apicid] = version; |
2166 | ||
2167 | if (version != apic_version[boot_cpu_physical_apicid]) { | |
2168 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", | |
2169 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
2170 | } | |
2171 | ||
2172 | physid_set(apicid, phys_cpu_present_map); | |
e0da3364 YL |
2173 | if (apicid > max_physical_apicid) |
2174 | max_physical_apicid = apicid; | |
2175 | ||
3e5095d1 | 2176 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2177 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2178 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2179 | #endif |
acb8bc09 TH |
2180 | #ifdef CONFIG_X86_32 |
2181 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2182 | apic->x86_32_early_logical_apicid(cpu); | |
2183 | #endif | |
1de88cd4 MT |
2184 | set_cpu_possible(cpu, true); |
2185 | set_cpu_present(cpu, true); | |
be8a5685 AS |
2186 | } |
2187 | ||
0c81c746 SS |
2188 | int hard_smp_processor_id(void) |
2189 | { | |
2190 | return read_apic_id(); | |
2191 | } | |
1dcdd3d1 IM |
2192 | |
2193 | void default_init_apic_ldr(void) | |
2194 | { | |
2195 | unsigned long val; | |
2196 | ||
2197 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2198 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2199 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2200 | apic_write(APIC_LDR, val); | |
2201 | } | |
2202 | ||
ff164324 AG |
2203 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
2204 | const struct cpumask *andmask, | |
2205 | unsigned int *apicid) | |
6398268d | 2206 | { |
ea3807ea | 2207 | unsigned int cpu; |
6398268d AG |
2208 | |
2209 | for_each_cpu_and(cpu, cpumask, andmask) { | |
2210 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
2211 | break; | |
2212 | } | |
ff164324 | 2213 | |
ea3807ea | 2214 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
2215 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
2216 | return 0; | |
a5a39156 | 2217 | } |
ea3807ea AG |
2218 | |
2219 | return -EINVAL; | |
6398268d AG |
2220 | } |
2221 | ||
1551df64 MT |
2222 | /* |
2223 | * Override the generic EOI implementation with an optimized version. | |
2224 | * Only called during early boot when only one CPU is active and with | |
2225 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2226 | * use. | |
2227 | */ | |
2228 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2229 | { | |
2230 | struct apic **drv; | |
2231 | ||
2232 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2233 | /* Should happen once for each apic */ | |
2234 | WARN_ON((*drv)->eoi_write == eoi_write); | |
2235 | (*drv)->eoi_write = eoi_write; | |
2236 | } | |
2237 | } | |
2238 | ||
89039b37 | 2239 | /* |
0e078e2f | 2240 | * Power management |
89039b37 | 2241 | */ |
0e078e2f TG |
2242 | #ifdef CONFIG_PM |
2243 | ||
2244 | static struct { | |
274cfe59 CG |
2245 | /* |
2246 | * 'active' is true if the local APIC was enabled by us and | |
2247 | * not the BIOS; this signifies that we are also responsible | |
2248 | * for disabling it before entering apm/acpi suspend | |
2249 | */ | |
0e078e2f TG |
2250 | int active; |
2251 | /* r/w apic fields */ | |
2252 | unsigned int apic_id; | |
2253 | unsigned int apic_taskpri; | |
2254 | unsigned int apic_ldr; | |
2255 | unsigned int apic_dfr; | |
2256 | unsigned int apic_spiv; | |
2257 | unsigned int apic_lvtt; | |
2258 | unsigned int apic_lvtpc; | |
2259 | unsigned int apic_lvt0; | |
2260 | unsigned int apic_lvt1; | |
2261 | unsigned int apic_lvterr; | |
2262 | unsigned int apic_tmict; | |
2263 | unsigned int apic_tdcr; | |
2264 | unsigned int apic_thmr; | |
2265 | } apic_pm_state; | |
2266 | ||
f3c6ea1b | 2267 | static int lapic_suspend(void) |
0e078e2f TG |
2268 | { |
2269 | unsigned long flags; | |
2270 | int maxlvt; | |
89039b37 | 2271 | |
0e078e2f TG |
2272 | if (!apic_pm_state.active) |
2273 | return 0; | |
89039b37 | 2274 | |
0e078e2f | 2275 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2276 | |
2d7a66d0 | 2277 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2278 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2279 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2280 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2281 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2282 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2283 | if (maxlvt >= 4) | |
2284 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2285 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2286 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2287 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2288 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2289 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2290 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2291 | if (maxlvt >= 5) |
2292 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2293 | #endif | |
24968cfd | 2294 | |
0e078e2f TG |
2295 | local_irq_save(flags); |
2296 | disable_local_APIC(); | |
fc1edaf9 | 2297 | |
70733e0c | 2298 | irq_remapping_disable(); |
fc1edaf9 | 2299 | |
0e078e2f TG |
2300 | local_irq_restore(flags); |
2301 | return 0; | |
1da177e4 LT |
2302 | } |
2303 | ||
f3c6ea1b | 2304 | static void lapic_resume(void) |
1da177e4 | 2305 | { |
0e078e2f TG |
2306 | unsigned int l, h; |
2307 | unsigned long flags; | |
31dce14a | 2308 | int maxlvt; |
b24696bc | 2309 | |
0e078e2f | 2310 | if (!apic_pm_state.active) |
f3c6ea1b | 2311 | return; |
89b831ef | 2312 | |
0e078e2f | 2313 | local_irq_save(flags); |
336224ba JR |
2314 | |
2315 | /* | |
2316 | * IO-APIC and PIC have their own resume routines. | |
2317 | * We just mask them here to make sure the interrupt | |
2318 | * subsystem is completely quiet while we enable x2apic | |
2319 | * and interrupt-remapping. | |
2320 | */ | |
2321 | mask_ioapic_entries(); | |
2322 | legacy_pic->mask_all(); | |
92206c90 | 2323 | |
fc1edaf9 | 2324 | if (x2apic_mode) |
92206c90 | 2325 | enable_x2apic(); |
cf6567fe | 2326 | else { |
92206c90 CG |
2327 | /* |
2328 | * Make sure the APICBASE points to the right address | |
2329 | * | |
2330 | * FIXME! This will be wrong if we ever support suspend on | |
2331 | * SMP! We'll need to do this as part of the CPU restore! | |
2332 | */ | |
cbf2829b BD |
2333 | if (boot_cpu_data.x86 >= 6) { |
2334 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2335 | l &= ~MSR_IA32_APICBASE_BASE; | |
2336 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2337 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2338 | } | |
d5e629a6 | 2339 | } |
6e1cb38a | 2340 | |
b24696bc | 2341 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2342 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2343 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2344 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2345 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2346 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2347 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2348 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2349 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
71c69f7f | 2350 | #if defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2351 | if (maxlvt >= 5) |
2352 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2353 | #endif | |
2354 | if (maxlvt >= 4) | |
2355 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2356 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2357 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2358 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2359 | apic_write(APIC_ESR, 0); | |
2360 | apic_read(APIC_ESR); | |
2361 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2362 | apic_write(APIC_ESR, 0); | |
2363 | apic_read(APIC_ESR); | |
92206c90 | 2364 | |
70733e0c | 2365 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2366 | |
0e078e2f | 2367 | local_irq_restore(flags); |
0e078e2f | 2368 | } |
b8ce3359 | 2369 | |
274cfe59 CG |
2370 | /* |
2371 | * This device has no shutdown method - fully functioning local APICs | |
2372 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2373 | */ | |
2374 | ||
f3c6ea1b | 2375 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2376 | .resume = lapic_resume, |
2377 | .suspend = lapic_suspend, | |
2378 | }; | |
b8ce3359 | 2379 | |
148f9bb8 | 2380 | static void apic_pm_activate(void) |
0e078e2f TG |
2381 | { |
2382 | apic_pm_state.active = 1; | |
1da177e4 LT |
2383 | } |
2384 | ||
0e078e2f | 2385 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2386 | { |
0e078e2f | 2387 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
f3c6ea1b RW |
2388 | if (cpu_has_apic) |
2389 | register_syscore_ops(&lapic_syscore_ops); | |
e83a5fdc | 2390 | |
f3c6ea1b | 2391 | return 0; |
1da177e4 | 2392 | } |
b24696bc FY |
2393 | |
2394 | /* local apic needs to resume before other devices access its registers. */ | |
2395 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2396 | |
2397 | #else /* CONFIG_PM */ | |
2398 | ||
2399 | static void apic_pm_activate(void) { } | |
2400 | ||
2401 | #endif /* CONFIG_PM */ | |
1da177e4 | 2402 | |
f28c0ae2 | 2403 | #ifdef CONFIG_X86_64 |
e0e42142 | 2404 | |
148f9bb8 | 2405 | static int apic_cluster_num(void) |
1da177e4 LT |
2406 | { |
2407 | int i, clusters, zeros; | |
2408 | unsigned id; | |
322850af | 2409 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2410 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2411 | ||
23ca4bba | 2412 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2413 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2414 | |
168ef543 | 2415 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2416 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2417 | if (bios_cpu_apicid) { |
2418 | id = bios_cpu_apicid[i]; | |
e423e33e | 2419 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2420 | if (cpu_present(i)) |
2421 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2422 | else | |
2423 | continue; | |
e423e33e | 2424 | } else |
e8c10ef9 | 2425 | break; |
2426 | ||
1da177e4 LT |
2427 | if (id != BAD_APICID) |
2428 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2429 | } | |
2430 | ||
2431 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2432 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2433 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2434 | * Since clusters are allocated sequentially, count zeros only if | |
2435 | * they are bounded by ones. | |
1da177e4 LT |
2436 | */ |
2437 | clusters = 0; | |
2438 | zeros = 0; | |
2439 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2440 | if (test_bit(i, clustermap)) { | |
2441 | clusters += 1 + zeros; | |
2442 | zeros = 0; | |
2443 | } else | |
2444 | ++zeros; | |
2445 | } | |
2446 | ||
e0e42142 YL |
2447 | return clusters; |
2448 | } | |
2449 | ||
148f9bb8 PG |
2450 | static int multi_checked; |
2451 | static int multi; | |
e0e42142 | 2452 | |
148f9bb8 | 2453 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2454 | { |
2455 | if (multi) | |
2456 | return 0; | |
6f0aced6 | 2457 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2458 | multi = 1; |
2459 | return 0; | |
2460 | } | |
2461 | ||
148f9bb8 | 2462 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2463 | { |
2464 | .callback = set_multi, | |
2465 | .ident = "IBM System Summit2", | |
2466 | .matches = { | |
2467 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2468 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2469 | }, | |
2470 | }, | |
2471 | {} | |
2472 | }; | |
2473 | ||
148f9bb8 | 2474 | static void dmi_check_multi(void) |
e0e42142 YL |
2475 | { |
2476 | if (multi_checked) | |
2477 | return; | |
2478 | ||
2479 | dmi_check_system(multi_dmi_table); | |
2480 | multi_checked = 1; | |
2481 | } | |
2482 | ||
2483 | /* | |
2484 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2485 | * | |
2486 | * Thus far, the major user of this is IBM's Summit2 series: | |
2487 | * Clustered boxes may have unsynced TSC problems if they are | |
2488 | * multi-chassis. | |
2489 | * Use DMI to check them | |
2490 | */ | |
148f9bb8 | 2491 | int apic_is_clustered_box(void) |
e0e42142 YL |
2492 | { |
2493 | dmi_check_multi(); | |
2494 | if (multi) | |
1cb68487 RT |
2495 | return 1; |
2496 | ||
e0e42142 YL |
2497 | if (!is_vsmp_box()) |
2498 | return 0; | |
2499 | ||
1da177e4 | 2500 | /* |
e0e42142 YL |
2501 | * ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2502 | * not guaranteed to be synced between boards | |
1da177e4 | 2503 | */ |
e0e42142 YL |
2504 | if (apic_cluster_num() > 1) |
2505 | return 1; | |
2506 | ||
2507 | return 0; | |
1da177e4 | 2508 | } |
f28c0ae2 | 2509 | #endif |
1da177e4 LT |
2510 | |
2511 | /* | |
0e078e2f | 2512 | * APIC command line parameters |
1da177e4 | 2513 | */ |
789fa735 | 2514 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2515 | { |
1da177e4 | 2516 | disable_apic = 1; |
9175fc06 | 2517 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2518 | return 0; |
2519 | } | |
2520 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2521 | |
2c8c0e6b | 2522 | /* same as disableapic, for compatibility */ |
789fa735 | 2523 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2524 | { |
789fa735 | 2525 | return setup_disableapic(arg); |
6935d1f9 | 2526 | } |
2c8c0e6b | 2527 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2528 | |
2e7c2838 LT |
2529 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2530 | { | |
2531 | local_apic_timer_c2_ok = 1; | |
2532 | return 0; | |
2533 | } | |
2534 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2535 | ||
36fef094 | 2536 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2537 | { |
1da177e4 | 2538 | disable_apic_timer = 1; |
36fef094 | 2539 | return 0; |
6935d1f9 | 2540 | } |
36fef094 CG |
2541 | early_param("noapictimer", parse_disable_apic_timer); |
2542 | ||
2543 | static int __init parse_nolapic_timer(char *arg) | |
2544 | { | |
2545 | disable_apic_timer = 1; | |
2546 | return 0; | |
6935d1f9 | 2547 | } |
36fef094 | 2548 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2549 | |
79af9bec CG |
2550 | static int __init apic_set_verbosity(char *arg) |
2551 | { | |
2552 | if (!arg) { | |
2553 | #ifdef CONFIG_X86_64 | |
2554 | skip_ioapic_setup = 0; | |
79af9bec CG |
2555 | return 0; |
2556 | #endif | |
2557 | return -EINVAL; | |
2558 | } | |
2559 | ||
2560 | if (strcmp("debug", arg) == 0) | |
2561 | apic_verbosity = APIC_DEBUG; | |
2562 | else if (strcmp("verbose", arg) == 0) | |
2563 | apic_verbosity = APIC_VERBOSE; | |
2564 | else { | |
ba21ebb6 | 2565 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2566 | " use apic=verbose or apic=debug\n", arg); |
2567 | return -EINVAL; | |
2568 | } | |
2569 | ||
2570 | return 0; | |
2571 | } | |
2572 | early_param("apic", apic_set_verbosity); | |
2573 | ||
1e934dda YL |
2574 | static int __init lapic_insert_resource(void) |
2575 | { | |
2576 | if (!apic_phys) | |
2577 | return -1; | |
2578 | ||
2579 | /* Put local APIC into the resource map. */ | |
2580 | lapic_resource.start = apic_phys; | |
2581 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2582 | insert_resource(&iomem_resource, &lapic_resource); | |
2583 | ||
2584 | return 0; | |
2585 | } | |
2586 | ||
2587 | /* | |
2588 | * need call insert after e820_reserve_resources() | |
2589 | * that is using request_resource | |
2590 | */ | |
2591 | late_initcall(lapic_insert_resource); |