Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 TG |
76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
77 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 78 | |
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
2a4ab640 FT |
88 | /* IO APIC gsi routing info */ |
89 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
90 | ||
a4384df3 EB |
91 | /* The one past the highest gsi number used */ |
92 | u32 gsi_top; | |
5777372a | 93 | |
584f734d | 94 | /* MP IRQ source entries */ |
c2c21745 | 95 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
96 | |
97 | /* # of MP IRQ source entries */ | |
98 | int mp_irq_entries; | |
99 | ||
bc07844a TG |
100 | /* GSI interrupts */ |
101 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
102 | ||
4c79185c SS |
103 | /* |
104 | * Saved I/O APIC state during suspend/resume. | |
105 | */ | |
106 | static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS]; | |
107 | ||
8732fc4b AS |
108 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
109 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
110 | #endif | |
111 | ||
112 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
113 | ||
efa2559f YL |
114 | int skip_ioapic_setup; |
115 | ||
7167d08e HK |
116 | /** |
117 | * disable_ioapic_support() - disables ioapic support at runtime | |
118 | */ | |
119 | void disable_ioapic_support(void) | |
65a4e574 IM |
120 | { |
121 | #ifdef CONFIG_PCI | |
122 | noioapicquirk = 1; | |
123 | noioapicreroute = -1; | |
124 | #endif | |
125 | skip_ioapic_setup = 1; | |
126 | } | |
127 | ||
54168ed7 | 128 | static int __init parse_noapic(char *str) |
efa2559f YL |
129 | { |
130 | /* disable IO-APIC */ | |
7167d08e | 131 | disable_ioapic_support(); |
efa2559f YL |
132 | return 0; |
133 | } | |
134 | early_param("noapic", parse_noapic); | |
66759a01 | 135 | |
20443598 SAS |
136 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
137 | struct io_apic_irq_attr *attr); | |
710dcda6 | 138 | |
2d8009ba FT |
139 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
140 | void mp_save_irq(struct mpc_intsrc *m) | |
141 | { | |
142 | int i; | |
143 | ||
144 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
145 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
146 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
147 | m->srcbusirq, m->dstapic, m->dstirq); | |
148 | ||
149 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 150 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
151 | return; |
152 | } | |
153 | ||
0e3fa13f | 154 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
155 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
156 | panic("Max # of irq sources exceeded!!\n"); | |
157 | } | |
158 | ||
0b8f1efa YL |
159 | struct irq_pin_list { |
160 | int apic, pin; | |
161 | struct irq_pin_list *next; | |
162 | }; | |
163 | ||
7e495529 | 164 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 165 | { |
2ee39065 | 166 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
167 | } |
168 | ||
2d8009ba | 169 | |
a1420f39 | 170 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 171 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 172 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 173 | #else |
97943390 | 174 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 175 | #endif |
a1420f39 | 176 | |
13a0c3c2 | 177 | int __init arch_early_irq_init(void) |
8f09cd20 | 178 | { |
0b8f1efa | 179 | struct irq_cfg *cfg; |
60c69948 | 180 | int count, node, i; |
d6c88a50 | 181 | |
1f91233c JP |
182 | if (!legacy_pic->nr_legacy_irqs) { |
183 | nr_irqs_gsi = 0; | |
184 | io_apic_irqs = ~0UL; | |
185 | } | |
186 | ||
4c79185c SS |
187 | for (i = 0; i < nr_ioapics; i++) { |
188 | ioapic_saved_data[i] = | |
189 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
190 | nr_ioapic_registers[i], GFP_KERNEL); | |
191 | if (!ioapic_saved_data[i]) | |
192 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); | |
193 | } | |
194 | ||
0b8f1efa YL |
195 | cfg = irq_cfgx; |
196 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 197 | node = cpu_to_node(0); |
8f09cd20 | 198 | |
fbc6bff0 TG |
199 | /* Make sure the legacy interrupts are marked in the bitmap */ |
200 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
201 | ||
0b8f1efa | 202 | for (i = 0; i < count; i++) { |
2c778651 | 203 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
204 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
205 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
206 | /* |
207 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
208 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
209 | */ | |
54b56170 | 210 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
211 | cfg[i].vector = IRQ0_VECTOR + i; |
212 | cpumask_set_cpu(0, cfg[i].domain); | |
213 | } | |
0b8f1efa | 214 | } |
13a0c3c2 YL |
215 | |
216 | return 0; | |
0b8f1efa | 217 | } |
8f09cd20 | 218 | |
0b8f1efa | 219 | #ifdef CONFIG_SPARSE_IRQ |
48b26501 | 220 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 221 | { |
2c778651 | 222 | return irq_get_chip_data(irq); |
8f09cd20 | 223 | } |
d6c88a50 | 224 | |
f981a3dc | 225 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 226 | { |
0b8f1efa | 227 | struct irq_cfg *cfg; |
0f978f45 | 228 | |
2ee39065 | 229 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
230 | if (!cfg) |
231 | return NULL; | |
2ee39065 | 232 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 233 | goto out_cfg; |
2ee39065 | 234 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 235 | goto out_domain; |
0b8f1efa | 236 | return cfg; |
6e2fff50 TG |
237 | out_domain: |
238 | free_cpumask_var(cfg->domain); | |
239 | out_cfg: | |
240 | kfree(cfg); | |
241 | return NULL; | |
8f09cd20 YL |
242 | } |
243 | ||
f981a3dc | 244 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 245 | { |
fbc6bff0 TG |
246 | if (!cfg) |
247 | return; | |
2c778651 | 248 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
249 | free_cpumask_var(cfg->domain); |
250 | free_cpumask_var(cfg->old_domain); | |
251 | kfree(cfg); | |
252 | } | |
253 | ||
0b8f1efa | 254 | #else |
08c33db6 | 255 | |
9338ad6f | 256 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
257 | { |
258 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 259 | } |
1da177e4 | 260 | |
f981a3dc | 261 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
08c33db6 TG |
262 | { |
263 | return irq_cfgx + irq; | |
264 | } | |
265 | ||
f981a3dc | 266 | static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } |
08c33db6 | 267 | |
0b8f1efa YL |
268 | #endif |
269 | ||
08c33db6 TG |
270 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
271 | { | |
272 | int res = irq_alloc_desc_at(at, node); | |
273 | struct irq_cfg *cfg; | |
274 | ||
275 | if (res < 0) { | |
276 | if (res != -EEXIST) | |
277 | return NULL; | |
2c778651 | 278 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
279 | if (cfg) |
280 | return cfg; | |
281 | } | |
282 | ||
f981a3dc | 283 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 284 | if (cfg) |
2c778651 | 285 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
286 | else |
287 | irq_free_desc(at); | |
288 | return cfg; | |
289 | } | |
290 | ||
291 | static int alloc_irq_from(unsigned int from, int node) | |
292 | { | |
293 | return irq_alloc_desc_from(from, node); | |
294 | } | |
295 | ||
296 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
297 | { | |
f981a3dc | 298 | free_irq_cfg(at, cfg); |
08c33db6 TG |
299 | irq_free_desc(at); |
300 | } | |
301 | ||
130fe05d LT |
302 | struct io_apic { |
303 | unsigned int index; | |
304 | unsigned int unused[3]; | |
305 | unsigned int data; | |
0280f7c4 SS |
306 | unsigned int unused2[11]; |
307 | unsigned int eoi; | |
130fe05d LT |
308 | }; |
309 | ||
310 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
311 | { | |
312 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 313 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
314 | } |
315 | ||
0280f7c4 SS |
316 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
317 | { | |
318 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
319 | writel(vector, &io_apic->eoi); | |
320 | } | |
321 | ||
130fe05d LT |
322 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
323 | { | |
324 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
325 | writel(reg, &io_apic->index); | |
326 | return readl(&io_apic->data); | |
327 | } | |
328 | ||
329 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
330 | { | |
331 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
332 | writel(reg, &io_apic->index); | |
333 | writel(value, &io_apic->data); | |
334 | } | |
335 | ||
336 | /* | |
337 | * Re-write a value: to be used for read-modify-write | |
338 | * cycles where the read already set up the index register. | |
339 | * | |
340 | * Older SiS APIC requires we rewrite the index register | |
341 | */ | |
342 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
343 | { | |
54168ed7 | 344 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
345 | |
346 | if (sis_apic_bug) | |
347 | writel(reg, &io_apic->index); | |
130fe05d LT |
348 | writel(value, &io_apic->data); |
349 | } | |
350 | ||
3145e941 | 351 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
352 | { |
353 | struct irq_pin_list *entry; | |
354 | unsigned long flags; | |
047c8fdb | 355 | |
dade7716 | 356 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 357 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
358 | unsigned int reg; |
359 | int pin; | |
360 | ||
047c8fdb YL |
361 | pin = entry->pin; |
362 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
363 | /* Is the remote IRR bit set? */ | |
364 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 365 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
366 | return true; |
367 | } | |
047c8fdb | 368 | } |
dade7716 | 369 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
370 | |
371 | return false; | |
372 | } | |
047c8fdb | 373 | |
cf4c6a2f AK |
374 | union entry_union { |
375 | struct { u32 w1, w2; }; | |
376 | struct IO_APIC_route_entry entry; | |
377 | }; | |
378 | ||
379 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
380 | { | |
381 | union entry_union eu; | |
382 | unsigned long flags; | |
dade7716 | 383 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
384 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
385 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 386 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
387 | return eu.entry; |
388 | } | |
389 | ||
f9dadfa7 LT |
390 | /* |
391 | * When we write a new IO APIC routing entry, we need to write the high | |
392 | * word first! If the mask bit in the low word is clear, we will enable | |
393 | * the interrupt, and we need to make sure the entry is fully populated | |
394 | * before that happens. | |
395 | */ | |
d15512f4 AK |
396 | static void |
397 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 398 | { |
50a8d4d2 F |
399 | union entry_union eu = {{0, 0}}; |
400 | ||
cf4c6a2f | 401 | eu.entry = e; |
f9dadfa7 LT |
402 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
403 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
404 | } |
405 | ||
1a8ce7ff | 406 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
407 | { |
408 | unsigned long flags; | |
dade7716 | 409 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 410 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 411 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
412 | } |
413 | ||
414 | /* | |
415 | * When we mask an IO APIC routing entry, we need to write the low | |
416 | * word first, in order to set the mask bit before we change the | |
417 | * high bits! | |
418 | */ | |
419 | static void ioapic_mask_entry(int apic, int pin) | |
420 | { | |
421 | unsigned long flags; | |
422 | union entry_union eu = { .entry.mask = 1 }; | |
423 | ||
dade7716 | 424 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
425 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
426 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 427 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
428 | } |
429 | ||
1da177e4 LT |
430 | /* |
431 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
432 | * shared ISA-space IRQs, so we have to support them. We are super | |
433 | * fast in the common case, and fast for shared ISA-space IRQs. | |
434 | */ | |
f3d1915a | 435 | static int |
7e495529 | 436 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 437 | { |
2977fb3f | 438 | struct irq_pin_list **last, *entry; |
0f978f45 | 439 | |
2977fb3f CG |
440 | /* don't allow duplicates */ |
441 | last = &cfg->irq_2_pin; | |
442 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 443 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 444 | return 0; |
2977fb3f | 445 | last = &entry->next; |
1da177e4 | 446 | } |
0f978f45 | 447 | |
7e495529 | 448 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 449 | if (!entry) { |
f3d1915a CG |
450 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
451 | node, apic, pin); | |
452 | return -ENOMEM; | |
a7428cd2 | 453 | } |
1da177e4 LT |
454 | entry->apic = apic; |
455 | entry->pin = pin; | |
875e68ec | 456 | |
2977fb3f | 457 | *last = entry; |
f3d1915a CG |
458 | return 0; |
459 | } | |
460 | ||
461 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
462 | { | |
7e495529 | 463 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 464 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
465 | } |
466 | ||
467 | /* | |
468 | * Reroute an IRQ to a different pin. | |
469 | */ | |
85ac16d0 | 470 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
471 | int oldapic, int oldpin, |
472 | int newapic, int newpin) | |
1da177e4 | 473 | { |
535b6429 | 474 | struct irq_pin_list *entry; |
1da177e4 | 475 | |
2977fb3f | 476 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
477 | if (entry->apic == oldapic && entry->pin == oldpin) { |
478 | entry->apic = newapic; | |
479 | entry->pin = newpin; | |
0f978f45 | 480 | /* every one is different, right? */ |
4eea6fff | 481 | return; |
0f978f45 | 482 | } |
1da177e4 | 483 | } |
0f978f45 | 484 | |
4eea6fff JF |
485 | /* old apic/pin didn't exist, so just add new ones */ |
486 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
487 | } |
488 | ||
c29d9db3 SS |
489 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
490 | int mask_and, int mask_or, | |
491 | void (*final)(struct irq_pin_list *entry)) | |
492 | { | |
493 | unsigned int reg, pin; | |
494 | ||
495 | pin = entry->pin; | |
496 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
497 | reg &= mask_and; | |
498 | reg |= mask_or; | |
499 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
500 | if (final) | |
501 | final(entry); | |
502 | } | |
503 | ||
2f210deb JF |
504 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
505 | int mask_and, int mask_or, | |
506 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 507 | { |
87783be4 | 508 | struct irq_pin_list *entry; |
047c8fdb | 509 | |
c29d9db3 SS |
510 | for_each_irq_pin(entry, cfg->irq_2_pin) |
511 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
512 | } | |
513 | ||
514 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
515 | { | |
516 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
517 | IO_APIC_REDIR_MASKED, NULL); | |
518 | } | |
519 | ||
520 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
521 | { | |
522 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
523 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 524 | } |
047c8fdb | 525 | |
7f3e632f | 526 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 527 | { |
87783be4 CG |
528 | /* |
529 | * Synchronize the IO-APIC and the CPU by doing | |
530 | * a dummy read from the IO-APIC | |
531 | */ | |
532 | struct io_apic __iomem *io_apic; | |
533 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 534 | readl(&io_apic->data); |
1da177e4 LT |
535 | } |
536 | ||
dd5f15e5 | 537 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 538 | { |
dd5f15e5 TG |
539 | unsigned long flags; |
540 | ||
541 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 542 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 543 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 544 | } |
1da177e4 | 545 | |
90297c5f | 546 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 547 | { |
90297c5f | 548 | mask_ioapic(data->chip_data); |
dd5f15e5 | 549 | } |
3145e941 | 550 | |
dd5f15e5 TG |
551 | static void __unmask_ioapic(struct irq_cfg *cfg) |
552 | { | |
553 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
554 | } |
555 | ||
dd5f15e5 | 556 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
557 | { |
558 | unsigned long flags; | |
559 | ||
dade7716 | 560 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 561 | __unmask_ioapic(cfg); |
dade7716 | 562 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
563 | } |
564 | ||
90297c5f | 565 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 566 | { |
90297c5f | 567 | unmask_ioapic(data->chip_data); |
3145e941 YL |
568 | } |
569 | ||
1da177e4 LT |
570 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
571 | { | |
572 | struct IO_APIC_route_entry entry; | |
36062448 | 573 | |
1da177e4 | 574 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 575 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
576 | if (entry.delivery_mode == dest_SMI) |
577 | return; | |
1da177e4 LT |
578 | /* |
579 | * Disable it in the IO-APIC irq-routing table: | |
580 | */ | |
f9dadfa7 | 581 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
582 | } |
583 | ||
54168ed7 | 584 | static void clear_IO_APIC (void) |
1da177e4 LT |
585 | { |
586 | int apic, pin; | |
587 | ||
588 | for (apic = 0; apic < nr_ioapics; apic++) | |
589 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
590 | clear_IO_APIC_pin(apic, pin); | |
591 | } | |
592 | ||
54168ed7 | 593 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
594 | /* |
595 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
596 | * specific CPU-side IRQs. | |
597 | */ | |
598 | ||
599 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
600 | static int pirq_entries[MAX_PIRQS] = { |
601 | [0 ... MAX_PIRQS - 1] = -1 | |
602 | }; | |
1da177e4 | 603 | |
1da177e4 LT |
604 | static int __init ioapic_pirq_setup(char *str) |
605 | { | |
606 | int i, max; | |
607 | int ints[MAX_PIRQS+1]; | |
608 | ||
609 | get_options(str, ARRAY_SIZE(ints), ints); | |
610 | ||
1da177e4 LT |
611 | apic_printk(APIC_VERBOSE, KERN_INFO |
612 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
613 | max = MAX_PIRQS; | |
614 | if (ints[0] < MAX_PIRQS) | |
615 | max = ints[0]; | |
616 | ||
617 | for (i = 0; i < max; i++) { | |
618 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
619 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
620 | /* | |
621 | * PIRQs are mapped upside down, usually. | |
622 | */ | |
623 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
624 | } | |
625 | return 1; | |
626 | } | |
627 | ||
628 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
629 | #endif /* CONFIG_X86_32 */ |
630 | ||
b24696bc FY |
631 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
632 | { | |
633 | int apic; | |
634 | struct IO_APIC_route_entry **ioapic_entries; | |
635 | ||
636 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
b64ce24d | 637 | GFP_ATOMIC); |
b24696bc FY |
638 | if (!ioapic_entries) |
639 | return 0; | |
640 | ||
641 | for (apic = 0; apic < nr_ioapics; apic++) { | |
642 | ioapic_entries[apic] = | |
643 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
b64ce24d | 644 | nr_ioapic_registers[apic], GFP_ATOMIC); |
b24696bc FY |
645 | if (!ioapic_entries[apic]) |
646 | goto nomem; | |
647 | } | |
648 | ||
649 | return ioapic_entries; | |
650 | ||
651 | nomem: | |
652 | while (--apic >= 0) | |
653 | kfree(ioapic_entries[apic]); | |
654 | kfree(ioapic_entries); | |
655 | ||
656 | return 0; | |
657 | } | |
54168ed7 IM |
658 | |
659 | /* | |
05c3dc2c | 660 | * Saves all the IO-APIC RTE's |
54168ed7 | 661 | */ |
b24696bc | 662 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 663 | { |
54168ed7 IM |
664 | int apic, pin; |
665 | ||
b24696bc FY |
666 | if (!ioapic_entries) |
667 | return -ENOMEM; | |
54168ed7 IM |
668 | |
669 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
670 | if (!ioapic_entries[apic]) |
671 | return -ENOMEM; | |
54168ed7 | 672 | |
05c3dc2c | 673 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 674 | ioapic_entries[apic][pin] = |
54168ed7 | 675 | ioapic_read_entry(apic, pin); |
b24696bc | 676 | } |
5ffa4eb2 | 677 | |
54168ed7 IM |
678 | return 0; |
679 | } | |
680 | ||
b24696bc FY |
681 | /* |
682 | * Mask all IO APIC entries. | |
683 | */ | |
684 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
685 | { |
686 | int apic, pin; | |
687 | ||
b24696bc FY |
688 | if (!ioapic_entries) |
689 | return; | |
690 | ||
05c3dc2c | 691 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 692 | if (!ioapic_entries[apic]) |
05c3dc2c | 693 | break; |
b24696bc | 694 | |
05c3dc2c SS |
695 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
696 | struct IO_APIC_route_entry entry; | |
697 | ||
b24696bc | 698 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
699 | if (!entry.mask) { |
700 | entry.mask = 1; | |
701 | ioapic_write_entry(apic, pin, entry); | |
702 | } | |
703 | } | |
704 | } | |
705 | } | |
706 | ||
b24696bc FY |
707 | /* |
708 | * Restore IO APIC entries which was saved in ioapic_entries. | |
709 | */ | |
710 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
711 | { |
712 | int apic, pin; | |
713 | ||
b24696bc FY |
714 | if (!ioapic_entries) |
715 | return -ENOMEM; | |
716 | ||
5ffa4eb2 | 717 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
718 | if (!ioapic_entries[apic]) |
719 | return -ENOMEM; | |
720 | ||
54168ed7 IM |
721 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
722 | ioapic_write_entry(apic, pin, | |
b24696bc | 723 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 724 | } |
b24696bc | 725 | return 0; |
54168ed7 IM |
726 | } |
727 | ||
b24696bc FY |
728 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
729 | { | |
730 | int apic; | |
731 | ||
732 | for (apic = 0; apic < nr_ioapics; apic++) | |
733 | kfree(ioapic_entries[apic]); | |
734 | ||
735 | kfree(ioapic_entries); | |
54168ed7 | 736 | } |
1da177e4 LT |
737 | |
738 | /* | |
739 | * Find the IRQ entry number of a certain pin. | |
740 | */ | |
741 | static int find_irq_entry(int apic, int pin, int type) | |
742 | { | |
743 | int i; | |
744 | ||
745 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
746 | if (mp_irqs[i].irqtype == type && |
747 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
748 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
749 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
750 | return i; |
751 | ||
752 | return -1; | |
753 | } | |
754 | ||
755 | /* | |
756 | * Find the pin to which IRQ[irq] (ISA) is connected | |
757 | */ | |
fcfd636a | 758 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
759 | { |
760 | int i; | |
761 | ||
762 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 763 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 764 | |
d27e2b8e | 765 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
766 | (mp_irqs[i].irqtype == type) && |
767 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 768 | |
c2c21745 | 769 | return mp_irqs[i].dstirq; |
1da177e4 LT |
770 | } |
771 | return -1; | |
772 | } | |
773 | ||
fcfd636a EB |
774 | static int __init find_isa_irq_apic(int irq, int type) |
775 | { | |
776 | int i; | |
777 | ||
778 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 779 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 780 | |
73b2961b | 781 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
782 | (mp_irqs[i].irqtype == type) && |
783 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
784 | break; |
785 | } | |
786 | if (i < mp_irq_entries) { | |
787 | int apic; | |
54168ed7 | 788 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 789 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
790 | return apic; |
791 | } | |
792 | } | |
793 | ||
794 | return -1; | |
795 | } | |
796 | ||
c0a282c2 | 797 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
798 | /* |
799 | * EISA Edge/Level control register, ELCR | |
800 | */ | |
801 | static int EISA_ELCR(unsigned int irq) | |
802 | { | |
b81bb373 | 803 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
804 | unsigned int port = 0x4d0 + (irq >> 3); |
805 | return (inb(port) >> (irq & 7)) & 1; | |
806 | } | |
807 | apic_printk(APIC_VERBOSE, KERN_INFO | |
808 | "Broken MPtable reports ISA irq %d\n", irq); | |
809 | return 0; | |
810 | } | |
54168ed7 | 811 | |
c0a282c2 | 812 | #endif |
1da177e4 | 813 | |
6728801d AS |
814 | /* ISA interrupts are always polarity zero edge triggered, |
815 | * when listed as conforming in the MP table. */ | |
816 | ||
817 | #define default_ISA_trigger(idx) (0) | |
818 | #define default_ISA_polarity(idx) (0) | |
819 | ||
1da177e4 LT |
820 | /* EISA interrupts are always polarity zero and can be edge or level |
821 | * trigger depending on the ELCR value. If an interrupt is listed as | |
822 | * EISA conforming in the MP table, that means its trigger type must | |
823 | * be read in from the ELCR */ | |
824 | ||
c2c21745 | 825 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 826 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
827 | |
828 | /* PCI interrupts are always polarity one level triggered, | |
829 | * when listed as conforming in the MP table. */ | |
830 | ||
831 | #define default_PCI_trigger(idx) (1) | |
832 | #define default_PCI_polarity(idx) (1) | |
833 | ||
834 | /* MCA interrupts are always polarity zero level triggered, | |
835 | * when listed as conforming in the MP table. */ | |
836 | ||
837 | #define default_MCA_trigger(idx) (1) | |
6728801d | 838 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 839 | |
b77cf6a8 | 840 | static int irq_polarity(int idx) |
1da177e4 | 841 | { |
c2c21745 | 842 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
843 | int polarity; |
844 | ||
845 | /* | |
846 | * Determine IRQ line polarity (high active or low active): | |
847 | */ | |
c2c21745 | 848 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 849 | { |
54168ed7 IM |
850 | case 0: /* conforms, ie. bus-type dependent polarity */ |
851 | if (test_bit(bus, mp_bus_not_pci)) | |
852 | polarity = default_ISA_polarity(idx); | |
853 | else | |
854 | polarity = default_PCI_polarity(idx); | |
855 | break; | |
856 | case 1: /* high active */ | |
857 | { | |
858 | polarity = 0; | |
859 | break; | |
860 | } | |
861 | case 2: /* reserved */ | |
862 | { | |
863 | printk(KERN_WARNING "broken BIOS!!\n"); | |
864 | polarity = 1; | |
865 | break; | |
866 | } | |
867 | case 3: /* low active */ | |
868 | { | |
869 | polarity = 1; | |
870 | break; | |
871 | } | |
872 | default: /* invalid */ | |
873 | { | |
874 | printk(KERN_WARNING "broken BIOS!!\n"); | |
875 | polarity = 1; | |
876 | break; | |
877 | } | |
1da177e4 LT |
878 | } |
879 | return polarity; | |
880 | } | |
881 | ||
b77cf6a8 | 882 | static int irq_trigger(int idx) |
1da177e4 | 883 | { |
c2c21745 | 884 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
885 | int trigger; |
886 | ||
887 | /* | |
888 | * Determine IRQ trigger mode (edge or level sensitive): | |
889 | */ | |
c2c21745 | 890 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 891 | { |
54168ed7 IM |
892 | case 0: /* conforms, ie. bus-type dependent */ |
893 | if (test_bit(bus, mp_bus_not_pci)) | |
894 | trigger = default_ISA_trigger(idx); | |
895 | else | |
896 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 897 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
898 | switch (mp_bus_id_to_type[bus]) { |
899 | case MP_BUS_ISA: /* ISA pin */ | |
900 | { | |
901 | /* set before the switch */ | |
902 | break; | |
903 | } | |
904 | case MP_BUS_EISA: /* EISA pin */ | |
905 | { | |
906 | trigger = default_EISA_trigger(idx); | |
907 | break; | |
908 | } | |
909 | case MP_BUS_PCI: /* PCI pin */ | |
910 | { | |
911 | /* set before the switch */ | |
912 | break; | |
913 | } | |
914 | case MP_BUS_MCA: /* MCA pin */ | |
915 | { | |
916 | trigger = default_MCA_trigger(idx); | |
917 | break; | |
918 | } | |
919 | default: | |
920 | { | |
921 | printk(KERN_WARNING "broken BIOS!!\n"); | |
922 | trigger = 1; | |
923 | break; | |
924 | } | |
925 | } | |
926 | #endif | |
1da177e4 | 927 | break; |
54168ed7 | 928 | case 1: /* edge */ |
1da177e4 | 929 | { |
54168ed7 | 930 | trigger = 0; |
1da177e4 LT |
931 | break; |
932 | } | |
54168ed7 | 933 | case 2: /* reserved */ |
1da177e4 | 934 | { |
54168ed7 IM |
935 | printk(KERN_WARNING "broken BIOS!!\n"); |
936 | trigger = 1; | |
1da177e4 LT |
937 | break; |
938 | } | |
54168ed7 | 939 | case 3: /* level */ |
1da177e4 | 940 | { |
54168ed7 | 941 | trigger = 1; |
1da177e4 LT |
942 | break; |
943 | } | |
54168ed7 | 944 | default: /* invalid */ |
1da177e4 LT |
945 | { |
946 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 947 | trigger = 0; |
1da177e4 LT |
948 | break; |
949 | } | |
950 | } | |
951 | return trigger; | |
952 | } | |
953 | ||
1da177e4 LT |
954 | static int pin_2_irq(int idx, int apic, int pin) |
955 | { | |
d464207c | 956 | int irq; |
c2c21745 | 957 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
958 | |
959 | /* | |
960 | * Debugging check, we are in big trouble if this message pops up! | |
961 | */ | |
c2c21745 | 962 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
963 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
964 | ||
54168ed7 | 965 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 966 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 967 | } else { |
d464207c | 968 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
969 | |
970 | if (gsi >= NR_IRQS_LEGACY) | |
971 | irq = gsi; | |
972 | else | |
a4384df3 | 973 | irq = gsi_top + gsi; |
1da177e4 LT |
974 | } |
975 | ||
54168ed7 | 976 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
977 | /* |
978 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
979 | */ | |
980 | if ((pin >= 16) && (pin <= 23)) { | |
981 | if (pirq_entries[pin-16] != -1) { | |
982 | if (!pirq_entries[pin-16]) { | |
983 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
984 | "disabling PIRQ%d\n", pin-16); | |
985 | } else { | |
986 | irq = pirq_entries[pin-16]; | |
987 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
988 | "using PIRQ%d -> IRQ %d\n", | |
989 | pin-16, irq); | |
990 | } | |
991 | } | |
992 | } | |
54168ed7 IM |
993 | #endif |
994 | ||
1da177e4 LT |
995 | return irq; |
996 | } | |
997 | ||
e20c06fd YL |
998 | /* |
999 | * Find a specific PCI IRQ entry. | |
1000 | * Not an __init, possibly needed by modules | |
1001 | */ | |
1002 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1003 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1004 | { |
1005 | int apic, i, best_guess = -1; | |
1006 | ||
1007 | apic_printk(APIC_DEBUG, | |
1008 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1009 | bus, slot, pin); | |
1010 | if (test_bit(bus, mp_bus_not_pci)) { | |
1011 | apic_printk(APIC_VERBOSE, | |
1012 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1013 | return -1; | |
1014 | } | |
1015 | for (i = 0; i < mp_irq_entries; i++) { | |
1016 | int lbus = mp_irqs[i].srcbus; | |
1017 | ||
1018 | for (apic = 0; apic < nr_ioapics; apic++) | |
1019 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1020 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1021 | break; | |
1022 | ||
1023 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1024 | !mp_irqs[i].irqtype && | |
1025 | (bus == lbus) && | |
1026 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1027 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1028 | ||
1029 | if (!(apic || IO_APIC_IRQ(irq))) | |
1030 | continue; | |
1031 | ||
1032 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1033 | set_io_apic_irq_attr(irq_attr, apic, |
1034 | mp_irqs[i].dstirq, | |
1035 | irq_trigger(i), | |
1036 | irq_polarity(i)); | |
e20c06fd YL |
1037 | return irq; |
1038 | } | |
1039 | /* | |
1040 | * Use the first all-but-pin matching entry as a | |
1041 | * best-guess fuzzy result for broken mptables. | |
1042 | */ | |
1043 | if (best_guess < 0) { | |
e5198075 YL |
1044 | set_io_apic_irq_attr(irq_attr, apic, |
1045 | mp_irqs[i].dstirq, | |
1046 | irq_trigger(i), | |
1047 | irq_polarity(i)); | |
e20c06fd YL |
1048 | best_guess = irq; |
1049 | } | |
1050 | } | |
1051 | } | |
1052 | return best_guess; | |
1053 | } | |
1054 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1055 | ||
497c9a19 YL |
1056 | void lock_vector_lock(void) |
1057 | { | |
1058 | /* Used to the online set of cpus does not change | |
1059 | * during assign_irq_vector. | |
1060 | */ | |
dade7716 | 1061 | raw_spin_lock(&vector_lock); |
497c9a19 | 1062 | } |
1da177e4 | 1063 | |
497c9a19 | 1064 | void unlock_vector_lock(void) |
1da177e4 | 1065 | { |
dade7716 | 1066 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1067 | } |
1da177e4 | 1068 | |
e7986739 MT |
1069 | static int |
1070 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1071 | { |
047c8fdb YL |
1072 | /* |
1073 | * NOTE! The local APIC isn't very good at handling | |
1074 | * multiple interrupts at the same interrupt level. | |
1075 | * As the interrupt level is determined by taking the | |
1076 | * vector number and shifting that right by 4, we | |
1077 | * want to spread these out a bit so that they don't | |
1078 | * all fall in the same interrupt level. | |
1079 | * | |
1080 | * Also, we've got to be careful not to trash gate | |
1081 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1082 | */ | |
6579b474 | 1083 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1084 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1085 | unsigned int old_vector; |
22f65d31 MT |
1086 | int cpu, err; |
1087 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1088 | |
23359a88 | 1089 | if (cfg->move_in_progress) |
54168ed7 | 1090 | return -EBUSY; |
0a1ad60d | 1091 | |
22f65d31 MT |
1092 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1093 | return -ENOMEM; | |
ace80ab7 | 1094 | |
54168ed7 IM |
1095 | old_vector = cfg->vector; |
1096 | if (old_vector) { | |
22f65d31 MT |
1097 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1098 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1099 | if (!cpumask_empty(tmp_mask)) { | |
1100 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1101 | return 0; |
22f65d31 | 1102 | } |
54168ed7 | 1103 | } |
497c9a19 | 1104 | |
e7986739 | 1105 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1106 | err = -ENOSPC; |
1107 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1108 | int new_cpu; |
1109 | int vector, offset; | |
497c9a19 | 1110 | |
e2d40b18 | 1111 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1112 | |
54168ed7 IM |
1113 | vector = current_vector; |
1114 | offset = current_offset; | |
497c9a19 | 1115 | next: |
54168ed7 IM |
1116 | vector += 8; |
1117 | if (vector >= first_system_vector) { | |
e7986739 | 1118 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1119 | offset = (offset + 1) % 8; |
6579b474 | 1120 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1121 | } |
1122 | if (unlikely(current_vector == vector)) | |
1123 | continue; | |
b77b881f YL |
1124 | |
1125 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1126 | goto next; |
b77b881f | 1127 | |
22f65d31 | 1128 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1129 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1130 | goto next; | |
1131 | /* Found one! */ | |
1132 | current_vector = vector; | |
1133 | current_offset = offset; | |
1134 | if (old_vector) { | |
1135 | cfg->move_in_progress = 1; | |
22f65d31 | 1136 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1137 | } |
22f65d31 | 1138 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1139 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1140 | cfg->vector = vector; | |
22f65d31 MT |
1141 | cpumask_copy(cfg->domain, tmp_mask); |
1142 | err = 0; | |
1143 | break; | |
54168ed7 | 1144 | } |
22f65d31 MT |
1145 | free_cpumask_var(tmp_mask); |
1146 | return err; | |
497c9a19 YL |
1147 | } |
1148 | ||
9338ad6f | 1149 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1150 | { |
1151 | int err; | |
ace80ab7 | 1152 | unsigned long flags; |
ace80ab7 | 1153 | |
dade7716 | 1154 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1155 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1156 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1157 | return err; |
1158 | } | |
1159 | ||
3145e941 | 1160 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1161 | { |
497c9a19 YL |
1162 | int cpu, vector; |
1163 | ||
497c9a19 YL |
1164 | BUG_ON(!cfg->vector); |
1165 | ||
1166 | vector = cfg->vector; | |
22f65d31 | 1167 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1168 | per_cpu(vector_irq, cpu)[vector] = -1; |
1169 | ||
1170 | cfg->vector = 0; | |
22f65d31 | 1171 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1172 | |
1173 | if (likely(!cfg->move_in_progress)) | |
1174 | return; | |
22f65d31 | 1175 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1176 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1177 | vector++) { | |
1178 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1179 | continue; | |
1180 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1181 | break; | |
1182 | } | |
1183 | } | |
1184 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1185 | } |
1186 | ||
1187 | void __setup_vector_irq(int cpu) | |
1188 | { | |
1189 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1190 | int irq, vector; |
1191 | struct irq_cfg *cfg; | |
1192 | ||
9d133e5d SS |
1193 | /* |
1194 | * vector_lock will make sure that we don't run into irq vector | |
1195 | * assignments that might be happening on another cpu in parallel, | |
1196 | * while we setup our initial vector to irq mappings. | |
1197 | */ | |
dade7716 | 1198 | raw_spin_lock(&vector_lock); |
497c9a19 | 1199 | /* Mark the inuse vectors */ |
ad9f4334 | 1200 | for_each_active_irq(irq) { |
2c778651 | 1201 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1202 | if (!cfg) |
1203 | continue; | |
36e9e1ea SS |
1204 | /* |
1205 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1206 | * will be part of the irq_cfg's domain. | |
1207 | */ | |
1208 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1209 | cpumask_set_cpu(cpu, cfg->domain); | |
1210 | ||
22f65d31 | 1211 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1212 | continue; |
1213 | vector = cfg->vector; | |
497c9a19 YL |
1214 | per_cpu(vector_irq, cpu)[vector] = irq; |
1215 | } | |
1216 | /* Mark the free vectors */ | |
1217 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1218 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1219 | if (irq < 0) | |
1220 | continue; | |
1221 | ||
1222 | cfg = irq_cfg(irq); | |
22f65d31 | 1223 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1224 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1225 | } |
dade7716 | 1226 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1227 | } |
3fde6900 | 1228 | |
f5b9ed7a | 1229 | static struct irq_chip ioapic_chip; |
54168ed7 | 1230 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1231 | |
047c8fdb | 1232 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1233 | static inline int IO_APIC_irq_trigger(int irq) |
1234 | { | |
d6c88a50 | 1235 | int apic, idx, pin; |
1d025192 | 1236 | |
d6c88a50 TG |
1237 | for (apic = 0; apic < nr_ioapics; apic++) { |
1238 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1239 | idx = find_irq_entry(apic, pin, mp_INT); | |
1240 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1241 | return irq_trigger(idx); | |
1242 | } | |
1243 | } | |
1244 | /* | |
54168ed7 IM |
1245 | * nonexistent IRQs are edge default |
1246 | */ | |
d6c88a50 | 1247 | return 0; |
1d025192 | 1248 | } |
047c8fdb YL |
1249 | #else |
1250 | static inline int IO_APIC_irq_trigger(int irq) | |
1251 | { | |
54168ed7 | 1252 | return 1; |
047c8fdb YL |
1253 | } |
1254 | #endif | |
1d025192 | 1255 | |
1a0e62a4 TG |
1256 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1257 | unsigned long trigger) | |
1da177e4 | 1258 | { |
c60eaf25 TG |
1259 | struct irq_chip *chip = &ioapic_chip; |
1260 | irq_flow_handler_t hdl; | |
1261 | bool fasteoi; | |
199751d7 | 1262 | |
6ebcc00e | 1263 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1264 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1265 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1266 | fasteoi = true; |
1267 | } else { | |
60c69948 | 1268 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1269 | fasteoi = false; |
1270 | } | |
047c8fdb | 1271 | |
1a0e62a4 | 1272 | if (irq_remapped(cfg)) { |
60c69948 | 1273 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
1274 | chip = &ir_ioapic_chip; |
1275 | fasteoi = trigger != 0; | |
54168ed7 | 1276 | } |
29b61be6 | 1277 | |
c60eaf25 TG |
1278 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1279 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1280 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1281 | } |
1282 | ||
1a8ce7ff TG |
1283 | static int setup_ioapic_entry(int apic_id, int irq, |
1284 | struct IO_APIC_route_entry *entry, | |
1285 | unsigned int destination, int trigger, | |
1286 | int polarity, int vector, int pin) | |
1da177e4 | 1287 | { |
497c9a19 YL |
1288 | /* |
1289 | * add it to the IO-APIC irq-routing table: | |
1290 | */ | |
1291 | memset(entry,0,sizeof(*entry)); | |
1292 | ||
54168ed7 | 1293 | if (intr_remapping_enabled) { |
c8d46cf0 | 1294 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1295 | struct irte irte; |
1296 | struct IR_IO_APIC_route_entry *ir_entry = | |
1297 | (struct IR_IO_APIC_route_entry *) entry; | |
1298 | int index; | |
1299 | ||
1300 | if (!iommu) | |
c8d46cf0 | 1301 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1302 | |
1303 | index = alloc_irte(iommu, irq, 1); | |
1304 | if (index < 0) | |
c8d46cf0 | 1305 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1306 | |
62a92f4c | 1307 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1308 | |
f007e99c WH |
1309 | /* Set source-id of interrupt request */ |
1310 | set_ioapic_sid(&irte, apic_id); | |
1311 | ||
54168ed7 IM |
1312 | modify_irte(irq, &irte); |
1313 | ||
1314 | ir_entry->index2 = (index >> 15) & 0x1; | |
1315 | ir_entry->zero = 0; | |
1316 | ir_entry->format = 1; | |
1317 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1318 | /* |
1319 | * IO-APIC RTE will be configured with virtual vector. | |
1320 | * irq handler will do the explicit EOI to the io-apic. | |
1321 | */ | |
1322 | ir_entry->vector = pin; | |
29b61be6 | 1323 | } else { |
9b5bc8dc IM |
1324 | entry->delivery_mode = apic->irq_delivery_mode; |
1325 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1326 | entry->dest = destination; |
0280f7c4 | 1327 | entry->vector = vector; |
54168ed7 | 1328 | } |
497c9a19 | 1329 | |
54168ed7 | 1330 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1331 | entry->trigger = trigger; |
1332 | entry->polarity = polarity; | |
497c9a19 YL |
1333 | |
1334 | /* Mask level triggered irqs. | |
1335 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1336 | */ | |
1337 | if (trigger) | |
1338 | entry->mask = 1; | |
497c9a19 YL |
1339 | return 0; |
1340 | } | |
1341 | ||
60c69948 TG |
1342 | static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, |
1343 | struct irq_cfg *cfg, int trigger, int polarity) | |
497c9a19 | 1344 | { |
1da177e4 | 1345 | struct IO_APIC_route_entry entry; |
22f65d31 | 1346 | unsigned int dest; |
497c9a19 YL |
1347 | |
1348 | if (!IO_APIC_IRQ(irq)) | |
1349 | return; | |
69c89efb SS |
1350 | /* |
1351 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1352 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1353 | * the cfg->domain. | |
1354 | */ | |
28c6a0ba | 1355 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1356 | apic->vector_allocation_domain(0, cfg->domain); |
1357 | ||
fe402e1f | 1358 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1359 | return; |
1360 | ||
debccb3e | 1361 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1362 | |
1363 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1364 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1365 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1366 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1367 | irq, trigger, polarity); |
1368 | ||
1369 | ||
c8d46cf0 | 1370 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1371 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1372 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1373 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1374 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1375 | return; |
1376 | } | |
1377 | ||
1a0e62a4 | 1378 | ioapic_register_intr(irq, cfg, trigger); |
b81bb373 | 1379 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1380 | legacy_pic->mask(irq); |
497c9a19 | 1381 | |
c8d46cf0 | 1382 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1383 | } |
1384 | ||
b9c61b70 YL |
1385 | static struct { |
1386 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1387 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1388 | ||
c8d6b8fe TG |
1389 | static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) |
1390 | { | |
1391 | if (idx != -1) | |
1392 | return false; | |
1393 | ||
1394 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
1395 | mp_ioapics[apic_id].apicid, pin); | |
1396 | return true; | |
1397 | } | |
1398 | ||
ed972ccf | 1399 | static void __init __io_apic_setup_irqs(unsigned int apic_id) |
497c9a19 | 1400 | { |
ed972ccf | 1401 | int idx, node = cpu_to_node(0); |
2d57e37d | 1402 | struct io_apic_irq_attr attr; |
ed972ccf | 1403 | unsigned int pin, irq; |
1da177e4 | 1404 | |
b9c61b70 YL |
1405 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1406 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
c8d6b8fe | 1407 | if (io_apic_pin_not_connected(idx, apic_id, pin)) |
b9c61b70 | 1408 | continue; |
33a201fa | 1409 | |
b9c61b70 | 1410 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1411 | |
fad53995 EB |
1412 | if ((apic_id > 0) && (irq > 16)) |
1413 | continue; | |
1414 | ||
b9c61b70 YL |
1415 | /* |
1416 | * Skip the timer IRQ if there's a quirk handler | |
1417 | * installed and if it returns 1: | |
1418 | */ | |
1419 | if (apic->multi_timer_check && | |
2d57e37d | 1420 | apic->multi_timer_check(apic_id, irq)) |
b9c61b70 | 1421 | continue; |
36062448 | 1422 | |
2d57e37d TG |
1423 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1424 | irq_polarity(idx)); | |
fbc6bff0 | 1425 | |
2d57e37d | 1426 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1427 | } |
1da177e4 LT |
1428 | } |
1429 | ||
ed972ccf TG |
1430 | static void __init setup_IO_APIC_irqs(void) |
1431 | { | |
1432 | unsigned int apic_id; | |
1433 | ||
1434 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1435 | ||
1436 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) | |
1437 | __io_apic_setup_irqs(apic_id); | |
1438 | } | |
1439 | ||
18dce6ba YL |
1440 | /* |
1441 | * for the gsit that is not in first ioapic | |
1442 | * but could not use acpi_register_gsi() | |
1443 | * like some special sci in IBM x3330 | |
1444 | */ | |
1445 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1446 | { | |
fbc6bff0 | 1447 | int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1448 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1449 | |
1450 | /* | |
1451 | * Convert 'gsi' to 'ioapic.pin'. | |
1452 | */ | |
1453 | apic_id = mp_find_ioapic(gsi); | |
1454 | if (apic_id < 0) | |
1455 | return; | |
1456 | ||
1457 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1458 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1459 | if (idx == -1) | |
1460 | return; | |
1461 | ||
1462 | irq = pin_2_irq(idx, apic_id, pin); | |
fe6dab4e YL |
1463 | |
1464 | /* Only handle the non legacy irqs on secondary ioapics */ | |
1465 | if (apic_id == 0 || irq < NR_IRQS_LEGACY) | |
18dce6ba | 1466 | return; |
fe6dab4e | 1467 | |
da1ad9d7 TG |
1468 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1469 | irq_polarity(idx)); | |
1470 | ||
710dcda6 | 1471 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1472 | } |
1473 | ||
1da177e4 | 1474 | /* |
f7633ce5 | 1475 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1476 | */ |
c8d46cf0 | 1477 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1478 | int vector) |
1da177e4 LT |
1479 | { |
1480 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1481 | |
54168ed7 IM |
1482 | if (intr_remapping_enabled) |
1483 | return; | |
54168ed7 | 1484 | |
36062448 | 1485 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1486 | |
1487 | /* | |
1488 | * We use logical delivery to get the timer IRQ | |
1489 | * to the first CPU. | |
1490 | */ | |
9b5bc8dc | 1491 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1492 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1493 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1494 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1495 | entry.polarity = 0; |
1496 | entry.trigger = 0; | |
1497 | entry.vector = vector; | |
1498 | ||
1499 | /* | |
1500 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1501 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1502 | */ |
2c778651 TG |
1503 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1504 | "edge"); | |
1da177e4 LT |
1505 | |
1506 | /* | |
1507 | * Add it to the IO-APIC irq-routing table: | |
1508 | */ | |
c8d46cf0 | 1509 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1510 | } |
1511 | ||
32f71aff MR |
1512 | |
1513 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1514 | { |
1515 | int apic, i; | |
1516 | union IO_APIC_reg_00 reg_00; | |
1517 | union IO_APIC_reg_01 reg_01; | |
1518 | union IO_APIC_reg_02 reg_02; | |
1519 | union IO_APIC_reg_03 reg_03; | |
1520 | unsigned long flags; | |
0f978f45 | 1521 | struct irq_cfg *cfg; |
8f09cd20 | 1522 | unsigned int irq; |
1da177e4 | 1523 | |
36062448 | 1524 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1525 | for (i = 0; i < nr_ioapics; i++) |
1526 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1527 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1528 | |
1529 | /* | |
1530 | * We are a bit conservative about what we expect. We have to | |
1531 | * know about every hardware change ASAP. | |
1532 | */ | |
1533 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1534 | ||
1535 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1536 | ||
dade7716 | 1537 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1538 | reg_00.raw = io_apic_read(apic, 0); |
1539 | reg_01.raw = io_apic_read(apic, 1); | |
1540 | if (reg_01.bits.version >= 0x10) | |
1541 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1542 | if (reg_01.bits.version >= 0x20) |
1543 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1544 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1545 | |
54168ed7 | 1546 | printk("\n"); |
b5ba7e6d | 1547 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1548 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1549 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1550 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1551 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1552 | |
54168ed7 | 1553 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1554 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1555 | |
1556 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1557 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1558 | |
1559 | /* | |
1560 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1561 | * but the value of reg_02 is read as the previous read register | |
1562 | * value, so ignore it if reg_02 == reg_01. | |
1563 | */ | |
1564 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1565 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1566 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1567 | } |
1568 | ||
1569 | /* | |
1570 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1571 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1572 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1573 | */ | |
1574 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1575 | reg_03.raw != reg_01.raw) { | |
1576 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1577 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1578 | } |
1579 | ||
1580 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1581 | ||
d83e94ac | 1582 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1583 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1584 | |
1585 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1586 | struct IO_APIC_route_entry entry; | |
1587 | ||
cf4c6a2f | 1588 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1589 | |
54168ed7 IM |
1590 | printk(KERN_DEBUG " %02x %03X ", |
1591 | i, | |
1592 | entry.dest | |
1593 | ); | |
1da177e4 LT |
1594 | |
1595 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1596 | entry.mask, | |
1597 | entry.trigger, | |
1598 | entry.irr, | |
1599 | entry.polarity, | |
1600 | entry.delivery_status, | |
1601 | entry.dest_mode, | |
1602 | entry.delivery_mode, | |
1603 | entry.vector | |
1604 | ); | |
1605 | } | |
1606 | } | |
1da177e4 | 1607 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1608 | for_each_active_irq(irq) { |
0b8f1efa YL |
1609 | struct irq_pin_list *entry; |
1610 | ||
2c778651 | 1611 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1612 | if (!cfg) |
1613 | continue; | |
0b8f1efa | 1614 | entry = cfg->irq_2_pin; |
0f978f45 | 1615 | if (!entry) |
1da177e4 | 1616 | continue; |
8f09cd20 | 1617 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1618 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1619 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1620 | printk("\n"); |
1621 | } | |
1622 | ||
1623 | printk(KERN_INFO ".................................... done.\n"); | |
1624 | ||
1625 | return; | |
1626 | } | |
1627 | ||
251e1e44 | 1628 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1629 | { |
251e1e44 | 1630 | int i; |
1da177e4 | 1631 | |
251e1e44 IM |
1632 | printk(KERN_DEBUG); |
1633 | ||
1634 | for (i = 0; i < 8; i++) | |
1635 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1636 | ||
1637 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1638 | } |
1639 | ||
32f71aff | 1640 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1641 | { |
97a52714 | 1642 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1643 | u64 icr; |
1da177e4 | 1644 | |
251e1e44 | 1645 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1646 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1647 | v = apic_read(APIC_ID); |
54168ed7 | 1648 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1649 | v = apic_read(APIC_LVR); |
1650 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1651 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1652 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1653 | |
1654 | v = apic_read(APIC_TASKPRI); | |
1655 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1656 | ||
54168ed7 | 1657 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1658 | if (!APIC_XAPIC(ver)) { |
1659 | v = apic_read(APIC_ARBPRI); | |
1660 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1661 | v & APIC_ARBPRI_MASK); | |
1662 | } | |
1da177e4 LT |
1663 | v = apic_read(APIC_PROCPRI); |
1664 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1665 | } | |
1666 | ||
a11b5abe YL |
1667 | /* |
1668 | * Remote read supported only in the 82489DX and local APIC for | |
1669 | * Pentium processors. | |
1670 | */ | |
1671 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1672 | v = apic_read(APIC_RRR); | |
1673 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1674 | } | |
1675 | ||
1da177e4 LT |
1676 | v = apic_read(APIC_LDR); |
1677 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1678 | if (!x2apic_enabled()) { |
1679 | v = apic_read(APIC_DFR); | |
1680 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1681 | } | |
1da177e4 LT |
1682 | v = apic_read(APIC_SPIV); |
1683 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1684 | ||
1685 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1686 | print_APIC_field(APIC_ISR); |
1da177e4 | 1687 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1688 | print_APIC_field(APIC_TMR); |
1da177e4 | 1689 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1690 | print_APIC_field(APIC_IRR); |
1da177e4 | 1691 | |
54168ed7 IM |
1692 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1693 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1694 | apic_write(APIC_ESR, 0); |
54168ed7 | 1695 | |
1da177e4 LT |
1696 | v = apic_read(APIC_ESR); |
1697 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1698 | } | |
1699 | ||
7ab6af7a | 1700 | icr = apic_icr_read(); |
0c425cec IM |
1701 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1702 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1703 | |
1704 | v = apic_read(APIC_LVTT); | |
1705 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1706 | ||
1707 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1708 | v = apic_read(APIC_LVTPC); | |
1709 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1710 | } | |
1711 | v = apic_read(APIC_LVT0); | |
1712 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1713 | v = apic_read(APIC_LVT1); | |
1714 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1715 | ||
1716 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1717 | v = apic_read(APIC_LVTERR); | |
1718 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1719 | } | |
1720 | ||
1721 | v = apic_read(APIC_TMICT); | |
1722 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1723 | v = apic_read(APIC_TMCCT); | |
1724 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1725 | v = apic_read(APIC_TDCR); | |
1726 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1727 | |
1728 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1729 | v = apic_read(APIC_EFEAT); | |
1730 | maxlvt = (v >> 16) & 0xff; | |
1731 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1732 | v = apic_read(APIC_ECTRL); | |
1733 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1734 | for (i = 0; i < maxlvt; i++) { | |
1735 | v = apic_read(APIC_EILVTn(i)); | |
1736 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1737 | } | |
1738 | } | |
1da177e4 LT |
1739 | printk("\n"); |
1740 | } | |
1741 | ||
2626eb2b | 1742 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1743 | { |
ffd5aae7 YL |
1744 | int cpu; |
1745 | ||
2626eb2b CG |
1746 | if (!maxcpu) |
1747 | return; | |
1748 | ||
ffd5aae7 | 1749 | preempt_disable(); |
2626eb2b CG |
1750 | for_each_online_cpu(cpu) { |
1751 | if (cpu >= maxcpu) | |
1752 | break; | |
ffd5aae7 | 1753 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1754 | } |
ffd5aae7 | 1755 | preempt_enable(); |
1da177e4 LT |
1756 | } |
1757 | ||
32f71aff | 1758 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1759 | { |
1da177e4 LT |
1760 | unsigned int v; |
1761 | unsigned long flags; | |
1762 | ||
b81bb373 | 1763 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1764 | return; |
1765 | ||
1766 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1767 | ||
5619c280 | 1768 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1769 | |
1770 | v = inb(0xa1) << 8 | inb(0x21); | |
1771 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1772 | ||
1773 | v = inb(0xa0) << 8 | inb(0x20); | |
1774 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1775 | ||
54168ed7 IM |
1776 | outb(0x0b,0xa0); |
1777 | outb(0x0b,0x20); | |
1da177e4 | 1778 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1779 | outb(0x0a,0xa0); |
1780 | outb(0x0a,0x20); | |
1da177e4 | 1781 | |
5619c280 | 1782 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1783 | |
1784 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1785 | ||
1786 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1787 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1788 | } | |
1789 | ||
2626eb2b CG |
1790 | static int __initdata show_lapic = 1; |
1791 | static __init int setup_show_lapic(char *arg) | |
1792 | { | |
1793 | int num = -1; | |
1794 | ||
1795 | if (strcmp(arg, "all") == 0) { | |
1796 | show_lapic = CONFIG_NR_CPUS; | |
1797 | } else { | |
1798 | get_option(&arg, &num); | |
1799 | if (num >= 0) | |
1800 | show_lapic = num; | |
1801 | } | |
1802 | ||
1803 | return 1; | |
1804 | } | |
1805 | __setup("show_lapic=", setup_show_lapic); | |
1806 | ||
1807 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1808 | { |
2626eb2b CG |
1809 | if (apic_verbosity == APIC_QUIET) |
1810 | return 0; | |
1811 | ||
32f71aff | 1812 | print_PIC(); |
4797f6b0 YL |
1813 | |
1814 | /* don't print out if apic is not there */ | |
8312136f | 1815 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1816 | return 0; |
1817 | ||
2626eb2b | 1818 | print_local_APICs(show_lapic); |
32f71aff MR |
1819 | print_IO_APIC(); |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
2626eb2b | 1824 | fs_initcall(print_ICs); |
32f71aff | 1825 | |
1da177e4 | 1826 | |
efa2559f YL |
1827 | /* Where if anywhere is the i8259 connect in external int mode */ |
1828 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1829 | ||
54168ed7 | 1830 | void __init enable_IO_APIC(void) |
1da177e4 | 1831 | { |
fcfd636a | 1832 | int i8259_apic, i8259_pin; |
54168ed7 | 1833 | int apic; |
bc07844a | 1834 | |
b81bb373 | 1835 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1836 | return; |
1837 | ||
54168ed7 | 1838 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1839 | int pin; |
1840 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1841 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1842 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1843 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1844 | |
fcfd636a EB |
1845 | /* If the interrupt line is enabled and in ExtInt mode |
1846 | * I have found the pin where the i8259 is connected. | |
1847 | */ | |
1848 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1849 | ioapic_i8259.apic = apic; | |
1850 | ioapic_i8259.pin = pin; | |
1851 | goto found_i8259; | |
1852 | } | |
1853 | } | |
1854 | } | |
1855 | found_i8259: | |
1856 | /* Look to see what if the MP table has reported the ExtINT */ | |
1857 | /* If we could not find the appropriate pin by looking at the ioapic | |
1858 | * the i8259 probably is not connected the ioapic but give the | |
1859 | * mptable a chance anyway. | |
1860 | */ | |
1861 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1862 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1863 | /* Trust the MP table if nothing is setup in the hardware */ | |
1864 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1865 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1866 | ioapic_i8259.pin = i8259_pin; | |
1867 | ioapic_i8259.apic = i8259_apic; | |
1868 | } | |
1869 | /* Complain if the MP table and the hardware disagree */ | |
1870 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1871 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1872 | { | |
1873 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1874 | } |
1875 | ||
1876 | /* | |
1877 | * Do not trust the IO-APIC being empty at bootup | |
1878 | */ | |
1879 | clear_IO_APIC(); | |
1880 | } | |
1881 | ||
1882 | /* | |
1883 | * Not an __init, needed by the reboot code | |
1884 | */ | |
1885 | void disable_IO_APIC(void) | |
1886 | { | |
1887 | /* | |
1888 | * Clear the IO-APIC before rebooting: | |
1889 | */ | |
1890 | clear_IO_APIC(); | |
1891 | ||
b81bb373 | 1892 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1893 | return; |
1894 | ||
650927ef | 1895 | /* |
0b968d23 | 1896 | * If the i8259 is routed through an IOAPIC |
650927ef | 1897 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1898 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1899 | * |
1900 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1901 | * as virtual wire B is little complex (need to configure both | |
0d2eb44f | 1902 | * IOAPIC RTE as well as interrupt-remapping table entry). |
7c6d9f97 | 1903 | * As this gets called during crash dump, keep this simple for now. |
650927ef | 1904 | */ |
7c6d9f97 | 1905 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1906 | struct IO_APIC_route_entry entry; |
650927ef EB |
1907 | |
1908 | memset(&entry, 0, sizeof(entry)); | |
1909 | entry.mask = 0; /* Enabled */ | |
1910 | entry.trigger = 0; /* Edge */ | |
1911 | entry.irr = 0; | |
1912 | entry.polarity = 0; /* High */ | |
1913 | entry.delivery_status = 0; | |
1914 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1915 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1916 | entry.vector = 0; |
54168ed7 | 1917 | entry.dest = read_apic_id(); |
650927ef EB |
1918 | |
1919 | /* | |
1920 | * Add it to the IO-APIC irq-routing table: | |
1921 | */ | |
cf4c6a2f | 1922 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1923 | } |
54168ed7 | 1924 | |
7c6d9f97 SS |
1925 | /* |
1926 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1927 | */ | |
8312136f | 1928 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1929 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1930 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1931 | } |
1932 | ||
54168ed7 | 1933 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1934 | /* |
1935 | * function to set the IO-APIC physical IDs based on the | |
1936 | * values stored in the MPC table. | |
1937 | * | |
1938 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1939 | */ | |
a38c5380 | 1940 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1941 | { |
1942 | union IO_APIC_reg_00 reg_00; | |
1943 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1944 | int apic_id; |
1da177e4 LT |
1945 | int i; |
1946 | unsigned char old_id; | |
1947 | unsigned long flags; | |
1948 | ||
1949 | /* | |
1950 | * This is broken; anything with a real cpu count has to | |
1951 | * circumvent this idiocy regardless. | |
1952 | */ | |
7abc0753 | 1953 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1954 | |
1955 | /* | |
1956 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1957 | */ | |
c8d46cf0 | 1958 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
1959 | |
1960 | /* Read the register 0 value */ | |
dade7716 | 1961 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1962 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1963 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1964 | |
c8d46cf0 | 1965 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 1966 | |
c8d46cf0 | 1967 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 1968 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 1969 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1970 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1971 | reg_00.bits.ID); | |
c8d46cf0 | 1972 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
1973 | } |
1974 | ||
1da177e4 LT |
1975 | /* |
1976 | * Sanity check, is the ID really free? Every APIC in a | |
1977 | * system must have a unique ID or we get lots of nice | |
1978 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1979 | */ | |
7abc0753 | 1980 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 1981 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 1982 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 1983 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1984 | for (i = 0; i < get_physical_broadcast(); i++) |
1985 | if (!physid_isset(i, phys_id_present_map)) | |
1986 | break; | |
1987 | if (i >= get_physical_broadcast()) | |
1988 | panic("Max APIC ID exceeded!\n"); | |
1989 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1990 | i); | |
1991 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 1992 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
1993 | } else { |
1994 | physid_mask_t tmp; | |
7abc0753 | 1995 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
1996 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1997 | "phys_id_present_map\n", | |
c8d46cf0 | 1998 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1999 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2000 | } | |
2001 | ||
1da177e4 LT |
2002 | /* |
2003 | * We need to adjust the IRQ routing table | |
2004 | * if the ID changed. | |
2005 | */ | |
c8d46cf0 | 2006 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2007 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2008 | if (mp_irqs[i].dstapic == old_id) |
2009 | mp_irqs[i].dstapic | |
c8d46cf0 | 2010 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2011 | |
2012 | /* | |
60d79fd9 YL |
2013 | * Update the ID register according to the right value |
2014 | * from the MPC table if they are different. | |
36062448 | 2015 | */ |
60d79fd9 YL |
2016 | if (mp_ioapics[apic_id].apicid == reg_00.bits.ID) |
2017 | continue; | |
2018 | ||
1da177e4 LT |
2019 | apic_printk(APIC_VERBOSE, KERN_INFO |
2020 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2021 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2022 | |
c8d46cf0 | 2023 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2024 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2025 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2026 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2027 | |
2028 | /* | |
2029 | * Sanity check | |
2030 | */ | |
dade7716 | 2031 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2032 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2033 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2034 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2035 | printk("could not set ID!\n"); |
2036 | else | |
2037 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2038 | } | |
2039 | } | |
a38c5380 SAS |
2040 | |
2041 | void __init setup_ioapic_ids_from_mpc(void) | |
2042 | { | |
2043 | ||
2044 | if (acpi_ioapic) | |
2045 | return; | |
2046 | /* | |
2047 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2048 | * no meaning without the serial APIC bus. | |
2049 | */ | |
2050 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2051 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2052 | return; | |
2053 | setup_ioapic_ids_from_mpc_nocheck(); | |
2054 | } | |
54168ed7 | 2055 | #endif |
1da177e4 | 2056 | |
7ce0bcfd | 2057 | int no_timer_check __initdata; |
8542b200 ZA |
2058 | |
2059 | static int __init notimercheck(char *s) | |
2060 | { | |
2061 | no_timer_check = 1; | |
2062 | return 1; | |
2063 | } | |
2064 | __setup("no_timer_check", notimercheck); | |
2065 | ||
1da177e4 LT |
2066 | /* |
2067 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2068 | * about the timer IRQ. We do the following to work around the situation: | |
2069 | * | |
2070 | * - timer IRQ defaults to IO-APIC IRQ | |
2071 | * - if this function detects that timer IRQs are defunct, then we fall | |
2072 | * back to ISA timer IRQs | |
2073 | */ | |
f0a7a5c9 | 2074 | static int __init timer_irq_works(void) |
1da177e4 LT |
2075 | { |
2076 | unsigned long t1 = jiffies; | |
4aae0702 | 2077 | unsigned long flags; |
1da177e4 | 2078 | |
8542b200 ZA |
2079 | if (no_timer_check) |
2080 | return 1; | |
2081 | ||
4aae0702 | 2082 | local_save_flags(flags); |
1da177e4 LT |
2083 | local_irq_enable(); |
2084 | /* Let ten ticks pass... */ | |
2085 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2086 | local_irq_restore(flags); |
1da177e4 LT |
2087 | |
2088 | /* | |
2089 | * Expect a few ticks at least, to be sure some possible | |
2090 | * glue logic does not lock up after one or two first | |
2091 | * ticks in a non-ExtINT mode. Also the local APIC | |
2092 | * might have cached one ExtINT interrupt. Finally, at | |
2093 | * least one tick may be lost due to delays. | |
2094 | */ | |
54168ed7 IM |
2095 | |
2096 | /* jiffies wrap? */ | |
1d16b53e | 2097 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2098 | return 1; |
1da177e4 LT |
2099 | return 0; |
2100 | } | |
2101 | ||
2102 | /* | |
2103 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2104 | * number of pending IRQ events unhandled. These cases are very rare, | |
2105 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2106 | * better to do it this way as thus we do not have to be aware of | |
2107 | * 'pending' interrupts in the IRQ path, except at this point. | |
2108 | */ | |
2109 | /* | |
2110 | * Edge triggered needs to resend any interrupt | |
2111 | * that was delayed but this is now handled in the device | |
2112 | * independent code. | |
2113 | */ | |
2114 | ||
2115 | /* | |
2116 | * Starting up a edge-triggered IO-APIC interrupt is | |
2117 | * nasty - we need to make sure that we get the edge. | |
2118 | * If it is already asserted for some reason, we need | |
2119 | * return 1 to indicate that is was pending. | |
2120 | * | |
2121 | * This is not complete - we should be able to fake | |
2122 | * an edge even if it isn't on the 8259A... | |
2123 | */ | |
54168ed7 | 2124 | |
61a38ce3 | 2125 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2126 | { |
61a38ce3 | 2127 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2128 | unsigned long flags; |
2129 | ||
dade7716 | 2130 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2131 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2132 | legacy_pic->mask(irq); |
b81bb373 | 2133 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2134 | was_pending = 1; |
2135 | } | |
61a38ce3 | 2136 | __unmask_ioapic(data->chip_data); |
dade7716 | 2137 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2138 | |
2139 | return was_pending; | |
2140 | } | |
2141 | ||
90297c5f | 2142 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2143 | { |
90297c5f | 2144 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2145 | unsigned long flags; |
2146 | ||
dade7716 | 2147 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2148 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2149 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2150 | |
2151 | return 1; | |
2152 | } | |
497c9a19 | 2153 | |
54168ed7 IM |
2154 | /* |
2155 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2156 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2157 | * handled with the level-triggered descriptor, but that one has slightly | |
2158 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2159 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2160 | * races. | |
2161 | */ | |
497c9a19 | 2162 | |
54168ed7 | 2163 | #ifdef CONFIG_SMP |
9338ad6f | 2164 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2165 | { |
2166 | cpumask_var_t cleanup_mask; | |
2167 | ||
2168 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2169 | unsigned int i; | |
e85abf8f GH |
2170 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2171 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2172 | } else { | |
2173 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2174 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2175 | free_cpumask_var(cleanup_mask); | |
2176 | } | |
2177 | cfg->move_in_progress = 0; | |
2178 | } | |
2179 | ||
4420471f | 2180 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2181 | { |
2182 | int apic, pin; | |
2183 | struct irq_pin_list *entry; | |
2184 | u8 vector = cfg->vector; | |
2185 | ||
2977fb3f | 2186 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2187 | unsigned int reg; |
2188 | ||
e85abf8f GH |
2189 | apic = entry->apic; |
2190 | pin = entry->pin; | |
2191 | /* | |
2192 | * With interrupt-remapping, destination information comes | |
2193 | * from interrupt-remapping table entry. | |
2194 | */ | |
1a0730d6 | 2195 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2196 | io_apic_write(apic, 0x11 + pin*2, dest); |
2197 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2198 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2199 | reg |= vector; | |
2200 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2201 | } |
2202 | } | |
2203 | ||
2204 | /* | |
f7e909ea | 2205 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2206 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2207 | * leaves data->affinity untouched. |
e85abf8f | 2208 | */ |
f7e909ea TG |
2209 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2210 | unsigned int *dest_id) | |
e85abf8f | 2211 | { |
f7e909ea | 2212 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2213 | |
2214 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2215 | return -1; |
e85abf8f | 2216 | |
f7e909ea | 2217 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2218 | return -1; |
e85abf8f | 2219 | |
f7e909ea | 2220 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2221 | |
f7e909ea | 2222 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2223 | return 0; |
e85abf8f GH |
2224 | } |
2225 | ||
4420471f | 2226 | static int |
f7e909ea TG |
2227 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2228 | bool force) | |
e85abf8f | 2229 | { |
f7e909ea | 2230 | unsigned int dest, irq = data->irq; |
e85abf8f | 2231 | unsigned long flags; |
f7e909ea | 2232 | int ret; |
e85abf8f | 2233 | |
dade7716 | 2234 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2235 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2236 | if (!ret) { |
e85abf8f GH |
2237 | /* Only the high 8 bits are valid. */ |
2238 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2239 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2240 | } |
dade7716 | 2241 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2242 | return ret; |
e85abf8f GH |
2243 | } |
2244 | ||
54168ed7 | 2245 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2246 | |
54168ed7 IM |
2247 | /* |
2248 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2249 | * | |
0280f7c4 SS |
2250 | * For both level and edge triggered, irq migration is a simple atomic |
2251 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2252 | * |
0280f7c4 SS |
2253 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2254 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2255 | * Real vector that is used for interrupting cpu will be coming from | |
2256 | * the interrupt-remapping table entry. | |
54168ed7 | 2257 | */ |
d5dedd45 | 2258 | static int |
f19f5ecc TG |
2259 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2260 | bool force) | |
497c9a19 | 2261 | { |
f19f5ecc TG |
2262 | struct irq_cfg *cfg = data->chip_data; |
2263 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2264 | struct irte irte; |
497c9a19 | 2265 | |
22f65d31 | 2266 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2267 | return -EINVAL; |
497c9a19 | 2268 | |
54168ed7 | 2269 | if (get_irte(irq, &irte)) |
f19f5ecc | 2270 | return -EBUSY; |
497c9a19 | 2271 | |
3145e941 | 2272 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2273 | return -EBUSY; |
54168ed7 | 2274 | |
debccb3e | 2275 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2276 | |
54168ed7 IM |
2277 | irte.vector = cfg->vector; |
2278 | irte.dest_id = IRTE_DEST(dest); | |
2279 | ||
2280 | /* | |
2281 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2282 | */ | |
2283 | modify_irte(irq, &irte); | |
2284 | ||
22f65d31 MT |
2285 | if (cfg->move_in_progress) |
2286 | send_cleanup_vector(cfg); | |
54168ed7 | 2287 | |
f19f5ecc | 2288 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2289 | return 0; |
54168ed7 IM |
2290 | } |
2291 | ||
29b61be6 | 2292 | #else |
f19f5ecc TG |
2293 | static inline int |
2294 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2295 | bool force) | |
29b61be6 | 2296 | { |
d5dedd45 | 2297 | return 0; |
29b61be6 | 2298 | } |
54168ed7 IM |
2299 | #endif |
2300 | ||
2301 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2302 | { | |
2303 | unsigned vector, me; | |
8f2466f4 | 2304 | |
54168ed7 | 2305 | ack_APIC_irq(); |
54168ed7 | 2306 | exit_idle(); |
54168ed7 IM |
2307 | irq_enter(); |
2308 | ||
2309 | me = smp_processor_id(); | |
2310 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2311 | unsigned int irq; | |
68a8ca59 | 2312 | unsigned int irr; |
54168ed7 IM |
2313 | struct irq_desc *desc; |
2314 | struct irq_cfg *cfg; | |
0a3aee0d | 2315 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2316 | |
0b8f1efa YL |
2317 | if (irq == -1) |
2318 | continue; | |
2319 | ||
54168ed7 IM |
2320 | desc = irq_to_desc(irq); |
2321 | if (!desc) | |
2322 | continue; | |
2323 | ||
2324 | cfg = irq_cfg(irq); | |
239007b8 | 2325 | raw_spin_lock(&desc->lock); |
54168ed7 | 2326 | |
7f41c2e1 SS |
2327 | /* |
2328 | * Check if the irq migration is in progress. If so, we | |
2329 | * haven't received the cleanup request yet for this irq. | |
2330 | */ | |
2331 | if (cfg->move_in_progress) | |
2332 | goto unlock; | |
2333 | ||
22f65d31 | 2334 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2335 | goto unlock; |
2336 | ||
68a8ca59 SS |
2337 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2338 | /* | |
2339 | * Check if the vector that needs to be cleanedup is | |
2340 | * registered at the cpu's IRR. If so, then this is not | |
2341 | * the best time to clean it up. Lets clean it up in the | |
2342 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2343 | * to myself. | |
2344 | */ | |
2345 | if (irr & (1 << (vector % 32))) { | |
2346 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2347 | goto unlock; | |
2348 | } | |
0a3aee0d | 2349 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2350 | unlock: |
239007b8 | 2351 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2352 | } |
2353 | ||
2354 | irq_exit(); | |
2355 | } | |
2356 | ||
dd5f15e5 | 2357 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2358 | { |
a5e74b84 | 2359 | unsigned me; |
54168ed7 | 2360 | |
fcef5911 | 2361 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2362 | return; |
2363 | ||
54168ed7 | 2364 | me = smp_processor_id(); |
10b888d6 | 2365 | |
fcef5911 | 2366 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2367 | send_cleanup_vector(cfg); |
497c9a19 | 2368 | } |
a5e74b84 | 2369 | |
dd5f15e5 | 2370 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2371 | { |
dd5f15e5 | 2372 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2373 | } |
2374 | ||
2375 | void irq_force_complete_move(int irq) | |
2376 | { | |
2c778651 | 2377 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2378 | |
bbd391a1 PB |
2379 | if (!cfg) |
2380 | return; | |
2381 | ||
dd5f15e5 | 2382 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2383 | } |
497c9a19 | 2384 | #else |
dd5f15e5 | 2385 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2386 | #endif |
3145e941 | 2387 | |
90297c5f | 2388 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2389 | { |
90297c5f | 2390 | irq_complete_move(data->chip_data); |
08221110 | 2391 | irq_move_irq(data); |
1d025192 YL |
2392 | ack_APIC_irq(); |
2393 | } | |
2394 | ||
3eb2cce8 | 2395 | atomic_t irq_mis_count; |
3eb2cce8 | 2396 | |
c29d9db3 SS |
2397 | /* |
2398 | * IO-APIC versions below 0x20 don't support EOI register. | |
2399 | * For the record, here is the information about various versions: | |
2400 | * 0Xh 82489DX | |
2401 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2402 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2403 | * 30h-FFh Reserved | |
2404 | * | |
2405 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2406 | * version as 0x2. This is an error with documentation and these ICH chips | |
2407 | * use io-apic's of version 0x20. | |
2408 | * | |
2409 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2410 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2411 | * mode to edge and then back to level, with RTE being masked during this. | |
2412 | */ | |
dd5f15e5 | 2413 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2414 | { |
2415 | struct irq_pin_list *entry; | |
dd5f15e5 | 2416 | unsigned long flags; |
b3ec0a37 | 2417 | |
dd5f15e5 | 2418 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2419 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2420 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2421 | /* | |
2422 | * Intr-remapping uses pin number as the virtual vector | |
2423 | * in the RTE. Actual vector is programmed in | |
2424 | * intr-remapping table entry. Hence for the io-apic | |
2425 | * EOI we use the pin number. | |
2426 | */ | |
1a0730d6 | 2427 | if (irq_remapped(cfg)) |
c29d9db3 SS |
2428 | io_apic_eoi(entry->apic, entry->pin); |
2429 | else | |
2430 | io_apic_eoi(entry->apic, cfg->vector); | |
2431 | } else { | |
2432 | __mask_and_edge_IO_APIC_irq(entry); | |
2433 | __unmask_and_level_IO_APIC_irq(entry); | |
2434 | } | |
b3ec0a37 | 2435 | } |
dade7716 | 2436 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2437 | } |
2438 | ||
90297c5f | 2439 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2440 | { |
90297c5f TG |
2441 | struct irq_cfg *cfg = data->chip_data; |
2442 | int i, do_unmask_irq = 0, irq = data->irq; | |
3eb2cce8 | 2443 | unsigned long v; |
047c8fdb | 2444 | |
dd5f15e5 | 2445 | irq_complete_move(cfg); |
047c8fdb | 2446 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2447 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2448 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
54168ed7 | 2449 | do_unmask_irq = 1; |
dd5f15e5 | 2450 | mask_ioapic(cfg); |
54168ed7 | 2451 | } |
047c8fdb YL |
2452 | #endif |
2453 | ||
3eb2cce8 | 2454 | /* |
916a0fe7 JF |
2455 | * It appears there is an erratum which affects at least version 0x11 |
2456 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2457 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2458 | * erroneously delivered as edge-triggered one but the respective IRR | |
2459 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2460 | * message but it will never arrive and further interrupts are blocked | |
2461 | * from the source. The exact reason is so far unknown, but the | |
2462 | * phenomenon was observed when two consecutive interrupt requests | |
2463 | * from a given source get delivered to the same CPU and the source is | |
2464 | * temporarily disabled in between. | |
2465 | * | |
2466 | * A workaround is to simulate an EOI message manually. We achieve it | |
2467 | * by setting the trigger mode to edge and then to level when the edge | |
2468 | * trigger mode gets detected in the TMR of a local APIC for a | |
2469 | * level-triggered interrupt. We mask the source for the time of the | |
2470 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2471 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2472 | * |
2473 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2474 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2475 | * destination that is handling the corresponding interrupt. This | |
2476 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2477 | * level-triggered io-apic interrupt will be seen as an edge | |
2478 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2479 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2480 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2481 | * supporting EOI register, we do an explicit EOI to clear the | |
2482 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2483 | * we use the above logic (mask+edge followed by unmask+level) from | |
2484 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2485 | */ |
3145e941 | 2486 | i = cfg->vector; |
3eb2cce8 | 2487 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2488 | |
54168ed7 IM |
2489 | /* |
2490 | * We must acknowledge the irq before we move it or the acknowledge will | |
2491 | * not propagate properly. | |
2492 | */ | |
2493 | ack_APIC_irq(); | |
2494 | ||
1c83995b SS |
2495 | /* |
2496 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2497 | * message via io-apic EOI register write or simulating it using | |
2498 | * mask+edge followed by unnask+level logic) manually when the | |
2499 | * level triggered interrupt is seen as the edge triggered interrupt | |
2500 | * at the cpu. | |
2501 | */ | |
ca64c47c MR |
2502 | if (!(v & (1 << (i & 0x1f)))) { |
2503 | atomic_inc(&irq_mis_count); | |
2504 | ||
dd5f15e5 | 2505 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2506 | } |
2507 | ||
54168ed7 IM |
2508 | /* Now we can move and renable the irq */ |
2509 | if (unlikely(do_unmask_irq)) { | |
2510 | /* Only migrate the irq if the ack has been received. | |
2511 | * | |
2512 | * On rare occasions the broadcast level triggered ack gets | |
2513 | * delayed going to ioapics, and if we reprogram the | |
2514 | * vector while Remote IRR is still set the irq will never | |
2515 | * fire again. | |
2516 | * | |
2517 | * To prevent this scenario we read the Remote IRR bit | |
2518 | * of the ioapic. This has two effects. | |
2519 | * - On any sane system the read of the ioapic will | |
2520 | * flush writes (and acks) going to the ioapic from | |
2521 | * this cpu. | |
2522 | * - We get to see if the ACK has actually been delivered. | |
2523 | * | |
2524 | * Based on failed experiments of reprogramming the | |
2525 | * ioapic entry from outside of irq context starting | |
2526 | * with masking the ioapic entry and then polling until | |
2527 | * Remote IRR was clear before reprogramming the | |
2528 | * ioapic I don't trust the Remote IRR bit to be | |
2529 | * completey accurate. | |
2530 | * | |
2531 | * However there appears to be no other way to plug | |
2532 | * this race, so if the Remote IRR bit is not | |
2533 | * accurate and is causing problems then it is a hardware bug | |
2534 | * and you can go talk to the chipset vendor about it. | |
2535 | */ | |
3145e941 | 2536 | if (!io_apic_level_ack_pending(cfg)) |
08221110 | 2537 | irq_move_masked_irq(data); |
dd5f15e5 | 2538 | unmask_ioapic(cfg); |
54168ed7 | 2539 | } |
3eb2cce8 | 2540 | } |
1d025192 | 2541 | |
d0b03bd1 | 2542 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2543 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2544 | { |
5d0ae2db | 2545 | ack_APIC_irq(); |
d0b03bd1 HW |
2546 | } |
2547 | ||
90297c5f | 2548 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2549 | { |
5d0ae2db | 2550 | ack_APIC_irq(); |
90297c5f | 2551 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2552 | } |
2553 | #endif /* CONFIG_INTR_REMAP */ | |
2554 | ||
f5b9ed7a | 2555 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2556 | .name = "IO-APIC", |
2557 | .irq_startup = startup_ioapic_irq, | |
2558 | .irq_mask = mask_ioapic_irq, | |
2559 | .irq_unmask = unmask_ioapic_irq, | |
2560 | .irq_ack = ack_apic_edge, | |
2561 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2562 | #ifdef CONFIG_SMP |
f7e909ea | 2563 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2564 | #endif |
f7e909ea | 2565 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2566 | }; |
2567 | ||
54168ed7 | 2568 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
f19f5ecc TG |
2569 | .name = "IR-IO-APIC", |
2570 | .irq_startup = startup_ioapic_irq, | |
2571 | .irq_mask = mask_ioapic_irq, | |
2572 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2573 | #ifdef CONFIG_INTR_REMAP |
f19f5ecc TG |
2574 | .irq_ack = ir_ack_apic_edge, |
2575 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2576 | #ifdef CONFIG_SMP |
f19f5ecc | 2577 | .irq_set_affinity = ir_ioapic_set_affinity, |
a1e38ca5 | 2578 | #endif |
54168ed7 | 2579 | #endif |
f19f5ecc | 2580 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2581 | }; |
1da177e4 LT |
2582 | |
2583 | static inline void init_IO_APIC_traps(void) | |
2584 | { | |
da51a821 | 2585 | struct irq_cfg *cfg; |
ad9f4334 | 2586 | unsigned int irq; |
1da177e4 LT |
2587 | |
2588 | /* | |
2589 | * NOTE! The local APIC isn't very good at handling | |
2590 | * multiple interrupts at the same interrupt level. | |
2591 | * As the interrupt level is determined by taking the | |
2592 | * vector number and shifting that right by 4, we | |
2593 | * want to spread these out a bit so that they don't | |
2594 | * all fall in the same interrupt level. | |
2595 | * | |
2596 | * Also, we've got to be careful not to trash gate | |
2597 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2598 | */ | |
ad9f4334 | 2599 | for_each_active_irq(irq) { |
2c778651 | 2600 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2601 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2602 | /* |
2603 | * Hmm.. We don't have an entry for this, | |
2604 | * so default to an old-fashioned 8259 | |
2605 | * interrupt if we can.. | |
2606 | */ | |
b81bb373 JP |
2607 | if (irq < legacy_pic->nr_legacy_irqs) |
2608 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2609 | else |
1da177e4 | 2610 | /* Strange. Oh, well.. */ |
2c778651 | 2611 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2612 | } |
2613 | } | |
2614 | } | |
2615 | ||
f5b9ed7a IM |
2616 | /* |
2617 | * The local APIC irq-chip implementation: | |
2618 | */ | |
1da177e4 | 2619 | |
90297c5f | 2620 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2621 | { |
2622 | unsigned long v; | |
2623 | ||
2624 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2625 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2626 | } |
2627 | ||
90297c5f | 2628 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2629 | { |
f5b9ed7a | 2630 | unsigned long v; |
1da177e4 | 2631 | |
f5b9ed7a | 2632 | v = apic_read(APIC_LVT0); |
593f4a78 | 2633 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2634 | } |
1da177e4 | 2635 | |
90297c5f | 2636 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2637 | { |
2638 | ack_APIC_irq(); | |
2639 | } | |
2640 | ||
f5b9ed7a | 2641 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2642 | .name = "local-APIC", |
90297c5f TG |
2643 | .irq_mask = mask_lapic_irq, |
2644 | .irq_unmask = unmask_lapic_irq, | |
2645 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2646 | }; |
2647 | ||
60c69948 | 2648 | static void lapic_register_intr(int irq) |
c88ac1df | 2649 | { |
60c69948 | 2650 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2651 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2652 | "edge"); |
c88ac1df MR |
2653 | } |
2654 | ||
1da177e4 LT |
2655 | /* |
2656 | * This looks a bit hackish but it's about the only one way of sending | |
2657 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2658 | * not support the ExtINT mode, unfortunately. We need to send these | |
2659 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2660 | * 8259A interrupt line asserted until INTA. --macro | |
2661 | */ | |
28acf285 | 2662 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2663 | { |
fcfd636a | 2664 | int apic, pin, i; |
1da177e4 LT |
2665 | struct IO_APIC_route_entry entry0, entry1; |
2666 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2667 | |
fcfd636a | 2668 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2669 | if (pin == -1) { |
2670 | WARN_ON_ONCE(1); | |
2671 | return; | |
2672 | } | |
fcfd636a | 2673 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2674 | if (apic == -1) { |
2675 | WARN_ON_ONCE(1); | |
1da177e4 | 2676 | return; |
956fb531 | 2677 | } |
1da177e4 | 2678 | |
cf4c6a2f | 2679 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2680 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2681 | |
2682 | memset(&entry1, 0, sizeof(entry1)); | |
2683 | ||
2684 | entry1.dest_mode = 0; /* physical delivery */ | |
2685 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2686 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2687 | entry1.delivery_mode = dest_ExtINT; |
2688 | entry1.polarity = entry0.polarity; | |
2689 | entry1.trigger = 0; | |
2690 | entry1.vector = 0; | |
2691 | ||
cf4c6a2f | 2692 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2693 | |
2694 | save_control = CMOS_READ(RTC_CONTROL); | |
2695 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2696 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2697 | RTC_FREQ_SELECT); | |
2698 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2699 | ||
2700 | i = 100; | |
2701 | while (i-- > 0) { | |
2702 | mdelay(10); | |
2703 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2704 | i -= 10; | |
2705 | } | |
2706 | ||
2707 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2708 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2709 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2710 | |
cf4c6a2f | 2711 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2712 | } |
2713 | ||
efa2559f | 2714 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2715 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2716 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2717 | { |
2718 | disable_timer_pin_1 = 1; | |
2719 | return 0; | |
2720 | } | |
54168ed7 | 2721 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2722 | |
2723 | int timer_through_8259 __initdata; | |
2724 | ||
1da177e4 LT |
2725 | /* |
2726 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2727 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2728 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2729 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2730 | * |
2731 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2732 | */ |
8542b200 | 2733 | static inline void __init check_timer(void) |
1da177e4 | 2734 | { |
2c778651 | 2735 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2736 | int node = cpu_to_node(0); |
fcfd636a | 2737 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2738 | unsigned long flags; |
047c8fdb | 2739 | int no_pin1 = 0; |
4aae0702 IM |
2740 | |
2741 | local_irq_save(flags); | |
d4d25dec | 2742 | |
1da177e4 LT |
2743 | /* |
2744 | * get/set the timer IRQ vector: | |
2745 | */ | |
4305df94 | 2746 | legacy_pic->mask(0); |
fe402e1f | 2747 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2748 | |
2749 | /* | |
d11d5794 MR |
2750 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2751 | * wire has to be disabled in the local APIC. Also | |
2752 | * timer interrupts need to be acknowledged manually in | |
2753 | * the 8259A for the i82489DX when using the NMI | |
2754 | * watchdog as that APIC treats NMIs as level-triggered. | |
2755 | * The AEOI mode will finish them in the 8259A | |
2756 | * automatically. | |
1da177e4 | 2757 | */ |
593f4a78 | 2758 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2759 | legacy_pic->init(1); |
1da177e4 | 2760 | |
fcfd636a EB |
2761 | pin1 = find_isa_irq_pin(0, mp_INT); |
2762 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2763 | pin2 = ioapic_i8259.pin; | |
2764 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2765 | |
49a66a0b MR |
2766 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2767 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2768 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2769 | |
691874fa MR |
2770 | /* |
2771 | * Some BIOS writers are clueless and report the ExtINTA | |
2772 | * I/O APIC input from the cascaded 8259A as the timer | |
2773 | * interrupt input. So just in case, if only one pin | |
2774 | * was found above, try it both directly and through the | |
2775 | * 8259A. | |
2776 | */ | |
2777 | if (pin1 == -1) { | |
54168ed7 IM |
2778 | if (intr_remapping_enabled) |
2779 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2780 | pin1 = pin2; |
2781 | apic1 = apic2; | |
2782 | no_pin1 = 1; | |
2783 | } else if (pin2 == -1) { | |
2784 | pin2 = pin1; | |
2785 | apic2 = apic1; | |
2786 | } | |
2787 | ||
1da177e4 LT |
2788 | if (pin1 != -1) { |
2789 | /* | |
2790 | * Ok, does IRQ0 through the IOAPIC work? | |
2791 | */ | |
691874fa | 2792 | if (no_pin1) { |
85ac16d0 | 2793 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2794 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2795 | } else { |
60c69948 | 2796 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2797 | * leave it unmasked. |
2798 | * so only need to unmask if it is level-trigger | |
2799 | * do we really have level trigger timer? | |
2800 | */ | |
2801 | int idx; | |
2802 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2803 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2804 | unmask_ioapic(cfg); |
691874fa | 2805 | } |
1da177e4 | 2806 | if (timer_irq_works()) { |
66759a01 CE |
2807 | if (disable_timer_pin_1 > 0) |
2808 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2809 | goto out; |
1da177e4 | 2810 | } |
54168ed7 IM |
2811 | if (intr_remapping_enabled) |
2812 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2813 | local_irq_disable(); |
fcfd636a | 2814 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2815 | if (!no_pin1) |
49a66a0b MR |
2816 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2817 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2818 | |
49a66a0b MR |
2819 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2820 | "(IRQ0) through the 8259A ...\n"); | |
2821 | apic_printk(APIC_QUIET, KERN_INFO | |
2822 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2823 | /* |
2824 | * legacy devices should be connected to IO APIC #0 | |
2825 | */ | |
85ac16d0 | 2826 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2827 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2828 | legacy_pic->unmask(0); |
1da177e4 | 2829 | if (timer_irq_works()) { |
49a66a0b | 2830 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2831 | timer_through_8259 = 1; |
4aae0702 | 2832 | goto out; |
1da177e4 LT |
2833 | } |
2834 | /* | |
2835 | * Cleanup, just in case ... | |
2836 | */ | |
f72dccac | 2837 | local_irq_disable(); |
4305df94 | 2838 | legacy_pic->mask(0); |
fcfd636a | 2839 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2840 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2841 | } |
1da177e4 | 2842 | |
49a66a0b MR |
2843 | apic_printk(APIC_QUIET, KERN_INFO |
2844 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2845 | |
60c69948 | 2846 | lapic_register_intr(0); |
497c9a19 | 2847 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2848 | legacy_pic->unmask(0); |
1da177e4 LT |
2849 | |
2850 | if (timer_irq_works()) { | |
49a66a0b | 2851 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2852 | goto out; |
1da177e4 | 2853 | } |
f72dccac | 2854 | local_irq_disable(); |
4305df94 | 2855 | legacy_pic->mask(0); |
497c9a19 | 2856 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2857 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2858 | |
49a66a0b MR |
2859 | apic_printk(APIC_QUIET, KERN_INFO |
2860 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2861 | |
b81bb373 JP |
2862 | legacy_pic->init(0); |
2863 | legacy_pic->make_irq(0); | |
593f4a78 | 2864 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2865 | |
2866 | unlock_ExtINT_logic(); | |
2867 | ||
2868 | if (timer_irq_works()) { | |
49a66a0b | 2869 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2870 | goto out; |
1da177e4 | 2871 | } |
f72dccac | 2872 | local_irq_disable(); |
49a66a0b | 2873 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2874 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2875 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2876 | out: |
2877 | local_irq_restore(flags); | |
1da177e4 LT |
2878 | } |
2879 | ||
2880 | /* | |
af174783 MR |
2881 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2882 | * to devices. However there may be an I/O APIC pin available for | |
2883 | * this interrupt regardless. The pin may be left unconnected, but | |
2884 | * typically it will be reused as an ExtINT cascade interrupt for | |
2885 | * the master 8259A. In the MPS case such a pin will normally be | |
2886 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2887 | * there is no provision for ExtINT interrupts, and in the absence | |
2888 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2889 | * interrupt, that is edge-triggered and unmasked by default. We | |
2890 | * used to do this, but it caused problems on some systems because | |
2891 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2892 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2893 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2894 | * the I/O APIC in all cases now. No actual device should request | |
2895 | * it anyway. --macro | |
1da177e4 | 2896 | */ |
bc07844a | 2897 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2898 | |
2899 | void __init setup_IO_APIC(void) | |
2900 | { | |
54168ed7 | 2901 | |
54168ed7 IM |
2902 | /* |
2903 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2904 | */ | |
b81bb373 | 2905 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2906 | |
54168ed7 | 2907 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2908 | /* |
54168ed7 IM |
2909 | * Set up IO-APIC IRQ routing. |
2910 | */ | |
de934103 TG |
2911 | x86_init.mpparse.setup_ioapic_ids(); |
2912 | ||
1da177e4 LT |
2913 | sync_Arb_IDs(); |
2914 | setup_IO_APIC_irqs(); | |
2915 | init_IO_APIC_traps(); | |
b81bb373 | 2916 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2917 | check_timer(); |
1da177e4 LT |
2918 | } |
2919 | ||
2920 | /* | |
0d2eb44f | 2921 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2922 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2923 | */ |
36062448 | 2924 | |
1da177e4 LT |
2925 | static int __init io_apic_bug_finalize(void) |
2926 | { | |
d6c88a50 TG |
2927 | if (sis_apic_bug == -1) |
2928 | sis_apic_bug = 0; | |
2929 | return 0; | |
1da177e4 LT |
2930 | } |
2931 | ||
2932 | late_initcall(io_apic_bug_finalize); | |
2933 | ||
f3c6ea1b | 2934 | static void suspend_ioapic(int ioapic_id) |
1da177e4 | 2935 | { |
f3c6ea1b | 2936 | struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id]; |
1da177e4 | 2937 | int i; |
36062448 | 2938 | |
f3c6ea1b RW |
2939 | if (!saved_data) |
2940 | return; | |
2941 | ||
2942 | for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++) | |
2943 | saved_data[i] = ioapic_read_entry(ioapic_id, i); | |
2944 | } | |
2945 | ||
2946 | static int ioapic_suspend(void) | |
2947 | { | |
2948 | int ioapic_id; | |
2949 | ||
2950 | for (ioapic_id = 0; ioapic_id < nr_ioapics; ioapic_id++) | |
2951 | suspend_ioapic(ioapic_id); | |
1da177e4 LT |
2952 | |
2953 | return 0; | |
2954 | } | |
2955 | ||
f3c6ea1b | 2956 | static void resume_ioapic(int ioapic_id) |
1da177e4 | 2957 | { |
f3c6ea1b | 2958 | struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id]; |
1da177e4 LT |
2959 | unsigned long flags; |
2960 | union IO_APIC_reg_00 reg_00; | |
2961 | int i; | |
36062448 | 2962 | |
f3c6ea1b RW |
2963 | if (!saved_data) |
2964 | return; | |
1da177e4 | 2965 | |
dade7716 | 2966 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f3c6ea1b RW |
2967 | reg_00.raw = io_apic_read(ioapic_id, 0); |
2968 | if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) { | |
2969 | reg_00.bits.ID = mp_ioapics[ioapic_id].apicid; | |
2970 | io_apic_write(ioapic_id, 0, reg_00.raw); | |
1da177e4 | 2971 | } |
dade7716 | 2972 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b RW |
2973 | for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++) |
2974 | ioapic_write_entry(ioapic_id, i, saved_data[i]); | |
2975 | } | |
1da177e4 | 2976 | |
f3c6ea1b RW |
2977 | static void ioapic_resume(void) |
2978 | { | |
2979 | int ioapic_id; | |
2980 | ||
2981 | for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--) | |
2982 | resume_ioapic(ioapic_id); | |
1da177e4 LT |
2983 | } |
2984 | ||
f3c6ea1b | 2985 | static struct syscore_ops ioapic_syscore_ops = { |
1da177e4 LT |
2986 | .suspend = ioapic_suspend, |
2987 | .resume = ioapic_resume, | |
2988 | }; | |
2989 | ||
f3c6ea1b | 2990 | static int __init ioapic_init_ops(void) |
1da177e4 | 2991 | { |
f3c6ea1b RW |
2992 | register_syscore_ops(&ioapic_syscore_ops); |
2993 | ||
1da177e4 LT |
2994 | return 0; |
2995 | } | |
2996 | ||
f3c6ea1b | 2997 | device_initcall(ioapic_init_ops); |
1da177e4 | 2998 | |
3fc471ed | 2999 | /* |
95d77884 | 3000 | * Dynamic irq allocate and deallocation |
3fc471ed | 3001 | */ |
fbc6bff0 | 3002 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 3003 | { |
fbc6bff0 | 3004 | struct irq_cfg *cfg; |
3fc471ed | 3005 | unsigned long flags; |
fbc6bff0 TG |
3006 | unsigned int ret = 0; |
3007 | int irq; | |
d047f53a | 3008 | |
fbc6bff0 TG |
3009 | if (from < nr_irqs_gsi) |
3010 | from = nr_irqs_gsi; | |
d047f53a | 3011 | |
fbc6bff0 TG |
3012 | irq = alloc_irq_from(from, node); |
3013 | if (irq < 0) | |
3014 | return 0; | |
3015 | cfg = alloc_irq_cfg(irq, node); | |
3016 | if (!cfg) { | |
3017 | free_irq_at(irq, NULL); | |
3018 | return 0; | |
ace80ab7 | 3019 | } |
3fc471ed | 3020 | |
fbc6bff0 TG |
3021 | raw_spin_lock_irqsave(&vector_lock, flags); |
3022 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
3023 | ret = irq; | |
3024 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3025 | |
fbc6bff0 | 3026 | if (ret) { |
2c778651 | 3027 | irq_set_chip_data(irq, cfg); |
fbc6bff0 TG |
3028 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
3029 | } else { | |
3030 | free_irq_at(irq, cfg); | |
3031 | } | |
3032 | return ret; | |
3fc471ed EB |
3033 | } |
3034 | ||
199751d7 YL |
3035 | int create_irq(void) |
3036 | { | |
f6e9456c | 3037 | int node = cpu_to_node(0); |
be5d5350 | 3038 | unsigned int irq_want; |
54168ed7 IM |
3039 | int irq; |
3040 | ||
be5d5350 | 3041 | irq_want = nr_irqs_gsi; |
d047f53a | 3042 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3043 | |
3044 | if (irq == 0) | |
3045 | irq = -1; | |
3046 | ||
3047 | return irq; | |
199751d7 YL |
3048 | } |
3049 | ||
3fc471ed EB |
3050 | void destroy_irq(unsigned int irq) |
3051 | { | |
2c778651 | 3052 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 3053 | unsigned long flags; |
3fc471ed | 3054 | |
fbc6bff0 | 3055 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3056 | |
7b79462a | 3057 | if (irq_remapped(cfg)) |
9717967c | 3058 | free_irte(irq); |
dade7716 | 3059 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3060 | __clear_irq_vector(irq, cfg); |
dade7716 | 3061 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3062 | free_irq_at(irq, cfg); |
3fc471ed | 3063 | } |
3fc471ed | 3064 | |
2d3fcc1c | 3065 | /* |
27b46d76 | 3066 | * MSI message composition |
2d3fcc1c EB |
3067 | */ |
3068 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3069 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3070 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3071 | { |
497c9a19 YL |
3072 | struct irq_cfg *cfg; |
3073 | int err; | |
2d3fcc1c EB |
3074 | unsigned dest; |
3075 | ||
f1182638 JB |
3076 | if (disable_apic) |
3077 | return -ENXIO; | |
3078 | ||
3145e941 | 3079 | cfg = irq_cfg(irq); |
fe402e1f | 3080 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3081 | if (err) |
3082 | return err; | |
2d3fcc1c | 3083 | |
debccb3e | 3084 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3085 | |
1a0e62a4 | 3086 | if (irq_remapped(cfg)) { |
54168ed7 IM |
3087 | struct irte irte; |
3088 | int ir_index; | |
3089 | u16 sub_handle; | |
3090 | ||
3091 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3092 | BUG_ON(ir_index == -1); | |
3093 | ||
62a92f4c | 3094 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3095 | |
f007e99c | 3096 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3097 | if (pdev) |
3098 | set_msi_sid(&irte, pdev); | |
3099 | else | |
3100 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3101 | |
54168ed7 IM |
3102 | modify_irte(irq, &irte); |
3103 | ||
3104 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3105 | msg->data = sub_handle; | |
3106 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3107 | MSI_ADDR_IR_SHV | | |
3108 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3109 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3110 | } else { |
9d783ba0 SS |
3111 | if (x2apic_enabled()) |
3112 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3113 | MSI_ADDR_EXT_DEST_ID(dest); | |
3114 | else | |
3115 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3116 | ||
54168ed7 IM |
3117 | msg->address_lo = |
3118 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3119 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3120 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3121 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3122 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3123 | MSI_ADDR_REDIRECTION_CPU: |
3124 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3125 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3126 | |
54168ed7 IM |
3127 | msg->data = |
3128 | MSI_DATA_TRIGGER_EDGE | | |
3129 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3130 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3131 | MSI_DATA_DELIVERY_FIXED: |
3132 | MSI_DATA_DELIVERY_LOWPRI) | | |
3133 | MSI_DATA_VECTOR(cfg->vector); | |
3134 | } | |
497c9a19 | 3135 | return err; |
2d3fcc1c EB |
3136 | } |
3137 | ||
3b7d1921 | 3138 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3139 | static int |
3140 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3141 | { |
5346b2a7 | 3142 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3143 | struct msi_msg msg; |
3144 | unsigned int dest; | |
3b7d1921 | 3145 | |
5346b2a7 | 3146 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3147 | return -1; |
2d3fcc1c | 3148 | |
5346b2a7 | 3149 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3150 | |
3151 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3152 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3153 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3154 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3155 | ||
5346b2a7 | 3156 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3157 | |
3158 | return 0; | |
2d3fcc1c | 3159 | } |
54168ed7 IM |
3160 | #ifdef CONFIG_INTR_REMAP |
3161 | /* | |
3162 | * Migrate the MSI irq to another cpumask. This migration is | |
3163 | * done in the process context using interrupt-remapping hardware. | |
3164 | */ | |
d5dedd45 | 3165 | static int |
b5d1c465 TG |
3166 | ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3167 | bool force) | |
54168ed7 | 3168 | { |
b5d1c465 TG |
3169 | struct irq_cfg *cfg = data->chip_data; |
3170 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3171 | struct irte irte; |
54168ed7 IM |
3172 | |
3173 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3174 | return -1; |
54168ed7 | 3175 | |
b5d1c465 | 3176 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3177 | return -1; |
54168ed7 | 3178 | |
54168ed7 IM |
3179 | irte.vector = cfg->vector; |
3180 | irte.dest_id = IRTE_DEST(dest); | |
3181 | ||
3182 | /* | |
3183 | * atomically update the IRTE with the new destination and vector. | |
3184 | */ | |
3185 | modify_irte(irq, &irte); | |
3186 | ||
3187 | /* | |
3188 | * After this point, all the interrupts will start arriving | |
3189 | * at the new destination. So, time to cleanup the previous | |
3190 | * vector allocation. | |
3191 | */ | |
22f65d31 MT |
3192 | if (cfg->move_in_progress) |
3193 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3194 | |
3195 | return 0; | |
54168ed7 | 3196 | } |
3145e941 | 3197 | |
54168ed7 | 3198 | #endif |
3b7d1921 | 3199 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3200 | |
3b7d1921 EB |
3201 | /* |
3202 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3203 | * which implement the MSI or MSI-X Capability Structure. | |
3204 | */ | |
3205 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3206 | .name = "PCI-MSI", |
3207 | .irq_unmask = unmask_msi_irq, | |
3208 | .irq_mask = mask_msi_irq, | |
3209 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3210 | #ifdef CONFIG_SMP |
5346b2a7 | 3211 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3212 | #endif |
5346b2a7 | 3213 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3214 | }; |
3215 | ||
54168ed7 | 3216 | static struct irq_chip msi_ir_chip = { |
b5d1c465 TG |
3217 | .name = "IR-PCI-MSI", |
3218 | .irq_unmask = unmask_msi_irq, | |
3219 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3220 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3221 | .irq_ack = ir_ack_apic_edge, |
54168ed7 | 3222 | #ifdef CONFIG_SMP |
b5d1c465 | 3223 | .irq_set_affinity = ir_msi_set_affinity, |
a1e38ca5 | 3224 | #endif |
54168ed7 | 3225 | #endif |
b5d1c465 | 3226 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3227 | }; |
3228 | ||
3229 | /* | |
3230 | * Map the PCI dev to the corresponding remapping hardware unit | |
3231 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3232 | * in it. | |
3233 | */ | |
3234 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3235 | { | |
3236 | struct intel_iommu *iommu; | |
3237 | int index; | |
3238 | ||
3239 | iommu = map_dev_to_ir(dev); | |
3240 | if (!iommu) { | |
3241 | printk(KERN_ERR | |
3242 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3243 | return -ENOENT; | |
3244 | } | |
3245 | ||
3246 | index = alloc_irte(iommu, irq, nvec); | |
3247 | if (index < 0) { | |
3248 | printk(KERN_ERR | |
3249 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3250 | pci_name(dev)); |
54168ed7 IM |
3251 | return -ENOSPC; |
3252 | } | |
3253 | return index; | |
3254 | } | |
1d025192 | 3255 | |
3145e941 | 3256 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3257 | { |
c60eaf25 | 3258 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3259 | struct msi_msg msg; |
60c69948 | 3260 | int ret; |
1d025192 | 3261 | |
c8bc6f3c | 3262 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3263 | if (ret < 0) |
3264 | return ret; | |
3265 | ||
2c778651 | 3266 | irq_set_msi_desc(irq, msidesc); |
1d025192 YL |
3267 | write_msi_msg(irq, &msg); |
3268 | ||
2c778651 | 3269 | if (irq_remapped(irq_get_chip_data(irq))) { |
60c69948 | 3270 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
3271 | chip = &msi_ir_chip; |
3272 | } | |
3273 | ||
3274 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3275 | |
c81bba49 YL |
3276 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3277 | ||
1d025192 YL |
3278 | return 0; |
3279 | } | |
3280 | ||
294ee6f8 | 3281 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3282 | { |
60c69948 TG |
3283 | int node, ret, sub_handle, index = 0; |
3284 | unsigned int irq, irq_want; | |
0b8f1efa | 3285 | struct msi_desc *msidesc; |
1cc18521 | 3286 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3287 | |
1c8d7b0a MW |
3288 | /* x86 doesn't support multiple MSI yet */ |
3289 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3290 | return 1; | |
3291 | ||
d047f53a | 3292 | node = dev_to_node(&dev->dev); |
be5d5350 | 3293 | irq_want = nr_irqs_gsi; |
54168ed7 | 3294 | sub_handle = 0; |
0b8f1efa | 3295 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3296 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3297 | if (irq == 0) |
3298 | return -1; | |
f1ee5548 | 3299 | irq_want = irq + 1; |
54168ed7 IM |
3300 | if (!intr_remapping_enabled) |
3301 | goto no_ir; | |
3302 | ||
3303 | if (!sub_handle) { | |
3304 | /* | |
3305 | * allocate the consecutive block of IRTE's | |
3306 | * for 'nvec' | |
3307 | */ | |
3308 | index = msi_alloc_irte(dev, irq, nvec); | |
3309 | if (index < 0) { | |
3310 | ret = index; | |
3311 | goto error; | |
3312 | } | |
3313 | } else { | |
3314 | iommu = map_dev_to_ir(dev); | |
3315 | if (!iommu) { | |
3316 | ret = -ENOENT; | |
3317 | goto error; | |
3318 | } | |
3319 | /* | |
3320 | * setup the mapping between the irq and the IRTE | |
3321 | * base index, the sub_handle pointing to the | |
3322 | * appropriate interrupt remap table entry. | |
3323 | */ | |
3324 | set_irte_irq(irq, iommu, index, sub_handle); | |
3325 | } | |
3326 | no_ir: | |
0b8f1efa | 3327 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3328 | if (ret < 0) |
3329 | goto error; | |
3330 | sub_handle++; | |
3331 | } | |
3332 | return 0; | |
047c8fdb YL |
3333 | |
3334 | error: | |
54168ed7 IM |
3335 | destroy_irq(irq); |
3336 | return ret; | |
047c8fdb YL |
3337 | } |
3338 | ||
294ee6f8 | 3339 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3340 | { |
f7feaca7 | 3341 | destroy_irq(irq); |
3b7d1921 EB |
3342 | } |
3343 | ||
9d783ba0 | 3344 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3345 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3346 | static int |
3347 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3348 | bool force) | |
54168ed7 | 3349 | { |
fe52b2d2 TG |
3350 | struct irq_cfg *cfg = data->chip_data; |
3351 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3352 | struct msi_msg msg; |
54168ed7 | 3353 | |
fe52b2d2 | 3354 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3355 | return -1; |
54168ed7 | 3356 | |
54168ed7 IM |
3357 | dmar_msi_read(irq, &msg); |
3358 | ||
3359 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3360 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3361 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3362 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3363 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3364 | |
3365 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3366 | |
3367 | return 0; | |
54168ed7 | 3368 | } |
3145e941 | 3369 | |
54168ed7 IM |
3370 | #endif /* CONFIG_SMP */ |
3371 | ||
8f7007aa | 3372 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3373 | .name = "DMAR_MSI", |
3374 | .irq_unmask = dmar_msi_unmask, | |
3375 | .irq_mask = dmar_msi_mask, | |
3376 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3377 | #ifdef CONFIG_SMP |
fe52b2d2 | 3378 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3379 | #endif |
fe52b2d2 | 3380 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3381 | }; |
3382 | ||
3383 | int arch_setup_dmar_msi(unsigned int irq) | |
3384 | { | |
3385 | int ret; | |
3386 | struct msi_msg msg; | |
2d3fcc1c | 3387 | |
c8bc6f3c | 3388 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3389 | if (ret < 0) |
3390 | return ret; | |
3391 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3392 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3393 | "edge"); | |
54168ed7 IM |
3394 | return 0; |
3395 | } | |
3396 | #endif | |
3397 | ||
58ac1e76 | 3398 | #ifdef CONFIG_HPET_TIMER |
3399 | ||
3400 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3401 | static int hpet_msi_set_affinity(struct irq_data *data, |
3402 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3403 | { |
d0fbca8f | 3404 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3405 | struct msi_msg msg; |
3406 | unsigned int dest; | |
58ac1e76 | 3407 | |
0e09ddf2 | 3408 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3409 | return -1; |
58ac1e76 | 3410 | |
d0fbca8f | 3411 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3412 | |
3413 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3414 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3415 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3416 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3417 | ||
d0fbca8f | 3418 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3419 | |
3420 | return 0; | |
58ac1e76 | 3421 | } |
3145e941 | 3422 | |
58ac1e76 | 3423 | #endif /* CONFIG_SMP */ |
3424 | ||
c8bc6f3c | 3425 | static struct irq_chip ir_hpet_msi_type = { |
b5d1c465 TG |
3426 | .name = "IR-HPET_MSI", |
3427 | .irq_unmask = hpet_msi_unmask, | |
3428 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3429 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3430 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c | 3431 | #ifdef CONFIG_SMP |
b5d1c465 | 3432 | .irq_set_affinity = ir_msi_set_affinity, |
c8bc6f3c SS |
3433 | #endif |
3434 | #endif | |
b5d1c465 | 3435 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3436 | }; |
3437 | ||
1cc18521 | 3438 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3439 | .name = "HPET_MSI", |
d0fbca8f TG |
3440 | .irq_unmask = hpet_msi_unmask, |
3441 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3442 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3443 | #ifdef CONFIG_SMP |
d0fbca8f | 3444 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3445 | #endif |
90297c5f | 3446 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3447 | }; |
3448 | ||
c8bc6f3c | 3449 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3450 | { |
c60eaf25 | 3451 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3452 | struct msi_msg msg; |
d0fbca8f | 3453 | int ret; |
58ac1e76 | 3454 | |
c8bc6f3c SS |
3455 | if (intr_remapping_enabled) { |
3456 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3457 | int index; | |
3458 | ||
3459 | if (!iommu) | |
3460 | return -1; | |
3461 | ||
3462 | index = alloc_irte(iommu, irq, 1); | |
3463 | if (index < 0) | |
3464 | return -1; | |
3465 | } | |
3466 | ||
3467 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3468 | if (ret < 0) |
3469 | return ret; | |
3470 | ||
2c778651 | 3471 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3472 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2c778651 | 3473 | if (irq_remapped(irq_get_chip_data(irq))) |
c60eaf25 | 3474 | chip = &ir_hpet_msi_type; |
c81bba49 | 3475 | |
c60eaf25 | 3476 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3477 | return 0; |
3478 | } | |
3479 | #endif | |
3480 | ||
54168ed7 | 3481 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3482 | /* |
3483 | * Hypertransport interrupt support | |
3484 | */ | |
3485 | #ifdef CONFIG_HT_IRQ | |
3486 | ||
3487 | #ifdef CONFIG_SMP | |
3488 | ||
497c9a19 | 3489 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3490 | { |
ec68307c EB |
3491 | struct ht_irq_msg msg; |
3492 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3493 | |
497c9a19 | 3494 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3495 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3496 | |
497c9a19 | 3497 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3498 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3499 | |
ec68307c | 3500 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3501 | } |
3502 | ||
be5b7bf7 TG |
3503 | static int |
3504 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3505 | { |
be5b7bf7 | 3506 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3507 | unsigned int dest; |
8b955b0d | 3508 | |
be5b7bf7 | 3509 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3510 | return -1; |
8b955b0d | 3511 | |
be5b7bf7 | 3512 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3513 | return 0; |
8b955b0d | 3514 | } |
3145e941 | 3515 | |
8b955b0d EB |
3516 | #endif |
3517 | ||
c37e108d | 3518 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3519 | .name = "PCI-HT", |
3520 | .irq_mask = mask_ht_irq, | |
3521 | .irq_unmask = unmask_ht_irq, | |
3522 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3523 | #ifdef CONFIG_SMP |
be5b7bf7 | 3524 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3525 | #endif |
be5b7bf7 | 3526 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3527 | }; |
3528 | ||
3529 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3530 | { | |
497c9a19 YL |
3531 | struct irq_cfg *cfg; |
3532 | int err; | |
8b955b0d | 3533 | |
f1182638 JB |
3534 | if (disable_apic) |
3535 | return -ENXIO; | |
3536 | ||
3145e941 | 3537 | cfg = irq_cfg(irq); |
fe402e1f | 3538 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3539 | if (!err) { |
ec68307c | 3540 | struct ht_irq_msg msg; |
8b955b0d | 3541 | unsigned dest; |
8b955b0d | 3542 | |
debccb3e IM |
3543 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3544 | apic->target_cpus()); | |
8b955b0d | 3545 | |
ec68307c | 3546 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3547 | |
ec68307c EB |
3548 | msg.address_lo = |
3549 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3550 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3551 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3552 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3553 | HT_IRQ_LOW_DM_PHYSICAL : |
3554 | HT_IRQ_LOW_DM_LOGICAL) | | |
3555 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3556 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3557 | HT_IRQ_LOW_MT_FIXED : |
3558 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3559 | HT_IRQ_LOW_IRQ_MASKED; | |
3560 | ||
ec68307c | 3561 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3562 | |
2c778651 | 3563 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
a460e745 | 3564 | handle_edge_irq, "edge"); |
c81bba49 YL |
3565 | |
3566 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3567 | } |
497c9a19 | 3568 | return err; |
8b955b0d EB |
3569 | } |
3570 | #endif /* CONFIG_HT_IRQ */ | |
3571 | ||
20443598 | 3572 | static int |
ff973d04 TG |
3573 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3574 | { | |
3575 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3576 | int ret; | |
3577 | ||
3578 | if (!cfg) | |
3579 | return -EINVAL; | |
3580 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3581 | if (!ret) | |
3582 | setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, | |
3583 | attr->trigger, attr->polarity); | |
3584 | return ret; | |
3585 | } | |
3586 | ||
20443598 SAS |
3587 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3588 | struct io_apic_irq_attr *attr) | |
710dcda6 TG |
3589 | { |
3590 | unsigned int id = attr->ioapic, pin = attr->ioapic_pin; | |
3591 | int ret; | |
3592 | ||
3593 | /* Avoid redundant programming */ | |
3594 | if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) { | |
3595 | pr_debug("Pin %d-%d already programmed\n", | |
3596 | mp_ioapics[id].apicid, pin); | |
3597 | return 0; | |
3598 | } | |
3599 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3600 | if (!ret) | |
3601 | set_bit(pin, mp_ioapic_routing[id].pin_programmed); | |
3602 | return ret; | |
3603 | } | |
3604 | ||
41098ffe | 3605 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3606 | { |
3607 | union IO_APIC_reg_01 reg_01; | |
3608 | unsigned long flags; | |
3609 | ||
dade7716 | 3610 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3611 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3612 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3613 | |
4b6b19a1 EB |
3614 | /* The register returns the maximum index redir index |
3615 | * supported, which is one less than the total number of redir | |
3616 | * entries. | |
3617 | */ | |
3618 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3619 | } |
3620 | ||
23f9b267 | 3621 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3622 | { |
4afc51a8 | 3623 | int nr; |
be5d5350 | 3624 | |
a4384df3 | 3625 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3626 | if (nr > nr_irqs_gsi) |
be5d5350 | 3627 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3628 | |
3629 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3630 | } |
3631 | ||
7b586d71 JF |
3632 | int get_nr_irqs_gsi(void) |
3633 | { | |
3634 | return nr_irqs_gsi; | |
3635 | } | |
3636 | ||
4a046d17 YL |
3637 | #ifdef CONFIG_SPARSE_IRQ |
3638 | int __init arch_probe_nr_irqs(void) | |
3639 | { | |
3640 | int nr; | |
3641 | ||
f1ee5548 YL |
3642 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3643 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3644 | |
f1ee5548 YL |
3645 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3646 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3647 | /* | |
3648 | * for MSI and HT dyn irq | |
3649 | */ | |
3650 | nr += nr_irqs_gsi * 16; | |
3651 | #endif | |
3652 | if (nr < nr_irqs) | |
4a046d17 YL |
3653 | nr_irqs = nr; |
3654 | ||
b683de2b | 3655 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3656 | } |
3657 | #endif | |
3658 | ||
710dcda6 TG |
3659 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3660 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3661 | { |
5ef21837 YL |
3662 | int node; |
3663 | ||
3664 | if (!IO_APIC_IRQ(irq)) { | |
3665 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3666 | irq_attr->ioapic); |
5ef21837 YL |
3667 | return -EINVAL; |
3668 | } | |
3669 | ||
e0799c04 | 3670 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3671 | |
710dcda6 | 3672 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3673 | } |
3674 | ||
54168ed7 | 3675 | #ifdef CONFIG_X86_32 |
41098ffe | 3676 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3677 | { |
3678 | union IO_APIC_reg_00 reg_00; | |
3679 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3680 | physid_mask_t tmp; | |
3681 | unsigned long flags; | |
3682 | int i = 0; | |
3683 | ||
3684 | /* | |
36062448 PC |
3685 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3686 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3687 | * supports up to 16 on one shared APIC bus. |
36062448 | 3688 | * |
1da177e4 LT |
3689 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3690 | * advantage of new APIC bus architecture. | |
3691 | */ | |
3692 | ||
3693 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3694 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3695 | |
dade7716 | 3696 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3697 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3698 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3699 | |
3700 | if (apic_id >= get_physical_broadcast()) { | |
3701 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3702 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3703 | apic_id = reg_00.bits.ID; | |
3704 | } | |
3705 | ||
3706 | /* | |
36062448 | 3707 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3708 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3709 | */ | |
7abc0753 | 3710 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3711 | |
3712 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3713 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3714 | break; |
3715 | } | |
3716 | ||
3717 | if (i == get_physical_broadcast()) | |
3718 | panic("Max apic_id exceeded!\n"); | |
3719 | ||
3720 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3721 | "trying %d\n", ioapic, apic_id, i); | |
3722 | ||
3723 | apic_id = i; | |
36062448 | 3724 | } |
1da177e4 | 3725 | |
7abc0753 | 3726 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3727 | physids_or(apic_id_map, apic_id_map, tmp); |
3728 | ||
3729 | if (reg_00.bits.ID != apic_id) { | |
3730 | reg_00.bits.ID = apic_id; | |
3731 | ||
dade7716 | 3732 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3733 | io_apic_write(ioapic, 0, reg_00.raw); |
3734 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3735 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3736 | |
3737 | /* Sanity check */ | |
6070f9ec AD |
3738 | if (reg_00.bits.ID != apic_id) { |
3739 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3740 | return -1; | |
3741 | } | |
1da177e4 LT |
3742 | } |
3743 | ||
3744 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3745 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3746 | ||
3747 | return apic_id; | |
3748 | } | |
41098ffe TG |
3749 | |
3750 | static u8 __init io_apic_unique_id(u8 id) | |
3751 | { | |
3752 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3753 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3754 | return io_apic_get_unique_id(nr_ioapics, id); | |
3755 | else | |
3756 | return id; | |
3757 | } | |
3758 | #else | |
3759 | static u8 __init io_apic_unique_id(u8 id) | |
3760 | { | |
3761 | int i; | |
3762 | DECLARE_BITMAP(used, 256); | |
3763 | ||
3764 | bitmap_zero(used, 256); | |
3765 | for (i = 0; i < nr_ioapics; i++) { | |
3766 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3767 | __set_bit(ia->apicid, used); | |
3768 | } | |
3769 | if (!test_bit(id, used)) | |
3770 | return id; | |
3771 | return find_first_zero_bit(used, 256); | |
3772 | } | |
58f892e0 | 3773 | #endif |
1da177e4 | 3774 | |
41098ffe | 3775 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3776 | { |
3777 | union IO_APIC_reg_01 reg_01; | |
3778 | unsigned long flags; | |
3779 | ||
dade7716 | 3780 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3781 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3782 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3783 | |
3784 | return reg_01.bits.version; | |
3785 | } | |
3786 | ||
9a0a91bb | 3787 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3788 | { |
9a0a91bb | 3789 | int ioapic, pin, idx; |
61fd47e0 SL |
3790 | |
3791 | if (skip_ioapic_setup) | |
3792 | return -1; | |
3793 | ||
9a0a91bb EB |
3794 | ioapic = mp_find_ioapic(gsi); |
3795 | if (ioapic < 0) | |
61fd47e0 SL |
3796 | return -1; |
3797 | ||
9a0a91bb EB |
3798 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3799 | if (pin < 0) | |
3800 | return -1; | |
3801 | ||
3802 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3803 | if (idx < 0) | |
61fd47e0 SL |
3804 | return -1; |
3805 | ||
9a0a91bb EB |
3806 | *trigger = irq_trigger(idx); |
3807 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3808 | return 0; |
3809 | } | |
3810 | ||
497c9a19 YL |
3811 | /* |
3812 | * This function currently is only a helper for the i386 smp boot process where | |
3813 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3814 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3815 | */ |
3816 | #ifdef CONFIG_SMP | |
3817 | void __init setup_ioapic_dest(void) | |
3818 | { | |
fad53995 | 3819 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3820 | const struct cpumask *mask; |
5451ddc5 | 3821 | struct irq_data *idata; |
497c9a19 YL |
3822 | |
3823 | if (skip_ioapic_setup == 1) | |
3824 | return; | |
3825 | ||
fad53995 | 3826 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
3827 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
3828 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3829 | if (irq_entry == -1) | |
3830 | continue; | |
3831 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3832 | |
fad53995 EB |
3833 | if ((ioapic > 0) && (irq > 16)) |
3834 | continue; | |
3835 | ||
5451ddc5 | 3836 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3837 | |
b9c61b70 YL |
3838 | /* |
3839 | * Honour affinities which have been set in early boot | |
3840 | */ | |
5451ddc5 TG |
3841 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3842 | mask = idata->affinity; | |
b9c61b70 YL |
3843 | else |
3844 | mask = apic->target_cpus(); | |
497c9a19 | 3845 | |
b9c61b70 | 3846 | if (intr_remapping_enabled) |
5451ddc5 | 3847 | ir_ioapic_set_affinity(idata, mask, false); |
b9c61b70 | 3848 | else |
5451ddc5 | 3849 | ioapic_set_affinity(idata, mask, false); |
497c9a19 | 3850 | } |
b9c61b70 | 3851 | |
497c9a19 YL |
3852 | } |
3853 | #endif | |
3854 | ||
54168ed7 IM |
3855 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3856 | ||
3857 | static struct resource *ioapic_resources; | |
3858 | ||
ffc43836 | 3859 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3860 | { |
3861 | unsigned long n; | |
3862 | struct resource *res; | |
3863 | char *mem; | |
3864 | int i; | |
3865 | ||
3866 | if (nr_ioapics <= 0) | |
3867 | return NULL; | |
3868 | ||
3869 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3870 | n *= nr_ioapics; | |
3871 | ||
3872 | mem = alloc_bootmem(n); | |
3873 | res = (void *)mem; | |
3874 | ||
ffc43836 | 3875 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3876 | |
ffc43836 CG |
3877 | for (i = 0; i < nr_ioapics; i++) { |
3878 | res[i].name = mem; | |
3879 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3880 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3881 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3882 | } |
3883 | ||
3884 | ioapic_resources = res; | |
3885 | ||
3886 | return res; | |
3887 | } | |
54168ed7 | 3888 | |
23f9b267 | 3889 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3890 | { |
3891 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3892 | struct resource *ioapic_res; |
d6c88a50 | 3893 | int i; |
f3294a33 | 3894 | |
ffc43836 | 3895 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3896 | for (i = 0; i < nr_ioapics; i++) { |
3897 | if (smp_found_config) { | |
b5ba7e6d | 3898 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 3899 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3900 | if (!ioapic_phys) { |
3901 | printk(KERN_ERR | |
3902 | "WARNING: bogus zero IO-APIC " | |
3903 | "address found in MPTABLE, " | |
3904 | "disabling IO/APIC support!\n"); | |
3905 | smp_found_config = 0; | |
3906 | skip_ioapic_setup = 1; | |
3907 | goto fake_ioapic_page; | |
3908 | } | |
54168ed7 | 3909 | #endif |
f3294a33 | 3910 | } else { |
54168ed7 | 3911 | #ifdef CONFIG_X86_32 |
f3294a33 | 3912 | fake_ioapic_page: |
54168ed7 | 3913 | #endif |
e79c65a9 | 3914 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3915 | ioapic_phys = __pa(ioapic_phys); |
3916 | } | |
3917 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3918 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3919 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3920 | ioapic_phys); | |
f3294a33 | 3921 | idx++; |
54168ed7 | 3922 | |
ffc43836 | 3923 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3924 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3925 | ioapic_res++; |
f3294a33 | 3926 | } |
23f9b267 TG |
3927 | |
3928 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3929 | } |
3930 | ||
857fdc53 | 3931 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3932 | { |
3933 | int i; | |
3934 | struct resource *r = ioapic_resources; | |
3935 | ||
3936 | if (!r) { | |
857fdc53 | 3937 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3938 | printk(KERN_ERR |
3939 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3940 | return; |
54168ed7 IM |
3941 | } |
3942 | ||
3943 | for (i = 0; i < nr_ioapics; i++) { | |
3944 | insert_resource(&iomem_resource, r); | |
3945 | r++; | |
3946 | } | |
54168ed7 | 3947 | } |
2a4ab640 | 3948 | |
eddb0c55 | 3949 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3950 | { |
3951 | int i = 0; | |
3952 | ||
678301ec PB |
3953 | if (nr_ioapics == 0) |
3954 | return -1; | |
3955 | ||
2a4ab640 FT |
3956 | /* Find the IOAPIC that manages this GSI. */ |
3957 | for (i = 0; i < nr_ioapics; i++) { | |
3958 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
3959 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
3960 | return i; | |
3961 | } | |
54168ed7 | 3962 | |
2a4ab640 FT |
3963 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3964 | return -1; | |
3965 | } | |
3966 | ||
eddb0c55 | 3967 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
3968 | { |
3969 | if (WARN_ON(ioapic == -1)) | |
3970 | return -1; | |
3971 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
3972 | return -1; | |
3973 | ||
3974 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
3975 | } | |
3976 | ||
41098ffe | 3977 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3978 | { |
3979 | if (nr_ioapics >= MAX_IO_APICS) { | |
45e8234c | 3980 | printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded " |
2a4ab640 FT |
3981 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); |
3982 | return 1; | |
3983 | } | |
3984 | if (!address) { | |
3985 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
3986 | " found in table, skipping!\n"); | |
3987 | return 1; | |
3988 | } | |
54168ed7 IM |
3989 | return 0; |
3990 | } | |
3991 | ||
2a4ab640 FT |
3992 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3993 | { | |
3994 | int idx = 0; | |
7716a5c4 | 3995 | int entries; |
2a4ab640 FT |
3996 | |
3997 | if (bad_ioapic(address)) | |
3998 | return; | |
3999 | ||
4000 | idx = nr_ioapics; | |
4001 | ||
4002 | mp_ioapics[idx].type = MP_IOAPIC; | |
4003 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4004 | mp_ioapics[idx].apicaddr = address; | |
4005 | ||
4006 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4007 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4008 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4009 | ||
4010 | /* | |
4011 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4012 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4013 | */ | |
7716a5c4 | 4014 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4015 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4016 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4017 | ||
4018 | /* | |
4019 | * The number of IO-APIC IRQ registers (== #pins): | |
4020 | */ | |
4021 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4022 | |
a4384df3 EB |
4023 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4024 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4025 | |
4026 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4027 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4028 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4029 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4030 | ||
4031 | nr_ioapics++; | |
4032 | } | |
05ddafb1 JP |
4033 | |
4034 | /* Enable IOAPIC early just for system timer */ | |
4035 | void __init pre_init_apic_IRQ0(void) | |
4036 | { | |
f880ec78 | 4037 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
4038 | |
4039 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4040 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
4041 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
4042 | &phys_cpu_present_map); | |
05ddafb1 | 4043 | #endif |
05ddafb1 JP |
4044 | setup_local_APIC(); |
4045 | ||
f880ec78 | 4046 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
4047 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
4048 | "edge"); | |
05ddafb1 | 4049 | } |