Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
4173a0e7 DN |
63 | #include <asm/uv/uv_hub.h> |
64 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 65 | |
7b6aa335 | 66 | #include <asm/apic.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
c2c21745 | 89 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
65a4e574 IM |
102 | void arch_disable_smp_support(void) |
103 | { | |
104 | #ifdef CONFIG_PCI | |
105 | noioapicquirk = 1; | |
106 | noioapicreroute = -1; | |
107 | #endif | |
108 | skip_ioapic_setup = 1; | |
109 | } | |
110 | ||
54168ed7 | 111 | static int __init parse_noapic(char *str) |
efa2559f YL |
112 | { |
113 | /* disable IO-APIC */ | |
65a4e574 | 114 | arch_disable_smp_support(); |
efa2559f YL |
115 | return 0; |
116 | } | |
117 | early_param("noapic", parse_noapic); | |
66759a01 | 118 | |
0f978f45 | 119 | struct irq_pin_list; |
0b8f1efa YL |
120 | |
121 | /* | |
122 | * This is performance-critical, we want to do it O(1) | |
123 | * | |
124 | * the indexing order of this array favors 1:1 mappings | |
125 | * between pins and IRQs. | |
126 | */ | |
127 | ||
128 | struct irq_pin_list { | |
129 | int apic, pin; | |
130 | struct irq_pin_list *next; | |
131 | }; | |
132 | ||
85ac16d0 | 133 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
134 | { |
135 | struct irq_pin_list *pin; | |
0b8f1efa YL |
136 | |
137 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
138 | |
139 | return pin; | |
140 | } | |
141 | ||
a1420f39 | 142 | struct irq_cfg { |
0f978f45 | 143 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
144 | cpumask_var_t domain; |
145 | cpumask_var_t old_domain; | |
497c9a19 | 146 | unsigned move_cleanup_count; |
a1420f39 | 147 | u8 vector; |
497c9a19 | 148 | u8 move_in_progress : 1; |
a1420f39 YL |
149 | }; |
150 | ||
a1420f39 | 151 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
152 | #ifdef CONFIG_SPARSE_IRQ |
153 | static struct irq_cfg irq_cfgx[] = { | |
154 | #else | |
d6c88a50 | 155 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 156 | #endif |
22f65d31 MT |
157 | [0] = { .vector = IRQ0_VECTOR, }, |
158 | [1] = { .vector = IRQ1_VECTOR, }, | |
159 | [2] = { .vector = IRQ2_VECTOR, }, | |
160 | [3] = { .vector = IRQ3_VECTOR, }, | |
161 | [4] = { .vector = IRQ4_VECTOR, }, | |
162 | [5] = { .vector = IRQ5_VECTOR, }, | |
163 | [6] = { .vector = IRQ6_VECTOR, }, | |
164 | [7] = { .vector = IRQ7_VECTOR, }, | |
165 | [8] = { .vector = IRQ8_VECTOR, }, | |
166 | [9] = { .vector = IRQ9_VECTOR, }, | |
167 | [10] = { .vector = IRQ10_VECTOR, }, | |
168 | [11] = { .vector = IRQ11_VECTOR, }, | |
169 | [12] = { .vector = IRQ12_VECTOR, }, | |
170 | [13] = { .vector = IRQ13_VECTOR, }, | |
171 | [14] = { .vector = IRQ14_VECTOR, }, | |
172 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
173 | }; |
174 | ||
13a0c3c2 | 175 | int __init arch_early_irq_init(void) |
8f09cd20 | 176 | { |
0b8f1efa YL |
177 | struct irq_cfg *cfg; |
178 | struct irq_desc *desc; | |
179 | int count; | |
dad213ae | 180 | int node; |
0b8f1efa | 181 | int i; |
d6c88a50 | 182 | |
0b8f1efa YL |
183 | cfg = irq_cfgx; |
184 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 185 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 186 | |
0b8f1efa YL |
187 | for (i = 0; i < count; i++) { |
188 | desc = irq_to_desc(i); | |
189 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
190 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
191 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
22f65d31 MT |
192 | if (i < NR_IRQS_LEGACY) |
193 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 194 | } |
13a0c3c2 YL |
195 | |
196 | return 0; | |
0b8f1efa | 197 | } |
8f09cd20 | 198 | |
0b8f1efa | 199 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 200 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 201 | { |
0b8f1efa YL |
202 | struct irq_cfg *cfg = NULL; |
203 | struct irq_desc *desc; | |
1da177e4 | 204 | |
0b8f1efa YL |
205 | desc = irq_to_desc(irq); |
206 | if (desc) | |
207 | cfg = desc->chip_data; | |
0f978f45 | 208 | |
0b8f1efa | 209 | return cfg; |
8f09cd20 | 210 | } |
d6c88a50 | 211 | |
85ac16d0 | 212 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 213 | { |
0b8f1efa | 214 | struct irq_cfg *cfg; |
0f978f45 | 215 | |
0b8f1efa | 216 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 217 | if (cfg) { |
80855f73 | 218 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
219 | kfree(cfg); |
220 | cfg = NULL; | |
80855f73 MT |
221 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
222 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
223 | free_cpumask_var(cfg->domain); |
224 | kfree(cfg); | |
225 | cfg = NULL; | |
226 | } else { | |
227 | cpumask_clear(cfg->domain); | |
228 | cpumask_clear(cfg->old_domain); | |
229 | } | |
230 | } | |
0f978f45 | 231 | |
0b8f1efa | 232 | return cfg; |
8f09cd20 YL |
233 | } |
234 | ||
85ac16d0 | 235 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 236 | { |
0b8f1efa | 237 | struct irq_cfg *cfg; |
d6c88a50 | 238 | |
0b8f1efa YL |
239 | cfg = desc->chip_data; |
240 | if (!cfg) { | |
85ac16d0 | 241 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
242 | if (!desc->chip_data) { |
243 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
244 | BUG_ON(1); | |
245 | } | |
246 | } | |
1da177e4 | 247 | |
13a0c3c2 | 248 | return 0; |
0b8f1efa | 249 | } |
0f978f45 | 250 | |
fcef5911 | 251 | /* for move_irq_desc */ |
48a1b10a | 252 | static void |
85ac16d0 | 253 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 254 | { |
48a1b10a YL |
255 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
256 | ||
257 | cfg->irq_2_pin = NULL; | |
258 | old_entry = old_cfg->irq_2_pin; | |
259 | if (!old_entry) | |
260 | return; | |
0f978f45 | 261 | |
85ac16d0 | 262 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
263 | if (!entry) |
264 | return; | |
0f978f45 | 265 | |
48a1b10a YL |
266 | entry->apic = old_entry->apic; |
267 | entry->pin = old_entry->pin; | |
268 | head = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | while (old_entry) { | |
85ac16d0 | 272 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
273 | if (!entry) { |
274 | entry = head; | |
275 | while (entry) { | |
276 | head = entry->next; | |
277 | kfree(entry); | |
278 | entry = head; | |
279 | } | |
280 | /* still use the old one */ | |
281 | return; | |
282 | } | |
283 | entry->apic = old_entry->apic; | |
284 | entry->pin = old_entry->pin; | |
285 | tail->next = entry; | |
286 | tail = entry; | |
287 | old_entry = old_entry->next; | |
288 | } | |
0f978f45 | 289 | |
48a1b10a YL |
290 | tail->next = NULL; |
291 | cfg->irq_2_pin = head; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 295 | { |
48a1b10a | 296 | struct irq_pin_list *entry, *next; |
0f978f45 | 297 | |
48a1b10a YL |
298 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
299 | return; | |
301e6190 | 300 | |
48a1b10a | 301 | entry = old_cfg->irq_2_pin; |
0f978f45 | 302 | |
48a1b10a YL |
303 | while (entry) { |
304 | next = entry->next; | |
305 | kfree(entry); | |
306 | entry = next; | |
307 | } | |
308 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 309 | } |
0f978f45 | 310 | |
48a1b10a | 311 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 312 | struct irq_desc *desc, int node) |
0f978f45 | 313 | { |
48a1b10a YL |
314 | struct irq_cfg *cfg; |
315 | struct irq_cfg *old_cfg; | |
0f978f45 | 316 | |
85ac16d0 | 317 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 318 | |
48a1b10a YL |
319 | if (!cfg) |
320 | return; | |
321 | ||
322 | desc->chip_data = cfg; | |
323 | ||
324 | old_cfg = old_desc->chip_data; | |
325 | ||
326 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
327 | ||
85ac16d0 | 328 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 329 | } |
1da177e4 | 330 | |
48a1b10a YL |
331 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
332 | { | |
333 | kfree(old_cfg); | |
334 | } | |
335 | ||
336 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
337 | { | |
338 | struct irq_cfg *old_cfg, *cfg; | |
339 | ||
340 | old_cfg = old_desc->chip_data; | |
341 | cfg = desc->chip_data; | |
342 | ||
343 | if (old_cfg == cfg) | |
344 | return; | |
345 | ||
346 | if (old_cfg) { | |
347 | free_irq_2_pin(old_cfg, cfg); | |
348 | free_irq_cfg(old_cfg); | |
349 | old_desc->chip_data = NULL; | |
350 | } | |
351 | } | |
fcef5911 | 352 | /* end for move_irq_desc */ |
48a1b10a | 353 | |
0b8f1efa YL |
354 | #else |
355 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
356 | { | |
357 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 358 | } |
1da177e4 | 359 | |
0b8f1efa YL |
360 | #endif |
361 | ||
130fe05d LT |
362 | struct io_apic { |
363 | unsigned int index; | |
364 | unsigned int unused[3]; | |
365 | unsigned int data; | |
0280f7c4 SS |
366 | unsigned int unused2[11]; |
367 | unsigned int eoi; | |
130fe05d LT |
368 | }; |
369 | ||
370 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
371 | { | |
372 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 373 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
374 | } |
375 | ||
0280f7c4 SS |
376 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
377 | { | |
378 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
379 | writel(vector, &io_apic->eoi); | |
380 | } | |
381 | ||
130fe05d LT |
382 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
383 | { | |
384 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
385 | writel(reg, &io_apic->index); | |
386 | return readl(&io_apic->data); | |
387 | } | |
388 | ||
389 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
390 | { | |
391 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
392 | writel(reg, &io_apic->index); | |
393 | writel(value, &io_apic->data); | |
394 | } | |
395 | ||
396 | /* | |
397 | * Re-write a value: to be used for read-modify-write | |
398 | * cycles where the read already set up the index register. | |
399 | * | |
400 | * Older SiS APIC requires we rewrite the index register | |
401 | */ | |
402 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
403 | { | |
54168ed7 | 404 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
405 | |
406 | if (sis_apic_bug) | |
407 | writel(reg, &io_apic->index); | |
130fe05d LT |
408 | writel(value, &io_apic->data); |
409 | } | |
410 | ||
3145e941 | 411 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
412 | { |
413 | struct irq_pin_list *entry; | |
414 | unsigned long flags; | |
047c8fdb YL |
415 | |
416 | spin_lock_irqsave(&ioapic_lock, flags); | |
417 | entry = cfg->irq_2_pin; | |
418 | for (;;) { | |
419 | unsigned int reg; | |
420 | int pin; | |
421 | ||
422 | if (!entry) | |
423 | break; | |
424 | pin = entry->pin; | |
425 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
426 | /* Is the remote IRR bit set? */ | |
427 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
428 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
429 | return true; | |
430 | } | |
431 | if (!entry->next) | |
432 | break; | |
433 | entry = entry->next; | |
434 | } | |
435 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
436 | ||
437 | return false; | |
438 | } | |
047c8fdb | 439 | |
cf4c6a2f AK |
440 | union entry_union { |
441 | struct { u32 w1, w2; }; | |
442 | struct IO_APIC_route_entry entry; | |
443 | }; | |
444 | ||
445 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
446 | { | |
447 | union entry_union eu; | |
448 | unsigned long flags; | |
449 | spin_lock_irqsave(&ioapic_lock, flags); | |
450 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
451 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
452 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
453 | return eu.entry; | |
454 | } | |
455 | ||
f9dadfa7 LT |
456 | /* |
457 | * When we write a new IO APIC routing entry, we need to write the high | |
458 | * word first! If the mask bit in the low word is clear, we will enable | |
459 | * the interrupt, and we need to make sure the entry is fully populated | |
460 | * before that happens. | |
461 | */ | |
d15512f4 AK |
462 | static void |
463 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 464 | { |
50a8d4d2 F |
465 | union entry_union eu = {{0, 0}}; |
466 | ||
cf4c6a2f | 467 | eu.entry = e; |
f9dadfa7 LT |
468 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
469 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
470 | } |
471 | ||
ca97ab90 | 472 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
473 | { |
474 | unsigned long flags; | |
475 | spin_lock_irqsave(&ioapic_lock, flags); | |
476 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
477 | spin_unlock_irqrestore(&ioapic_lock, flags); |
478 | } | |
479 | ||
480 | /* | |
481 | * When we mask an IO APIC routing entry, we need to write the low | |
482 | * word first, in order to set the mask bit before we change the | |
483 | * high bits! | |
484 | */ | |
485 | static void ioapic_mask_entry(int apic, int pin) | |
486 | { | |
487 | unsigned long flags; | |
488 | union entry_union eu = { .entry.mask = 1 }; | |
489 | ||
cf4c6a2f AK |
490 | spin_lock_irqsave(&ioapic_lock, flags); |
491 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
492 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
493 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
494 | } | |
495 | ||
1da177e4 LT |
496 | /* |
497 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
498 | * shared ISA-space IRQs, so we have to support them. We are super | |
499 | * fast in the common case, and fast for shared ISA-space IRQs. | |
500 | */ | |
85ac16d0 | 501 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 502 | { |
0f978f45 YL |
503 | struct irq_pin_list *entry; |
504 | ||
0f978f45 YL |
505 | entry = cfg->irq_2_pin; |
506 | if (!entry) { | |
85ac16d0 | 507 | entry = get_one_free_irq_2_pin(node); |
0b8f1efa YL |
508 | if (!entry) { |
509 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
510 | apic, pin); | |
511 | return; | |
512 | } | |
0f978f45 YL |
513 | cfg->irq_2_pin = entry; |
514 | entry->apic = apic; | |
515 | entry->pin = pin; | |
0f978f45 YL |
516 | return; |
517 | } | |
1da177e4 | 518 | |
0f978f45 YL |
519 | while (entry->next) { |
520 | /* not again, please */ | |
521 | if (entry->apic == apic && entry->pin == pin) | |
522 | return; | |
1da177e4 | 523 | |
0f978f45 | 524 | entry = entry->next; |
1da177e4 | 525 | } |
0f978f45 | 526 | |
85ac16d0 | 527 | entry->next = get_one_free_irq_2_pin(node); |
0f978f45 | 528 | entry = entry->next; |
1da177e4 LT |
529 | entry->apic = apic; |
530 | entry->pin = pin; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Reroute an IRQ to a different pin. | |
535 | */ | |
85ac16d0 | 536 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
1da177e4 LT |
537 | int oldapic, int oldpin, |
538 | int newapic, int newpin) | |
539 | { | |
0f978f45 YL |
540 | struct irq_pin_list *entry = cfg->irq_2_pin; |
541 | int replaced = 0; | |
1da177e4 | 542 | |
0f978f45 | 543 | while (entry) { |
1da177e4 LT |
544 | if (entry->apic == oldapic && entry->pin == oldpin) { |
545 | entry->apic = newapic; | |
546 | entry->pin = newpin; | |
0f978f45 YL |
547 | replaced = 1; |
548 | /* every one is different, right? */ | |
1da177e4 | 549 | break; |
0f978f45 YL |
550 | } |
551 | entry = entry->next; | |
1da177e4 | 552 | } |
0f978f45 YL |
553 | |
554 | /* why? call replace before add? */ | |
555 | if (!replaced) | |
85ac16d0 | 556 | add_pin_to_irq_node(cfg, node, newapic, newpin); |
1da177e4 LT |
557 | } |
558 | ||
3145e941 | 559 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
560 | int mask_and, int mask_or, |
561 | void (*final)(struct irq_pin_list *entry)) | |
562 | { | |
563 | int pin; | |
87783be4 | 564 | struct irq_pin_list *entry; |
047c8fdb | 565 | |
87783be4 CG |
566 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
567 | unsigned int reg; | |
568 | pin = entry->pin; | |
569 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
570 | reg &= mask_and; | |
571 | reg |= mask_or; | |
572 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
573 | if (final) | |
574 | final(entry); | |
575 | } | |
576 | } | |
047c8fdb | 577 | |
3145e941 | 578 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 579 | { |
3145e941 | 580 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 581 | } |
047c8fdb | 582 | |
4e738e2f | 583 | #ifdef CONFIG_X86_64 |
7f3e632f | 584 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 585 | { |
87783be4 CG |
586 | /* |
587 | * Synchronize the IO-APIC and the CPU by doing | |
588 | * a dummy read from the IO-APIC | |
589 | */ | |
590 | struct io_apic __iomem *io_apic; | |
591 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 592 | readl(&io_apic->data); |
1da177e4 LT |
593 | } |
594 | ||
3145e941 | 595 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 596 | { |
3145e941 | 597 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
598 | } |
599 | #else /* CONFIG_X86_32 */ | |
3145e941 | 600 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 601 | { |
3145e941 | 602 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 603 | } |
1da177e4 | 604 | |
3145e941 | 605 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 606 | { |
3145e941 | 607 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
608 | IO_APIC_REDIR_MASKED, NULL); |
609 | } | |
1da177e4 | 610 | |
3145e941 | 611 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 612 | { |
3145e941 | 613 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
614 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
615 | } | |
616 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 617 | |
3145e941 | 618 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 619 | { |
3145e941 | 620 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
621 | unsigned long flags; |
622 | ||
3145e941 YL |
623 | BUG_ON(!cfg); |
624 | ||
1da177e4 | 625 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 626 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
627 | spin_unlock_irqrestore(&ioapic_lock, flags); |
628 | } | |
629 | ||
3145e941 | 630 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 631 | { |
3145e941 | 632 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
633 | unsigned long flags; |
634 | ||
635 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 636 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
637 | spin_unlock_irqrestore(&ioapic_lock, flags); |
638 | } | |
639 | ||
3145e941 YL |
640 | static void mask_IO_APIC_irq(unsigned int irq) |
641 | { | |
642 | struct irq_desc *desc = irq_to_desc(irq); | |
643 | ||
644 | mask_IO_APIC_irq_desc(desc); | |
645 | } | |
646 | static void unmask_IO_APIC_irq(unsigned int irq) | |
647 | { | |
648 | struct irq_desc *desc = irq_to_desc(irq); | |
649 | ||
650 | unmask_IO_APIC_irq_desc(desc); | |
651 | } | |
652 | ||
1da177e4 LT |
653 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
654 | { | |
655 | struct IO_APIC_route_entry entry; | |
36062448 | 656 | |
1da177e4 | 657 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 658 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
659 | if (entry.delivery_mode == dest_SMI) |
660 | return; | |
1da177e4 LT |
661 | /* |
662 | * Disable it in the IO-APIC irq-routing table: | |
663 | */ | |
f9dadfa7 | 664 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
665 | } |
666 | ||
54168ed7 | 667 | static void clear_IO_APIC (void) |
1da177e4 LT |
668 | { |
669 | int apic, pin; | |
670 | ||
671 | for (apic = 0; apic < nr_ioapics; apic++) | |
672 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
673 | clear_IO_APIC_pin(apic, pin); | |
674 | } | |
675 | ||
54168ed7 | 676 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
677 | /* |
678 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
679 | * specific CPU-side IRQs. | |
680 | */ | |
681 | ||
682 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
683 | static int pirq_entries[MAX_PIRQS] = { |
684 | [0 ... MAX_PIRQS - 1] = -1 | |
685 | }; | |
1da177e4 | 686 | |
1da177e4 LT |
687 | static int __init ioapic_pirq_setup(char *str) |
688 | { | |
689 | int i, max; | |
690 | int ints[MAX_PIRQS+1]; | |
691 | ||
692 | get_options(str, ARRAY_SIZE(ints), ints); | |
693 | ||
1da177e4 LT |
694 | apic_printk(APIC_VERBOSE, KERN_INFO |
695 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
696 | max = MAX_PIRQS; | |
697 | if (ints[0] < MAX_PIRQS) | |
698 | max = ints[0]; | |
699 | ||
700 | for (i = 0; i < max; i++) { | |
701 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
702 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
703 | /* | |
704 | * PIRQs are mapped upside down, usually. | |
705 | */ | |
706 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
707 | } | |
708 | return 1; | |
709 | } | |
710 | ||
711 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
712 | #endif /* CONFIG_X86_32 */ |
713 | ||
b24696bc FY |
714 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
715 | { | |
716 | int apic; | |
717 | struct IO_APIC_route_entry **ioapic_entries; | |
718 | ||
719 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
720 | GFP_ATOMIC); | |
721 | if (!ioapic_entries) | |
722 | return 0; | |
723 | ||
724 | for (apic = 0; apic < nr_ioapics; apic++) { | |
725 | ioapic_entries[apic] = | |
726 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
727 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
728 | if (!ioapic_entries[apic]) | |
729 | goto nomem; | |
730 | } | |
731 | ||
732 | return ioapic_entries; | |
733 | ||
734 | nomem: | |
735 | while (--apic >= 0) | |
736 | kfree(ioapic_entries[apic]); | |
737 | kfree(ioapic_entries); | |
738 | ||
739 | return 0; | |
740 | } | |
54168ed7 IM |
741 | |
742 | /* | |
05c3dc2c | 743 | * Saves all the IO-APIC RTE's |
54168ed7 | 744 | */ |
b24696bc | 745 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 746 | { |
54168ed7 IM |
747 | int apic, pin; |
748 | ||
b24696bc FY |
749 | if (!ioapic_entries) |
750 | return -ENOMEM; | |
54168ed7 IM |
751 | |
752 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
753 | if (!ioapic_entries[apic]) |
754 | return -ENOMEM; | |
54168ed7 | 755 | |
05c3dc2c | 756 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 757 | ioapic_entries[apic][pin] = |
54168ed7 | 758 | ioapic_read_entry(apic, pin); |
b24696bc | 759 | } |
5ffa4eb2 | 760 | |
54168ed7 IM |
761 | return 0; |
762 | } | |
763 | ||
b24696bc FY |
764 | /* |
765 | * Mask all IO APIC entries. | |
766 | */ | |
767 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
768 | { |
769 | int apic, pin; | |
770 | ||
b24696bc FY |
771 | if (!ioapic_entries) |
772 | return; | |
773 | ||
05c3dc2c | 774 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 775 | if (!ioapic_entries[apic]) |
05c3dc2c | 776 | break; |
b24696bc | 777 | |
05c3dc2c SS |
778 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
779 | struct IO_APIC_route_entry entry; | |
780 | ||
b24696bc | 781 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
782 | if (!entry.mask) { |
783 | entry.mask = 1; | |
784 | ioapic_write_entry(apic, pin, entry); | |
785 | } | |
786 | } | |
787 | } | |
788 | } | |
789 | ||
b24696bc FY |
790 | /* |
791 | * Restore IO APIC entries which was saved in ioapic_entries. | |
792 | */ | |
793 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
794 | { |
795 | int apic, pin; | |
796 | ||
b24696bc FY |
797 | if (!ioapic_entries) |
798 | return -ENOMEM; | |
799 | ||
5ffa4eb2 | 800 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
801 | if (!ioapic_entries[apic]) |
802 | return -ENOMEM; | |
803 | ||
54168ed7 IM |
804 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
805 | ioapic_write_entry(apic, pin, | |
b24696bc | 806 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 807 | } |
b24696bc | 808 | return 0; |
54168ed7 IM |
809 | } |
810 | ||
b24696bc FY |
811 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
812 | { | |
813 | int apic; | |
814 | ||
815 | for (apic = 0; apic < nr_ioapics; apic++) | |
816 | kfree(ioapic_entries[apic]); | |
817 | ||
818 | kfree(ioapic_entries); | |
54168ed7 | 819 | } |
1da177e4 LT |
820 | |
821 | /* | |
822 | * Find the IRQ entry number of a certain pin. | |
823 | */ | |
824 | static int find_irq_entry(int apic, int pin, int type) | |
825 | { | |
826 | int i; | |
827 | ||
828 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
829 | if (mp_irqs[i].irqtype == type && |
830 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
831 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
832 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
833 | return i; |
834 | ||
835 | return -1; | |
836 | } | |
837 | ||
838 | /* | |
839 | * Find the pin to which IRQ[irq] (ISA) is connected | |
840 | */ | |
fcfd636a | 841 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
842 | { |
843 | int i; | |
844 | ||
845 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 846 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 847 | |
d27e2b8e | 848 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
849 | (mp_irqs[i].irqtype == type) && |
850 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 851 | |
c2c21745 | 852 | return mp_irqs[i].dstirq; |
1da177e4 LT |
853 | } |
854 | return -1; | |
855 | } | |
856 | ||
fcfd636a EB |
857 | static int __init find_isa_irq_apic(int irq, int type) |
858 | { | |
859 | int i; | |
860 | ||
861 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 862 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 863 | |
73b2961b | 864 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
865 | (mp_irqs[i].irqtype == type) && |
866 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
867 | break; |
868 | } | |
869 | if (i < mp_irq_entries) { | |
870 | int apic; | |
54168ed7 | 871 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 872 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
873 | return apic; |
874 | } | |
875 | } | |
876 | ||
877 | return -1; | |
878 | } | |
879 | ||
c0a282c2 | 880 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
881 | /* |
882 | * EISA Edge/Level control register, ELCR | |
883 | */ | |
884 | static int EISA_ELCR(unsigned int irq) | |
885 | { | |
99d093d1 | 886 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
887 | unsigned int port = 0x4d0 + (irq >> 3); |
888 | return (inb(port) >> (irq & 7)) & 1; | |
889 | } | |
890 | apic_printk(APIC_VERBOSE, KERN_INFO | |
891 | "Broken MPtable reports ISA irq %d\n", irq); | |
892 | return 0; | |
893 | } | |
54168ed7 | 894 | |
c0a282c2 | 895 | #endif |
1da177e4 | 896 | |
6728801d AS |
897 | /* ISA interrupts are always polarity zero edge triggered, |
898 | * when listed as conforming in the MP table. */ | |
899 | ||
900 | #define default_ISA_trigger(idx) (0) | |
901 | #define default_ISA_polarity(idx) (0) | |
902 | ||
1da177e4 LT |
903 | /* EISA interrupts are always polarity zero and can be edge or level |
904 | * trigger depending on the ELCR value. If an interrupt is listed as | |
905 | * EISA conforming in the MP table, that means its trigger type must | |
906 | * be read in from the ELCR */ | |
907 | ||
c2c21745 | 908 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 909 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
910 | |
911 | /* PCI interrupts are always polarity one level triggered, | |
912 | * when listed as conforming in the MP table. */ | |
913 | ||
914 | #define default_PCI_trigger(idx) (1) | |
915 | #define default_PCI_polarity(idx) (1) | |
916 | ||
917 | /* MCA interrupts are always polarity zero level triggered, | |
918 | * when listed as conforming in the MP table. */ | |
919 | ||
920 | #define default_MCA_trigger(idx) (1) | |
6728801d | 921 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 922 | |
61fd47e0 | 923 | static int MPBIOS_polarity(int idx) |
1da177e4 | 924 | { |
c2c21745 | 925 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
926 | int polarity; |
927 | ||
928 | /* | |
929 | * Determine IRQ line polarity (high active or low active): | |
930 | */ | |
c2c21745 | 931 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 932 | { |
54168ed7 IM |
933 | case 0: /* conforms, ie. bus-type dependent polarity */ |
934 | if (test_bit(bus, mp_bus_not_pci)) | |
935 | polarity = default_ISA_polarity(idx); | |
936 | else | |
937 | polarity = default_PCI_polarity(idx); | |
938 | break; | |
939 | case 1: /* high active */ | |
940 | { | |
941 | polarity = 0; | |
942 | break; | |
943 | } | |
944 | case 2: /* reserved */ | |
945 | { | |
946 | printk(KERN_WARNING "broken BIOS!!\n"); | |
947 | polarity = 1; | |
948 | break; | |
949 | } | |
950 | case 3: /* low active */ | |
951 | { | |
952 | polarity = 1; | |
953 | break; | |
954 | } | |
955 | default: /* invalid */ | |
956 | { | |
957 | printk(KERN_WARNING "broken BIOS!!\n"); | |
958 | polarity = 1; | |
959 | break; | |
960 | } | |
1da177e4 LT |
961 | } |
962 | return polarity; | |
963 | } | |
964 | ||
965 | static int MPBIOS_trigger(int idx) | |
966 | { | |
c2c21745 | 967 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
968 | int trigger; |
969 | ||
970 | /* | |
971 | * Determine IRQ trigger mode (edge or level sensitive): | |
972 | */ | |
c2c21745 | 973 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 974 | { |
54168ed7 IM |
975 | case 0: /* conforms, ie. bus-type dependent */ |
976 | if (test_bit(bus, mp_bus_not_pci)) | |
977 | trigger = default_ISA_trigger(idx); | |
978 | else | |
979 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 980 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
981 | switch (mp_bus_id_to_type[bus]) { |
982 | case MP_BUS_ISA: /* ISA pin */ | |
983 | { | |
984 | /* set before the switch */ | |
985 | break; | |
986 | } | |
987 | case MP_BUS_EISA: /* EISA pin */ | |
988 | { | |
989 | trigger = default_EISA_trigger(idx); | |
990 | break; | |
991 | } | |
992 | case MP_BUS_PCI: /* PCI pin */ | |
993 | { | |
994 | /* set before the switch */ | |
995 | break; | |
996 | } | |
997 | case MP_BUS_MCA: /* MCA pin */ | |
998 | { | |
999 | trigger = default_MCA_trigger(idx); | |
1000 | break; | |
1001 | } | |
1002 | default: | |
1003 | { | |
1004 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1005 | trigger = 1; | |
1006 | break; | |
1007 | } | |
1008 | } | |
1009 | #endif | |
1da177e4 | 1010 | break; |
54168ed7 | 1011 | case 1: /* edge */ |
1da177e4 | 1012 | { |
54168ed7 | 1013 | trigger = 0; |
1da177e4 LT |
1014 | break; |
1015 | } | |
54168ed7 | 1016 | case 2: /* reserved */ |
1da177e4 | 1017 | { |
54168ed7 IM |
1018 | printk(KERN_WARNING "broken BIOS!!\n"); |
1019 | trigger = 1; | |
1da177e4 LT |
1020 | break; |
1021 | } | |
54168ed7 | 1022 | case 3: /* level */ |
1da177e4 | 1023 | { |
54168ed7 | 1024 | trigger = 1; |
1da177e4 LT |
1025 | break; |
1026 | } | |
54168ed7 | 1027 | default: /* invalid */ |
1da177e4 LT |
1028 | { |
1029 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1030 | trigger = 0; |
1da177e4 LT |
1031 | break; |
1032 | } | |
1033 | } | |
1034 | return trigger; | |
1035 | } | |
1036 | ||
1037 | static inline int irq_polarity(int idx) | |
1038 | { | |
1039 | return MPBIOS_polarity(idx); | |
1040 | } | |
1041 | ||
1042 | static inline int irq_trigger(int idx) | |
1043 | { | |
1044 | return MPBIOS_trigger(idx); | |
1045 | } | |
1046 | ||
efa2559f | 1047 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1048 | static int pin_2_irq(int idx, int apic, int pin) |
1049 | { | |
1050 | int irq, i; | |
c2c21745 | 1051 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1052 | |
1053 | /* | |
1054 | * Debugging check, we are in big trouble if this message pops up! | |
1055 | */ | |
c2c21745 | 1056 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1057 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1058 | ||
54168ed7 | 1059 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1060 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1061 | } else { |
643befed AS |
1062 | /* |
1063 | * PCI IRQs are mapped in order | |
1064 | */ | |
1065 | i = irq = 0; | |
1066 | while (i < apic) | |
1067 | irq += nr_ioapic_registers[i++]; | |
1068 | irq += pin; | |
d6c88a50 | 1069 | /* |
54168ed7 IM |
1070 | * For MPS mode, so far only needed by ES7000 platform |
1071 | */ | |
d6c88a50 TG |
1072 | if (ioapic_renumber_irq) |
1073 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1074 | } |
1075 | ||
54168ed7 | 1076 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1077 | /* |
1078 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1079 | */ | |
1080 | if ((pin >= 16) && (pin <= 23)) { | |
1081 | if (pirq_entries[pin-16] != -1) { | |
1082 | if (!pirq_entries[pin-16]) { | |
1083 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1084 | "disabling PIRQ%d\n", pin-16); | |
1085 | } else { | |
1086 | irq = pirq_entries[pin-16]; | |
1087 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1088 | "using PIRQ%d -> IRQ %d\n", | |
1089 | pin-16, irq); | |
1090 | } | |
1091 | } | |
1092 | } | |
54168ed7 IM |
1093 | #endif |
1094 | ||
1da177e4 LT |
1095 | return irq; |
1096 | } | |
1097 | ||
e20c06fd YL |
1098 | /* |
1099 | * Find a specific PCI IRQ entry. | |
1100 | * Not an __init, possibly needed by modules | |
1101 | */ | |
1102 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1103 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1104 | { |
1105 | int apic, i, best_guess = -1; | |
1106 | ||
1107 | apic_printk(APIC_DEBUG, | |
1108 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1109 | bus, slot, pin); | |
1110 | if (test_bit(bus, mp_bus_not_pci)) { | |
1111 | apic_printk(APIC_VERBOSE, | |
1112 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1113 | return -1; | |
1114 | } | |
1115 | for (i = 0; i < mp_irq_entries; i++) { | |
1116 | int lbus = mp_irqs[i].srcbus; | |
1117 | ||
1118 | for (apic = 0; apic < nr_ioapics; apic++) | |
1119 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1120 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1121 | break; | |
1122 | ||
1123 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1124 | !mp_irqs[i].irqtype && | |
1125 | (bus == lbus) && | |
1126 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1127 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1128 | ||
1129 | if (!(apic || IO_APIC_IRQ(irq))) | |
1130 | continue; | |
1131 | ||
1132 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1133 | set_io_apic_irq_attr(irq_attr, apic, |
1134 | mp_irqs[i].dstirq, | |
1135 | irq_trigger(i), | |
1136 | irq_polarity(i)); | |
e20c06fd YL |
1137 | return irq; |
1138 | } | |
1139 | /* | |
1140 | * Use the first all-but-pin matching entry as a | |
1141 | * best-guess fuzzy result for broken mptables. | |
1142 | */ | |
1143 | if (best_guess < 0) { | |
e5198075 YL |
1144 | set_io_apic_irq_attr(irq_attr, apic, |
1145 | mp_irqs[i].dstirq, | |
1146 | irq_trigger(i), | |
1147 | irq_polarity(i)); | |
e20c06fd YL |
1148 | best_guess = irq; |
1149 | } | |
1150 | } | |
1151 | } | |
1152 | return best_guess; | |
1153 | } | |
1154 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1155 | ||
497c9a19 YL |
1156 | void lock_vector_lock(void) |
1157 | { | |
1158 | /* Used to the online set of cpus does not change | |
1159 | * during assign_irq_vector. | |
1160 | */ | |
1161 | spin_lock(&vector_lock); | |
1162 | } | |
1da177e4 | 1163 | |
497c9a19 | 1164 | void unlock_vector_lock(void) |
1da177e4 | 1165 | { |
497c9a19 YL |
1166 | spin_unlock(&vector_lock); |
1167 | } | |
1da177e4 | 1168 | |
e7986739 MT |
1169 | static int |
1170 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1171 | { |
047c8fdb YL |
1172 | /* |
1173 | * NOTE! The local APIC isn't very good at handling | |
1174 | * multiple interrupts at the same interrupt level. | |
1175 | * As the interrupt level is determined by taking the | |
1176 | * vector number and shifting that right by 4, we | |
1177 | * want to spread these out a bit so that they don't | |
1178 | * all fall in the same interrupt level. | |
1179 | * | |
1180 | * Also, we've got to be careful not to trash gate | |
1181 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1182 | */ | |
54168ed7 IM |
1183 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1184 | unsigned int old_vector; | |
22f65d31 MT |
1185 | int cpu, err; |
1186 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1187 | |
54168ed7 IM |
1188 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1189 | return -EBUSY; | |
0a1ad60d | 1190 | |
22f65d31 MT |
1191 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1192 | return -ENOMEM; | |
ace80ab7 | 1193 | |
54168ed7 IM |
1194 | old_vector = cfg->vector; |
1195 | if (old_vector) { | |
22f65d31 MT |
1196 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1197 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1198 | if (!cpumask_empty(tmp_mask)) { | |
1199 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1200 | return 0; |
22f65d31 | 1201 | } |
54168ed7 | 1202 | } |
497c9a19 | 1203 | |
e7986739 | 1204 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1205 | err = -ENOSPC; |
1206 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1207 | int new_cpu; |
1208 | int vector, offset; | |
497c9a19 | 1209 | |
e2d40b18 | 1210 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1211 | |
54168ed7 IM |
1212 | vector = current_vector; |
1213 | offset = current_offset; | |
497c9a19 | 1214 | next: |
54168ed7 IM |
1215 | vector += 8; |
1216 | if (vector >= first_system_vector) { | |
e7986739 | 1217 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1218 | offset = (offset + 1) % 8; |
1219 | vector = FIRST_DEVICE_VECTOR + offset; | |
1220 | } | |
1221 | if (unlikely(current_vector == vector)) | |
1222 | continue; | |
b77b881f YL |
1223 | |
1224 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1225 | goto next; |
b77b881f | 1226 | |
22f65d31 | 1227 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1228 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1229 | goto next; | |
1230 | /* Found one! */ | |
1231 | current_vector = vector; | |
1232 | current_offset = offset; | |
1233 | if (old_vector) { | |
1234 | cfg->move_in_progress = 1; | |
22f65d31 | 1235 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1236 | } |
22f65d31 | 1237 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1238 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1239 | cfg->vector = vector; | |
22f65d31 MT |
1240 | cpumask_copy(cfg->domain, tmp_mask); |
1241 | err = 0; | |
1242 | break; | |
54168ed7 | 1243 | } |
22f65d31 MT |
1244 | free_cpumask_var(tmp_mask); |
1245 | return err; | |
497c9a19 YL |
1246 | } |
1247 | ||
e7986739 MT |
1248 | static int |
1249 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1250 | { |
1251 | int err; | |
ace80ab7 | 1252 | unsigned long flags; |
ace80ab7 EB |
1253 | |
1254 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1255 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1256 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1257 | return err; |
1258 | } | |
1259 | ||
3145e941 | 1260 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1261 | { |
497c9a19 YL |
1262 | int cpu, vector; |
1263 | ||
497c9a19 YL |
1264 | BUG_ON(!cfg->vector); |
1265 | ||
1266 | vector = cfg->vector; | |
22f65d31 | 1267 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1268 | per_cpu(vector_irq, cpu)[vector] = -1; |
1269 | ||
1270 | cfg->vector = 0; | |
22f65d31 | 1271 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1272 | |
1273 | if (likely(!cfg->move_in_progress)) | |
1274 | return; | |
22f65d31 | 1275 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1276 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1277 | vector++) { | |
1278 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1279 | continue; | |
1280 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1281 | break; | |
1282 | } | |
1283 | } | |
1284 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1285 | } |
1286 | ||
1287 | void __setup_vector_irq(int cpu) | |
1288 | { | |
1289 | /* Initialize vector_irq on a new cpu */ | |
1290 | /* This function must be called with vector_lock held */ | |
1291 | int irq, vector; | |
1292 | struct irq_cfg *cfg; | |
0b8f1efa | 1293 | struct irq_desc *desc; |
497c9a19 YL |
1294 | |
1295 | /* Mark the inuse vectors */ | |
0b8f1efa | 1296 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1297 | cfg = desc->chip_data; |
22f65d31 | 1298 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1299 | continue; |
1300 | vector = cfg->vector; | |
497c9a19 YL |
1301 | per_cpu(vector_irq, cpu)[vector] = irq; |
1302 | } | |
1303 | /* Mark the free vectors */ | |
1304 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1305 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1306 | if (irq < 0) | |
1307 | continue; | |
1308 | ||
1309 | cfg = irq_cfg(irq); | |
22f65d31 | 1310 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1311 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1312 | } |
1da177e4 | 1313 | } |
3fde6900 | 1314 | |
f5b9ed7a | 1315 | static struct irq_chip ioapic_chip; |
54168ed7 | 1316 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1317 | |
54168ed7 IM |
1318 | #define IOAPIC_AUTO -1 |
1319 | #define IOAPIC_EDGE 0 | |
1320 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1321 | |
047c8fdb | 1322 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1323 | static inline int IO_APIC_irq_trigger(int irq) |
1324 | { | |
d6c88a50 | 1325 | int apic, idx, pin; |
1d025192 | 1326 | |
d6c88a50 TG |
1327 | for (apic = 0; apic < nr_ioapics; apic++) { |
1328 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1329 | idx = find_irq_entry(apic, pin, mp_INT); | |
1330 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1331 | return irq_trigger(idx); | |
1332 | } | |
1333 | } | |
1334 | /* | |
54168ed7 IM |
1335 | * nonexistent IRQs are edge default |
1336 | */ | |
d6c88a50 | 1337 | return 0; |
1d025192 | 1338 | } |
047c8fdb YL |
1339 | #else |
1340 | static inline int IO_APIC_irq_trigger(int irq) | |
1341 | { | |
54168ed7 | 1342 | return 1; |
047c8fdb YL |
1343 | } |
1344 | #endif | |
1d025192 | 1345 | |
3145e941 | 1346 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1347 | { |
199751d7 | 1348 | |
6ebcc00e | 1349 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1350 | trigger == IOAPIC_LEVEL) |
08678b08 | 1351 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1352 | else |
1353 | desc->status &= ~IRQ_LEVEL; | |
1354 | ||
54168ed7 IM |
1355 | if (irq_remapped(irq)) { |
1356 | desc->status |= IRQ_MOVE_PCNTXT; | |
1357 | if (trigger) | |
1358 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1359 | handle_fasteoi_irq, | |
1360 | "fasteoi"); | |
1361 | else | |
1362 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1363 | handle_edge_irq, "edge"); | |
1364 | return; | |
1365 | } | |
29b61be6 | 1366 | |
047c8fdb YL |
1367 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1368 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1369 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1370 | handle_fasteoi_irq, |
1371 | "fasteoi"); | |
047c8fdb | 1372 | else |
a460e745 | 1373 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1374 | handle_edge_irq, "edge"); |
1da177e4 LT |
1375 | } |
1376 | ||
ca97ab90 JF |
1377 | int setup_ioapic_entry(int apic_id, int irq, |
1378 | struct IO_APIC_route_entry *entry, | |
1379 | unsigned int destination, int trigger, | |
0280f7c4 | 1380 | int polarity, int vector, int pin) |
1da177e4 | 1381 | { |
497c9a19 YL |
1382 | /* |
1383 | * add it to the IO-APIC irq-routing table: | |
1384 | */ | |
1385 | memset(entry,0,sizeof(*entry)); | |
1386 | ||
54168ed7 | 1387 | if (intr_remapping_enabled) { |
c8d46cf0 | 1388 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1389 | struct irte irte; |
1390 | struct IR_IO_APIC_route_entry *ir_entry = | |
1391 | (struct IR_IO_APIC_route_entry *) entry; | |
1392 | int index; | |
1393 | ||
1394 | if (!iommu) | |
c8d46cf0 | 1395 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1396 | |
1397 | index = alloc_irte(iommu, irq, 1); | |
1398 | if (index < 0) | |
c8d46cf0 | 1399 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1400 | |
1401 | memset(&irte, 0, sizeof(irte)); | |
1402 | ||
1403 | irte.present = 1; | |
9b5bc8dc | 1404 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1405 | /* |
1406 | * Trigger mode in the IRTE will always be edge, and the | |
1407 | * actual level or edge trigger will be setup in the IO-APIC | |
1408 | * RTE. This will help simplify level triggered irq migration. | |
1409 | * For more details, see the comments above explainig IO-APIC | |
1410 | * irq migration in the presence of interrupt-remapping. | |
1411 | */ | |
1412 | irte.trigger_mode = 0; | |
9b5bc8dc | 1413 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1414 | irte.vector = vector; |
1415 | irte.dest_id = IRTE_DEST(destination); | |
1416 | ||
1417 | modify_irte(irq, &irte); | |
1418 | ||
1419 | ir_entry->index2 = (index >> 15) & 0x1; | |
1420 | ir_entry->zero = 0; | |
1421 | ir_entry->format = 1; | |
1422 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1423 | /* |
1424 | * IO-APIC RTE will be configured with virtual vector. | |
1425 | * irq handler will do the explicit EOI to the io-apic. | |
1426 | */ | |
1427 | ir_entry->vector = pin; | |
29b61be6 | 1428 | } else { |
9b5bc8dc IM |
1429 | entry->delivery_mode = apic->irq_delivery_mode; |
1430 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1431 | entry->dest = destination; |
0280f7c4 | 1432 | entry->vector = vector; |
54168ed7 | 1433 | } |
497c9a19 | 1434 | |
54168ed7 | 1435 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1436 | entry->trigger = trigger; |
1437 | entry->polarity = polarity; | |
497c9a19 YL |
1438 | |
1439 | /* Mask level triggered irqs. | |
1440 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1441 | */ | |
1442 | if (trigger) | |
1443 | entry->mask = 1; | |
497c9a19 YL |
1444 | return 0; |
1445 | } | |
1446 | ||
c8d46cf0 | 1447 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1448 | int trigger, int polarity) |
497c9a19 YL |
1449 | { |
1450 | struct irq_cfg *cfg; | |
1da177e4 | 1451 | struct IO_APIC_route_entry entry; |
22f65d31 | 1452 | unsigned int dest; |
497c9a19 YL |
1453 | |
1454 | if (!IO_APIC_IRQ(irq)) | |
1455 | return; | |
1456 | ||
3145e941 | 1457 | cfg = desc->chip_data; |
497c9a19 | 1458 | |
fe402e1f | 1459 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1460 | return; |
1461 | ||
debccb3e | 1462 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1463 | |
1464 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1465 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1466 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1467 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1468 | irq, trigger, polarity); |
1469 | ||
1470 | ||
c8d46cf0 | 1471 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1472 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1473 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1474 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1475 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1476 | return; |
1477 | } | |
1478 | ||
3145e941 | 1479 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1480 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1481 | disable_8259A_irq(irq); |
1482 | ||
c8d46cf0 | 1483 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1484 | } |
1485 | ||
b9c61b70 YL |
1486 | static struct { |
1487 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1488 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1489 | ||
497c9a19 YL |
1490 | static void __init setup_IO_APIC_irqs(void) |
1491 | { | |
b9c61b70 | 1492 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1493 | int notcon = 0; |
0b8f1efa | 1494 | struct irq_desc *desc; |
3145e941 | 1495 | struct irq_cfg *cfg; |
85ac16d0 | 1496 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1497 | |
1498 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1499 | ||
b9c61b70 YL |
1500 | #ifdef CONFIG_ACPI |
1501 | if (!acpi_disabled && acpi_ioapic) { | |
1502 | apic_id = mp_find_ioapic(0); | |
1503 | if (apic_id < 0) | |
1504 | apic_id = 0; | |
1505 | } | |
1506 | #endif | |
3c2cbd24 | 1507 | |
b9c61b70 YL |
1508 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1509 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1510 | if (idx == -1) { | |
1511 | if (!notcon) { | |
1512 | notcon = 1; | |
1513 | apic_printk(APIC_VERBOSE, | |
1514 | KERN_DEBUG " %d-%d", | |
1515 | mp_ioapics[apic_id].apicid, pin); | |
1516 | } else | |
1517 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1518 | mp_ioapics[apic_id].apicid, pin); | |
1519 | continue; | |
1520 | } | |
1521 | if (notcon) { | |
1522 | apic_printk(APIC_VERBOSE, | |
1523 | " (apicid-pin) not connected\n"); | |
1524 | notcon = 0; | |
1525 | } | |
33a201fa | 1526 | |
b9c61b70 | 1527 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1528 | |
b9c61b70 YL |
1529 | /* |
1530 | * Skip the timer IRQ if there's a quirk handler | |
1531 | * installed and if it returns 1: | |
1532 | */ | |
1533 | if (apic->multi_timer_check && | |
1534 | apic->multi_timer_check(apic_id, irq)) | |
1535 | continue; | |
36062448 | 1536 | |
b9c61b70 YL |
1537 | desc = irq_to_desc_alloc_node(irq, node); |
1538 | if (!desc) { | |
1539 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1540 | continue; | |
3c2cbd24 | 1541 | } |
b9c61b70 YL |
1542 | cfg = desc->chip_data; |
1543 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1544 | /* |
1545 | * don't mark it in pin_programmed, so later acpi could | |
1546 | * set it correctly when irq < 16 | |
1547 | */ | |
b9c61b70 YL |
1548 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1549 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1550 | } |
1551 | ||
3c2cbd24 CG |
1552 | if (notcon) |
1553 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1554 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1555 | } |
1556 | ||
1557 | /* | |
f7633ce5 | 1558 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1559 | */ |
c8d46cf0 | 1560 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1561 | int vector) |
1da177e4 LT |
1562 | { |
1563 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1564 | |
54168ed7 IM |
1565 | if (intr_remapping_enabled) |
1566 | return; | |
54168ed7 | 1567 | |
36062448 | 1568 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1569 | |
1570 | /* | |
1571 | * We use logical delivery to get the timer IRQ | |
1572 | * to the first CPU. | |
1573 | */ | |
9b5bc8dc | 1574 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1575 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1576 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1577 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1578 | entry.polarity = 0; |
1579 | entry.trigger = 0; | |
1580 | entry.vector = vector; | |
1581 | ||
1582 | /* | |
1583 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1584 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1585 | */ |
54168ed7 | 1586 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1587 | |
1588 | /* | |
1589 | * Add it to the IO-APIC irq-routing table: | |
1590 | */ | |
c8d46cf0 | 1591 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1592 | } |
1593 | ||
32f71aff MR |
1594 | |
1595 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1596 | { |
1597 | int apic, i; | |
1598 | union IO_APIC_reg_00 reg_00; | |
1599 | union IO_APIC_reg_01 reg_01; | |
1600 | union IO_APIC_reg_02 reg_02; | |
1601 | union IO_APIC_reg_03 reg_03; | |
1602 | unsigned long flags; | |
0f978f45 | 1603 | struct irq_cfg *cfg; |
0b8f1efa | 1604 | struct irq_desc *desc; |
8f09cd20 | 1605 | unsigned int irq; |
1da177e4 LT |
1606 | |
1607 | if (apic_verbosity == APIC_QUIET) | |
1608 | return; | |
1609 | ||
36062448 | 1610 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1611 | for (i = 0; i < nr_ioapics; i++) |
1612 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1613 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1614 | |
1615 | /* | |
1616 | * We are a bit conservative about what we expect. We have to | |
1617 | * know about every hardware change ASAP. | |
1618 | */ | |
1619 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1620 | ||
1621 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1622 | ||
1623 | spin_lock_irqsave(&ioapic_lock, flags); | |
1624 | reg_00.raw = io_apic_read(apic, 0); | |
1625 | reg_01.raw = io_apic_read(apic, 1); | |
1626 | if (reg_01.bits.version >= 0x10) | |
1627 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1628 | if (reg_01.bits.version >= 0x20) |
1629 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1630 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1631 | ||
54168ed7 | 1632 | printk("\n"); |
b5ba7e6d | 1633 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1634 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1635 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1636 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1637 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1638 | |
54168ed7 | 1639 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1640 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1641 | |
1642 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1643 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1644 | |
1645 | /* | |
1646 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1647 | * but the value of reg_02 is read as the previous read register | |
1648 | * value, so ignore it if reg_02 == reg_01. | |
1649 | */ | |
1650 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1651 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1652 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1653 | } |
1654 | ||
1655 | /* | |
1656 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1657 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1658 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1659 | */ | |
1660 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1661 | reg_03.raw != reg_01.raw) { | |
1662 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1663 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1664 | } |
1665 | ||
1666 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1667 | ||
d83e94ac YL |
1668 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1669 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1670 | |
1671 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1672 | struct IO_APIC_route_entry entry; | |
1673 | ||
cf4c6a2f | 1674 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1675 | |
54168ed7 IM |
1676 | printk(KERN_DEBUG " %02x %03X ", |
1677 | i, | |
1678 | entry.dest | |
1679 | ); | |
1da177e4 LT |
1680 | |
1681 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1682 | entry.mask, | |
1683 | entry.trigger, | |
1684 | entry.irr, | |
1685 | entry.polarity, | |
1686 | entry.delivery_status, | |
1687 | entry.dest_mode, | |
1688 | entry.delivery_mode, | |
1689 | entry.vector | |
1690 | ); | |
1691 | } | |
1692 | } | |
1da177e4 | 1693 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1694 | for_each_irq_desc(irq, desc) { |
1695 | struct irq_pin_list *entry; | |
1696 | ||
0b8f1efa YL |
1697 | cfg = desc->chip_data; |
1698 | entry = cfg->irq_2_pin; | |
0f978f45 | 1699 | if (!entry) |
1da177e4 | 1700 | continue; |
8f09cd20 | 1701 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1702 | for (;;) { |
1703 | printk("-> %d:%d", entry->apic, entry->pin); | |
1704 | if (!entry->next) | |
1705 | break; | |
0f978f45 | 1706 | entry = entry->next; |
1da177e4 LT |
1707 | } |
1708 | printk("\n"); | |
1709 | } | |
1710 | ||
1711 | printk(KERN_INFO ".................................... done.\n"); | |
1712 | ||
1713 | return; | |
1714 | } | |
1715 | ||
32f71aff | 1716 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1717 | { |
1718 | unsigned int v; | |
1719 | int i, j; | |
1720 | ||
1721 | if (apic_verbosity == APIC_QUIET) | |
1722 | return; | |
1723 | ||
1724 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1725 | for (i = 0; i < 8; i++) { | |
1726 | v = apic_read(base + i*0x10); | |
1727 | for (j = 0; j < 32; j++) { | |
1728 | if (v & (1<<j)) | |
1729 | printk("1"); | |
1730 | else | |
1731 | printk("0"); | |
1732 | } | |
1733 | printk("\n"); | |
1734 | } | |
1735 | } | |
1736 | ||
32f71aff | 1737 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1738 | { |
97a52714 | 1739 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1740 | u64 icr; |
1da177e4 LT |
1741 | |
1742 | if (apic_verbosity == APIC_QUIET) | |
1743 | return; | |
1744 | ||
1745 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1746 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1747 | v = apic_read(APIC_ID); |
54168ed7 | 1748 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1749 | v = apic_read(APIC_LVR); |
1750 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1751 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1752 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1753 | |
1754 | v = apic_read(APIC_TASKPRI); | |
1755 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1756 | ||
54168ed7 | 1757 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1758 | if (!APIC_XAPIC(ver)) { |
1759 | v = apic_read(APIC_ARBPRI); | |
1760 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1761 | v & APIC_ARBPRI_MASK); | |
1762 | } | |
1da177e4 LT |
1763 | v = apic_read(APIC_PROCPRI); |
1764 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1765 | } | |
1766 | ||
a11b5abe YL |
1767 | /* |
1768 | * Remote read supported only in the 82489DX and local APIC for | |
1769 | * Pentium processors. | |
1770 | */ | |
1771 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1772 | v = apic_read(APIC_RRR); | |
1773 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1774 | } | |
1775 | ||
1da177e4 LT |
1776 | v = apic_read(APIC_LDR); |
1777 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1778 | if (!x2apic_enabled()) { |
1779 | v = apic_read(APIC_DFR); | |
1780 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1781 | } | |
1da177e4 LT |
1782 | v = apic_read(APIC_SPIV); |
1783 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1784 | ||
1785 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1786 | print_APIC_bitfield(APIC_ISR); | |
1787 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1788 | print_APIC_bitfield(APIC_TMR); | |
1789 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1790 | print_APIC_bitfield(APIC_IRR); | |
1791 | ||
54168ed7 IM |
1792 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1793 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1794 | apic_write(APIC_ESR, 0); |
54168ed7 | 1795 | |
1da177e4 LT |
1796 | v = apic_read(APIC_ESR); |
1797 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1798 | } | |
1799 | ||
7ab6af7a | 1800 | icr = apic_icr_read(); |
0c425cec IM |
1801 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1802 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1803 | |
1804 | v = apic_read(APIC_LVTT); | |
1805 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1806 | ||
1807 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1808 | v = apic_read(APIC_LVTPC); | |
1809 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1810 | } | |
1811 | v = apic_read(APIC_LVT0); | |
1812 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1813 | v = apic_read(APIC_LVT1); | |
1814 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1815 | ||
1816 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1817 | v = apic_read(APIC_LVTERR); | |
1818 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1819 | } | |
1820 | ||
1821 | v = apic_read(APIC_TMICT); | |
1822 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1823 | v = apic_read(APIC_TMCCT); | |
1824 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1825 | v = apic_read(APIC_TDCR); | |
1826 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1827 | |
1828 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1829 | v = apic_read(APIC_EFEAT); | |
1830 | maxlvt = (v >> 16) & 0xff; | |
1831 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1832 | v = apic_read(APIC_ECTRL); | |
1833 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1834 | for (i = 0; i < maxlvt; i++) { | |
1835 | v = apic_read(APIC_EILVTn(i)); | |
1836 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1837 | } | |
1838 | } | |
1da177e4 LT |
1839 | printk("\n"); |
1840 | } | |
1841 | ||
32f71aff | 1842 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1843 | { |
ffd5aae7 YL |
1844 | int cpu; |
1845 | ||
1846 | preempt_disable(); | |
1847 | for_each_online_cpu(cpu) | |
1848 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1849 | preempt_enable(); | |
1da177e4 LT |
1850 | } |
1851 | ||
32f71aff | 1852 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1853 | { |
1da177e4 LT |
1854 | unsigned int v; |
1855 | unsigned long flags; | |
1856 | ||
1857 | if (apic_verbosity == APIC_QUIET) | |
1858 | return; | |
1859 | ||
1860 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1861 | ||
1862 | spin_lock_irqsave(&i8259A_lock, flags); | |
1863 | ||
1864 | v = inb(0xa1) << 8 | inb(0x21); | |
1865 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1866 | ||
1867 | v = inb(0xa0) << 8 | inb(0x20); | |
1868 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1869 | ||
54168ed7 IM |
1870 | outb(0x0b,0xa0); |
1871 | outb(0x0b,0x20); | |
1da177e4 | 1872 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1873 | outb(0x0a,0xa0); |
1874 | outb(0x0a,0x20); | |
1da177e4 LT |
1875 | |
1876 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1877 | ||
1878 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1879 | ||
1880 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1881 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1882 | } | |
1883 | ||
32f71aff MR |
1884 | __apicdebuginit(int) print_all_ICs(void) |
1885 | { | |
1886 | print_PIC(); | |
4797f6b0 YL |
1887 | |
1888 | /* don't print out if apic is not there */ | |
1889 | if (!cpu_has_apic || disable_apic) | |
1890 | return 0; | |
1891 | ||
32f71aff MR |
1892 | print_all_local_APICs(); |
1893 | print_IO_APIC(); | |
1894 | ||
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | fs_initcall(print_all_ICs); | |
1899 | ||
1da177e4 | 1900 | |
efa2559f YL |
1901 | /* Where if anywhere is the i8259 connect in external int mode */ |
1902 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1903 | ||
54168ed7 | 1904 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1905 | { |
1906 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1907 | int i8259_apic, i8259_pin; |
54168ed7 | 1908 | int apic; |
1da177e4 LT |
1909 | unsigned long flags; |
1910 | ||
1da177e4 LT |
1911 | /* |
1912 | * The number of IO-APIC IRQ registers (== #pins): | |
1913 | */ | |
fcfd636a | 1914 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1915 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1916 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1917 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1918 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1919 | } | |
54168ed7 | 1920 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1921 | int pin; |
1922 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1923 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1924 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1925 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1926 | |
fcfd636a EB |
1927 | /* If the interrupt line is enabled and in ExtInt mode |
1928 | * I have found the pin where the i8259 is connected. | |
1929 | */ | |
1930 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1931 | ioapic_i8259.apic = apic; | |
1932 | ioapic_i8259.pin = pin; | |
1933 | goto found_i8259; | |
1934 | } | |
1935 | } | |
1936 | } | |
1937 | found_i8259: | |
1938 | /* Look to see what if the MP table has reported the ExtINT */ | |
1939 | /* If we could not find the appropriate pin by looking at the ioapic | |
1940 | * the i8259 probably is not connected the ioapic but give the | |
1941 | * mptable a chance anyway. | |
1942 | */ | |
1943 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1944 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1945 | /* Trust the MP table if nothing is setup in the hardware */ | |
1946 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1947 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1948 | ioapic_i8259.pin = i8259_pin; | |
1949 | ioapic_i8259.apic = i8259_apic; | |
1950 | } | |
1951 | /* Complain if the MP table and the hardware disagree */ | |
1952 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1953 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1954 | { | |
1955 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1956 | } |
1957 | ||
1958 | /* | |
1959 | * Do not trust the IO-APIC being empty at bootup | |
1960 | */ | |
1961 | clear_IO_APIC(); | |
1962 | } | |
1963 | ||
1964 | /* | |
1965 | * Not an __init, needed by the reboot code | |
1966 | */ | |
1967 | void disable_IO_APIC(void) | |
1968 | { | |
1969 | /* | |
1970 | * Clear the IO-APIC before rebooting: | |
1971 | */ | |
1972 | clear_IO_APIC(); | |
1973 | ||
650927ef | 1974 | /* |
0b968d23 | 1975 | * If the i8259 is routed through an IOAPIC |
650927ef | 1976 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1977 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1978 | * |
1979 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1980 | * as virtual wire B is little complex (need to configure both | |
1981 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1982 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1983 | */ |
7c6d9f97 | 1984 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1985 | struct IO_APIC_route_entry entry; |
650927ef EB |
1986 | |
1987 | memset(&entry, 0, sizeof(entry)); | |
1988 | entry.mask = 0; /* Enabled */ | |
1989 | entry.trigger = 0; /* Edge */ | |
1990 | entry.irr = 0; | |
1991 | entry.polarity = 0; /* High */ | |
1992 | entry.delivery_status = 0; | |
1993 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1994 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1995 | entry.vector = 0; |
54168ed7 | 1996 | entry.dest = read_apic_id(); |
650927ef EB |
1997 | |
1998 | /* | |
1999 | * Add it to the IO-APIC irq-routing table: | |
2000 | */ | |
cf4c6a2f | 2001 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2002 | } |
54168ed7 | 2003 | |
7c6d9f97 SS |
2004 | /* |
2005 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2006 | */ | |
2007 | disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); | |
1da177e4 LT |
2008 | } |
2009 | ||
54168ed7 | 2010 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2011 | /* |
2012 | * function to set the IO-APIC physical IDs based on the | |
2013 | * values stored in the MPC table. | |
2014 | * | |
2015 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2016 | */ | |
2017 | ||
1da177e4 LT |
2018 | static void __init setup_ioapic_ids_from_mpc(void) |
2019 | { | |
2020 | union IO_APIC_reg_00 reg_00; | |
2021 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2022 | int apic_id; |
1da177e4 LT |
2023 | int i; |
2024 | unsigned char old_id; | |
2025 | unsigned long flags; | |
2026 | ||
a4dbc34d | 2027 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2028 | return; |
d49c4288 | 2029 | |
ca05fea6 NP |
2030 | /* |
2031 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2032 | * no meaning without the serial APIC bus. | |
2033 | */ | |
7c5c1e42 SL |
2034 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2035 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2036 | return; |
1da177e4 LT |
2037 | /* |
2038 | * This is broken; anything with a real cpu count has to | |
2039 | * circumvent this idiocy regardless. | |
2040 | */ | |
d190cb87 | 2041 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2042 | |
2043 | /* | |
2044 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2045 | */ | |
c8d46cf0 | 2046 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2047 | |
2048 | /* Read the register 0 value */ | |
2049 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2050 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2051 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2052 | |
c8d46cf0 | 2053 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2054 | |
c8d46cf0 | 2055 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2056 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2057 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2058 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2059 | reg_00.bits.ID); | |
c8d46cf0 | 2060 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2061 | } |
2062 | ||
1da177e4 LT |
2063 | /* |
2064 | * Sanity check, is the ID really free? Every APIC in a | |
2065 | * system must have a unique ID or we get lots of nice | |
2066 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2067 | */ | |
d1d7cae8 | 2068 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2069 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2070 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2071 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2072 | for (i = 0; i < get_physical_broadcast(); i++) |
2073 | if (!physid_isset(i, phys_id_present_map)) | |
2074 | break; | |
2075 | if (i >= get_physical_broadcast()) | |
2076 | panic("Max APIC ID exceeded!\n"); | |
2077 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2078 | i); | |
2079 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2080 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2081 | } else { |
2082 | physid_mask_t tmp; | |
8058714a | 2083 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2084 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2085 | "phys_id_present_map\n", | |
c8d46cf0 | 2086 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2087 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2088 | } | |
2089 | ||
2090 | ||
2091 | /* | |
2092 | * We need to adjust the IRQ routing table | |
2093 | * if the ID changed. | |
2094 | */ | |
c8d46cf0 | 2095 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2096 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2097 | if (mp_irqs[i].dstapic == old_id) |
2098 | mp_irqs[i].dstapic | |
c8d46cf0 | 2099 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2100 | |
2101 | /* | |
2102 | * Read the right value from the MPC table and | |
2103 | * write it into the ID register. | |
36062448 | 2104 | */ |
1da177e4 LT |
2105 | apic_printk(APIC_VERBOSE, KERN_INFO |
2106 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2107 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2108 | |
c8d46cf0 | 2109 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2110 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2111 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2112 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2113 | |
2114 | /* | |
2115 | * Sanity check | |
2116 | */ | |
2117 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2118 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2119 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2120 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2121 | printk("could not set ID!\n"); |
2122 | else | |
2123 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2124 | } | |
2125 | } | |
54168ed7 | 2126 | #endif |
1da177e4 | 2127 | |
7ce0bcfd | 2128 | int no_timer_check __initdata; |
8542b200 ZA |
2129 | |
2130 | static int __init notimercheck(char *s) | |
2131 | { | |
2132 | no_timer_check = 1; | |
2133 | return 1; | |
2134 | } | |
2135 | __setup("no_timer_check", notimercheck); | |
2136 | ||
1da177e4 LT |
2137 | /* |
2138 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2139 | * about the timer IRQ. We do the following to work around the situation: | |
2140 | * | |
2141 | * - timer IRQ defaults to IO-APIC IRQ | |
2142 | * - if this function detects that timer IRQs are defunct, then we fall | |
2143 | * back to ISA timer IRQs | |
2144 | */ | |
f0a7a5c9 | 2145 | static int __init timer_irq_works(void) |
1da177e4 LT |
2146 | { |
2147 | unsigned long t1 = jiffies; | |
4aae0702 | 2148 | unsigned long flags; |
1da177e4 | 2149 | |
8542b200 ZA |
2150 | if (no_timer_check) |
2151 | return 1; | |
2152 | ||
4aae0702 | 2153 | local_save_flags(flags); |
1da177e4 LT |
2154 | local_irq_enable(); |
2155 | /* Let ten ticks pass... */ | |
2156 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2157 | local_irq_restore(flags); |
1da177e4 LT |
2158 | |
2159 | /* | |
2160 | * Expect a few ticks at least, to be sure some possible | |
2161 | * glue logic does not lock up after one or two first | |
2162 | * ticks in a non-ExtINT mode. Also the local APIC | |
2163 | * might have cached one ExtINT interrupt. Finally, at | |
2164 | * least one tick may be lost due to delays. | |
2165 | */ | |
54168ed7 IM |
2166 | |
2167 | /* jiffies wrap? */ | |
1d16b53e | 2168 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2169 | return 1; |
1da177e4 LT |
2170 | return 0; |
2171 | } | |
2172 | ||
2173 | /* | |
2174 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2175 | * number of pending IRQ events unhandled. These cases are very rare, | |
2176 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2177 | * better to do it this way as thus we do not have to be aware of | |
2178 | * 'pending' interrupts in the IRQ path, except at this point. | |
2179 | */ | |
2180 | /* | |
2181 | * Edge triggered needs to resend any interrupt | |
2182 | * that was delayed but this is now handled in the device | |
2183 | * independent code. | |
2184 | */ | |
2185 | ||
2186 | /* | |
2187 | * Starting up a edge-triggered IO-APIC interrupt is | |
2188 | * nasty - we need to make sure that we get the edge. | |
2189 | * If it is already asserted for some reason, we need | |
2190 | * return 1 to indicate that is was pending. | |
2191 | * | |
2192 | * This is not complete - we should be able to fake | |
2193 | * an edge even if it isn't on the 8259A... | |
2194 | */ | |
54168ed7 | 2195 | |
f5b9ed7a | 2196 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2197 | { |
2198 | int was_pending = 0; | |
2199 | unsigned long flags; | |
0b8f1efa | 2200 | struct irq_cfg *cfg; |
1da177e4 LT |
2201 | |
2202 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2203 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2204 | disable_8259A_irq(irq); |
2205 | if (i8259A_irq_pending(irq)) | |
2206 | was_pending = 1; | |
2207 | } | |
0b8f1efa | 2208 | cfg = irq_cfg(irq); |
3145e941 | 2209 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2210 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2211 | ||
2212 | return was_pending; | |
2213 | } | |
2214 | ||
54168ed7 | 2215 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2216 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2217 | { |
54168ed7 IM |
2218 | |
2219 | struct irq_cfg *cfg = irq_cfg(irq); | |
2220 | unsigned long flags; | |
2221 | ||
2222 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2223 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2224 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2225 | |
2226 | return 1; | |
2227 | } | |
54168ed7 IM |
2228 | #else |
2229 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2230 | { |
dac5f412 | 2231 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2232 | |
d6c88a50 | 2233 | return 1; |
54168ed7 IM |
2234 | } |
2235 | #endif | |
497c9a19 | 2236 | |
54168ed7 IM |
2237 | /* |
2238 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2239 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2240 | * handled with the level-triggered descriptor, but that one has slightly | |
2241 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2242 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2243 | * races. | |
2244 | */ | |
497c9a19 | 2245 | |
54168ed7 | 2246 | #ifdef CONFIG_SMP |
e85abf8f GH |
2247 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2248 | { | |
2249 | cpumask_var_t cleanup_mask; | |
2250 | ||
2251 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2252 | unsigned int i; | |
2253 | cfg->move_cleanup_count = 0; | |
2254 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2255 | cfg->move_cleanup_count++; | |
2256 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2257 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2258 | } else { | |
2259 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2260 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2261 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2262 | free_cpumask_var(cleanup_mask); | |
2263 | } | |
2264 | cfg->move_in_progress = 0; | |
2265 | } | |
2266 | ||
4420471f | 2267 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2268 | { |
2269 | int apic, pin; | |
2270 | struct irq_pin_list *entry; | |
2271 | u8 vector = cfg->vector; | |
2272 | ||
2273 | entry = cfg->irq_2_pin; | |
2274 | for (;;) { | |
2275 | unsigned int reg; | |
2276 | ||
2277 | if (!entry) | |
2278 | break; | |
2279 | ||
2280 | apic = entry->apic; | |
2281 | pin = entry->pin; | |
2282 | /* | |
2283 | * With interrupt-remapping, destination information comes | |
2284 | * from interrupt-remapping table entry. | |
2285 | */ | |
2286 | if (!irq_remapped(irq)) | |
2287 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2288 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2289 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2290 | reg |= vector; | |
2291 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2292 | if (!entry->next) | |
2293 | break; | |
2294 | entry = entry->next; | |
2295 | } | |
2296 | } | |
2297 | ||
4420471f IM |
2298 | static int |
2299 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2300 | ||
e85abf8f GH |
2301 | /* |
2302 | * Either sets desc->affinity to a valid value, and returns | |
2303 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2304 | * leaves desc->affinity untouched. | |
2305 | */ | |
2306 | static unsigned int | |
2307 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2308 | { | |
2309 | struct irq_cfg *cfg; | |
2310 | unsigned int irq; | |
2311 | ||
2312 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2313 | return BAD_APICID; | |
2314 | ||
2315 | irq = desc->irq; | |
2316 | cfg = desc->chip_data; | |
2317 | if (assign_irq_vector(irq, cfg, mask)) | |
2318 | return BAD_APICID; | |
2319 | ||
e85abf8f GH |
2320 | cpumask_copy(desc->affinity, mask); |
2321 | ||
2322 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2323 | } | |
2324 | ||
4420471f | 2325 | static int |
e85abf8f GH |
2326 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2327 | { | |
2328 | struct irq_cfg *cfg; | |
2329 | unsigned long flags; | |
2330 | unsigned int dest; | |
2331 | unsigned int irq; | |
4420471f | 2332 | int ret = -1; |
e85abf8f GH |
2333 | |
2334 | irq = desc->irq; | |
2335 | cfg = desc->chip_data; | |
2336 | ||
2337 | spin_lock_irqsave(&ioapic_lock, flags); | |
2338 | dest = set_desc_affinity(desc, mask); | |
2339 | if (dest != BAD_APICID) { | |
2340 | /* Only the high 8 bits are valid. */ | |
2341 | dest = SET_APIC_LOGICAL_ID(dest); | |
2342 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2343 | ret = 0; |
e85abf8f GH |
2344 | } |
2345 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2346 | |
2347 | return ret; | |
e85abf8f GH |
2348 | } |
2349 | ||
4420471f | 2350 | static int |
e85abf8f GH |
2351 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2352 | { | |
2353 | struct irq_desc *desc; | |
2354 | ||
2355 | desc = irq_to_desc(irq); | |
2356 | ||
4420471f | 2357 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2358 | } |
497c9a19 | 2359 | |
54168ed7 | 2360 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2361 | |
54168ed7 IM |
2362 | /* |
2363 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2364 | * | |
0280f7c4 SS |
2365 | * For both level and edge triggered, irq migration is a simple atomic |
2366 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2367 | * |
0280f7c4 SS |
2368 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2369 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2370 | * Real vector that is used for interrupting cpu will be coming from | |
2371 | * the interrupt-remapping table entry. | |
54168ed7 | 2372 | */ |
d5dedd45 | 2373 | static int |
e7986739 | 2374 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2375 | { |
54168ed7 | 2376 | struct irq_cfg *cfg; |
54168ed7 | 2377 | struct irte irte; |
54168ed7 | 2378 | unsigned int dest; |
3145e941 | 2379 | unsigned int irq; |
d5dedd45 | 2380 | int ret = -1; |
497c9a19 | 2381 | |
22f65d31 | 2382 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2383 | return ret; |
497c9a19 | 2384 | |
3145e941 | 2385 | irq = desc->irq; |
54168ed7 | 2386 | if (get_irte(irq, &irte)) |
d5dedd45 | 2387 | return ret; |
497c9a19 | 2388 | |
3145e941 YL |
2389 | cfg = desc->chip_data; |
2390 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2391 | return ret; |
54168ed7 | 2392 | |
debccb3e | 2393 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2394 | |
54168ed7 IM |
2395 | irte.vector = cfg->vector; |
2396 | irte.dest_id = IRTE_DEST(dest); | |
2397 | ||
2398 | /* | |
2399 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2400 | */ | |
2401 | modify_irte(irq, &irte); | |
2402 | ||
22f65d31 MT |
2403 | if (cfg->move_in_progress) |
2404 | send_cleanup_vector(cfg); | |
54168ed7 | 2405 | |
7f7ace0c | 2406 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2407 | |
2408 | return 0; | |
54168ed7 IM |
2409 | } |
2410 | ||
54168ed7 IM |
2411 | /* |
2412 | * Migrates the IRQ destination in the process context. | |
2413 | */ | |
d5dedd45 | 2414 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2415 | const struct cpumask *mask) |
54168ed7 | 2416 | { |
d5dedd45 | 2417 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2418 | } |
d5dedd45 | 2419 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2420 | const struct cpumask *mask) |
3145e941 YL |
2421 | { |
2422 | struct irq_desc *desc = irq_to_desc(irq); | |
2423 | ||
d5dedd45 | 2424 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2425 | } |
29b61be6 | 2426 | #else |
d5dedd45 | 2427 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2428 | const struct cpumask *mask) |
2429 | { | |
d5dedd45 | 2430 | return 0; |
29b61be6 | 2431 | } |
54168ed7 IM |
2432 | #endif |
2433 | ||
2434 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2435 | { | |
2436 | unsigned vector, me; | |
8f2466f4 | 2437 | |
54168ed7 | 2438 | ack_APIC_irq(); |
54168ed7 | 2439 | exit_idle(); |
54168ed7 IM |
2440 | irq_enter(); |
2441 | ||
2442 | me = smp_processor_id(); | |
2443 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2444 | unsigned int irq; | |
68a8ca59 | 2445 | unsigned int irr; |
54168ed7 IM |
2446 | struct irq_desc *desc; |
2447 | struct irq_cfg *cfg; | |
2448 | irq = __get_cpu_var(vector_irq)[vector]; | |
2449 | ||
0b8f1efa YL |
2450 | if (irq == -1) |
2451 | continue; | |
2452 | ||
54168ed7 IM |
2453 | desc = irq_to_desc(irq); |
2454 | if (!desc) | |
2455 | continue; | |
2456 | ||
2457 | cfg = irq_cfg(irq); | |
2458 | spin_lock(&desc->lock); | |
2459 | if (!cfg->move_cleanup_count) | |
2460 | goto unlock; | |
2461 | ||
22f65d31 | 2462 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2463 | goto unlock; |
2464 | ||
68a8ca59 SS |
2465 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2466 | /* | |
2467 | * Check if the vector that needs to be cleanedup is | |
2468 | * registered at the cpu's IRR. If so, then this is not | |
2469 | * the best time to clean it up. Lets clean it up in the | |
2470 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2471 | * to myself. | |
2472 | */ | |
2473 | if (irr & (1 << (vector % 32))) { | |
2474 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2475 | goto unlock; | |
2476 | } | |
54168ed7 IM |
2477 | __get_cpu_var(vector_irq)[vector] = -1; |
2478 | cfg->move_cleanup_count--; | |
2479 | unlock: | |
2480 | spin_unlock(&desc->lock); | |
2481 | } | |
2482 | ||
2483 | irq_exit(); | |
2484 | } | |
2485 | ||
3145e941 | 2486 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2487 | { |
3145e941 YL |
2488 | struct irq_desc *desc = *descp; |
2489 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2490 | unsigned vector, me; |
2491 | ||
fcef5911 | 2492 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2493 | return; |
2494 | ||
2495 | vector = ~get_irq_regs()->orig_ax; | |
2496 | me = smp_processor_id(); | |
10b888d6 | 2497 | |
fcef5911 | 2498 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2499 | send_cleanup_vector(cfg); |
497c9a19 YL |
2500 | } |
2501 | #else | |
3145e941 | 2502 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2503 | #endif |
3145e941 | 2504 | |
1d025192 YL |
2505 | static void ack_apic_edge(unsigned int irq) |
2506 | { | |
3145e941 YL |
2507 | struct irq_desc *desc = irq_to_desc(irq); |
2508 | ||
2509 | irq_complete_move(&desc); | |
1d025192 YL |
2510 | move_native_irq(irq); |
2511 | ack_APIC_irq(); | |
2512 | } | |
2513 | ||
3eb2cce8 | 2514 | atomic_t irq_mis_count; |
3eb2cce8 | 2515 | |
047c8fdb YL |
2516 | static void ack_apic_level(unsigned int irq) |
2517 | { | |
3145e941 YL |
2518 | struct irq_desc *desc = irq_to_desc(irq); |
2519 | ||
3eb2cce8 YL |
2520 | #ifdef CONFIG_X86_32 |
2521 | unsigned long v; | |
2522 | int i; | |
2523 | #endif | |
3145e941 | 2524 | struct irq_cfg *cfg; |
54168ed7 | 2525 | int do_unmask_irq = 0; |
047c8fdb | 2526 | |
3145e941 | 2527 | irq_complete_move(&desc); |
047c8fdb | 2528 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2529 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2530 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2531 | do_unmask_irq = 1; |
3145e941 | 2532 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2533 | } |
047c8fdb YL |
2534 | #endif |
2535 | ||
3eb2cce8 YL |
2536 | #ifdef CONFIG_X86_32 |
2537 | /* | |
2538 | * It appears there is an erratum which affects at least version 0x11 | |
2539 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2540 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2541 | * erroneously delivered as edge-triggered one but the respective IRR | |
2542 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2543 | * message but it will never arrive and further interrupts are blocked | |
2544 | * from the source. The exact reason is so far unknown, but the | |
2545 | * phenomenon was observed when two consecutive interrupt requests | |
2546 | * from a given source get delivered to the same CPU and the source is | |
2547 | * temporarily disabled in between. | |
2548 | * | |
2549 | * A workaround is to simulate an EOI message manually. We achieve it | |
2550 | * by setting the trigger mode to edge and then to level when the edge | |
2551 | * trigger mode gets detected in the TMR of a local APIC for a | |
2552 | * level-triggered interrupt. We mask the source for the time of the | |
2553 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2554 | * The idea is from Manfred Spraul. --macro | |
2555 | */ | |
3145e941 YL |
2556 | cfg = desc->chip_data; |
2557 | i = cfg->vector; | |
3eb2cce8 YL |
2558 | |
2559 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2560 | #endif | |
2561 | ||
54168ed7 IM |
2562 | /* |
2563 | * We must acknowledge the irq before we move it or the acknowledge will | |
2564 | * not propagate properly. | |
2565 | */ | |
2566 | ack_APIC_irq(); | |
2567 | ||
2568 | /* Now we can move and renable the irq */ | |
2569 | if (unlikely(do_unmask_irq)) { | |
2570 | /* Only migrate the irq if the ack has been received. | |
2571 | * | |
2572 | * On rare occasions the broadcast level triggered ack gets | |
2573 | * delayed going to ioapics, and if we reprogram the | |
2574 | * vector while Remote IRR is still set the irq will never | |
2575 | * fire again. | |
2576 | * | |
2577 | * To prevent this scenario we read the Remote IRR bit | |
2578 | * of the ioapic. This has two effects. | |
2579 | * - On any sane system the read of the ioapic will | |
2580 | * flush writes (and acks) going to the ioapic from | |
2581 | * this cpu. | |
2582 | * - We get to see if the ACK has actually been delivered. | |
2583 | * | |
2584 | * Based on failed experiments of reprogramming the | |
2585 | * ioapic entry from outside of irq context starting | |
2586 | * with masking the ioapic entry and then polling until | |
2587 | * Remote IRR was clear before reprogramming the | |
2588 | * ioapic I don't trust the Remote IRR bit to be | |
2589 | * completey accurate. | |
2590 | * | |
2591 | * However there appears to be no other way to plug | |
2592 | * this race, so if the Remote IRR bit is not | |
2593 | * accurate and is causing problems then it is a hardware bug | |
2594 | * and you can go talk to the chipset vendor about it. | |
2595 | */ | |
3145e941 YL |
2596 | cfg = desc->chip_data; |
2597 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2598 | move_masked_irq(irq); |
3145e941 | 2599 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2600 | } |
1d025192 | 2601 | |
3eb2cce8 | 2602 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2603 | if (!(v & (1 << (i & 0x1f)))) { |
2604 | atomic_inc(&irq_mis_count); | |
2605 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2606 | __mask_and_edge_IO_APIC_irq(cfg); |
2607 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2608 | spin_unlock(&ioapic_lock); |
2609 | } | |
047c8fdb | 2610 | #endif |
3eb2cce8 | 2611 | } |
1d025192 | 2612 | |
d0b03bd1 | 2613 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2614 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2615 | { | |
2616 | int apic, pin; | |
2617 | struct irq_pin_list *entry; | |
2618 | ||
2619 | entry = cfg->irq_2_pin; | |
2620 | for (;;) { | |
2621 | ||
2622 | if (!entry) | |
2623 | break; | |
2624 | ||
2625 | apic = entry->apic; | |
2626 | pin = entry->pin; | |
2627 | io_apic_eoi(apic, pin); | |
2628 | entry = entry->next; | |
2629 | } | |
2630 | } | |
2631 | ||
2632 | static void | |
2633 | eoi_ioapic_irq(struct irq_desc *desc) | |
2634 | { | |
2635 | struct irq_cfg *cfg; | |
2636 | unsigned long flags; | |
2637 | unsigned int irq; | |
2638 | ||
2639 | irq = desc->irq; | |
2640 | cfg = desc->chip_data; | |
2641 | ||
2642 | spin_lock_irqsave(&ioapic_lock, flags); | |
2643 | __eoi_ioapic_irq(irq, cfg); | |
2644 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2645 | } | |
2646 | ||
d0b03bd1 HW |
2647 | static void ir_ack_apic_edge(unsigned int irq) |
2648 | { | |
5d0ae2db | 2649 | ack_APIC_irq(); |
d0b03bd1 HW |
2650 | } |
2651 | ||
2652 | static void ir_ack_apic_level(unsigned int irq) | |
2653 | { | |
5d0ae2db WH |
2654 | struct irq_desc *desc = irq_to_desc(irq); |
2655 | ||
2656 | ack_APIC_irq(); | |
2657 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2658 | } |
2659 | #endif /* CONFIG_INTR_REMAP */ | |
2660 | ||
f5b9ed7a | 2661 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2662 | .name = "IO-APIC", |
2663 | .startup = startup_ioapic_irq, | |
2664 | .mask = mask_IO_APIC_irq, | |
2665 | .unmask = unmask_IO_APIC_irq, | |
2666 | .ack = ack_apic_edge, | |
2667 | .eoi = ack_apic_level, | |
54d5d424 | 2668 | #ifdef CONFIG_SMP |
d6c88a50 | 2669 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2670 | #endif |
ace80ab7 | 2671 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2672 | }; |
2673 | ||
54168ed7 | 2674 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2675 | .name = "IR-IO-APIC", |
2676 | .startup = startup_ioapic_irq, | |
2677 | .mask = mask_IO_APIC_irq, | |
2678 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2679 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2680 | .ack = ir_ack_apic_edge, |
2681 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2682 | #ifdef CONFIG_SMP |
d6c88a50 | 2683 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2684 | #endif |
54168ed7 IM |
2685 | #endif |
2686 | .retrigger = ioapic_retrigger_irq, | |
2687 | }; | |
1da177e4 LT |
2688 | |
2689 | static inline void init_IO_APIC_traps(void) | |
2690 | { | |
2691 | int irq; | |
08678b08 | 2692 | struct irq_desc *desc; |
da51a821 | 2693 | struct irq_cfg *cfg; |
1da177e4 LT |
2694 | |
2695 | /* | |
2696 | * NOTE! The local APIC isn't very good at handling | |
2697 | * multiple interrupts at the same interrupt level. | |
2698 | * As the interrupt level is determined by taking the | |
2699 | * vector number and shifting that right by 4, we | |
2700 | * want to spread these out a bit so that they don't | |
2701 | * all fall in the same interrupt level. | |
2702 | * | |
2703 | * Also, we've got to be careful not to trash gate | |
2704 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2705 | */ | |
0b8f1efa | 2706 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2707 | cfg = desc->chip_data; |
2708 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2709 | /* |
2710 | * Hmm.. We don't have an entry for this, | |
2711 | * so default to an old-fashioned 8259 | |
2712 | * interrupt if we can.. | |
2713 | */ | |
99d093d1 | 2714 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2715 | make_8259A_irq(irq); |
0b8f1efa | 2716 | else |
1da177e4 | 2717 | /* Strange. Oh, well.. */ |
08678b08 | 2718 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2719 | } |
2720 | } | |
2721 | } | |
2722 | ||
f5b9ed7a IM |
2723 | /* |
2724 | * The local APIC irq-chip implementation: | |
2725 | */ | |
1da177e4 | 2726 | |
36062448 | 2727 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2728 | { |
2729 | unsigned long v; | |
2730 | ||
2731 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2732 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2733 | } |
2734 | ||
36062448 | 2735 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2736 | { |
f5b9ed7a | 2737 | unsigned long v; |
1da177e4 | 2738 | |
f5b9ed7a | 2739 | v = apic_read(APIC_LVT0); |
593f4a78 | 2740 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2741 | } |
1da177e4 | 2742 | |
3145e941 | 2743 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2744 | { |
2745 | ack_APIC_irq(); | |
2746 | } | |
2747 | ||
f5b9ed7a | 2748 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2749 | .name = "local-APIC", |
f5b9ed7a IM |
2750 | .mask = mask_lapic_irq, |
2751 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2752 | .ack = ack_lapic_irq, |
1da177e4 LT |
2753 | }; |
2754 | ||
3145e941 | 2755 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2756 | { |
08678b08 | 2757 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2758 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2759 | "edge"); | |
c88ac1df MR |
2760 | } |
2761 | ||
e9427101 | 2762 | static void __init setup_nmi(void) |
1da177e4 LT |
2763 | { |
2764 | /* | |
36062448 | 2765 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2766 | * We put the 8259A master into AEOI mode and |
2767 | * unmask on all local APICs LVT0 as NMI. | |
2768 | * | |
2769 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2770 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2771 | * the NMI handler or the timer interrupt. | |
36062448 | 2772 | */ |
1da177e4 LT |
2773 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2774 | ||
e9427101 | 2775 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2776 | |
2777 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2778 | } | |
2779 | ||
2780 | /* | |
2781 | * This looks a bit hackish but it's about the only one way of sending | |
2782 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2783 | * not support the ExtINT mode, unfortunately. We need to send these | |
2784 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2785 | * 8259A interrupt line asserted until INTA. --macro | |
2786 | */ | |
28acf285 | 2787 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2788 | { |
fcfd636a | 2789 | int apic, pin, i; |
1da177e4 LT |
2790 | struct IO_APIC_route_entry entry0, entry1; |
2791 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2792 | |
fcfd636a | 2793 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2794 | if (pin == -1) { |
2795 | WARN_ON_ONCE(1); | |
2796 | return; | |
2797 | } | |
fcfd636a | 2798 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2799 | if (apic == -1) { |
2800 | WARN_ON_ONCE(1); | |
1da177e4 | 2801 | return; |
956fb531 | 2802 | } |
1da177e4 | 2803 | |
cf4c6a2f | 2804 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2805 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2806 | |
2807 | memset(&entry1, 0, sizeof(entry1)); | |
2808 | ||
2809 | entry1.dest_mode = 0; /* physical delivery */ | |
2810 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2811 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2812 | entry1.delivery_mode = dest_ExtINT; |
2813 | entry1.polarity = entry0.polarity; | |
2814 | entry1.trigger = 0; | |
2815 | entry1.vector = 0; | |
2816 | ||
cf4c6a2f | 2817 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2818 | |
2819 | save_control = CMOS_READ(RTC_CONTROL); | |
2820 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2821 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2822 | RTC_FREQ_SELECT); | |
2823 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2824 | ||
2825 | i = 100; | |
2826 | while (i-- > 0) { | |
2827 | mdelay(10); | |
2828 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2829 | i -= 10; | |
2830 | } | |
2831 | ||
2832 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2833 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2834 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2835 | |
cf4c6a2f | 2836 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2837 | } |
2838 | ||
efa2559f | 2839 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2840 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2841 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2842 | { |
2843 | disable_timer_pin_1 = 1; | |
2844 | return 0; | |
2845 | } | |
54168ed7 | 2846 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2847 | |
2848 | int timer_through_8259 __initdata; | |
2849 | ||
1da177e4 LT |
2850 | /* |
2851 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2852 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2853 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2854 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2855 | * |
2856 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2857 | */ |
8542b200 | 2858 | static inline void __init check_timer(void) |
1da177e4 | 2859 | { |
3145e941 YL |
2860 | struct irq_desc *desc = irq_to_desc(0); |
2861 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2862 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2863 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2864 | unsigned long flags; |
047c8fdb | 2865 | int no_pin1 = 0; |
4aae0702 IM |
2866 | |
2867 | local_irq_save(flags); | |
d4d25dec | 2868 | |
1da177e4 LT |
2869 | /* |
2870 | * get/set the timer IRQ vector: | |
2871 | */ | |
2872 | disable_8259A_irq(0); | |
fe402e1f | 2873 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2874 | |
2875 | /* | |
d11d5794 MR |
2876 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2877 | * wire has to be disabled in the local APIC. Also | |
2878 | * timer interrupts need to be acknowledged manually in | |
2879 | * the 8259A for the i82489DX when using the NMI | |
2880 | * watchdog as that APIC treats NMIs as level-triggered. | |
2881 | * The AEOI mode will finish them in the 8259A | |
2882 | * automatically. | |
1da177e4 | 2883 | */ |
593f4a78 | 2884 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2885 | init_8259A(1); |
54168ed7 | 2886 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2887 | { |
2888 | unsigned int ver; | |
2889 | ||
2890 | ver = apic_read(APIC_LVR); | |
2891 | ver = GET_APIC_VERSION(ver); | |
2892 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2893 | } | |
54168ed7 | 2894 | #endif |
1da177e4 | 2895 | |
fcfd636a EB |
2896 | pin1 = find_isa_irq_pin(0, mp_INT); |
2897 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2898 | pin2 = ioapic_i8259.pin; | |
2899 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2900 | |
49a66a0b MR |
2901 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2902 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2903 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2904 | |
691874fa MR |
2905 | /* |
2906 | * Some BIOS writers are clueless and report the ExtINTA | |
2907 | * I/O APIC input from the cascaded 8259A as the timer | |
2908 | * interrupt input. So just in case, if only one pin | |
2909 | * was found above, try it both directly and through the | |
2910 | * 8259A. | |
2911 | */ | |
2912 | if (pin1 == -1) { | |
54168ed7 IM |
2913 | if (intr_remapping_enabled) |
2914 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2915 | pin1 = pin2; |
2916 | apic1 = apic2; | |
2917 | no_pin1 = 1; | |
2918 | } else if (pin2 == -1) { | |
2919 | pin2 = pin1; | |
2920 | apic2 = apic1; | |
2921 | } | |
2922 | ||
1da177e4 LT |
2923 | if (pin1 != -1) { |
2924 | /* | |
2925 | * Ok, does IRQ0 through the IOAPIC work? | |
2926 | */ | |
691874fa | 2927 | if (no_pin1) { |
85ac16d0 | 2928 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2929 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2930 | } else { |
2931 | /* for edge trigger, setup_IO_APIC_irq already | |
2932 | * leave it unmasked. | |
2933 | * so only need to unmask if it is level-trigger | |
2934 | * do we really have level trigger timer? | |
2935 | */ | |
2936 | int idx; | |
2937 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2938 | if (idx != -1 && irq_trigger(idx)) | |
2939 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2940 | } |
1da177e4 LT |
2941 | if (timer_irq_works()) { |
2942 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2943 | setup_nmi(); |
2944 | enable_8259A_irq(0); | |
1da177e4 | 2945 | } |
66759a01 CE |
2946 | if (disable_timer_pin_1 > 0) |
2947 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2948 | goto out; |
1da177e4 | 2949 | } |
54168ed7 IM |
2950 | if (intr_remapping_enabled) |
2951 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2952 | local_irq_disable(); |
fcfd636a | 2953 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2954 | if (!no_pin1) |
49a66a0b MR |
2955 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2956 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2957 | |
49a66a0b MR |
2958 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2959 | "(IRQ0) through the 8259A ...\n"); | |
2960 | apic_printk(APIC_QUIET, KERN_INFO | |
2961 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2962 | /* |
2963 | * legacy devices should be connected to IO APIC #0 | |
2964 | */ | |
85ac16d0 | 2965 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2966 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2967 | enable_8259A_irq(0); |
1da177e4 | 2968 | if (timer_irq_works()) { |
49a66a0b | 2969 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2970 | timer_through_8259 = 1; |
1da177e4 | 2971 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2972 | disable_8259A_irq(0); |
1da177e4 | 2973 | setup_nmi(); |
60134ebe | 2974 | enable_8259A_irq(0); |
1da177e4 | 2975 | } |
4aae0702 | 2976 | goto out; |
1da177e4 LT |
2977 | } |
2978 | /* | |
2979 | * Cleanup, just in case ... | |
2980 | */ | |
f72dccac | 2981 | local_irq_disable(); |
ecd29476 | 2982 | disable_8259A_irq(0); |
fcfd636a | 2983 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2984 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2985 | } |
1da177e4 LT |
2986 | |
2987 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2988 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2989 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2990 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2991 | } |
54168ed7 | 2992 | #ifdef CONFIG_X86_32 |
d11d5794 | 2993 | timer_ack = 0; |
54168ed7 | 2994 | #endif |
1da177e4 | 2995 | |
49a66a0b MR |
2996 | apic_printk(APIC_QUIET, KERN_INFO |
2997 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2998 | |
3145e941 | 2999 | lapic_register_intr(0, desc); |
497c9a19 | 3000 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3001 | enable_8259A_irq(0); |
3002 | ||
3003 | if (timer_irq_works()) { | |
49a66a0b | 3004 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3005 | goto out; |
1da177e4 | 3006 | } |
f72dccac | 3007 | local_irq_disable(); |
e67465f1 | 3008 | disable_8259A_irq(0); |
497c9a19 | 3009 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3010 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3011 | |
49a66a0b MR |
3012 | apic_printk(APIC_QUIET, KERN_INFO |
3013 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3014 | |
1da177e4 LT |
3015 | init_8259A(0); |
3016 | make_8259A_irq(0); | |
593f4a78 | 3017 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3018 | |
3019 | unlock_ExtINT_logic(); | |
3020 | ||
3021 | if (timer_irq_works()) { | |
49a66a0b | 3022 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3023 | goto out; |
1da177e4 | 3024 | } |
f72dccac | 3025 | local_irq_disable(); |
49a66a0b | 3026 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3027 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3028 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3029 | out: |
3030 | local_irq_restore(flags); | |
1da177e4 LT |
3031 | } |
3032 | ||
3033 | /* | |
af174783 MR |
3034 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3035 | * to devices. However there may be an I/O APIC pin available for | |
3036 | * this interrupt regardless. The pin may be left unconnected, but | |
3037 | * typically it will be reused as an ExtINT cascade interrupt for | |
3038 | * the master 8259A. In the MPS case such a pin will normally be | |
3039 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3040 | * there is no provision for ExtINT interrupts, and in the absence | |
3041 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3042 | * interrupt, that is edge-triggered and unmasked by default. We | |
3043 | * used to do this, but it caused problems on some systems because | |
3044 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3045 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3046 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3047 | * the I/O APIC in all cases now. No actual device should request | |
3048 | * it anyway. --macro | |
1da177e4 LT |
3049 | */ |
3050 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3051 | ||
3052 | void __init setup_IO_APIC(void) | |
3053 | { | |
54168ed7 | 3054 | |
54168ed7 IM |
3055 | /* |
3056 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3057 | */ | |
1da177e4 | 3058 | |
af174783 | 3059 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3060 | |
54168ed7 | 3061 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3062 | /* |
54168ed7 IM |
3063 | * Set up IO-APIC IRQ routing. |
3064 | */ | |
3065 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3066 | if (!acpi_ioapic) |
3067 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3068 | #endif |
1da177e4 LT |
3069 | sync_Arb_IDs(); |
3070 | setup_IO_APIC_irqs(); | |
3071 | init_IO_APIC_traps(); | |
1e4c85f9 | 3072 | check_timer(); |
1da177e4 LT |
3073 | } |
3074 | ||
3075 | /* | |
54168ed7 IM |
3076 | * Called after all the initialization is done. If we didnt find any |
3077 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3078 | */ |
36062448 | 3079 | |
1da177e4 LT |
3080 | static int __init io_apic_bug_finalize(void) |
3081 | { | |
d6c88a50 TG |
3082 | if (sis_apic_bug == -1) |
3083 | sis_apic_bug = 0; | |
3084 | return 0; | |
1da177e4 LT |
3085 | } |
3086 | ||
3087 | late_initcall(io_apic_bug_finalize); | |
3088 | ||
3089 | struct sysfs_ioapic_data { | |
3090 | struct sys_device dev; | |
3091 | struct IO_APIC_route_entry entry[0]; | |
3092 | }; | |
54168ed7 | 3093 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3094 | |
438510f6 | 3095 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3096 | { |
3097 | struct IO_APIC_route_entry *entry; | |
3098 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3099 | int i; |
36062448 | 3100 | |
1da177e4 LT |
3101 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3102 | entry = data->entry; | |
54168ed7 IM |
3103 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3104 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3105 | |
3106 | return 0; | |
3107 | } | |
3108 | ||
3109 | static int ioapic_resume(struct sys_device *dev) | |
3110 | { | |
3111 | struct IO_APIC_route_entry *entry; | |
3112 | struct sysfs_ioapic_data *data; | |
3113 | unsigned long flags; | |
3114 | union IO_APIC_reg_00 reg_00; | |
3115 | int i; | |
36062448 | 3116 | |
1da177e4 LT |
3117 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3118 | entry = data->entry; | |
3119 | ||
3120 | spin_lock_irqsave(&ioapic_lock, flags); | |
3121 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3122 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3123 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3124 | io_apic_write(dev->id, 0, reg_00.raw); |
3125 | } | |
1da177e4 | 3126 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3127 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3128 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3129 | |
3130 | return 0; | |
3131 | } | |
3132 | ||
3133 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3134 | .name = "ioapic", |
1da177e4 LT |
3135 | .suspend = ioapic_suspend, |
3136 | .resume = ioapic_resume, | |
3137 | }; | |
3138 | ||
3139 | static int __init ioapic_init_sysfs(void) | |
3140 | { | |
54168ed7 IM |
3141 | struct sys_device * dev; |
3142 | int i, size, error; | |
1da177e4 LT |
3143 | |
3144 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3145 | if (error) | |
3146 | return error; | |
3147 | ||
54168ed7 | 3148 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3149 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3150 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3151 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3152 | if (!mp_ioapic_data[i]) { |
3153 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3154 | continue; | |
3155 | } | |
1da177e4 | 3156 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3157 | dev->id = i; |
1da177e4 LT |
3158 | dev->cls = &ioapic_sysdev_class; |
3159 | error = sysdev_register(dev); | |
3160 | if (error) { | |
3161 | kfree(mp_ioapic_data[i]); | |
3162 | mp_ioapic_data[i] = NULL; | |
3163 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3164 | continue; | |
3165 | } | |
3166 | } | |
3167 | ||
3168 | return 0; | |
3169 | } | |
3170 | ||
3171 | device_initcall(ioapic_init_sysfs); | |
3172 | ||
abcaa2b8 | 3173 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3174 | /* |
95d77884 | 3175 | * Dynamic irq allocate and deallocation |
3fc471ed | 3176 | */ |
d047f53a | 3177 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3178 | { |
ace80ab7 | 3179 | /* Allocate an unused irq */ |
54168ed7 IM |
3180 | unsigned int irq; |
3181 | unsigned int new; | |
3fc471ed | 3182 | unsigned long flags; |
0b8f1efa | 3183 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3184 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3185 | |
3186 | irq = 0; | |
abcaa2b8 YL |
3187 | if (irq_want < nr_irqs_gsi) |
3188 | irq_want = nr_irqs_gsi; | |
3189 | ||
ace80ab7 | 3190 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3191 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3192 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3193 | if (!desc_new) { |
3194 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3195 | continue; |
0b8f1efa YL |
3196 | } |
3197 | cfg_new = desc_new->chip_data; | |
3198 | ||
3199 | if (cfg_new->vector != 0) | |
ace80ab7 | 3200 | continue; |
d047f53a | 3201 | |
15e957d0 | 3202 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3203 | |
fe402e1f | 3204 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3205 | irq = new; |
3206 | break; | |
3207 | } | |
3208 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3209 | |
199751d7 | 3210 | if (irq > 0) { |
3fc471ed | 3211 | dynamic_irq_init(irq); |
0b8f1efa YL |
3212 | /* restore it, in case dynamic_irq_init clear it */ |
3213 | if (desc_new) | |
3214 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3215 | } |
3216 | return irq; | |
3217 | } | |
3218 | ||
199751d7 YL |
3219 | int create_irq(void) |
3220 | { | |
d047f53a | 3221 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3222 | unsigned int irq_want; |
54168ed7 IM |
3223 | int irq; |
3224 | ||
be5d5350 | 3225 | irq_want = nr_irqs_gsi; |
d047f53a | 3226 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3227 | |
3228 | if (irq == 0) | |
3229 | irq = -1; | |
3230 | ||
3231 | return irq; | |
199751d7 YL |
3232 | } |
3233 | ||
3fc471ed EB |
3234 | void destroy_irq(unsigned int irq) |
3235 | { | |
3236 | unsigned long flags; | |
0b8f1efa YL |
3237 | struct irq_cfg *cfg; |
3238 | struct irq_desc *desc; | |
3fc471ed | 3239 | |
0b8f1efa YL |
3240 | /* store it, in case dynamic_irq_cleanup clear it */ |
3241 | desc = irq_to_desc(irq); | |
3242 | cfg = desc->chip_data; | |
3fc471ed | 3243 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3244 | /* connect back irq_cfg */ |
3245 | if (desc) | |
3246 | desc->chip_data = cfg; | |
3fc471ed | 3247 | |
54168ed7 | 3248 | free_irte(irq); |
3fc471ed | 3249 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3250 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3251 | spin_unlock_irqrestore(&vector_lock, flags); |
3252 | } | |
3fc471ed | 3253 | |
2d3fcc1c | 3254 | /* |
27b46d76 | 3255 | * MSI message composition |
2d3fcc1c EB |
3256 | */ |
3257 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3258 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3259 | { |
497c9a19 YL |
3260 | struct irq_cfg *cfg; |
3261 | int err; | |
2d3fcc1c EB |
3262 | unsigned dest; |
3263 | ||
f1182638 JB |
3264 | if (disable_apic) |
3265 | return -ENXIO; | |
3266 | ||
3145e941 | 3267 | cfg = irq_cfg(irq); |
fe402e1f | 3268 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3269 | if (err) |
3270 | return err; | |
2d3fcc1c | 3271 | |
debccb3e | 3272 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3273 | |
54168ed7 IM |
3274 | if (irq_remapped(irq)) { |
3275 | struct irte irte; | |
3276 | int ir_index; | |
3277 | u16 sub_handle; | |
3278 | ||
3279 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3280 | BUG_ON(ir_index == -1); | |
3281 | ||
3282 | memset (&irte, 0, sizeof(irte)); | |
3283 | ||
3284 | irte.present = 1; | |
9b5bc8dc | 3285 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3286 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3287 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3288 | irte.vector = cfg->vector; |
3289 | irte.dest_id = IRTE_DEST(dest); | |
3290 | ||
3291 | modify_irte(irq, &irte); | |
3292 | ||
3293 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3294 | msg->data = sub_handle; | |
3295 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3296 | MSI_ADDR_IR_SHV | | |
3297 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3298 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3299 | } else { |
9d783ba0 SS |
3300 | if (x2apic_enabled()) |
3301 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3302 | MSI_ADDR_EXT_DEST_ID(dest); | |
3303 | else | |
3304 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3305 | ||
54168ed7 IM |
3306 | msg->address_lo = |
3307 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3308 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3309 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3310 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3311 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3312 | MSI_ADDR_REDIRECTION_CPU: |
3313 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3314 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3315 | |
54168ed7 IM |
3316 | msg->data = |
3317 | MSI_DATA_TRIGGER_EDGE | | |
3318 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3319 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3320 | MSI_DATA_DELIVERY_FIXED: |
3321 | MSI_DATA_DELIVERY_LOWPRI) | | |
3322 | MSI_DATA_VECTOR(cfg->vector); | |
3323 | } | |
497c9a19 | 3324 | return err; |
2d3fcc1c EB |
3325 | } |
3326 | ||
3b7d1921 | 3327 | #ifdef CONFIG_SMP |
d5dedd45 | 3328 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3329 | { |
3145e941 | 3330 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3331 | struct irq_cfg *cfg; |
3b7d1921 EB |
3332 | struct msi_msg msg; |
3333 | unsigned int dest; | |
3b7d1921 | 3334 | |
22f65d31 MT |
3335 | dest = set_desc_affinity(desc, mask); |
3336 | if (dest == BAD_APICID) | |
d5dedd45 | 3337 | return -1; |
2d3fcc1c | 3338 | |
3145e941 | 3339 | cfg = desc->chip_data; |
2d3fcc1c | 3340 | |
3145e941 | 3341 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3342 | |
3343 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3344 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3345 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3346 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3347 | ||
3145e941 | 3348 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3349 | |
3350 | return 0; | |
2d3fcc1c | 3351 | } |
54168ed7 IM |
3352 | #ifdef CONFIG_INTR_REMAP |
3353 | /* | |
3354 | * Migrate the MSI irq to another cpumask. This migration is | |
3355 | * done in the process context using interrupt-remapping hardware. | |
3356 | */ | |
d5dedd45 | 3357 | static int |
e7986739 | 3358 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3359 | { |
3145e941 | 3360 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3361 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3362 | unsigned int dest; |
54168ed7 | 3363 | struct irte irte; |
54168ed7 IM |
3364 | |
3365 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3366 | return -1; |
54168ed7 | 3367 | |
22f65d31 MT |
3368 | dest = set_desc_affinity(desc, mask); |
3369 | if (dest == BAD_APICID) | |
d5dedd45 | 3370 | return -1; |
54168ed7 | 3371 | |
54168ed7 IM |
3372 | irte.vector = cfg->vector; |
3373 | irte.dest_id = IRTE_DEST(dest); | |
3374 | ||
3375 | /* | |
3376 | * atomically update the IRTE with the new destination and vector. | |
3377 | */ | |
3378 | modify_irte(irq, &irte); | |
3379 | ||
3380 | /* | |
3381 | * After this point, all the interrupts will start arriving | |
3382 | * at the new destination. So, time to cleanup the previous | |
3383 | * vector allocation. | |
3384 | */ | |
22f65d31 MT |
3385 | if (cfg->move_in_progress) |
3386 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3387 | |
3388 | return 0; | |
54168ed7 | 3389 | } |
3145e941 | 3390 | |
54168ed7 | 3391 | #endif |
3b7d1921 | 3392 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3393 | |
3b7d1921 EB |
3394 | /* |
3395 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3396 | * which implement the MSI or MSI-X Capability Structure. | |
3397 | */ | |
3398 | static struct irq_chip msi_chip = { | |
3399 | .name = "PCI-MSI", | |
3400 | .unmask = unmask_msi_irq, | |
3401 | .mask = mask_msi_irq, | |
1d025192 | 3402 | .ack = ack_apic_edge, |
3b7d1921 EB |
3403 | #ifdef CONFIG_SMP |
3404 | .set_affinity = set_msi_irq_affinity, | |
3405 | #endif | |
3406 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3407 | }; |
3408 | ||
54168ed7 IM |
3409 | static struct irq_chip msi_ir_chip = { |
3410 | .name = "IR-PCI-MSI", | |
3411 | .unmask = unmask_msi_irq, | |
3412 | .mask = mask_msi_irq, | |
a1e38ca5 | 3413 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3414 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3415 | #ifdef CONFIG_SMP |
3416 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3417 | #endif |
54168ed7 IM |
3418 | #endif |
3419 | .retrigger = ioapic_retrigger_irq, | |
3420 | }; | |
3421 | ||
3422 | /* | |
3423 | * Map the PCI dev to the corresponding remapping hardware unit | |
3424 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3425 | * in it. | |
3426 | */ | |
3427 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3428 | { | |
3429 | struct intel_iommu *iommu; | |
3430 | int index; | |
3431 | ||
3432 | iommu = map_dev_to_ir(dev); | |
3433 | if (!iommu) { | |
3434 | printk(KERN_ERR | |
3435 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3436 | return -ENOENT; | |
3437 | } | |
3438 | ||
3439 | index = alloc_irte(iommu, irq, nvec); | |
3440 | if (index < 0) { | |
3441 | printk(KERN_ERR | |
3442 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3443 | pci_name(dev)); |
54168ed7 IM |
3444 | return -ENOSPC; |
3445 | } | |
3446 | return index; | |
3447 | } | |
1d025192 | 3448 | |
3145e941 | 3449 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3450 | { |
3451 | int ret; | |
3452 | struct msi_msg msg; | |
3453 | ||
3454 | ret = msi_compose_msg(dev, irq, &msg); | |
3455 | if (ret < 0) | |
3456 | return ret; | |
3457 | ||
3145e941 | 3458 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3459 | write_msi_msg(irq, &msg); |
3460 | ||
54168ed7 IM |
3461 | if (irq_remapped(irq)) { |
3462 | struct irq_desc *desc = irq_to_desc(irq); | |
3463 | /* | |
3464 | * irq migration in process context | |
3465 | */ | |
3466 | desc->status |= IRQ_MOVE_PCNTXT; | |
3467 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3468 | } else | |
54168ed7 | 3469 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3470 | |
c81bba49 YL |
3471 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3472 | ||
1d025192 YL |
3473 | return 0; |
3474 | } | |
3475 | ||
047c8fdb YL |
3476 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3477 | { | |
54168ed7 IM |
3478 | unsigned int irq; |
3479 | int ret, sub_handle; | |
0b8f1efa | 3480 | struct msi_desc *msidesc; |
54168ed7 | 3481 | unsigned int irq_want; |
1cc18521 | 3482 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3483 | int index = 0; |
d047f53a | 3484 | int node; |
54168ed7 | 3485 | |
1c8d7b0a MW |
3486 | /* x86 doesn't support multiple MSI yet */ |
3487 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3488 | return 1; | |
3489 | ||
d047f53a | 3490 | node = dev_to_node(&dev->dev); |
be5d5350 | 3491 | irq_want = nr_irqs_gsi; |
54168ed7 | 3492 | sub_handle = 0; |
0b8f1efa | 3493 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3494 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3495 | if (irq == 0) |
3496 | return -1; | |
f1ee5548 | 3497 | irq_want = irq + 1; |
54168ed7 IM |
3498 | if (!intr_remapping_enabled) |
3499 | goto no_ir; | |
3500 | ||
3501 | if (!sub_handle) { | |
3502 | /* | |
3503 | * allocate the consecutive block of IRTE's | |
3504 | * for 'nvec' | |
3505 | */ | |
3506 | index = msi_alloc_irte(dev, irq, nvec); | |
3507 | if (index < 0) { | |
3508 | ret = index; | |
3509 | goto error; | |
3510 | } | |
3511 | } else { | |
3512 | iommu = map_dev_to_ir(dev); | |
3513 | if (!iommu) { | |
3514 | ret = -ENOENT; | |
3515 | goto error; | |
3516 | } | |
3517 | /* | |
3518 | * setup the mapping between the irq and the IRTE | |
3519 | * base index, the sub_handle pointing to the | |
3520 | * appropriate interrupt remap table entry. | |
3521 | */ | |
3522 | set_irte_irq(irq, iommu, index, sub_handle); | |
3523 | } | |
3524 | no_ir: | |
0b8f1efa | 3525 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3526 | if (ret < 0) |
3527 | goto error; | |
3528 | sub_handle++; | |
3529 | } | |
3530 | return 0; | |
047c8fdb YL |
3531 | |
3532 | error: | |
54168ed7 IM |
3533 | destroy_irq(irq); |
3534 | return ret; | |
047c8fdb YL |
3535 | } |
3536 | ||
3b7d1921 EB |
3537 | void arch_teardown_msi_irq(unsigned int irq) |
3538 | { | |
f7feaca7 | 3539 | destroy_irq(irq); |
3b7d1921 EB |
3540 | } |
3541 | ||
9d783ba0 | 3542 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3543 | #ifdef CONFIG_SMP |
d5dedd45 | 3544 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3545 | { |
3145e941 | 3546 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3547 | struct irq_cfg *cfg; |
3548 | struct msi_msg msg; | |
3549 | unsigned int dest; | |
54168ed7 | 3550 | |
22f65d31 MT |
3551 | dest = set_desc_affinity(desc, mask); |
3552 | if (dest == BAD_APICID) | |
d5dedd45 | 3553 | return -1; |
54168ed7 | 3554 | |
3145e941 | 3555 | cfg = desc->chip_data; |
54168ed7 IM |
3556 | |
3557 | dmar_msi_read(irq, &msg); | |
3558 | ||
3559 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3560 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3561 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3562 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3563 | ||
3564 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3565 | |
3566 | return 0; | |
54168ed7 | 3567 | } |
3145e941 | 3568 | |
54168ed7 IM |
3569 | #endif /* CONFIG_SMP */ |
3570 | ||
3571 | struct irq_chip dmar_msi_type = { | |
3572 | .name = "DMAR_MSI", | |
3573 | .unmask = dmar_msi_unmask, | |
3574 | .mask = dmar_msi_mask, | |
3575 | .ack = ack_apic_edge, | |
3576 | #ifdef CONFIG_SMP | |
3577 | .set_affinity = dmar_msi_set_affinity, | |
3578 | #endif | |
3579 | .retrigger = ioapic_retrigger_irq, | |
3580 | }; | |
3581 | ||
3582 | int arch_setup_dmar_msi(unsigned int irq) | |
3583 | { | |
3584 | int ret; | |
3585 | struct msi_msg msg; | |
2d3fcc1c | 3586 | |
54168ed7 IM |
3587 | ret = msi_compose_msg(NULL, irq, &msg); |
3588 | if (ret < 0) | |
3589 | return ret; | |
3590 | dmar_msi_write(irq, &msg); | |
3591 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3592 | "edge"); | |
3593 | return 0; | |
3594 | } | |
3595 | #endif | |
3596 | ||
58ac1e76 | 3597 | #ifdef CONFIG_HPET_TIMER |
3598 | ||
3599 | #ifdef CONFIG_SMP | |
d5dedd45 | 3600 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3601 | { |
3145e941 | 3602 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3603 | struct irq_cfg *cfg; |
58ac1e76 | 3604 | struct msi_msg msg; |
3605 | unsigned int dest; | |
58ac1e76 | 3606 | |
22f65d31 MT |
3607 | dest = set_desc_affinity(desc, mask); |
3608 | if (dest == BAD_APICID) | |
d5dedd45 | 3609 | return -1; |
58ac1e76 | 3610 | |
3145e941 | 3611 | cfg = desc->chip_data; |
58ac1e76 | 3612 | |
3613 | hpet_msi_read(irq, &msg); | |
3614 | ||
3615 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3616 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3617 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3618 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3619 | ||
3620 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3621 | |
3622 | return 0; | |
58ac1e76 | 3623 | } |
3145e941 | 3624 | |
58ac1e76 | 3625 | #endif /* CONFIG_SMP */ |
3626 | ||
1cc18521 | 3627 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3628 | .name = "HPET_MSI", |
3629 | .unmask = hpet_msi_unmask, | |
3630 | .mask = hpet_msi_mask, | |
3631 | .ack = ack_apic_edge, | |
3632 | #ifdef CONFIG_SMP | |
3633 | .set_affinity = hpet_msi_set_affinity, | |
3634 | #endif | |
3635 | .retrigger = ioapic_retrigger_irq, | |
3636 | }; | |
3637 | ||
3638 | int arch_setup_hpet_msi(unsigned int irq) | |
3639 | { | |
3640 | int ret; | |
3641 | struct msi_msg msg; | |
6ec3cfec | 3642 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3643 | |
3644 | ret = msi_compose_msg(NULL, irq, &msg); | |
3645 | if (ret < 0) | |
3646 | return ret; | |
3647 | ||
3648 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3649 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3650 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3651 | "edge"); | |
c81bba49 | 3652 | |
58ac1e76 | 3653 | return 0; |
3654 | } | |
3655 | #endif | |
3656 | ||
54168ed7 | 3657 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3658 | /* |
3659 | * Hypertransport interrupt support | |
3660 | */ | |
3661 | #ifdef CONFIG_HT_IRQ | |
3662 | ||
3663 | #ifdef CONFIG_SMP | |
3664 | ||
497c9a19 | 3665 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3666 | { |
ec68307c EB |
3667 | struct ht_irq_msg msg; |
3668 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3669 | |
497c9a19 | 3670 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3671 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3672 | |
497c9a19 | 3673 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3674 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3675 | |
ec68307c | 3676 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3677 | } |
3678 | ||
d5dedd45 | 3679 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3680 | { |
3145e941 | 3681 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3682 | struct irq_cfg *cfg; |
8b955b0d | 3683 | unsigned int dest; |
8b955b0d | 3684 | |
22f65d31 MT |
3685 | dest = set_desc_affinity(desc, mask); |
3686 | if (dest == BAD_APICID) | |
d5dedd45 | 3687 | return -1; |
8b955b0d | 3688 | |
3145e941 | 3689 | cfg = desc->chip_data; |
8b955b0d | 3690 | |
497c9a19 | 3691 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3692 | |
3693 | return 0; | |
8b955b0d | 3694 | } |
3145e941 | 3695 | |
8b955b0d EB |
3696 | #endif |
3697 | ||
c37e108d | 3698 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3699 | .name = "PCI-HT", |
3700 | .mask = mask_ht_irq, | |
3701 | .unmask = unmask_ht_irq, | |
1d025192 | 3702 | .ack = ack_apic_edge, |
8b955b0d EB |
3703 | #ifdef CONFIG_SMP |
3704 | .set_affinity = set_ht_irq_affinity, | |
3705 | #endif | |
3706 | .retrigger = ioapic_retrigger_irq, | |
3707 | }; | |
3708 | ||
3709 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3710 | { | |
497c9a19 YL |
3711 | struct irq_cfg *cfg; |
3712 | int err; | |
8b955b0d | 3713 | |
f1182638 JB |
3714 | if (disable_apic) |
3715 | return -ENXIO; | |
3716 | ||
3145e941 | 3717 | cfg = irq_cfg(irq); |
fe402e1f | 3718 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3719 | if (!err) { |
ec68307c | 3720 | struct ht_irq_msg msg; |
8b955b0d | 3721 | unsigned dest; |
8b955b0d | 3722 | |
debccb3e IM |
3723 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3724 | apic->target_cpus()); | |
8b955b0d | 3725 | |
ec68307c | 3726 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3727 | |
ec68307c EB |
3728 | msg.address_lo = |
3729 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3730 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3731 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3732 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3733 | HT_IRQ_LOW_DM_PHYSICAL : |
3734 | HT_IRQ_LOW_DM_LOGICAL) | | |
3735 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3736 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3737 | HT_IRQ_LOW_MT_FIXED : |
3738 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3739 | HT_IRQ_LOW_IRQ_MASKED; | |
3740 | ||
ec68307c | 3741 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3742 | |
a460e745 IM |
3743 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3744 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3745 | |
3746 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3747 | } |
497c9a19 | 3748 | return err; |
8b955b0d EB |
3749 | } |
3750 | #endif /* CONFIG_HT_IRQ */ | |
3751 | ||
03b48632 | 3752 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3753 | /* |
3754 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3755 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3756 | */ | |
3757 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3758 | unsigned long mmr_offset) | |
3759 | { | |
22f65d31 | 3760 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3761 | struct irq_cfg *cfg; |
3762 | int mmr_pnode; | |
3763 | unsigned long mmr_value; | |
3764 | struct uv_IO_APIC_route_entry *entry; | |
3765 | unsigned long flags; | |
3766 | int err; | |
3767 | ||
1cbac972 CG |
3768 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3769 | ||
3145e941 YL |
3770 | cfg = irq_cfg(irq); |
3771 | ||
e7986739 | 3772 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3773 | if (err != 0) |
3774 | return err; | |
3775 | ||
3776 | spin_lock_irqsave(&vector_lock, flags); | |
3777 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3778 | irq_name); | |
3779 | spin_unlock_irqrestore(&vector_lock, flags); | |
3780 | ||
4173a0e7 DN |
3781 | mmr_value = 0; |
3782 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
1cbac972 CG |
3783 | entry->vector = cfg->vector; |
3784 | entry->delivery_mode = apic->irq_delivery_mode; | |
3785 | entry->dest_mode = apic->irq_dest_mode; | |
3786 | entry->polarity = 0; | |
3787 | entry->trigger = 0; | |
3788 | entry->mask = 0; | |
3789 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | |
4173a0e7 DN |
3790 | |
3791 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3792 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3793 | ||
3794 | return irq; | |
3795 | } | |
3796 | ||
3797 | /* | |
3798 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3799 | * longer allowed to be sent. | |
3800 | */ | |
3801 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3802 | { | |
3803 | unsigned long mmr_value; | |
3804 | struct uv_IO_APIC_route_entry *entry; | |
3805 | int mmr_pnode; | |
3806 | ||
1cbac972 CG |
3807 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3808 | ||
4173a0e7 DN |
3809 | mmr_value = 0; |
3810 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
4173a0e7 DN |
3811 | entry->mask = 1; |
3812 | ||
3813 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3814 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3815 | } | |
3816 | #endif /* CONFIG_X86_64 */ | |
3817 | ||
9d6a4d08 YL |
3818 | int __init io_apic_get_redir_entries (int ioapic) |
3819 | { | |
3820 | union IO_APIC_reg_01 reg_01; | |
3821 | unsigned long flags; | |
3822 | ||
3823 | spin_lock_irqsave(&ioapic_lock, flags); | |
3824 | reg_01.raw = io_apic_read(ioapic, 1); | |
3825 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3826 | ||
3827 | return reg_01.bits.entries; | |
3828 | } | |
3829 | ||
be5d5350 | 3830 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3831 | { |
be5d5350 YL |
3832 | int nr = 0; |
3833 | ||
cc6c5006 YL |
3834 | nr = acpi_probe_gsi(); |
3835 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3836 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3837 | } else { |
3838 | /* for acpi=off or acpi is not compiled in */ | |
3839 | int idx; | |
3840 | ||
3841 | nr = 0; | |
3842 | for (idx = 0; idx < nr_ioapics; idx++) | |
3843 | nr += io_apic_get_redir_entries(idx) + 1; | |
3844 | ||
3845 | if (nr > nr_irqs_gsi) | |
3846 | nr_irqs_gsi = nr; | |
3847 | } | |
3848 | ||
3849 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3850 | } |
3851 | ||
4a046d17 YL |
3852 | #ifdef CONFIG_SPARSE_IRQ |
3853 | int __init arch_probe_nr_irqs(void) | |
3854 | { | |
3855 | int nr; | |
3856 | ||
f1ee5548 YL |
3857 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3858 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3859 | |
f1ee5548 YL |
3860 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3861 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3862 | /* | |
3863 | * for MSI and HT dyn irq | |
3864 | */ | |
3865 | nr += nr_irqs_gsi * 16; | |
3866 | #endif | |
3867 | if (nr < nr_irqs) | |
4a046d17 YL |
3868 | nr_irqs = nr; |
3869 | ||
3870 | return 0; | |
3871 | } | |
3872 | #endif | |
3873 | ||
e5198075 YL |
3874 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3875 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3876 | { |
3877 | struct irq_desc *desc; | |
3878 | struct irq_cfg *cfg; | |
3879 | int node; | |
e5198075 YL |
3880 | int ioapic, pin; |
3881 | int trigger, polarity; | |
5ef21837 | 3882 | |
e5198075 | 3883 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3884 | if (!IO_APIC_IRQ(irq)) { |
3885 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3886 | ioapic); | |
3887 | return -EINVAL; | |
3888 | } | |
3889 | ||
3890 | if (dev) | |
3891 | node = dev_to_node(dev); | |
3892 | else | |
3893 | node = cpu_to_node(boot_cpu_id); | |
3894 | ||
3895 | desc = irq_to_desc_alloc_node(irq, node); | |
3896 | if (!desc) { | |
3897 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3898 | return 0; | |
3899 | } | |
3900 | ||
e5198075 YL |
3901 | pin = irq_attr->ioapic_pin; |
3902 | trigger = irq_attr->trigger; | |
3903 | polarity = irq_attr->polarity; | |
3904 | ||
5ef21837 YL |
3905 | /* |
3906 | * IRQs < 16 are already in the irq_2_pin[] map | |
3907 | */ | |
3908 | if (irq >= NR_IRQS_LEGACY) { | |
3909 | cfg = desc->chip_data; | |
3910 | add_pin_to_irq_node(cfg, node, ioapic, pin); | |
3911 | } | |
3912 | ||
e5198075 | 3913 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3914 | |
3915 | return 0; | |
3916 | } | |
3917 | ||
e5198075 YL |
3918 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3919 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3920 | { |
e5198075 | 3921 | int ioapic, pin; |
5ef21837 YL |
3922 | /* |
3923 | * Avoid pin reprogramming. PRTs typically include entries | |
3924 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3925 | * we only program the IOAPIC on the first. | |
3926 | */ | |
e5198075 YL |
3927 | ioapic = irq_attr->ioapic; |
3928 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3929 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3930 | pr_debug("Pin %d-%d already programmed\n", | |
3931 | mp_ioapics[ioapic].apicid, pin); | |
3932 | return 0; | |
3933 | } | |
3934 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3935 | ||
e5198075 | 3936 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3937 | } |
3938 | ||
1da177e4 | 3939 | /* -------------------------------------------------------------------------- |
54168ed7 | 3940 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3941 | -------------------------------------------------------------------------- */ |
3942 | ||
888ba6c6 | 3943 | #ifdef CONFIG_ACPI |
1da177e4 | 3944 | |
54168ed7 | 3945 | #ifdef CONFIG_X86_32 |
36062448 | 3946 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3947 | { |
3948 | union IO_APIC_reg_00 reg_00; | |
3949 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3950 | physid_mask_t tmp; | |
3951 | unsigned long flags; | |
3952 | int i = 0; | |
3953 | ||
3954 | /* | |
36062448 PC |
3955 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3956 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3957 | * supports up to 16 on one shared APIC bus. |
36062448 | 3958 | * |
1da177e4 LT |
3959 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3960 | * advantage of new APIC bus architecture. | |
3961 | */ | |
3962 | ||
3963 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3964 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3965 | |
3966 | spin_lock_irqsave(&ioapic_lock, flags); | |
3967 | reg_00.raw = io_apic_read(ioapic, 0); | |
3968 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3969 | ||
3970 | if (apic_id >= get_physical_broadcast()) { | |
3971 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3972 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3973 | apic_id = reg_00.bits.ID; | |
3974 | } | |
3975 | ||
3976 | /* | |
36062448 | 3977 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3978 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3979 | */ | |
d1d7cae8 | 3980 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3981 | |
3982 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3983 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3984 | break; |
3985 | } | |
3986 | ||
3987 | if (i == get_physical_broadcast()) | |
3988 | panic("Max apic_id exceeded!\n"); | |
3989 | ||
3990 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3991 | "trying %d\n", ioapic, apic_id, i); | |
3992 | ||
3993 | apic_id = i; | |
36062448 | 3994 | } |
1da177e4 | 3995 | |
8058714a | 3996 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3997 | physids_or(apic_id_map, apic_id_map, tmp); |
3998 | ||
3999 | if (reg_00.bits.ID != apic_id) { | |
4000 | reg_00.bits.ID = apic_id; | |
4001 | ||
4002 | spin_lock_irqsave(&ioapic_lock, flags); | |
4003 | io_apic_write(ioapic, 0, reg_00.raw); | |
4004 | reg_00.raw = io_apic_read(ioapic, 0); | |
4005 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4006 | ||
4007 | /* Sanity check */ | |
6070f9ec AD |
4008 | if (reg_00.bits.ID != apic_id) { |
4009 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4010 | return -1; | |
4011 | } | |
1da177e4 LT |
4012 | } |
4013 | ||
4014 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4015 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4016 | ||
4017 | return apic_id; | |
4018 | } | |
58f892e0 | 4019 | #endif |
1da177e4 | 4020 | |
36062448 | 4021 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4022 | { |
4023 | union IO_APIC_reg_01 reg_01; | |
4024 | unsigned long flags; | |
4025 | ||
4026 | spin_lock_irqsave(&ioapic_lock, flags); | |
4027 | reg_01.raw = io_apic_read(ioapic, 1); | |
4028 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4029 | ||
4030 | return reg_01.bits.version; | |
4031 | } | |
4032 | ||
61fd47e0 SL |
4033 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4034 | { | |
4035 | int i; | |
4036 | ||
4037 | if (skip_ioapic_setup) | |
4038 | return -1; | |
4039 | ||
4040 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4041 | if (mp_irqs[i].irqtype == mp_INT && |
4042 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4043 | break; |
4044 | if (i >= mp_irq_entries) | |
4045 | return -1; | |
4046 | ||
4047 | *trigger = irq_trigger(i); | |
4048 | *polarity = irq_polarity(i); | |
4049 | return 0; | |
4050 | } | |
4051 | ||
888ba6c6 | 4052 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4053 | |
497c9a19 YL |
4054 | /* |
4055 | * This function currently is only a helper for the i386 smp boot process where | |
4056 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4057 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4058 | */ |
4059 | #ifdef CONFIG_SMP | |
4060 | void __init setup_ioapic_dest(void) | |
4061 | { | |
b9c61b70 | 4062 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4063 | struct irq_desc *desc; |
22f65d31 | 4064 | const struct cpumask *mask; |
497c9a19 YL |
4065 | |
4066 | if (skip_ioapic_setup == 1) | |
4067 | return; | |
4068 | ||
b9c61b70 YL |
4069 | #ifdef CONFIG_ACPI |
4070 | if (!acpi_disabled && acpi_ioapic) { | |
4071 | ioapic = mp_find_ioapic(0); | |
4072 | if (ioapic < 0) | |
4073 | ioapic = 0; | |
4074 | } | |
4075 | #endif | |
6c2e9403 | 4076 | |
b9c61b70 YL |
4077 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4078 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4079 | if (irq_entry == -1) | |
4080 | continue; | |
4081 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4082 | |
b9c61b70 | 4083 | desc = irq_to_desc(irq); |
6c2e9403 | 4084 | |
b9c61b70 YL |
4085 | /* |
4086 | * Honour affinities which have been set in early boot | |
4087 | */ | |
4088 | if (desc->status & | |
4089 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4090 | mask = desc->affinity; | |
4091 | else | |
4092 | mask = apic->target_cpus(); | |
497c9a19 | 4093 | |
b9c61b70 YL |
4094 | if (intr_remapping_enabled) |
4095 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4096 | else | |
4097 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4098 | } |
b9c61b70 | 4099 | |
497c9a19 YL |
4100 | } |
4101 | #endif | |
4102 | ||
54168ed7 IM |
4103 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4104 | ||
4105 | static struct resource *ioapic_resources; | |
4106 | ||
4107 | static struct resource * __init ioapic_setup_resources(void) | |
4108 | { | |
4109 | unsigned long n; | |
4110 | struct resource *res; | |
4111 | char *mem; | |
4112 | int i; | |
4113 | ||
4114 | if (nr_ioapics <= 0) | |
4115 | return NULL; | |
4116 | ||
4117 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4118 | n *= nr_ioapics; | |
4119 | ||
4120 | mem = alloc_bootmem(n); | |
4121 | res = (void *)mem; | |
4122 | ||
4123 | if (mem != NULL) { | |
4124 | mem += sizeof(struct resource) * nr_ioapics; | |
4125 | ||
4126 | for (i = 0; i < nr_ioapics; i++) { | |
4127 | res[i].name = mem; | |
4128 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4129 | sprintf(mem, "IOAPIC %u", i); | |
4130 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4131 | } | |
4132 | } | |
4133 | ||
4134 | ioapic_resources = res; | |
4135 | ||
4136 | return res; | |
4137 | } | |
54168ed7 | 4138 | |
f3294a33 YL |
4139 | void __init ioapic_init_mappings(void) |
4140 | { | |
4141 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4142 | struct resource *ioapic_res; |
d6c88a50 | 4143 | int i; |
f3294a33 | 4144 | |
54168ed7 | 4145 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4146 | for (i = 0; i < nr_ioapics; i++) { |
4147 | if (smp_found_config) { | |
b5ba7e6d | 4148 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4149 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4150 | if (!ioapic_phys) { |
4151 | printk(KERN_ERR | |
4152 | "WARNING: bogus zero IO-APIC " | |
4153 | "address found in MPTABLE, " | |
4154 | "disabling IO/APIC support!\n"); | |
4155 | smp_found_config = 0; | |
4156 | skip_ioapic_setup = 1; | |
4157 | goto fake_ioapic_page; | |
4158 | } | |
54168ed7 | 4159 | #endif |
f3294a33 | 4160 | } else { |
54168ed7 | 4161 | #ifdef CONFIG_X86_32 |
f3294a33 | 4162 | fake_ioapic_page: |
54168ed7 | 4163 | #endif |
f3294a33 | 4164 | ioapic_phys = (unsigned long) |
54168ed7 | 4165 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4166 | ioapic_phys = __pa(ioapic_phys); |
4167 | } | |
4168 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4169 | apic_printk(APIC_VERBOSE, |
4170 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4171 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4172 | idx++; |
54168ed7 | 4173 | |
54168ed7 IM |
4174 | if (ioapic_res != NULL) { |
4175 | ioapic_res->start = ioapic_phys; | |
4176 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4177 | ioapic_res++; | |
4178 | } | |
f3294a33 YL |
4179 | } |
4180 | } | |
4181 | ||
54168ed7 IM |
4182 | static int __init ioapic_insert_resources(void) |
4183 | { | |
4184 | int i; | |
4185 | struct resource *r = ioapic_resources; | |
4186 | ||
4187 | if (!r) { | |
04c93ce4 BZ |
4188 | if (nr_ioapics > 0) { |
4189 | printk(KERN_ERR | |
4190 | "IO APIC resources couldn't be allocated.\n"); | |
4191 | return -1; | |
4192 | } | |
4193 | return 0; | |
54168ed7 IM |
4194 | } |
4195 | ||
4196 | for (i = 0; i < nr_ioapics; i++) { | |
4197 | insert_resource(&iomem_resource, r); | |
4198 | r++; | |
4199 | } | |
4200 | ||
4201 | return 0; | |
4202 | } | |
4203 | ||
4204 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4205 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4206 | late_initcall(ioapic_insert_resources); |