Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
a4384df3 EB |
92 | /* The one past the highest gsi number used */ |
93 | u32 gsi_top; | |
5777372a | 94 | |
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
a1420f39 | 143 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 144 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 146 | #else |
97943390 | 147 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 148 | #endif |
a1420f39 | 149 | |
13a0c3c2 | 150 | int __init arch_early_irq_init(void) |
8f09cd20 | 151 | { |
0b8f1efa YL |
152 | struct irq_cfg *cfg; |
153 | struct irq_desc *desc; | |
154 | int count; | |
dad213ae | 155 | int node; |
0b8f1efa | 156 | int i; |
d6c88a50 | 157 | |
1f91233c JP |
158 | if (!legacy_pic->nr_legacy_irqs) { |
159 | nr_irqs_gsi = 0; | |
160 | io_apic_irqs = ~0UL; | |
161 | } | |
162 | ||
0b8f1efa YL |
163 | cfg = irq_cfgx; |
164 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 165 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 166 | |
0b8f1efa YL |
167 | for (i = 0; i < count; i++) { |
168 | desc = irq_to_desc(i); | |
169 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
170 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
171 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
172 | /* |
173 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
174 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
175 | */ | |
54b56170 | 176 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
177 | cfg[i].vector = IRQ0_VECTOR + i; |
178 | cpumask_set_cpu(0, cfg[i].domain); | |
179 | } | |
0b8f1efa | 180 | } |
13a0c3c2 YL |
181 | |
182 | return 0; | |
0b8f1efa | 183 | } |
8f09cd20 | 184 | |
0b8f1efa | 185 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 186 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 187 | { |
0b8f1efa YL |
188 | struct irq_cfg *cfg = NULL; |
189 | struct irq_desc *desc; | |
1da177e4 | 190 | |
0b8f1efa YL |
191 | desc = irq_to_desc(irq); |
192 | if (desc) | |
193 | cfg = desc->chip_data; | |
0f978f45 | 194 | |
0b8f1efa | 195 | return cfg; |
8f09cd20 | 196 | } |
d6c88a50 | 197 | |
85ac16d0 | 198 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 199 | { |
0b8f1efa | 200 | struct irq_cfg *cfg; |
0f978f45 | 201 | |
0b8f1efa | 202 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 203 | if (cfg) { |
79f55997 | 204 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
205 | kfree(cfg); |
206 | cfg = NULL; | |
79f55997 | 207 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 208 | GFP_ATOMIC, node)) { |
22f65d31 MT |
209 | free_cpumask_var(cfg->domain); |
210 | kfree(cfg); | |
211 | cfg = NULL; | |
22f65d31 MT |
212 | } |
213 | } | |
0f978f45 | 214 | |
0b8f1efa | 215 | return cfg; |
8f09cd20 YL |
216 | } |
217 | ||
85ac16d0 | 218 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 219 | { |
0b8f1efa | 220 | struct irq_cfg *cfg; |
d6c88a50 | 221 | |
0b8f1efa YL |
222 | cfg = desc->chip_data; |
223 | if (!cfg) { | |
85ac16d0 | 224 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
225 | if (!desc->chip_data) { |
226 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
227 | BUG_ON(1); | |
228 | } | |
229 | } | |
1da177e4 | 230 | |
13a0c3c2 | 231 | return 0; |
0b8f1efa | 232 | } |
0f978f45 | 233 | |
fcef5911 | 234 | /* for move_irq_desc */ |
48a1b10a | 235 | static void |
85ac16d0 | 236 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 237 | { |
48a1b10a YL |
238 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
239 | ||
240 | cfg->irq_2_pin = NULL; | |
241 | old_entry = old_cfg->irq_2_pin; | |
242 | if (!old_entry) | |
243 | return; | |
0f978f45 | 244 | |
85ac16d0 | 245 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
246 | if (!entry) |
247 | return; | |
0f978f45 | 248 | |
48a1b10a YL |
249 | entry->apic = old_entry->apic; |
250 | entry->pin = old_entry->pin; | |
251 | head = entry; | |
252 | tail = entry; | |
253 | old_entry = old_entry->next; | |
254 | while (old_entry) { | |
85ac16d0 | 255 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
256 | if (!entry) { |
257 | entry = head; | |
258 | while (entry) { | |
259 | head = entry->next; | |
260 | kfree(entry); | |
261 | entry = head; | |
262 | } | |
263 | /* still use the old one */ | |
264 | return; | |
265 | } | |
266 | entry->apic = old_entry->apic; | |
267 | entry->pin = old_entry->pin; | |
268 | tail->next = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | } | |
0f978f45 | 272 | |
48a1b10a YL |
273 | tail->next = NULL; |
274 | cfg->irq_2_pin = head; | |
0f978f45 | 275 | } |
0f978f45 | 276 | |
48a1b10a | 277 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 278 | { |
48a1b10a | 279 | struct irq_pin_list *entry, *next; |
0f978f45 | 280 | |
48a1b10a YL |
281 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
282 | return; | |
301e6190 | 283 | |
48a1b10a | 284 | entry = old_cfg->irq_2_pin; |
0f978f45 | 285 | |
48a1b10a YL |
286 | while (entry) { |
287 | next = entry->next; | |
288 | kfree(entry); | |
289 | entry = next; | |
290 | } | |
291 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 295 | struct irq_desc *desc, int node) |
0f978f45 | 296 | { |
48a1b10a YL |
297 | struct irq_cfg *cfg; |
298 | struct irq_cfg *old_cfg; | |
0f978f45 | 299 | |
85ac16d0 | 300 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 301 | |
48a1b10a YL |
302 | if (!cfg) |
303 | return; | |
304 | ||
305 | desc->chip_data = cfg; | |
306 | ||
307 | old_cfg = old_desc->chip_data; | |
308 | ||
309 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
310 | ||
85ac16d0 | 311 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 312 | } |
1da177e4 | 313 | |
48a1b10a YL |
314 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
315 | { | |
316 | kfree(old_cfg); | |
317 | } | |
318 | ||
319 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
320 | { | |
321 | struct irq_cfg *old_cfg, *cfg; | |
322 | ||
323 | old_cfg = old_desc->chip_data; | |
324 | cfg = desc->chip_data; | |
325 | ||
326 | if (old_cfg == cfg) | |
327 | return; | |
328 | ||
329 | if (old_cfg) { | |
330 | free_irq_2_pin(old_cfg, cfg); | |
331 | free_irq_cfg(old_cfg); | |
332 | old_desc->chip_data = NULL; | |
333 | } | |
334 | } | |
fcef5911 | 335 | /* end for move_irq_desc */ |
48a1b10a | 336 | |
0b8f1efa | 337 | #else |
9338ad6f | 338 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
339 | { |
340 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 341 | } |
1da177e4 | 342 | |
0b8f1efa YL |
343 | #endif |
344 | ||
130fe05d LT |
345 | struct io_apic { |
346 | unsigned int index; | |
347 | unsigned int unused[3]; | |
348 | unsigned int data; | |
0280f7c4 SS |
349 | unsigned int unused2[11]; |
350 | unsigned int eoi; | |
130fe05d LT |
351 | }; |
352 | ||
353 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
354 | { | |
355 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 356 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
357 | } |
358 | ||
0280f7c4 SS |
359 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
360 | { | |
361 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
362 | writel(vector, &io_apic->eoi); | |
363 | } | |
364 | ||
130fe05d LT |
365 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
366 | { | |
367 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
368 | writel(reg, &io_apic->index); | |
369 | return readl(&io_apic->data); | |
370 | } | |
371 | ||
372 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
373 | { | |
374 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
375 | writel(reg, &io_apic->index); | |
376 | writel(value, &io_apic->data); | |
377 | } | |
378 | ||
379 | /* | |
380 | * Re-write a value: to be used for read-modify-write | |
381 | * cycles where the read already set up the index register. | |
382 | * | |
383 | * Older SiS APIC requires we rewrite the index register | |
384 | */ | |
385 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
386 | { | |
54168ed7 | 387 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
388 | |
389 | if (sis_apic_bug) | |
390 | writel(reg, &io_apic->index); | |
130fe05d LT |
391 | writel(value, &io_apic->data); |
392 | } | |
393 | ||
3145e941 | 394 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
395 | { |
396 | struct irq_pin_list *entry; | |
397 | unsigned long flags; | |
047c8fdb | 398 | |
dade7716 | 399 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 400 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
401 | unsigned int reg; |
402 | int pin; | |
403 | ||
047c8fdb YL |
404 | pin = entry->pin; |
405 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
406 | /* Is the remote IRR bit set? */ | |
407 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 408 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
409 | return true; |
410 | } | |
047c8fdb | 411 | } |
dade7716 | 412 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
413 | |
414 | return false; | |
415 | } | |
047c8fdb | 416 | |
cf4c6a2f AK |
417 | union entry_union { |
418 | struct { u32 w1, w2; }; | |
419 | struct IO_APIC_route_entry entry; | |
420 | }; | |
421 | ||
422 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
423 | { | |
424 | union entry_union eu; | |
425 | unsigned long flags; | |
dade7716 | 426 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
427 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
428 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 429 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
430 | return eu.entry; |
431 | } | |
432 | ||
f9dadfa7 LT |
433 | /* |
434 | * When we write a new IO APIC routing entry, we need to write the high | |
435 | * word first! If the mask bit in the low word is clear, we will enable | |
436 | * the interrupt, and we need to make sure the entry is fully populated | |
437 | * before that happens. | |
438 | */ | |
d15512f4 AK |
439 | static void |
440 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 441 | { |
50a8d4d2 F |
442 | union entry_union eu = {{0, 0}}; |
443 | ||
cf4c6a2f | 444 | eu.entry = e; |
f9dadfa7 LT |
445 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
446 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
447 | } |
448 | ||
ca97ab90 | 449 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
450 | { |
451 | unsigned long flags; | |
dade7716 | 452 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 453 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 454 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
455 | } |
456 | ||
457 | /* | |
458 | * When we mask an IO APIC routing entry, we need to write the low | |
459 | * word first, in order to set the mask bit before we change the | |
460 | * high bits! | |
461 | */ | |
462 | static void ioapic_mask_entry(int apic, int pin) | |
463 | { | |
464 | unsigned long flags; | |
465 | union entry_union eu = { .entry.mask = 1 }; | |
466 | ||
dade7716 | 467 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
468 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
469 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 470 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
471 | } |
472 | ||
1da177e4 LT |
473 | /* |
474 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
475 | * shared ISA-space IRQs, so we have to support them. We are super | |
476 | * fast in the common case, and fast for shared ISA-space IRQs. | |
477 | */ | |
f3d1915a CG |
478 | static int |
479 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 480 | { |
2977fb3f | 481 | struct irq_pin_list **last, *entry; |
0f978f45 | 482 | |
2977fb3f CG |
483 | /* don't allow duplicates */ |
484 | last = &cfg->irq_2_pin; | |
485 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 486 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 487 | return 0; |
2977fb3f | 488 | last = &entry->next; |
1da177e4 | 489 | } |
0f978f45 | 490 | |
875e68ec | 491 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 492 | if (!entry) { |
f3d1915a CG |
493 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
494 | node, apic, pin); | |
495 | return -ENOMEM; | |
a7428cd2 | 496 | } |
1da177e4 LT |
497 | entry->apic = apic; |
498 | entry->pin = pin; | |
875e68ec | 499 | |
2977fb3f | 500 | *last = entry; |
f3d1915a CG |
501 | return 0; |
502 | } | |
503 | ||
504 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
505 | { | |
506 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
507 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
508 | } |
509 | ||
510 | /* | |
511 | * Reroute an IRQ to a different pin. | |
512 | */ | |
85ac16d0 | 513 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
514 | int oldapic, int oldpin, |
515 | int newapic, int newpin) | |
1da177e4 | 516 | { |
535b6429 | 517 | struct irq_pin_list *entry; |
1da177e4 | 518 | |
2977fb3f | 519 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
520 | if (entry->apic == oldapic && entry->pin == oldpin) { |
521 | entry->apic = newapic; | |
522 | entry->pin = newpin; | |
0f978f45 | 523 | /* every one is different, right? */ |
4eea6fff | 524 | return; |
0f978f45 | 525 | } |
1da177e4 | 526 | } |
0f978f45 | 527 | |
4eea6fff JF |
528 | /* old apic/pin didn't exist, so just add new ones */ |
529 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
530 | } |
531 | ||
c29d9db3 SS |
532 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
533 | int mask_and, int mask_or, | |
534 | void (*final)(struct irq_pin_list *entry)) | |
535 | { | |
536 | unsigned int reg, pin; | |
537 | ||
538 | pin = entry->pin; | |
539 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
540 | reg &= mask_and; | |
541 | reg |= mask_or; | |
542 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
543 | if (final) | |
544 | final(entry); | |
545 | } | |
546 | ||
2f210deb JF |
547 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
548 | int mask_and, int mask_or, | |
549 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 550 | { |
87783be4 | 551 | struct irq_pin_list *entry; |
047c8fdb | 552 | |
c29d9db3 SS |
553 | for_each_irq_pin(entry, cfg->irq_2_pin) |
554 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
555 | } | |
556 | ||
557 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
558 | { | |
559 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
560 | IO_APIC_REDIR_MASKED, NULL); | |
561 | } | |
562 | ||
563 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
564 | { | |
565 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
566 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 567 | } |
047c8fdb | 568 | |
3145e941 | 569 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 570 | { |
3145e941 | 571 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 572 | } |
047c8fdb | 573 | |
7f3e632f | 574 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 575 | { |
87783be4 CG |
576 | /* |
577 | * Synchronize the IO-APIC and the CPU by doing | |
578 | * a dummy read from the IO-APIC | |
579 | */ | |
580 | struct io_apic __iomem *io_apic; | |
581 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 582 | readl(&io_apic->data); |
1da177e4 LT |
583 | } |
584 | ||
3145e941 | 585 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 586 | { |
3145e941 | 587 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 588 | } |
1da177e4 | 589 | |
3145e941 | 590 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 591 | { |
3145e941 | 592 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
593 | unsigned long flags; |
594 | ||
3145e941 YL |
595 | BUG_ON(!cfg); |
596 | ||
dade7716 | 597 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 598 | __mask_IO_APIC_irq(cfg); |
dade7716 | 599 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
600 | } |
601 | ||
3145e941 | 602 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 603 | { |
3145e941 | 604 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
605 | unsigned long flags; |
606 | ||
dade7716 | 607 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 608 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 609 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
610 | } |
611 | ||
3145e941 YL |
612 | static void mask_IO_APIC_irq(unsigned int irq) |
613 | { | |
614 | struct irq_desc *desc = irq_to_desc(irq); | |
615 | ||
616 | mask_IO_APIC_irq_desc(desc); | |
617 | } | |
618 | static void unmask_IO_APIC_irq(unsigned int irq) | |
619 | { | |
620 | struct irq_desc *desc = irq_to_desc(irq); | |
621 | ||
622 | unmask_IO_APIC_irq_desc(desc); | |
623 | } | |
624 | ||
1da177e4 LT |
625 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
626 | { | |
627 | struct IO_APIC_route_entry entry; | |
36062448 | 628 | |
1da177e4 | 629 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 630 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
631 | if (entry.delivery_mode == dest_SMI) |
632 | return; | |
1da177e4 LT |
633 | /* |
634 | * Disable it in the IO-APIC irq-routing table: | |
635 | */ | |
f9dadfa7 | 636 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
637 | } |
638 | ||
54168ed7 | 639 | static void clear_IO_APIC (void) |
1da177e4 LT |
640 | { |
641 | int apic, pin; | |
642 | ||
643 | for (apic = 0; apic < nr_ioapics; apic++) | |
644 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
645 | clear_IO_APIC_pin(apic, pin); | |
646 | } | |
647 | ||
54168ed7 | 648 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
649 | /* |
650 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
651 | * specific CPU-side IRQs. | |
652 | */ | |
653 | ||
654 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
655 | static int pirq_entries[MAX_PIRQS] = { |
656 | [0 ... MAX_PIRQS - 1] = -1 | |
657 | }; | |
1da177e4 | 658 | |
1da177e4 LT |
659 | static int __init ioapic_pirq_setup(char *str) |
660 | { | |
661 | int i, max; | |
662 | int ints[MAX_PIRQS+1]; | |
663 | ||
664 | get_options(str, ARRAY_SIZE(ints), ints); | |
665 | ||
1da177e4 LT |
666 | apic_printk(APIC_VERBOSE, KERN_INFO |
667 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
668 | max = MAX_PIRQS; | |
669 | if (ints[0] < MAX_PIRQS) | |
670 | max = ints[0]; | |
671 | ||
672 | for (i = 0; i < max; i++) { | |
673 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
674 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
675 | /* | |
676 | * PIRQs are mapped upside down, usually. | |
677 | */ | |
678 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
679 | } | |
680 | return 1; | |
681 | } | |
682 | ||
683 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
684 | #endif /* CONFIG_X86_32 */ |
685 | ||
b24696bc FY |
686 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
687 | { | |
688 | int apic; | |
689 | struct IO_APIC_route_entry **ioapic_entries; | |
690 | ||
691 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
692 | GFP_ATOMIC); | |
693 | if (!ioapic_entries) | |
694 | return 0; | |
695 | ||
696 | for (apic = 0; apic < nr_ioapics; apic++) { | |
697 | ioapic_entries[apic] = | |
698 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
699 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
700 | if (!ioapic_entries[apic]) | |
701 | goto nomem; | |
702 | } | |
703 | ||
704 | return ioapic_entries; | |
705 | ||
706 | nomem: | |
707 | while (--apic >= 0) | |
708 | kfree(ioapic_entries[apic]); | |
709 | kfree(ioapic_entries); | |
710 | ||
711 | return 0; | |
712 | } | |
54168ed7 IM |
713 | |
714 | /* | |
05c3dc2c | 715 | * Saves all the IO-APIC RTE's |
54168ed7 | 716 | */ |
b24696bc | 717 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 718 | { |
54168ed7 IM |
719 | int apic, pin; |
720 | ||
b24696bc FY |
721 | if (!ioapic_entries) |
722 | return -ENOMEM; | |
54168ed7 IM |
723 | |
724 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
725 | if (!ioapic_entries[apic]) |
726 | return -ENOMEM; | |
54168ed7 | 727 | |
05c3dc2c | 728 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 729 | ioapic_entries[apic][pin] = |
54168ed7 | 730 | ioapic_read_entry(apic, pin); |
b24696bc | 731 | } |
5ffa4eb2 | 732 | |
54168ed7 IM |
733 | return 0; |
734 | } | |
735 | ||
b24696bc FY |
736 | /* |
737 | * Mask all IO APIC entries. | |
738 | */ | |
739 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
740 | { |
741 | int apic, pin; | |
742 | ||
b24696bc FY |
743 | if (!ioapic_entries) |
744 | return; | |
745 | ||
05c3dc2c | 746 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 747 | if (!ioapic_entries[apic]) |
05c3dc2c | 748 | break; |
b24696bc | 749 | |
05c3dc2c SS |
750 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
751 | struct IO_APIC_route_entry entry; | |
752 | ||
b24696bc | 753 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
754 | if (!entry.mask) { |
755 | entry.mask = 1; | |
756 | ioapic_write_entry(apic, pin, entry); | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
b24696bc FY |
762 | /* |
763 | * Restore IO APIC entries which was saved in ioapic_entries. | |
764 | */ | |
765 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
766 | { |
767 | int apic, pin; | |
768 | ||
b24696bc FY |
769 | if (!ioapic_entries) |
770 | return -ENOMEM; | |
771 | ||
5ffa4eb2 | 772 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
773 | if (!ioapic_entries[apic]) |
774 | return -ENOMEM; | |
775 | ||
54168ed7 IM |
776 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
777 | ioapic_write_entry(apic, pin, | |
b24696bc | 778 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 779 | } |
b24696bc | 780 | return 0; |
54168ed7 IM |
781 | } |
782 | ||
b24696bc FY |
783 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
784 | { | |
785 | int apic; | |
786 | ||
787 | for (apic = 0; apic < nr_ioapics; apic++) | |
788 | kfree(ioapic_entries[apic]); | |
789 | ||
790 | kfree(ioapic_entries); | |
54168ed7 | 791 | } |
1da177e4 LT |
792 | |
793 | /* | |
794 | * Find the IRQ entry number of a certain pin. | |
795 | */ | |
796 | static int find_irq_entry(int apic, int pin, int type) | |
797 | { | |
798 | int i; | |
799 | ||
800 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
801 | if (mp_irqs[i].irqtype == type && |
802 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
803 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
804 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
805 | return i; |
806 | ||
807 | return -1; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Find the pin to which IRQ[irq] (ISA) is connected | |
812 | */ | |
fcfd636a | 813 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
814 | { |
815 | int i; | |
816 | ||
817 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 818 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 819 | |
d27e2b8e | 820 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
821 | (mp_irqs[i].irqtype == type) && |
822 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 823 | |
c2c21745 | 824 | return mp_irqs[i].dstirq; |
1da177e4 LT |
825 | } |
826 | return -1; | |
827 | } | |
828 | ||
fcfd636a EB |
829 | static int __init find_isa_irq_apic(int irq, int type) |
830 | { | |
831 | int i; | |
832 | ||
833 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 834 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 835 | |
73b2961b | 836 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
837 | (mp_irqs[i].irqtype == type) && |
838 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
839 | break; |
840 | } | |
841 | if (i < mp_irq_entries) { | |
842 | int apic; | |
54168ed7 | 843 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 844 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
845 | return apic; |
846 | } | |
847 | } | |
848 | ||
849 | return -1; | |
850 | } | |
851 | ||
c0a282c2 | 852 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
853 | /* |
854 | * EISA Edge/Level control register, ELCR | |
855 | */ | |
856 | static int EISA_ELCR(unsigned int irq) | |
857 | { | |
b81bb373 | 858 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
859 | unsigned int port = 0x4d0 + (irq >> 3); |
860 | return (inb(port) >> (irq & 7)) & 1; | |
861 | } | |
862 | apic_printk(APIC_VERBOSE, KERN_INFO | |
863 | "Broken MPtable reports ISA irq %d\n", irq); | |
864 | return 0; | |
865 | } | |
54168ed7 | 866 | |
c0a282c2 | 867 | #endif |
1da177e4 | 868 | |
6728801d AS |
869 | /* ISA interrupts are always polarity zero edge triggered, |
870 | * when listed as conforming in the MP table. */ | |
871 | ||
872 | #define default_ISA_trigger(idx) (0) | |
873 | #define default_ISA_polarity(idx) (0) | |
874 | ||
1da177e4 LT |
875 | /* EISA interrupts are always polarity zero and can be edge or level |
876 | * trigger depending on the ELCR value. If an interrupt is listed as | |
877 | * EISA conforming in the MP table, that means its trigger type must | |
878 | * be read in from the ELCR */ | |
879 | ||
c2c21745 | 880 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 881 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
882 | |
883 | /* PCI interrupts are always polarity one level triggered, | |
884 | * when listed as conforming in the MP table. */ | |
885 | ||
886 | #define default_PCI_trigger(idx) (1) | |
887 | #define default_PCI_polarity(idx) (1) | |
888 | ||
889 | /* MCA interrupts are always polarity zero level triggered, | |
890 | * when listed as conforming in the MP table. */ | |
891 | ||
892 | #define default_MCA_trigger(idx) (1) | |
6728801d | 893 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 894 | |
61fd47e0 | 895 | static int MPBIOS_polarity(int idx) |
1da177e4 | 896 | { |
c2c21745 | 897 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
898 | int polarity; |
899 | ||
900 | /* | |
901 | * Determine IRQ line polarity (high active or low active): | |
902 | */ | |
c2c21745 | 903 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 904 | { |
54168ed7 IM |
905 | case 0: /* conforms, ie. bus-type dependent polarity */ |
906 | if (test_bit(bus, mp_bus_not_pci)) | |
907 | polarity = default_ISA_polarity(idx); | |
908 | else | |
909 | polarity = default_PCI_polarity(idx); | |
910 | break; | |
911 | case 1: /* high active */ | |
912 | { | |
913 | polarity = 0; | |
914 | break; | |
915 | } | |
916 | case 2: /* reserved */ | |
917 | { | |
918 | printk(KERN_WARNING "broken BIOS!!\n"); | |
919 | polarity = 1; | |
920 | break; | |
921 | } | |
922 | case 3: /* low active */ | |
923 | { | |
924 | polarity = 1; | |
925 | break; | |
926 | } | |
927 | default: /* invalid */ | |
928 | { | |
929 | printk(KERN_WARNING "broken BIOS!!\n"); | |
930 | polarity = 1; | |
931 | break; | |
932 | } | |
1da177e4 LT |
933 | } |
934 | return polarity; | |
935 | } | |
936 | ||
937 | static int MPBIOS_trigger(int idx) | |
938 | { | |
c2c21745 | 939 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
940 | int trigger; |
941 | ||
942 | /* | |
943 | * Determine IRQ trigger mode (edge or level sensitive): | |
944 | */ | |
c2c21745 | 945 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 946 | { |
54168ed7 IM |
947 | case 0: /* conforms, ie. bus-type dependent */ |
948 | if (test_bit(bus, mp_bus_not_pci)) | |
949 | trigger = default_ISA_trigger(idx); | |
950 | else | |
951 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 952 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
953 | switch (mp_bus_id_to_type[bus]) { |
954 | case MP_BUS_ISA: /* ISA pin */ | |
955 | { | |
956 | /* set before the switch */ | |
957 | break; | |
958 | } | |
959 | case MP_BUS_EISA: /* EISA pin */ | |
960 | { | |
961 | trigger = default_EISA_trigger(idx); | |
962 | break; | |
963 | } | |
964 | case MP_BUS_PCI: /* PCI pin */ | |
965 | { | |
966 | /* set before the switch */ | |
967 | break; | |
968 | } | |
969 | case MP_BUS_MCA: /* MCA pin */ | |
970 | { | |
971 | trigger = default_MCA_trigger(idx); | |
972 | break; | |
973 | } | |
974 | default: | |
975 | { | |
976 | printk(KERN_WARNING "broken BIOS!!\n"); | |
977 | trigger = 1; | |
978 | break; | |
979 | } | |
980 | } | |
981 | #endif | |
1da177e4 | 982 | break; |
54168ed7 | 983 | case 1: /* edge */ |
1da177e4 | 984 | { |
54168ed7 | 985 | trigger = 0; |
1da177e4 LT |
986 | break; |
987 | } | |
54168ed7 | 988 | case 2: /* reserved */ |
1da177e4 | 989 | { |
54168ed7 IM |
990 | printk(KERN_WARNING "broken BIOS!!\n"); |
991 | trigger = 1; | |
1da177e4 LT |
992 | break; |
993 | } | |
54168ed7 | 994 | case 3: /* level */ |
1da177e4 | 995 | { |
54168ed7 | 996 | trigger = 1; |
1da177e4 LT |
997 | break; |
998 | } | |
54168ed7 | 999 | default: /* invalid */ |
1da177e4 LT |
1000 | { |
1001 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1002 | trigger = 0; |
1da177e4 LT |
1003 | break; |
1004 | } | |
1005 | } | |
1006 | return trigger; | |
1007 | } | |
1008 | ||
1009 | static inline int irq_polarity(int idx) | |
1010 | { | |
1011 | return MPBIOS_polarity(idx); | |
1012 | } | |
1013 | ||
1014 | static inline int irq_trigger(int idx) | |
1015 | { | |
1016 | return MPBIOS_trigger(idx); | |
1017 | } | |
1018 | ||
1019 | static int pin_2_irq(int idx, int apic, int pin) | |
1020 | { | |
d464207c | 1021 | int irq; |
c2c21745 | 1022 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1023 | |
1024 | /* | |
1025 | * Debugging check, we are in big trouble if this message pops up! | |
1026 | */ | |
c2c21745 | 1027 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1028 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1029 | ||
54168ed7 | 1030 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1031 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1032 | } else { |
d464207c | 1033 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
1034 | |
1035 | if (gsi >= NR_IRQS_LEGACY) | |
1036 | irq = gsi; | |
1037 | else | |
a4384df3 | 1038 | irq = gsi_top + gsi; |
1da177e4 LT |
1039 | } |
1040 | ||
54168ed7 | 1041 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1042 | /* |
1043 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1044 | */ | |
1045 | if ((pin >= 16) && (pin <= 23)) { | |
1046 | if (pirq_entries[pin-16] != -1) { | |
1047 | if (!pirq_entries[pin-16]) { | |
1048 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1049 | "disabling PIRQ%d\n", pin-16); | |
1050 | } else { | |
1051 | irq = pirq_entries[pin-16]; | |
1052 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1053 | "using PIRQ%d -> IRQ %d\n", | |
1054 | pin-16, irq); | |
1055 | } | |
1056 | } | |
1057 | } | |
54168ed7 IM |
1058 | #endif |
1059 | ||
1da177e4 LT |
1060 | return irq; |
1061 | } | |
1062 | ||
e20c06fd YL |
1063 | /* |
1064 | * Find a specific PCI IRQ entry. | |
1065 | * Not an __init, possibly needed by modules | |
1066 | */ | |
1067 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1068 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1069 | { |
1070 | int apic, i, best_guess = -1; | |
1071 | ||
1072 | apic_printk(APIC_DEBUG, | |
1073 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1074 | bus, slot, pin); | |
1075 | if (test_bit(bus, mp_bus_not_pci)) { | |
1076 | apic_printk(APIC_VERBOSE, | |
1077 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1078 | return -1; | |
1079 | } | |
1080 | for (i = 0; i < mp_irq_entries; i++) { | |
1081 | int lbus = mp_irqs[i].srcbus; | |
1082 | ||
1083 | for (apic = 0; apic < nr_ioapics; apic++) | |
1084 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1085 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1086 | break; | |
1087 | ||
1088 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1089 | !mp_irqs[i].irqtype && | |
1090 | (bus == lbus) && | |
1091 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1092 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1093 | ||
1094 | if (!(apic || IO_APIC_IRQ(irq))) | |
1095 | continue; | |
1096 | ||
1097 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1098 | set_io_apic_irq_attr(irq_attr, apic, |
1099 | mp_irqs[i].dstirq, | |
1100 | irq_trigger(i), | |
1101 | irq_polarity(i)); | |
e20c06fd YL |
1102 | return irq; |
1103 | } | |
1104 | /* | |
1105 | * Use the first all-but-pin matching entry as a | |
1106 | * best-guess fuzzy result for broken mptables. | |
1107 | */ | |
1108 | if (best_guess < 0) { | |
e5198075 YL |
1109 | set_io_apic_irq_attr(irq_attr, apic, |
1110 | mp_irqs[i].dstirq, | |
1111 | irq_trigger(i), | |
1112 | irq_polarity(i)); | |
e20c06fd YL |
1113 | best_guess = irq; |
1114 | } | |
1115 | } | |
1116 | } | |
1117 | return best_guess; | |
1118 | } | |
1119 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1120 | ||
497c9a19 YL |
1121 | void lock_vector_lock(void) |
1122 | { | |
1123 | /* Used to the online set of cpus does not change | |
1124 | * during assign_irq_vector. | |
1125 | */ | |
dade7716 | 1126 | raw_spin_lock(&vector_lock); |
497c9a19 | 1127 | } |
1da177e4 | 1128 | |
497c9a19 | 1129 | void unlock_vector_lock(void) |
1da177e4 | 1130 | { |
dade7716 | 1131 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1132 | } |
1da177e4 | 1133 | |
e7986739 MT |
1134 | static int |
1135 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1136 | { |
047c8fdb YL |
1137 | /* |
1138 | * NOTE! The local APIC isn't very good at handling | |
1139 | * multiple interrupts at the same interrupt level. | |
1140 | * As the interrupt level is determined by taking the | |
1141 | * vector number and shifting that right by 4, we | |
1142 | * want to spread these out a bit so that they don't | |
1143 | * all fall in the same interrupt level. | |
1144 | * | |
1145 | * Also, we've got to be careful not to trash gate | |
1146 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1147 | */ | |
6579b474 | 1148 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1149 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1150 | unsigned int old_vector; |
22f65d31 MT |
1151 | int cpu, err; |
1152 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1153 | |
23359a88 | 1154 | if (cfg->move_in_progress) |
54168ed7 | 1155 | return -EBUSY; |
0a1ad60d | 1156 | |
22f65d31 MT |
1157 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1158 | return -ENOMEM; | |
ace80ab7 | 1159 | |
54168ed7 IM |
1160 | old_vector = cfg->vector; |
1161 | if (old_vector) { | |
22f65d31 MT |
1162 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1163 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1164 | if (!cpumask_empty(tmp_mask)) { | |
1165 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1166 | return 0; |
22f65d31 | 1167 | } |
54168ed7 | 1168 | } |
497c9a19 | 1169 | |
e7986739 | 1170 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1171 | err = -ENOSPC; |
1172 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1173 | int new_cpu; |
1174 | int vector, offset; | |
497c9a19 | 1175 | |
e2d40b18 | 1176 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1177 | |
54168ed7 IM |
1178 | vector = current_vector; |
1179 | offset = current_offset; | |
497c9a19 | 1180 | next: |
54168ed7 IM |
1181 | vector += 8; |
1182 | if (vector >= first_system_vector) { | |
e7986739 | 1183 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1184 | offset = (offset + 1) % 8; |
6579b474 | 1185 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1186 | } |
1187 | if (unlikely(current_vector == vector)) | |
1188 | continue; | |
b77b881f YL |
1189 | |
1190 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1191 | goto next; |
b77b881f | 1192 | |
22f65d31 | 1193 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1194 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1195 | goto next; | |
1196 | /* Found one! */ | |
1197 | current_vector = vector; | |
1198 | current_offset = offset; | |
1199 | if (old_vector) { | |
1200 | cfg->move_in_progress = 1; | |
22f65d31 | 1201 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1202 | } |
22f65d31 | 1203 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1204 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1205 | cfg->vector = vector; | |
22f65d31 MT |
1206 | cpumask_copy(cfg->domain, tmp_mask); |
1207 | err = 0; | |
1208 | break; | |
54168ed7 | 1209 | } |
22f65d31 MT |
1210 | free_cpumask_var(tmp_mask); |
1211 | return err; | |
497c9a19 YL |
1212 | } |
1213 | ||
9338ad6f | 1214 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1215 | { |
1216 | int err; | |
ace80ab7 | 1217 | unsigned long flags; |
ace80ab7 | 1218 | |
dade7716 | 1219 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1220 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1221 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1222 | return err; |
1223 | } | |
1224 | ||
3145e941 | 1225 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1226 | { |
497c9a19 YL |
1227 | int cpu, vector; |
1228 | ||
497c9a19 YL |
1229 | BUG_ON(!cfg->vector); |
1230 | ||
1231 | vector = cfg->vector; | |
22f65d31 | 1232 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1233 | per_cpu(vector_irq, cpu)[vector] = -1; |
1234 | ||
1235 | cfg->vector = 0; | |
22f65d31 | 1236 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1237 | |
1238 | if (likely(!cfg->move_in_progress)) | |
1239 | return; | |
22f65d31 | 1240 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1241 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1242 | vector++) { | |
1243 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1244 | continue; | |
1245 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1246 | break; | |
1247 | } | |
1248 | } | |
1249 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1250 | } |
1251 | ||
1252 | void __setup_vector_irq(int cpu) | |
1253 | { | |
1254 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1255 | int irq, vector; |
1256 | struct irq_cfg *cfg; | |
0b8f1efa | 1257 | struct irq_desc *desc; |
497c9a19 | 1258 | |
9d133e5d SS |
1259 | /* |
1260 | * vector_lock will make sure that we don't run into irq vector | |
1261 | * assignments that might be happening on another cpu in parallel, | |
1262 | * while we setup our initial vector to irq mappings. | |
1263 | */ | |
dade7716 | 1264 | raw_spin_lock(&vector_lock); |
497c9a19 | 1265 | /* Mark the inuse vectors */ |
0b8f1efa | 1266 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1267 | cfg = desc->chip_data; |
36e9e1ea SS |
1268 | |
1269 | /* | |
1270 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1271 | * will be part of the irq_cfg's domain. | |
1272 | */ | |
1273 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1274 | cpumask_set_cpu(cpu, cfg->domain); | |
1275 | ||
22f65d31 | 1276 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1277 | continue; |
1278 | vector = cfg->vector; | |
497c9a19 YL |
1279 | per_cpu(vector_irq, cpu)[vector] = irq; |
1280 | } | |
1281 | /* Mark the free vectors */ | |
1282 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1283 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1284 | if (irq < 0) | |
1285 | continue; | |
1286 | ||
1287 | cfg = irq_cfg(irq); | |
22f65d31 | 1288 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1289 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1290 | } |
dade7716 | 1291 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1292 | } |
3fde6900 | 1293 | |
f5b9ed7a | 1294 | static struct irq_chip ioapic_chip; |
54168ed7 | 1295 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1296 | |
54168ed7 IM |
1297 | #define IOAPIC_AUTO -1 |
1298 | #define IOAPIC_EDGE 0 | |
1299 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1300 | |
047c8fdb | 1301 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1302 | static inline int IO_APIC_irq_trigger(int irq) |
1303 | { | |
d6c88a50 | 1304 | int apic, idx, pin; |
1d025192 | 1305 | |
d6c88a50 TG |
1306 | for (apic = 0; apic < nr_ioapics; apic++) { |
1307 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1308 | idx = find_irq_entry(apic, pin, mp_INT); | |
1309 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1310 | return irq_trigger(idx); | |
1311 | } | |
1312 | } | |
1313 | /* | |
54168ed7 IM |
1314 | * nonexistent IRQs are edge default |
1315 | */ | |
d6c88a50 | 1316 | return 0; |
1d025192 | 1317 | } |
047c8fdb YL |
1318 | #else |
1319 | static inline int IO_APIC_irq_trigger(int irq) | |
1320 | { | |
54168ed7 | 1321 | return 1; |
047c8fdb YL |
1322 | } |
1323 | #endif | |
1d025192 | 1324 | |
3145e941 | 1325 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1326 | { |
199751d7 | 1327 | |
6ebcc00e | 1328 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1329 | trigger == IOAPIC_LEVEL) |
08678b08 | 1330 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1331 | else |
1332 | desc->status &= ~IRQ_LEVEL; | |
1333 | ||
54168ed7 IM |
1334 | if (irq_remapped(irq)) { |
1335 | desc->status |= IRQ_MOVE_PCNTXT; | |
1336 | if (trigger) | |
1337 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1338 | handle_fasteoi_irq, | |
1339 | "fasteoi"); | |
1340 | else | |
1341 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1342 | handle_edge_irq, "edge"); | |
1343 | return; | |
1344 | } | |
29b61be6 | 1345 | |
047c8fdb YL |
1346 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1347 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1348 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1349 | handle_fasteoi_irq, |
1350 | "fasteoi"); | |
047c8fdb | 1351 | else |
a460e745 | 1352 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1353 | handle_edge_irq, "edge"); |
1da177e4 LT |
1354 | } |
1355 | ||
ca97ab90 JF |
1356 | int setup_ioapic_entry(int apic_id, int irq, |
1357 | struct IO_APIC_route_entry *entry, | |
1358 | unsigned int destination, int trigger, | |
0280f7c4 | 1359 | int polarity, int vector, int pin) |
1da177e4 | 1360 | { |
497c9a19 YL |
1361 | /* |
1362 | * add it to the IO-APIC irq-routing table: | |
1363 | */ | |
1364 | memset(entry,0,sizeof(*entry)); | |
1365 | ||
54168ed7 | 1366 | if (intr_remapping_enabled) { |
c8d46cf0 | 1367 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1368 | struct irte irte; |
1369 | struct IR_IO_APIC_route_entry *ir_entry = | |
1370 | (struct IR_IO_APIC_route_entry *) entry; | |
1371 | int index; | |
1372 | ||
1373 | if (!iommu) | |
c8d46cf0 | 1374 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1375 | |
1376 | index = alloc_irte(iommu, irq, 1); | |
1377 | if (index < 0) | |
c8d46cf0 | 1378 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1379 | |
1380 | memset(&irte, 0, sizeof(irte)); | |
1381 | ||
1382 | irte.present = 1; | |
9b5bc8dc | 1383 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1384 | /* |
1385 | * Trigger mode in the IRTE will always be edge, and the | |
1386 | * actual level or edge trigger will be setup in the IO-APIC | |
1387 | * RTE. This will help simplify level triggered irq migration. | |
1388 | * For more details, see the comments above explainig IO-APIC | |
1389 | * irq migration in the presence of interrupt-remapping. | |
1390 | */ | |
1391 | irte.trigger_mode = 0; | |
9b5bc8dc | 1392 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1393 | irte.vector = vector; |
1394 | irte.dest_id = IRTE_DEST(destination); | |
75e3cfbe | 1395 | irte.redir_hint = 1; |
54168ed7 | 1396 | |
f007e99c WH |
1397 | /* Set source-id of interrupt request */ |
1398 | set_ioapic_sid(&irte, apic_id); | |
1399 | ||
54168ed7 IM |
1400 | modify_irte(irq, &irte); |
1401 | ||
1402 | ir_entry->index2 = (index >> 15) & 0x1; | |
1403 | ir_entry->zero = 0; | |
1404 | ir_entry->format = 1; | |
1405 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1406 | /* |
1407 | * IO-APIC RTE will be configured with virtual vector. | |
1408 | * irq handler will do the explicit EOI to the io-apic. | |
1409 | */ | |
1410 | ir_entry->vector = pin; | |
29b61be6 | 1411 | } else { |
9b5bc8dc IM |
1412 | entry->delivery_mode = apic->irq_delivery_mode; |
1413 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1414 | entry->dest = destination; |
0280f7c4 | 1415 | entry->vector = vector; |
54168ed7 | 1416 | } |
497c9a19 | 1417 | |
54168ed7 | 1418 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1419 | entry->trigger = trigger; |
1420 | entry->polarity = polarity; | |
497c9a19 YL |
1421 | |
1422 | /* Mask level triggered irqs. | |
1423 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1424 | */ | |
1425 | if (trigger) | |
1426 | entry->mask = 1; | |
497c9a19 YL |
1427 | return 0; |
1428 | } | |
1429 | ||
c8d46cf0 | 1430 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1431 | int trigger, int polarity) |
497c9a19 YL |
1432 | { |
1433 | struct irq_cfg *cfg; | |
1da177e4 | 1434 | struct IO_APIC_route_entry entry; |
22f65d31 | 1435 | unsigned int dest; |
497c9a19 YL |
1436 | |
1437 | if (!IO_APIC_IRQ(irq)) | |
1438 | return; | |
1439 | ||
3145e941 | 1440 | cfg = desc->chip_data; |
497c9a19 | 1441 | |
69c89efb SS |
1442 | /* |
1443 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1444 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1445 | * the cfg->domain. | |
1446 | */ | |
28c6a0ba | 1447 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1448 | apic->vector_allocation_domain(0, cfg->domain); |
1449 | ||
fe402e1f | 1450 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1451 | return; |
1452 | ||
debccb3e | 1453 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1454 | |
1455 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1456 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1457 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1458 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1459 | irq, trigger, polarity); |
1460 | ||
1461 | ||
c8d46cf0 | 1462 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1463 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1464 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1465 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1466 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1467 | return; |
1468 | } | |
1469 | ||
3145e941 | 1470 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 JP |
1471 | if (irq < legacy_pic->nr_legacy_irqs) |
1472 | legacy_pic->chip->mask(irq); | |
497c9a19 | 1473 | |
c8d46cf0 | 1474 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1475 | } |
1476 | ||
b9c61b70 YL |
1477 | static struct { |
1478 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1479 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1480 | ||
497c9a19 YL |
1481 | static void __init setup_IO_APIC_irqs(void) |
1482 | { | |
fad53995 | 1483 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1484 | int notcon = 0; |
0b8f1efa | 1485 | struct irq_desc *desc; |
3145e941 | 1486 | struct irq_cfg *cfg; |
85ac16d0 | 1487 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1488 | |
1489 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1490 | ||
fad53995 | 1491 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1492 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1493 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1494 | if (idx == -1) { | |
1495 | if (!notcon) { | |
1496 | notcon = 1; | |
1497 | apic_printk(APIC_VERBOSE, | |
1498 | KERN_DEBUG " %d-%d", | |
1499 | mp_ioapics[apic_id].apicid, pin); | |
1500 | } else | |
1501 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1502 | mp_ioapics[apic_id].apicid, pin); | |
1503 | continue; | |
1504 | } | |
1505 | if (notcon) { | |
1506 | apic_printk(APIC_VERBOSE, | |
1507 | " (apicid-pin) not connected\n"); | |
1508 | notcon = 0; | |
1509 | } | |
33a201fa | 1510 | |
b9c61b70 | 1511 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1512 | |
fad53995 EB |
1513 | if ((apic_id > 0) && (irq > 16)) |
1514 | continue; | |
1515 | ||
b9c61b70 YL |
1516 | /* |
1517 | * Skip the timer IRQ if there's a quirk handler | |
1518 | * installed and if it returns 1: | |
1519 | */ | |
1520 | if (apic->multi_timer_check && | |
1521 | apic->multi_timer_check(apic_id, irq)) | |
1522 | continue; | |
36062448 | 1523 | |
b9c61b70 YL |
1524 | desc = irq_to_desc_alloc_node(irq, node); |
1525 | if (!desc) { | |
1526 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1527 | continue; | |
3c2cbd24 | 1528 | } |
b9c61b70 YL |
1529 | cfg = desc->chip_data; |
1530 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1531 | /* |
1532 | * don't mark it in pin_programmed, so later acpi could | |
1533 | * set it correctly when irq < 16 | |
1534 | */ | |
b9c61b70 YL |
1535 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1536 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1537 | } |
1538 | ||
3c2cbd24 CG |
1539 | if (notcon) |
1540 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1541 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1542 | } |
1543 | ||
18dce6ba YL |
1544 | /* |
1545 | * for the gsit that is not in first ioapic | |
1546 | * but could not use acpi_register_gsi() | |
1547 | * like some special sci in IBM x3330 | |
1548 | */ | |
1549 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1550 | { | |
1551 | int apic_id = 0, pin, idx, irq; | |
1552 | int node = cpu_to_node(boot_cpu_id); | |
1553 | struct irq_desc *desc; | |
1554 | struct irq_cfg *cfg; | |
1555 | ||
1556 | /* | |
1557 | * Convert 'gsi' to 'ioapic.pin'. | |
1558 | */ | |
1559 | apic_id = mp_find_ioapic(gsi); | |
1560 | if (apic_id < 0) | |
1561 | return; | |
1562 | ||
1563 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1564 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1565 | if (idx == -1) | |
1566 | return; | |
1567 | ||
1568 | irq = pin_2_irq(idx, apic_id, pin); | |
1569 | #ifdef CONFIG_SPARSE_IRQ | |
1570 | desc = irq_to_desc(irq); | |
1571 | if (desc) | |
1572 | return; | |
1573 | #endif | |
1574 | desc = irq_to_desc_alloc_node(irq, node); | |
1575 | if (!desc) { | |
1576 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1577 | return; | |
1578 | } | |
1579 | ||
1580 | cfg = desc->chip_data; | |
1581 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
1582 | ||
1583 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1584 | pr_debug("Pin %d-%d already programmed\n", | |
1585 | mp_ioapics[apic_id].apicid, pin); | |
1586 | return; | |
1587 | } | |
1588 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1589 | ||
1590 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1591 | irq_trigger(idx), irq_polarity(idx)); | |
1592 | } | |
1593 | ||
1da177e4 | 1594 | /* |
f7633ce5 | 1595 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1596 | */ |
c8d46cf0 | 1597 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1598 | int vector) |
1da177e4 LT |
1599 | { |
1600 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1601 | |
54168ed7 IM |
1602 | if (intr_remapping_enabled) |
1603 | return; | |
54168ed7 | 1604 | |
36062448 | 1605 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1606 | |
1607 | /* | |
1608 | * We use logical delivery to get the timer IRQ | |
1609 | * to the first CPU. | |
1610 | */ | |
9b5bc8dc | 1611 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1612 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1613 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1614 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1615 | entry.polarity = 0; |
1616 | entry.trigger = 0; | |
1617 | entry.vector = vector; | |
1618 | ||
1619 | /* | |
1620 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1621 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1622 | */ |
54168ed7 | 1623 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1624 | |
1625 | /* | |
1626 | * Add it to the IO-APIC irq-routing table: | |
1627 | */ | |
c8d46cf0 | 1628 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1629 | } |
1630 | ||
32f71aff MR |
1631 | |
1632 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1633 | { |
1634 | int apic, i; | |
1635 | union IO_APIC_reg_00 reg_00; | |
1636 | union IO_APIC_reg_01 reg_01; | |
1637 | union IO_APIC_reg_02 reg_02; | |
1638 | union IO_APIC_reg_03 reg_03; | |
1639 | unsigned long flags; | |
0f978f45 | 1640 | struct irq_cfg *cfg; |
0b8f1efa | 1641 | struct irq_desc *desc; |
8f09cd20 | 1642 | unsigned int irq; |
1da177e4 | 1643 | |
36062448 | 1644 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1645 | for (i = 0; i < nr_ioapics; i++) |
1646 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1647 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1648 | |
1649 | /* | |
1650 | * We are a bit conservative about what we expect. We have to | |
1651 | * know about every hardware change ASAP. | |
1652 | */ | |
1653 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1654 | ||
1655 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1656 | ||
dade7716 | 1657 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1658 | reg_00.raw = io_apic_read(apic, 0); |
1659 | reg_01.raw = io_apic_read(apic, 1); | |
1660 | if (reg_01.bits.version >= 0x10) | |
1661 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1662 | if (reg_01.bits.version >= 0x20) |
1663 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1664 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1665 | |
54168ed7 | 1666 | printk("\n"); |
b5ba7e6d | 1667 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1668 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1669 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1670 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1671 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1672 | |
54168ed7 | 1673 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1674 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1675 | |
1676 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1677 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1678 | |
1679 | /* | |
1680 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1681 | * but the value of reg_02 is read as the previous read register | |
1682 | * value, so ignore it if reg_02 == reg_01. | |
1683 | */ | |
1684 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1685 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1686 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1687 | } |
1688 | ||
1689 | /* | |
1690 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1691 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1692 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1693 | */ | |
1694 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1695 | reg_03.raw != reg_01.raw) { | |
1696 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1697 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1698 | } |
1699 | ||
1700 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1701 | ||
d83e94ac | 1702 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1703 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1704 | |
1705 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1706 | struct IO_APIC_route_entry entry; | |
1707 | ||
cf4c6a2f | 1708 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1709 | |
54168ed7 IM |
1710 | printk(KERN_DEBUG " %02x %03X ", |
1711 | i, | |
1712 | entry.dest | |
1713 | ); | |
1da177e4 LT |
1714 | |
1715 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1716 | entry.mask, | |
1717 | entry.trigger, | |
1718 | entry.irr, | |
1719 | entry.polarity, | |
1720 | entry.delivery_status, | |
1721 | entry.dest_mode, | |
1722 | entry.delivery_mode, | |
1723 | entry.vector | |
1724 | ); | |
1725 | } | |
1726 | } | |
1da177e4 | 1727 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1728 | for_each_irq_desc(irq, desc) { |
1729 | struct irq_pin_list *entry; | |
1730 | ||
0b8f1efa | 1731 | cfg = desc->chip_data; |
05e40760 DK |
1732 | if (!cfg) |
1733 | continue; | |
0b8f1efa | 1734 | entry = cfg->irq_2_pin; |
0f978f45 | 1735 | if (!entry) |
1da177e4 | 1736 | continue; |
8f09cd20 | 1737 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1738 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1739 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1740 | printk("\n"); |
1741 | } | |
1742 | ||
1743 | printk(KERN_INFO ".................................... done.\n"); | |
1744 | ||
1745 | return; | |
1746 | } | |
1747 | ||
251e1e44 | 1748 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1749 | { |
251e1e44 | 1750 | int i; |
1da177e4 | 1751 | |
251e1e44 IM |
1752 | printk(KERN_DEBUG); |
1753 | ||
1754 | for (i = 0; i < 8; i++) | |
1755 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1756 | ||
1757 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1758 | } |
1759 | ||
32f71aff | 1760 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1761 | { |
97a52714 | 1762 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1763 | u64 icr; |
1da177e4 | 1764 | |
251e1e44 | 1765 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1766 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1767 | v = apic_read(APIC_ID); |
54168ed7 | 1768 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1769 | v = apic_read(APIC_LVR); |
1770 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1771 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1772 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1773 | |
1774 | v = apic_read(APIC_TASKPRI); | |
1775 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1776 | ||
54168ed7 | 1777 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1778 | if (!APIC_XAPIC(ver)) { |
1779 | v = apic_read(APIC_ARBPRI); | |
1780 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1781 | v & APIC_ARBPRI_MASK); | |
1782 | } | |
1da177e4 LT |
1783 | v = apic_read(APIC_PROCPRI); |
1784 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1785 | } | |
1786 | ||
a11b5abe YL |
1787 | /* |
1788 | * Remote read supported only in the 82489DX and local APIC for | |
1789 | * Pentium processors. | |
1790 | */ | |
1791 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1792 | v = apic_read(APIC_RRR); | |
1793 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1794 | } | |
1795 | ||
1da177e4 LT |
1796 | v = apic_read(APIC_LDR); |
1797 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1798 | if (!x2apic_enabled()) { |
1799 | v = apic_read(APIC_DFR); | |
1800 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1801 | } | |
1da177e4 LT |
1802 | v = apic_read(APIC_SPIV); |
1803 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1804 | ||
1805 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1806 | print_APIC_field(APIC_ISR); |
1da177e4 | 1807 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1808 | print_APIC_field(APIC_TMR); |
1da177e4 | 1809 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1810 | print_APIC_field(APIC_IRR); |
1da177e4 | 1811 | |
54168ed7 IM |
1812 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1813 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1814 | apic_write(APIC_ESR, 0); |
54168ed7 | 1815 | |
1da177e4 LT |
1816 | v = apic_read(APIC_ESR); |
1817 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1818 | } | |
1819 | ||
7ab6af7a | 1820 | icr = apic_icr_read(); |
0c425cec IM |
1821 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1822 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1823 | |
1824 | v = apic_read(APIC_LVTT); | |
1825 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1826 | ||
1827 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1828 | v = apic_read(APIC_LVTPC); | |
1829 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1830 | } | |
1831 | v = apic_read(APIC_LVT0); | |
1832 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1833 | v = apic_read(APIC_LVT1); | |
1834 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1835 | ||
1836 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1837 | v = apic_read(APIC_LVTERR); | |
1838 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1839 | } | |
1840 | ||
1841 | v = apic_read(APIC_TMICT); | |
1842 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1843 | v = apic_read(APIC_TMCCT); | |
1844 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1845 | v = apic_read(APIC_TDCR); | |
1846 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1847 | |
1848 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1849 | v = apic_read(APIC_EFEAT); | |
1850 | maxlvt = (v >> 16) & 0xff; | |
1851 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1852 | v = apic_read(APIC_ECTRL); | |
1853 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1854 | for (i = 0; i < maxlvt; i++) { | |
1855 | v = apic_read(APIC_EILVTn(i)); | |
1856 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1857 | } | |
1858 | } | |
1da177e4 LT |
1859 | printk("\n"); |
1860 | } | |
1861 | ||
2626eb2b | 1862 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1863 | { |
ffd5aae7 YL |
1864 | int cpu; |
1865 | ||
2626eb2b CG |
1866 | if (!maxcpu) |
1867 | return; | |
1868 | ||
ffd5aae7 | 1869 | preempt_disable(); |
2626eb2b CG |
1870 | for_each_online_cpu(cpu) { |
1871 | if (cpu >= maxcpu) | |
1872 | break; | |
ffd5aae7 | 1873 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1874 | } |
ffd5aae7 | 1875 | preempt_enable(); |
1da177e4 LT |
1876 | } |
1877 | ||
32f71aff | 1878 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1879 | { |
1da177e4 LT |
1880 | unsigned int v; |
1881 | unsigned long flags; | |
1882 | ||
b81bb373 | 1883 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1884 | return; |
1885 | ||
1886 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1887 | ||
5619c280 | 1888 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1889 | |
1890 | v = inb(0xa1) << 8 | inb(0x21); | |
1891 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1892 | ||
1893 | v = inb(0xa0) << 8 | inb(0x20); | |
1894 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1895 | ||
54168ed7 IM |
1896 | outb(0x0b,0xa0); |
1897 | outb(0x0b,0x20); | |
1da177e4 | 1898 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1899 | outb(0x0a,0xa0); |
1900 | outb(0x0a,0x20); | |
1da177e4 | 1901 | |
5619c280 | 1902 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1903 | |
1904 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1905 | ||
1906 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1907 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1908 | } | |
1909 | ||
2626eb2b CG |
1910 | static int __initdata show_lapic = 1; |
1911 | static __init int setup_show_lapic(char *arg) | |
1912 | { | |
1913 | int num = -1; | |
1914 | ||
1915 | if (strcmp(arg, "all") == 0) { | |
1916 | show_lapic = CONFIG_NR_CPUS; | |
1917 | } else { | |
1918 | get_option(&arg, &num); | |
1919 | if (num >= 0) | |
1920 | show_lapic = num; | |
1921 | } | |
1922 | ||
1923 | return 1; | |
1924 | } | |
1925 | __setup("show_lapic=", setup_show_lapic); | |
1926 | ||
1927 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1928 | { |
2626eb2b CG |
1929 | if (apic_verbosity == APIC_QUIET) |
1930 | return 0; | |
1931 | ||
32f71aff | 1932 | print_PIC(); |
4797f6b0 YL |
1933 | |
1934 | /* don't print out if apic is not there */ | |
8312136f | 1935 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1936 | return 0; |
1937 | ||
2626eb2b | 1938 | print_local_APICs(show_lapic); |
32f71aff MR |
1939 | print_IO_APIC(); |
1940 | ||
1941 | return 0; | |
1942 | } | |
1943 | ||
2626eb2b | 1944 | fs_initcall(print_ICs); |
32f71aff | 1945 | |
1da177e4 | 1946 | |
efa2559f YL |
1947 | /* Where if anywhere is the i8259 connect in external int mode */ |
1948 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1949 | ||
54168ed7 | 1950 | void __init enable_IO_APIC(void) |
1da177e4 | 1951 | { |
fcfd636a | 1952 | int i8259_apic, i8259_pin; |
54168ed7 | 1953 | int apic; |
bc07844a | 1954 | |
b81bb373 | 1955 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1956 | return; |
1957 | ||
54168ed7 | 1958 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1959 | int pin; |
1960 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1961 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1962 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1963 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1964 | |
fcfd636a EB |
1965 | /* If the interrupt line is enabled and in ExtInt mode |
1966 | * I have found the pin where the i8259 is connected. | |
1967 | */ | |
1968 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1969 | ioapic_i8259.apic = apic; | |
1970 | ioapic_i8259.pin = pin; | |
1971 | goto found_i8259; | |
1972 | } | |
1973 | } | |
1974 | } | |
1975 | found_i8259: | |
1976 | /* Look to see what if the MP table has reported the ExtINT */ | |
1977 | /* If we could not find the appropriate pin by looking at the ioapic | |
1978 | * the i8259 probably is not connected the ioapic but give the | |
1979 | * mptable a chance anyway. | |
1980 | */ | |
1981 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1982 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1983 | /* Trust the MP table if nothing is setup in the hardware */ | |
1984 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1985 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1986 | ioapic_i8259.pin = i8259_pin; | |
1987 | ioapic_i8259.apic = i8259_apic; | |
1988 | } | |
1989 | /* Complain if the MP table and the hardware disagree */ | |
1990 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1991 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1992 | { | |
1993 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1994 | } |
1995 | ||
1996 | /* | |
1997 | * Do not trust the IO-APIC being empty at bootup | |
1998 | */ | |
1999 | clear_IO_APIC(); | |
2000 | } | |
2001 | ||
2002 | /* | |
2003 | * Not an __init, needed by the reboot code | |
2004 | */ | |
2005 | void disable_IO_APIC(void) | |
2006 | { | |
2007 | /* | |
2008 | * Clear the IO-APIC before rebooting: | |
2009 | */ | |
2010 | clear_IO_APIC(); | |
2011 | ||
b81bb373 | 2012 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
2013 | return; |
2014 | ||
650927ef | 2015 | /* |
0b968d23 | 2016 | * If the i8259 is routed through an IOAPIC |
650927ef | 2017 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2018 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2019 | * |
2020 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2021 | * as virtual wire B is little complex (need to configure both | |
2022 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2023 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2024 | */ |
7c6d9f97 | 2025 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2026 | struct IO_APIC_route_entry entry; |
650927ef EB |
2027 | |
2028 | memset(&entry, 0, sizeof(entry)); | |
2029 | entry.mask = 0; /* Enabled */ | |
2030 | entry.trigger = 0; /* Edge */ | |
2031 | entry.irr = 0; | |
2032 | entry.polarity = 0; /* High */ | |
2033 | entry.delivery_status = 0; | |
2034 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2035 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2036 | entry.vector = 0; |
54168ed7 | 2037 | entry.dest = read_apic_id(); |
650927ef EB |
2038 | |
2039 | /* | |
2040 | * Add it to the IO-APIC irq-routing table: | |
2041 | */ | |
cf4c6a2f | 2042 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2043 | } |
54168ed7 | 2044 | |
7c6d9f97 SS |
2045 | /* |
2046 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2047 | */ | |
8312136f | 2048 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2049 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2050 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2051 | } |
2052 | ||
54168ed7 | 2053 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2054 | /* |
2055 | * function to set the IO-APIC physical IDs based on the | |
2056 | * values stored in the MPC table. | |
2057 | * | |
2058 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2059 | */ | |
2060 | ||
de934103 | 2061 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2062 | { |
2063 | union IO_APIC_reg_00 reg_00; | |
2064 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2065 | int apic_id; |
1da177e4 LT |
2066 | int i; |
2067 | unsigned char old_id; | |
2068 | unsigned long flags; | |
2069 | ||
de934103 | 2070 | if (acpi_ioapic) |
d49c4288 | 2071 | return; |
ca05fea6 NP |
2072 | /* |
2073 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2074 | * no meaning without the serial APIC bus. | |
2075 | */ | |
7c5c1e42 SL |
2076 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2077 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2078 | return; |
1da177e4 LT |
2079 | /* |
2080 | * This is broken; anything with a real cpu count has to | |
2081 | * circumvent this idiocy regardless. | |
2082 | */ | |
7abc0753 | 2083 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2084 | |
2085 | /* | |
2086 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2087 | */ | |
c8d46cf0 | 2088 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2089 | |
2090 | /* Read the register 0 value */ | |
dade7716 | 2091 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2092 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2093 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2094 | |
c8d46cf0 | 2095 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2096 | |
c8d46cf0 | 2097 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2098 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2099 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2100 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2101 | reg_00.bits.ID); | |
c8d46cf0 | 2102 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2103 | } |
2104 | ||
1da177e4 LT |
2105 | /* |
2106 | * Sanity check, is the ID really free? Every APIC in a | |
2107 | * system must have a unique ID or we get lots of nice | |
2108 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2109 | */ | |
7abc0753 | 2110 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2111 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2112 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2113 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2114 | for (i = 0; i < get_physical_broadcast(); i++) |
2115 | if (!physid_isset(i, phys_id_present_map)) | |
2116 | break; | |
2117 | if (i >= get_physical_broadcast()) | |
2118 | panic("Max APIC ID exceeded!\n"); | |
2119 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2120 | i); | |
2121 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2122 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2123 | } else { |
2124 | physid_mask_t tmp; | |
7abc0753 | 2125 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2126 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2127 | "phys_id_present_map\n", | |
c8d46cf0 | 2128 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2129 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2130 | } | |
2131 | ||
2132 | ||
2133 | /* | |
2134 | * We need to adjust the IRQ routing table | |
2135 | * if the ID changed. | |
2136 | */ | |
c8d46cf0 | 2137 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2138 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2139 | if (mp_irqs[i].dstapic == old_id) |
2140 | mp_irqs[i].dstapic | |
c8d46cf0 | 2141 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2142 | |
2143 | /* | |
2144 | * Read the right value from the MPC table and | |
2145 | * write it into the ID register. | |
36062448 | 2146 | */ |
1da177e4 LT |
2147 | apic_printk(APIC_VERBOSE, KERN_INFO |
2148 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2149 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2150 | |
c8d46cf0 | 2151 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2152 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2153 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2154 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2155 | |
2156 | /* | |
2157 | * Sanity check | |
2158 | */ | |
dade7716 | 2159 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2160 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2161 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2162 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2163 | printk("could not set ID!\n"); |
2164 | else | |
2165 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2166 | } | |
2167 | } | |
54168ed7 | 2168 | #endif |
1da177e4 | 2169 | |
7ce0bcfd | 2170 | int no_timer_check __initdata; |
8542b200 ZA |
2171 | |
2172 | static int __init notimercheck(char *s) | |
2173 | { | |
2174 | no_timer_check = 1; | |
2175 | return 1; | |
2176 | } | |
2177 | __setup("no_timer_check", notimercheck); | |
2178 | ||
1da177e4 LT |
2179 | /* |
2180 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2181 | * about the timer IRQ. We do the following to work around the situation: | |
2182 | * | |
2183 | * - timer IRQ defaults to IO-APIC IRQ | |
2184 | * - if this function detects that timer IRQs are defunct, then we fall | |
2185 | * back to ISA timer IRQs | |
2186 | */ | |
f0a7a5c9 | 2187 | static int __init timer_irq_works(void) |
1da177e4 LT |
2188 | { |
2189 | unsigned long t1 = jiffies; | |
4aae0702 | 2190 | unsigned long flags; |
1da177e4 | 2191 | |
8542b200 ZA |
2192 | if (no_timer_check) |
2193 | return 1; | |
2194 | ||
4aae0702 | 2195 | local_save_flags(flags); |
1da177e4 LT |
2196 | local_irq_enable(); |
2197 | /* Let ten ticks pass... */ | |
2198 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2199 | local_irq_restore(flags); |
1da177e4 LT |
2200 | |
2201 | /* | |
2202 | * Expect a few ticks at least, to be sure some possible | |
2203 | * glue logic does not lock up after one or two first | |
2204 | * ticks in a non-ExtINT mode. Also the local APIC | |
2205 | * might have cached one ExtINT interrupt. Finally, at | |
2206 | * least one tick may be lost due to delays. | |
2207 | */ | |
54168ed7 IM |
2208 | |
2209 | /* jiffies wrap? */ | |
1d16b53e | 2210 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2211 | return 1; |
1da177e4 LT |
2212 | return 0; |
2213 | } | |
2214 | ||
2215 | /* | |
2216 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2217 | * number of pending IRQ events unhandled. These cases are very rare, | |
2218 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2219 | * better to do it this way as thus we do not have to be aware of | |
2220 | * 'pending' interrupts in the IRQ path, except at this point. | |
2221 | */ | |
2222 | /* | |
2223 | * Edge triggered needs to resend any interrupt | |
2224 | * that was delayed but this is now handled in the device | |
2225 | * independent code. | |
2226 | */ | |
2227 | ||
2228 | /* | |
2229 | * Starting up a edge-triggered IO-APIC interrupt is | |
2230 | * nasty - we need to make sure that we get the edge. | |
2231 | * If it is already asserted for some reason, we need | |
2232 | * return 1 to indicate that is was pending. | |
2233 | * | |
2234 | * This is not complete - we should be able to fake | |
2235 | * an edge even if it isn't on the 8259A... | |
2236 | */ | |
54168ed7 | 2237 | |
f5b9ed7a | 2238 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2239 | { |
2240 | int was_pending = 0; | |
2241 | unsigned long flags; | |
0b8f1efa | 2242 | struct irq_cfg *cfg; |
1da177e4 | 2243 | |
dade7716 | 2244 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 JP |
2245 | if (irq < legacy_pic->nr_legacy_irqs) { |
2246 | legacy_pic->chip->mask(irq); | |
2247 | if (legacy_pic->irq_pending(irq)) | |
1da177e4 LT |
2248 | was_pending = 1; |
2249 | } | |
0b8f1efa | 2250 | cfg = irq_cfg(irq); |
3145e941 | 2251 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 2252 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2253 | |
2254 | return was_pending; | |
2255 | } | |
2256 | ||
ace80ab7 | 2257 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2258 | { |
54168ed7 IM |
2259 | |
2260 | struct irq_cfg *cfg = irq_cfg(irq); | |
2261 | unsigned long flags; | |
2262 | ||
dade7716 | 2263 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2264 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2265 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2266 | |
2267 | return 1; | |
2268 | } | |
497c9a19 | 2269 | |
54168ed7 IM |
2270 | /* |
2271 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2272 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2273 | * handled with the level-triggered descriptor, but that one has slightly | |
2274 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2275 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2276 | * races. | |
2277 | */ | |
497c9a19 | 2278 | |
54168ed7 | 2279 | #ifdef CONFIG_SMP |
9338ad6f | 2280 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2281 | { |
2282 | cpumask_var_t cleanup_mask; | |
2283 | ||
2284 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2285 | unsigned int i; | |
e85abf8f GH |
2286 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2287 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2288 | } else { | |
2289 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2290 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2291 | free_cpumask_var(cleanup_mask); | |
2292 | } | |
2293 | cfg->move_in_progress = 0; | |
2294 | } | |
2295 | ||
4420471f | 2296 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2297 | { |
2298 | int apic, pin; | |
2299 | struct irq_pin_list *entry; | |
2300 | u8 vector = cfg->vector; | |
2301 | ||
2977fb3f | 2302 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2303 | unsigned int reg; |
2304 | ||
e85abf8f GH |
2305 | apic = entry->apic; |
2306 | pin = entry->pin; | |
2307 | /* | |
2308 | * With interrupt-remapping, destination information comes | |
2309 | * from interrupt-remapping table entry. | |
2310 | */ | |
2311 | if (!irq_remapped(irq)) | |
2312 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2313 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2314 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2315 | reg |= vector; | |
2316 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2317 | } |
2318 | } | |
2319 | ||
2320 | /* | |
2321 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2322 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2323 | * leaves desc->affinity untouched. |
2324 | */ | |
9338ad6f | 2325 | unsigned int |
18374d89 SS |
2326 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2327 | unsigned int *dest_id) | |
e85abf8f GH |
2328 | { |
2329 | struct irq_cfg *cfg; | |
2330 | unsigned int irq; | |
2331 | ||
2332 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2333 | return -1; |
e85abf8f GH |
2334 | |
2335 | irq = desc->irq; | |
2336 | cfg = desc->chip_data; | |
2337 | if (assign_irq_vector(irq, cfg, mask)) | |
18374d89 | 2338 | return -1; |
e85abf8f | 2339 | |
e85abf8f GH |
2340 | cpumask_copy(desc->affinity, mask); |
2341 | ||
18374d89 SS |
2342 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2343 | return 0; | |
e85abf8f GH |
2344 | } |
2345 | ||
4420471f | 2346 | static int |
e85abf8f GH |
2347 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2348 | { | |
2349 | struct irq_cfg *cfg; | |
2350 | unsigned long flags; | |
2351 | unsigned int dest; | |
2352 | unsigned int irq; | |
4420471f | 2353 | int ret = -1; |
e85abf8f GH |
2354 | |
2355 | irq = desc->irq; | |
2356 | cfg = desc->chip_data; | |
2357 | ||
dade7716 | 2358 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2359 | ret = set_desc_affinity(desc, mask, &dest); |
2360 | if (!ret) { | |
e85abf8f GH |
2361 | /* Only the high 8 bits are valid. */ |
2362 | dest = SET_APIC_LOGICAL_ID(dest); | |
2363 | __target_IO_APIC_irq(irq, dest, cfg); | |
2364 | } | |
dade7716 | 2365 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2366 | |
2367 | return ret; | |
e85abf8f GH |
2368 | } |
2369 | ||
4420471f | 2370 | static int |
e85abf8f GH |
2371 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2372 | { | |
2373 | struct irq_desc *desc; | |
2374 | ||
2375 | desc = irq_to_desc(irq); | |
2376 | ||
4420471f | 2377 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2378 | } |
497c9a19 | 2379 | |
54168ed7 | 2380 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2381 | |
54168ed7 IM |
2382 | /* |
2383 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2384 | * | |
0280f7c4 SS |
2385 | * For both level and edge triggered, irq migration is a simple atomic |
2386 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2387 | * |
0280f7c4 SS |
2388 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2389 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2390 | * Real vector that is used for interrupting cpu will be coming from | |
2391 | * the interrupt-remapping table entry. | |
54168ed7 | 2392 | */ |
d5dedd45 | 2393 | static int |
e7986739 | 2394 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2395 | { |
54168ed7 | 2396 | struct irq_cfg *cfg; |
54168ed7 | 2397 | struct irte irte; |
54168ed7 | 2398 | unsigned int dest; |
3145e941 | 2399 | unsigned int irq; |
d5dedd45 | 2400 | int ret = -1; |
497c9a19 | 2401 | |
22f65d31 | 2402 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2403 | return ret; |
497c9a19 | 2404 | |
3145e941 | 2405 | irq = desc->irq; |
54168ed7 | 2406 | if (get_irte(irq, &irte)) |
d5dedd45 | 2407 | return ret; |
497c9a19 | 2408 | |
3145e941 YL |
2409 | cfg = desc->chip_data; |
2410 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2411 | return ret; |
54168ed7 | 2412 | |
debccb3e | 2413 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2414 | |
54168ed7 IM |
2415 | irte.vector = cfg->vector; |
2416 | irte.dest_id = IRTE_DEST(dest); | |
2417 | ||
2418 | /* | |
2419 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2420 | */ | |
2421 | modify_irte(irq, &irte); | |
2422 | ||
22f65d31 MT |
2423 | if (cfg->move_in_progress) |
2424 | send_cleanup_vector(cfg); | |
54168ed7 | 2425 | |
7f7ace0c | 2426 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2427 | |
2428 | return 0; | |
54168ed7 IM |
2429 | } |
2430 | ||
54168ed7 IM |
2431 | /* |
2432 | * Migrates the IRQ destination in the process context. | |
2433 | */ | |
d5dedd45 | 2434 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2435 | const struct cpumask *mask) |
54168ed7 | 2436 | { |
d5dedd45 | 2437 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2438 | } |
d5dedd45 | 2439 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2440 | const struct cpumask *mask) |
3145e941 YL |
2441 | { |
2442 | struct irq_desc *desc = irq_to_desc(irq); | |
2443 | ||
d5dedd45 | 2444 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2445 | } |
29b61be6 | 2446 | #else |
d5dedd45 | 2447 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2448 | const struct cpumask *mask) |
2449 | { | |
d5dedd45 | 2450 | return 0; |
29b61be6 | 2451 | } |
54168ed7 IM |
2452 | #endif |
2453 | ||
2454 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2455 | { | |
2456 | unsigned vector, me; | |
8f2466f4 | 2457 | |
54168ed7 | 2458 | ack_APIC_irq(); |
54168ed7 | 2459 | exit_idle(); |
54168ed7 IM |
2460 | irq_enter(); |
2461 | ||
2462 | me = smp_processor_id(); | |
2463 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2464 | unsigned int irq; | |
68a8ca59 | 2465 | unsigned int irr; |
54168ed7 IM |
2466 | struct irq_desc *desc; |
2467 | struct irq_cfg *cfg; | |
2468 | irq = __get_cpu_var(vector_irq)[vector]; | |
2469 | ||
0b8f1efa YL |
2470 | if (irq == -1) |
2471 | continue; | |
2472 | ||
54168ed7 IM |
2473 | desc = irq_to_desc(irq); |
2474 | if (!desc) | |
2475 | continue; | |
2476 | ||
2477 | cfg = irq_cfg(irq); | |
239007b8 | 2478 | raw_spin_lock(&desc->lock); |
54168ed7 | 2479 | |
7f41c2e1 SS |
2480 | /* |
2481 | * Check if the irq migration is in progress. If so, we | |
2482 | * haven't received the cleanup request yet for this irq. | |
2483 | */ | |
2484 | if (cfg->move_in_progress) | |
2485 | goto unlock; | |
2486 | ||
22f65d31 | 2487 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2488 | goto unlock; |
2489 | ||
68a8ca59 SS |
2490 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2491 | /* | |
2492 | * Check if the vector that needs to be cleanedup is | |
2493 | * registered at the cpu's IRR. If so, then this is not | |
2494 | * the best time to clean it up. Lets clean it up in the | |
2495 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2496 | * to myself. | |
2497 | */ | |
2498 | if (irr & (1 << (vector % 32))) { | |
2499 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2500 | goto unlock; | |
2501 | } | |
54168ed7 | 2502 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2503 | unlock: |
239007b8 | 2504 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2505 | } |
2506 | ||
2507 | irq_exit(); | |
2508 | } | |
2509 | ||
a5e74b84 | 2510 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2511 | { |
3145e941 YL |
2512 | struct irq_desc *desc = *descp; |
2513 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2514 | unsigned me; |
54168ed7 | 2515 | |
fcef5911 | 2516 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2517 | return; |
2518 | ||
54168ed7 | 2519 | me = smp_processor_id(); |
10b888d6 | 2520 | |
fcef5911 | 2521 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2522 | send_cleanup_vector(cfg); |
497c9a19 | 2523 | } |
a5e74b84 SS |
2524 | |
2525 | static void irq_complete_move(struct irq_desc **descp) | |
2526 | { | |
2527 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2528 | } | |
2529 | ||
2530 | void irq_force_complete_move(int irq) | |
2531 | { | |
2532 | struct irq_desc *desc = irq_to_desc(irq); | |
2533 | struct irq_cfg *cfg = desc->chip_data; | |
2534 | ||
bbd391a1 PB |
2535 | if (!cfg) |
2536 | return; | |
2537 | ||
a5e74b84 SS |
2538 | __irq_complete_move(&desc, cfg->vector); |
2539 | } | |
497c9a19 | 2540 | #else |
3145e941 | 2541 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2542 | #endif |
3145e941 | 2543 | |
1d025192 YL |
2544 | static void ack_apic_edge(unsigned int irq) |
2545 | { | |
3145e941 YL |
2546 | struct irq_desc *desc = irq_to_desc(irq); |
2547 | ||
2548 | irq_complete_move(&desc); | |
1d025192 YL |
2549 | move_native_irq(irq); |
2550 | ack_APIC_irq(); | |
2551 | } | |
2552 | ||
3eb2cce8 | 2553 | atomic_t irq_mis_count; |
3eb2cce8 | 2554 | |
c29d9db3 SS |
2555 | /* |
2556 | * IO-APIC versions below 0x20 don't support EOI register. | |
2557 | * For the record, here is the information about various versions: | |
2558 | * 0Xh 82489DX | |
2559 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2560 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2561 | * 30h-FFh Reserved | |
2562 | * | |
2563 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2564 | * version as 0x2. This is an error with documentation and these ICH chips | |
2565 | * use io-apic's of version 0x20. | |
2566 | * | |
2567 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2568 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2569 | * mode to edge and then back to level, with RTE being masked during this. | |
2570 | */ | |
b3ec0a37 SS |
2571 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2572 | { | |
2573 | struct irq_pin_list *entry; | |
2574 | ||
2575 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
c29d9db3 SS |
2576 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2577 | /* | |
2578 | * Intr-remapping uses pin number as the virtual vector | |
2579 | * in the RTE. Actual vector is programmed in | |
2580 | * intr-remapping table entry. Hence for the io-apic | |
2581 | * EOI we use the pin number. | |
2582 | */ | |
2583 | if (irq_remapped(irq)) | |
2584 | io_apic_eoi(entry->apic, entry->pin); | |
2585 | else | |
2586 | io_apic_eoi(entry->apic, cfg->vector); | |
2587 | } else { | |
2588 | __mask_and_edge_IO_APIC_irq(entry); | |
2589 | __unmask_and_level_IO_APIC_irq(entry); | |
2590 | } | |
b3ec0a37 SS |
2591 | } |
2592 | } | |
2593 | ||
2594 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2595 | { | |
2596 | struct irq_cfg *cfg; | |
2597 | unsigned long flags; | |
2598 | unsigned int irq; | |
2599 | ||
2600 | irq = desc->irq; | |
2601 | cfg = desc->chip_data; | |
2602 | ||
dade7716 | 2603 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2604 | __eoi_ioapic_irq(irq, cfg); |
dade7716 | 2605 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2606 | } |
2607 | ||
047c8fdb YL |
2608 | static void ack_apic_level(unsigned int irq) |
2609 | { | |
3145e941 | 2610 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2611 | unsigned long v; |
2612 | int i; | |
3145e941 | 2613 | struct irq_cfg *cfg; |
54168ed7 | 2614 | int do_unmask_irq = 0; |
047c8fdb | 2615 | |
3145e941 | 2616 | irq_complete_move(&desc); |
047c8fdb | 2617 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2618 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2619 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2620 | do_unmask_irq = 1; |
3145e941 | 2621 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2622 | } |
047c8fdb YL |
2623 | #endif |
2624 | ||
3eb2cce8 | 2625 | /* |
916a0fe7 JF |
2626 | * It appears there is an erratum which affects at least version 0x11 |
2627 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2628 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2629 | * erroneously delivered as edge-triggered one but the respective IRR | |
2630 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2631 | * message but it will never arrive and further interrupts are blocked | |
2632 | * from the source. The exact reason is so far unknown, but the | |
2633 | * phenomenon was observed when two consecutive interrupt requests | |
2634 | * from a given source get delivered to the same CPU and the source is | |
2635 | * temporarily disabled in between. | |
2636 | * | |
2637 | * A workaround is to simulate an EOI message manually. We achieve it | |
2638 | * by setting the trigger mode to edge and then to level when the edge | |
2639 | * trigger mode gets detected in the TMR of a local APIC for a | |
2640 | * level-triggered interrupt. We mask the source for the time of the | |
2641 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2642 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2643 | * |
2644 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2645 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2646 | * destination that is handling the corresponding interrupt. This | |
2647 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2648 | * level-triggered io-apic interrupt will be seen as an edge | |
2649 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2650 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2651 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2652 | * supporting EOI register, we do an explicit EOI to clear the | |
2653 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2654 | * we use the above logic (mask+edge followed by unmask+level) from | |
2655 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2656 | */ |
3145e941 YL |
2657 | cfg = desc->chip_data; |
2658 | i = cfg->vector; | |
3eb2cce8 | 2659 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2660 | |
54168ed7 IM |
2661 | /* |
2662 | * We must acknowledge the irq before we move it or the acknowledge will | |
2663 | * not propagate properly. | |
2664 | */ | |
2665 | ack_APIC_irq(); | |
2666 | ||
1c83995b SS |
2667 | /* |
2668 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2669 | * message via io-apic EOI register write or simulating it using | |
2670 | * mask+edge followed by unnask+level logic) manually when the | |
2671 | * level triggered interrupt is seen as the edge triggered interrupt | |
2672 | * at the cpu. | |
2673 | */ | |
ca64c47c MR |
2674 | if (!(v & (1 << (i & 0x1f)))) { |
2675 | atomic_inc(&irq_mis_count); | |
2676 | ||
c29d9db3 | 2677 | eoi_ioapic_irq(desc); |
ca64c47c MR |
2678 | } |
2679 | ||
54168ed7 IM |
2680 | /* Now we can move and renable the irq */ |
2681 | if (unlikely(do_unmask_irq)) { | |
2682 | /* Only migrate the irq if the ack has been received. | |
2683 | * | |
2684 | * On rare occasions the broadcast level triggered ack gets | |
2685 | * delayed going to ioapics, and if we reprogram the | |
2686 | * vector while Remote IRR is still set the irq will never | |
2687 | * fire again. | |
2688 | * | |
2689 | * To prevent this scenario we read the Remote IRR bit | |
2690 | * of the ioapic. This has two effects. | |
2691 | * - On any sane system the read of the ioapic will | |
2692 | * flush writes (and acks) going to the ioapic from | |
2693 | * this cpu. | |
2694 | * - We get to see if the ACK has actually been delivered. | |
2695 | * | |
2696 | * Based on failed experiments of reprogramming the | |
2697 | * ioapic entry from outside of irq context starting | |
2698 | * with masking the ioapic entry and then polling until | |
2699 | * Remote IRR was clear before reprogramming the | |
2700 | * ioapic I don't trust the Remote IRR bit to be | |
2701 | * completey accurate. | |
2702 | * | |
2703 | * However there appears to be no other way to plug | |
2704 | * this race, so if the Remote IRR bit is not | |
2705 | * accurate and is causing problems then it is a hardware bug | |
2706 | * and you can go talk to the chipset vendor about it. | |
2707 | */ | |
3145e941 YL |
2708 | cfg = desc->chip_data; |
2709 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2710 | move_masked_irq(irq); |
3145e941 | 2711 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2712 | } |
3eb2cce8 | 2713 | } |
1d025192 | 2714 | |
d0b03bd1 HW |
2715 | #ifdef CONFIG_INTR_REMAP |
2716 | static void ir_ack_apic_edge(unsigned int irq) | |
2717 | { | |
5d0ae2db | 2718 | ack_APIC_irq(); |
d0b03bd1 HW |
2719 | } |
2720 | ||
2721 | static void ir_ack_apic_level(unsigned int irq) | |
2722 | { | |
5d0ae2db WH |
2723 | struct irq_desc *desc = irq_to_desc(irq); |
2724 | ||
2725 | ack_APIC_irq(); | |
2726 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2727 | } |
2728 | #endif /* CONFIG_INTR_REMAP */ | |
2729 | ||
f5b9ed7a | 2730 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2731 | .name = "IO-APIC", |
2732 | .startup = startup_ioapic_irq, | |
2733 | .mask = mask_IO_APIC_irq, | |
2734 | .unmask = unmask_IO_APIC_irq, | |
2735 | .ack = ack_apic_edge, | |
2736 | .eoi = ack_apic_level, | |
54d5d424 | 2737 | #ifdef CONFIG_SMP |
d6c88a50 | 2738 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2739 | #endif |
ace80ab7 | 2740 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2741 | }; |
2742 | ||
54168ed7 | 2743 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2744 | .name = "IR-IO-APIC", |
2745 | .startup = startup_ioapic_irq, | |
2746 | .mask = mask_IO_APIC_irq, | |
2747 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2748 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2749 | .ack = ir_ack_apic_edge, |
2750 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2751 | #ifdef CONFIG_SMP |
d6c88a50 | 2752 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2753 | #endif |
54168ed7 IM |
2754 | #endif |
2755 | .retrigger = ioapic_retrigger_irq, | |
2756 | }; | |
1da177e4 LT |
2757 | |
2758 | static inline void init_IO_APIC_traps(void) | |
2759 | { | |
2760 | int irq; | |
08678b08 | 2761 | struct irq_desc *desc; |
da51a821 | 2762 | struct irq_cfg *cfg; |
1da177e4 LT |
2763 | |
2764 | /* | |
2765 | * NOTE! The local APIC isn't very good at handling | |
2766 | * multiple interrupts at the same interrupt level. | |
2767 | * As the interrupt level is determined by taking the | |
2768 | * vector number and shifting that right by 4, we | |
2769 | * want to spread these out a bit so that they don't | |
2770 | * all fall in the same interrupt level. | |
2771 | * | |
2772 | * Also, we've got to be careful not to trash gate | |
2773 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2774 | */ | |
0b8f1efa | 2775 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2776 | cfg = desc->chip_data; |
2777 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2778 | /* |
2779 | * Hmm.. We don't have an entry for this, | |
2780 | * so default to an old-fashioned 8259 | |
2781 | * interrupt if we can.. | |
2782 | */ | |
b81bb373 JP |
2783 | if (irq < legacy_pic->nr_legacy_irqs) |
2784 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2785 | else |
1da177e4 | 2786 | /* Strange. Oh, well.. */ |
08678b08 | 2787 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2788 | } |
2789 | } | |
2790 | } | |
2791 | ||
f5b9ed7a IM |
2792 | /* |
2793 | * The local APIC irq-chip implementation: | |
2794 | */ | |
1da177e4 | 2795 | |
36062448 | 2796 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2797 | { |
2798 | unsigned long v; | |
2799 | ||
2800 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2801 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2802 | } |
2803 | ||
36062448 | 2804 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2805 | { |
f5b9ed7a | 2806 | unsigned long v; |
1da177e4 | 2807 | |
f5b9ed7a | 2808 | v = apic_read(APIC_LVT0); |
593f4a78 | 2809 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2810 | } |
1da177e4 | 2811 | |
3145e941 | 2812 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2813 | { |
2814 | ack_APIC_irq(); | |
2815 | } | |
2816 | ||
f5b9ed7a | 2817 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2818 | .name = "local-APIC", |
f5b9ed7a IM |
2819 | .mask = mask_lapic_irq, |
2820 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2821 | .ack = ack_lapic_irq, |
1da177e4 LT |
2822 | }; |
2823 | ||
3145e941 | 2824 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2825 | { |
08678b08 | 2826 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2827 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2828 | "edge"); | |
c88ac1df MR |
2829 | } |
2830 | ||
e9427101 | 2831 | static void __init setup_nmi(void) |
1da177e4 LT |
2832 | { |
2833 | /* | |
36062448 | 2834 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2835 | * We put the 8259A master into AEOI mode and |
2836 | * unmask on all local APICs LVT0 as NMI. | |
2837 | * | |
2838 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2839 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2840 | * the NMI handler or the timer interrupt. | |
36062448 | 2841 | */ |
1da177e4 LT |
2842 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2843 | ||
e9427101 | 2844 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2845 | |
2846 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2847 | } | |
2848 | ||
2849 | /* | |
2850 | * This looks a bit hackish but it's about the only one way of sending | |
2851 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2852 | * not support the ExtINT mode, unfortunately. We need to send these | |
2853 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2854 | * 8259A interrupt line asserted until INTA. --macro | |
2855 | */ | |
28acf285 | 2856 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2857 | { |
fcfd636a | 2858 | int apic, pin, i; |
1da177e4 LT |
2859 | struct IO_APIC_route_entry entry0, entry1; |
2860 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2861 | |
fcfd636a | 2862 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2863 | if (pin == -1) { |
2864 | WARN_ON_ONCE(1); | |
2865 | return; | |
2866 | } | |
fcfd636a | 2867 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2868 | if (apic == -1) { |
2869 | WARN_ON_ONCE(1); | |
1da177e4 | 2870 | return; |
956fb531 | 2871 | } |
1da177e4 | 2872 | |
cf4c6a2f | 2873 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2874 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2875 | |
2876 | memset(&entry1, 0, sizeof(entry1)); | |
2877 | ||
2878 | entry1.dest_mode = 0; /* physical delivery */ | |
2879 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2880 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2881 | entry1.delivery_mode = dest_ExtINT; |
2882 | entry1.polarity = entry0.polarity; | |
2883 | entry1.trigger = 0; | |
2884 | entry1.vector = 0; | |
2885 | ||
cf4c6a2f | 2886 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2887 | |
2888 | save_control = CMOS_READ(RTC_CONTROL); | |
2889 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2890 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2891 | RTC_FREQ_SELECT); | |
2892 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2893 | ||
2894 | i = 100; | |
2895 | while (i-- > 0) { | |
2896 | mdelay(10); | |
2897 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2898 | i -= 10; | |
2899 | } | |
2900 | ||
2901 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2902 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2903 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2904 | |
cf4c6a2f | 2905 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2906 | } |
2907 | ||
efa2559f | 2908 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2909 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2910 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2911 | { |
2912 | disable_timer_pin_1 = 1; | |
2913 | return 0; | |
2914 | } | |
54168ed7 | 2915 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2916 | |
2917 | int timer_through_8259 __initdata; | |
2918 | ||
1da177e4 LT |
2919 | /* |
2920 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2921 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2922 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2923 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2924 | * |
2925 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2926 | */ |
8542b200 | 2927 | static inline void __init check_timer(void) |
1da177e4 | 2928 | { |
3145e941 YL |
2929 | struct irq_desc *desc = irq_to_desc(0); |
2930 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2931 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2932 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2933 | unsigned long flags; |
047c8fdb | 2934 | int no_pin1 = 0; |
4aae0702 IM |
2935 | |
2936 | local_irq_save(flags); | |
d4d25dec | 2937 | |
1da177e4 LT |
2938 | /* |
2939 | * get/set the timer IRQ vector: | |
2940 | */ | |
b81bb373 | 2941 | legacy_pic->chip->mask(0); |
fe402e1f | 2942 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2943 | |
2944 | /* | |
d11d5794 MR |
2945 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2946 | * wire has to be disabled in the local APIC. Also | |
2947 | * timer interrupts need to be acknowledged manually in | |
2948 | * the 8259A for the i82489DX when using the NMI | |
2949 | * watchdog as that APIC treats NMIs as level-triggered. | |
2950 | * The AEOI mode will finish them in the 8259A | |
2951 | * automatically. | |
1da177e4 | 2952 | */ |
593f4a78 | 2953 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2954 | legacy_pic->init(1); |
54168ed7 | 2955 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2956 | { |
2957 | unsigned int ver; | |
2958 | ||
2959 | ver = apic_read(APIC_LVR); | |
2960 | ver = GET_APIC_VERSION(ver); | |
2961 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2962 | } | |
54168ed7 | 2963 | #endif |
1da177e4 | 2964 | |
fcfd636a EB |
2965 | pin1 = find_isa_irq_pin(0, mp_INT); |
2966 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2967 | pin2 = ioapic_i8259.pin; | |
2968 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2969 | |
49a66a0b MR |
2970 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2971 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2972 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2973 | |
691874fa MR |
2974 | /* |
2975 | * Some BIOS writers are clueless and report the ExtINTA | |
2976 | * I/O APIC input from the cascaded 8259A as the timer | |
2977 | * interrupt input. So just in case, if only one pin | |
2978 | * was found above, try it both directly and through the | |
2979 | * 8259A. | |
2980 | */ | |
2981 | if (pin1 == -1) { | |
54168ed7 IM |
2982 | if (intr_remapping_enabled) |
2983 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2984 | pin1 = pin2; |
2985 | apic1 = apic2; | |
2986 | no_pin1 = 1; | |
2987 | } else if (pin2 == -1) { | |
2988 | pin2 = pin1; | |
2989 | apic2 = apic1; | |
2990 | } | |
2991 | ||
1da177e4 LT |
2992 | if (pin1 != -1) { |
2993 | /* | |
2994 | * Ok, does IRQ0 through the IOAPIC work? | |
2995 | */ | |
691874fa | 2996 | if (no_pin1) { |
85ac16d0 | 2997 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2998 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2999 | } else { |
3000 | /* for edge trigger, setup_IO_APIC_irq already | |
3001 | * leave it unmasked. | |
3002 | * so only need to unmask if it is level-trigger | |
3003 | * do we really have level trigger timer? | |
3004 | */ | |
3005 | int idx; | |
3006 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
3007 | if (idx != -1 && irq_trigger(idx)) | |
3008 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 3009 | } |
1da177e4 LT |
3010 | if (timer_irq_works()) { |
3011 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 3012 | setup_nmi(); |
b81bb373 | 3013 | legacy_pic->chip->unmask(0); |
1da177e4 | 3014 | } |
66759a01 CE |
3015 | if (disable_timer_pin_1 > 0) |
3016 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 3017 | goto out; |
1da177e4 | 3018 | } |
54168ed7 IM |
3019 | if (intr_remapping_enabled) |
3020 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 3021 | local_irq_disable(); |
fcfd636a | 3022 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 3023 | if (!no_pin1) |
49a66a0b MR |
3024 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
3025 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 3026 | |
49a66a0b MR |
3027 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
3028 | "(IRQ0) through the 8259A ...\n"); | |
3029 | apic_printk(APIC_QUIET, KERN_INFO | |
3030 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
3031 | /* |
3032 | * legacy devices should be connected to IO APIC #0 | |
3033 | */ | |
85ac16d0 | 3034 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 3035 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
b81bb373 | 3036 | legacy_pic->chip->unmask(0); |
1da177e4 | 3037 | if (timer_irq_works()) { |
49a66a0b | 3038 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3039 | timer_through_8259 = 1; |
1da177e4 | 3040 | if (nmi_watchdog == NMI_IO_APIC) { |
b81bb373 | 3041 | legacy_pic->chip->mask(0); |
1da177e4 | 3042 | setup_nmi(); |
b81bb373 | 3043 | legacy_pic->chip->unmask(0); |
1da177e4 | 3044 | } |
4aae0702 | 3045 | goto out; |
1da177e4 LT |
3046 | } |
3047 | /* | |
3048 | * Cleanup, just in case ... | |
3049 | */ | |
f72dccac | 3050 | local_irq_disable(); |
b81bb373 | 3051 | legacy_pic->chip->mask(0); |
fcfd636a | 3052 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3053 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3054 | } |
1da177e4 LT |
3055 | |
3056 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3057 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3058 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3059 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3060 | } |
54168ed7 | 3061 | #ifdef CONFIG_X86_32 |
d11d5794 | 3062 | timer_ack = 0; |
54168ed7 | 3063 | #endif |
1da177e4 | 3064 | |
49a66a0b MR |
3065 | apic_printk(APIC_QUIET, KERN_INFO |
3066 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3067 | |
3145e941 | 3068 | lapic_register_intr(0, desc); |
497c9a19 | 3069 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
b81bb373 | 3070 | legacy_pic->chip->unmask(0); |
1da177e4 LT |
3071 | |
3072 | if (timer_irq_works()) { | |
49a66a0b | 3073 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3074 | goto out; |
1da177e4 | 3075 | } |
f72dccac | 3076 | local_irq_disable(); |
b81bb373 | 3077 | legacy_pic->chip->mask(0); |
497c9a19 | 3078 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3079 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3080 | |
49a66a0b MR |
3081 | apic_printk(APIC_QUIET, KERN_INFO |
3082 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3083 | |
b81bb373 JP |
3084 | legacy_pic->init(0); |
3085 | legacy_pic->make_irq(0); | |
593f4a78 | 3086 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3087 | |
3088 | unlock_ExtINT_logic(); | |
3089 | ||
3090 | if (timer_irq_works()) { | |
49a66a0b | 3091 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3092 | goto out; |
1da177e4 | 3093 | } |
f72dccac | 3094 | local_irq_disable(); |
49a66a0b | 3095 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3096 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3097 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3098 | out: |
3099 | local_irq_restore(flags); | |
1da177e4 LT |
3100 | } |
3101 | ||
3102 | /* | |
af174783 MR |
3103 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3104 | * to devices. However there may be an I/O APIC pin available for | |
3105 | * this interrupt regardless. The pin may be left unconnected, but | |
3106 | * typically it will be reused as an ExtINT cascade interrupt for | |
3107 | * the master 8259A. In the MPS case such a pin will normally be | |
3108 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3109 | * there is no provision for ExtINT interrupts, and in the absence | |
3110 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3111 | * interrupt, that is edge-triggered and unmasked by default. We | |
3112 | * used to do this, but it caused problems on some systems because | |
3113 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3114 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3115 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3116 | * the I/O APIC in all cases now. No actual device should request | |
3117 | * it anyway. --macro | |
1da177e4 | 3118 | */ |
bc07844a | 3119 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3120 | |
3121 | void __init setup_IO_APIC(void) | |
3122 | { | |
54168ed7 | 3123 | |
54168ed7 IM |
3124 | /* |
3125 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3126 | */ | |
b81bb373 | 3127 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3128 | |
54168ed7 | 3129 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3130 | /* |
54168ed7 IM |
3131 | * Set up IO-APIC IRQ routing. |
3132 | */ | |
de934103 TG |
3133 | x86_init.mpparse.setup_ioapic_ids(); |
3134 | ||
1da177e4 LT |
3135 | sync_Arb_IDs(); |
3136 | setup_IO_APIC_irqs(); | |
3137 | init_IO_APIC_traps(); | |
b81bb373 | 3138 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3139 | check_timer(); |
1da177e4 LT |
3140 | } |
3141 | ||
3142 | /* | |
54168ed7 IM |
3143 | * Called after all the initialization is done. If we didnt find any |
3144 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3145 | */ |
36062448 | 3146 | |
1da177e4 LT |
3147 | static int __init io_apic_bug_finalize(void) |
3148 | { | |
d6c88a50 TG |
3149 | if (sis_apic_bug == -1) |
3150 | sis_apic_bug = 0; | |
3151 | return 0; | |
1da177e4 LT |
3152 | } |
3153 | ||
3154 | late_initcall(io_apic_bug_finalize); | |
3155 | ||
3156 | struct sysfs_ioapic_data { | |
3157 | struct sys_device dev; | |
3158 | struct IO_APIC_route_entry entry[0]; | |
3159 | }; | |
54168ed7 | 3160 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3161 | |
438510f6 | 3162 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3163 | { |
3164 | struct IO_APIC_route_entry *entry; | |
3165 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3166 | int i; |
36062448 | 3167 | |
1da177e4 LT |
3168 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3169 | entry = data->entry; | |
54168ed7 IM |
3170 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3171 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3172 | |
3173 | return 0; | |
3174 | } | |
3175 | ||
3176 | static int ioapic_resume(struct sys_device *dev) | |
3177 | { | |
3178 | struct IO_APIC_route_entry *entry; | |
3179 | struct sysfs_ioapic_data *data; | |
3180 | unsigned long flags; | |
3181 | union IO_APIC_reg_00 reg_00; | |
3182 | int i; | |
36062448 | 3183 | |
1da177e4 LT |
3184 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3185 | entry = data->entry; | |
3186 | ||
dade7716 | 3187 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3188 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3189 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3190 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3191 | io_apic_write(dev->id, 0, reg_00.raw); |
3192 | } | |
dade7716 | 3193 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3194 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3195 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3196 | |
3197 | return 0; | |
3198 | } | |
3199 | ||
3200 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3201 | .name = "ioapic", |
1da177e4 LT |
3202 | .suspend = ioapic_suspend, |
3203 | .resume = ioapic_resume, | |
3204 | }; | |
3205 | ||
3206 | static int __init ioapic_init_sysfs(void) | |
3207 | { | |
54168ed7 IM |
3208 | struct sys_device * dev; |
3209 | int i, size, error; | |
1da177e4 LT |
3210 | |
3211 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3212 | if (error) | |
3213 | return error; | |
3214 | ||
54168ed7 | 3215 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3216 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3217 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3218 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3219 | if (!mp_ioapic_data[i]) { |
3220 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3221 | continue; | |
3222 | } | |
1da177e4 | 3223 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3224 | dev->id = i; |
1da177e4 LT |
3225 | dev->cls = &ioapic_sysdev_class; |
3226 | error = sysdev_register(dev); | |
3227 | if (error) { | |
3228 | kfree(mp_ioapic_data[i]); | |
3229 | mp_ioapic_data[i] = NULL; | |
3230 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3231 | continue; | |
3232 | } | |
3233 | } | |
3234 | ||
3235 | return 0; | |
3236 | } | |
3237 | ||
3238 | device_initcall(ioapic_init_sysfs); | |
3239 | ||
3fc471ed | 3240 | /* |
95d77884 | 3241 | * Dynamic irq allocate and deallocation |
3fc471ed | 3242 | */ |
d047f53a | 3243 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3244 | { |
ace80ab7 | 3245 | /* Allocate an unused irq */ |
54168ed7 IM |
3246 | unsigned int irq; |
3247 | unsigned int new; | |
3fc471ed | 3248 | unsigned long flags; |
0b8f1efa | 3249 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3250 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3251 | |
3252 | irq = 0; | |
abcaa2b8 YL |
3253 | if (irq_want < nr_irqs_gsi) |
3254 | irq_want = nr_irqs_gsi; | |
3255 | ||
dade7716 | 3256 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3257 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3258 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3259 | if (!desc_new) { |
3260 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3261 | continue; |
0b8f1efa YL |
3262 | } |
3263 | cfg_new = desc_new->chip_data; | |
3264 | ||
3265 | if (cfg_new->vector != 0) | |
ace80ab7 | 3266 | continue; |
d047f53a | 3267 | |
15e957d0 | 3268 | desc_new = move_irq_desc(desc_new, node); |
37ef2a30 | 3269 | cfg_new = desc_new->chip_data; |
d047f53a | 3270 | |
fe402e1f | 3271 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3272 | irq = new; |
3273 | break; | |
3274 | } | |
dade7716 | 3275 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3276 | |
ced5b697 BP |
3277 | if (irq > 0) |
3278 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3279 | |
3fc471ed EB |
3280 | return irq; |
3281 | } | |
3282 | ||
199751d7 YL |
3283 | int create_irq(void) |
3284 | { | |
d047f53a | 3285 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3286 | unsigned int irq_want; |
54168ed7 IM |
3287 | int irq; |
3288 | ||
be5d5350 | 3289 | irq_want = nr_irqs_gsi; |
d047f53a | 3290 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3291 | |
3292 | if (irq == 0) | |
3293 | irq = -1; | |
3294 | ||
3295 | return irq; | |
199751d7 YL |
3296 | } |
3297 | ||
3fc471ed EB |
3298 | void destroy_irq(unsigned int irq) |
3299 | { | |
3300 | unsigned long flags; | |
3fc471ed | 3301 | |
ced5b697 | 3302 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3303 | |
54168ed7 | 3304 | free_irte(irq); |
dade7716 | 3305 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3306 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3307 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3308 | } |
3fc471ed | 3309 | |
2d3fcc1c | 3310 | /* |
27b46d76 | 3311 | * MSI message composition |
2d3fcc1c EB |
3312 | */ |
3313 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3314 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3315 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3316 | { |
497c9a19 YL |
3317 | struct irq_cfg *cfg; |
3318 | int err; | |
2d3fcc1c EB |
3319 | unsigned dest; |
3320 | ||
f1182638 JB |
3321 | if (disable_apic) |
3322 | return -ENXIO; | |
3323 | ||
3145e941 | 3324 | cfg = irq_cfg(irq); |
fe402e1f | 3325 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3326 | if (err) |
3327 | return err; | |
2d3fcc1c | 3328 | |
debccb3e | 3329 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3330 | |
54168ed7 IM |
3331 | if (irq_remapped(irq)) { |
3332 | struct irte irte; | |
3333 | int ir_index; | |
3334 | u16 sub_handle; | |
3335 | ||
3336 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3337 | BUG_ON(ir_index == -1); | |
3338 | ||
3339 | memset (&irte, 0, sizeof(irte)); | |
3340 | ||
3341 | irte.present = 1; | |
9b5bc8dc | 3342 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3343 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3344 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3345 | irte.vector = cfg->vector; |
3346 | irte.dest_id = IRTE_DEST(dest); | |
75e3cfbe | 3347 | irte.redir_hint = 1; |
54168ed7 | 3348 | |
f007e99c | 3349 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3350 | if (pdev) |
3351 | set_msi_sid(&irte, pdev); | |
3352 | else | |
3353 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3354 | |
54168ed7 IM |
3355 | modify_irte(irq, &irte); |
3356 | ||
3357 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3358 | msg->data = sub_handle; | |
3359 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3360 | MSI_ADDR_IR_SHV | | |
3361 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3362 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3363 | } else { |
9d783ba0 SS |
3364 | if (x2apic_enabled()) |
3365 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3366 | MSI_ADDR_EXT_DEST_ID(dest); | |
3367 | else | |
3368 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3369 | ||
54168ed7 IM |
3370 | msg->address_lo = |
3371 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3372 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3373 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3374 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3375 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3376 | MSI_ADDR_REDIRECTION_CPU: |
3377 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3378 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3379 | |
54168ed7 IM |
3380 | msg->data = |
3381 | MSI_DATA_TRIGGER_EDGE | | |
3382 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3383 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3384 | MSI_DATA_DELIVERY_FIXED: |
3385 | MSI_DATA_DELIVERY_LOWPRI) | | |
3386 | MSI_DATA_VECTOR(cfg->vector); | |
3387 | } | |
497c9a19 | 3388 | return err; |
2d3fcc1c EB |
3389 | } |
3390 | ||
3b7d1921 | 3391 | #ifdef CONFIG_SMP |
d5dedd45 | 3392 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3393 | { |
3145e941 | 3394 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3395 | struct irq_cfg *cfg; |
3b7d1921 EB |
3396 | struct msi_msg msg; |
3397 | unsigned int dest; | |
3b7d1921 | 3398 | |
18374d89 | 3399 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3400 | return -1; |
2d3fcc1c | 3401 | |
3145e941 | 3402 | cfg = desc->chip_data; |
2d3fcc1c | 3403 | |
30da5524 | 3404 | get_cached_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3405 | |
3406 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3407 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3408 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3409 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3410 | ||
3145e941 | 3411 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3412 | |
3413 | return 0; | |
2d3fcc1c | 3414 | } |
54168ed7 IM |
3415 | #ifdef CONFIG_INTR_REMAP |
3416 | /* | |
3417 | * Migrate the MSI irq to another cpumask. This migration is | |
3418 | * done in the process context using interrupt-remapping hardware. | |
3419 | */ | |
d5dedd45 | 3420 | static int |
e7986739 | 3421 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3422 | { |
3145e941 | 3423 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3424 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3425 | unsigned int dest; |
54168ed7 | 3426 | struct irte irte; |
54168ed7 IM |
3427 | |
3428 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3429 | return -1; |
54168ed7 | 3430 | |
18374d89 | 3431 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3432 | return -1; |
54168ed7 | 3433 | |
54168ed7 IM |
3434 | irte.vector = cfg->vector; |
3435 | irte.dest_id = IRTE_DEST(dest); | |
3436 | ||
3437 | /* | |
3438 | * atomically update the IRTE with the new destination and vector. | |
3439 | */ | |
3440 | modify_irte(irq, &irte); | |
3441 | ||
3442 | /* | |
3443 | * After this point, all the interrupts will start arriving | |
3444 | * at the new destination. So, time to cleanup the previous | |
3445 | * vector allocation. | |
3446 | */ | |
22f65d31 MT |
3447 | if (cfg->move_in_progress) |
3448 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3449 | |
3450 | return 0; | |
54168ed7 | 3451 | } |
3145e941 | 3452 | |
54168ed7 | 3453 | #endif |
3b7d1921 | 3454 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3455 | |
3b7d1921 EB |
3456 | /* |
3457 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3458 | * which implement the MSI or MSI-X Capability Structure. | |
3459 | */ | |
3460 | static struct irq_chip msi_chip = { | |
3461 | .name = "PCI-MSI", | |
3462 | .unmask = unmask_msi_irq, | |
3463 | .mask = mask_msi_irq, | |
1d025192 | 3464 | .ack = ack_apic_edge, |
3b7d1921 EB |
3465 | #ifdef CONFIG_SMP |
3466 | .set_affinity = set_msi_irq_affinity, | |
3467 | #endif | |
3468 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3469 | }; |
3470 | ||
54168ed7 IM |
3471 | static struct irq_chip msi_ir_chip = { |
3472 | .name = "IR-PCI-MSI", | |
3473 | .unmask = unmask_msi_irq, | |
3474 | .mask = mask_msi_irq, | |
a1e38ca5 | 3475 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3476 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3477 | #ifdef CONFIG_SMP |
3478 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3479 | #endif |
54168ed7 IM |
3480 | #endif |
3481 | .retrigger = ioapic_retrigger_irq, | |
3482 | }; | |
3483 | ||
3484 | /* | |
3485 | * Map the PCI dev to the corresponding remapping hardware unit | |
3486 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3487 | * in it. | |
3488 | */ | |
3489 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3490 | { | |
3491 | struct intel_iommu *iommu; | |
3492 | int index; | |
3493 | ||
3494 | iommu = map_dev_to_ir(dev); | |
3495 | if (!iommu) { | |
3496 | printk(KERN_ERR | |
3497 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3498 | return -ENOENT; | |
3499 | } | |
3500 | ||
3501 | index = alloc_irte(iommu, irq, nvec); | |
3502 | if (index < 0) { | |
3503 | printk(KERN_ERR | |
3504 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3505 | pci_name(dev)); |
54168ed7 IM |
3506 | return -ENOSPC; |
3507 | } | |
3508 | return index; | |
3509 | } | |
1d025192 | 3510 | |
3145e941 | 3511 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3512 | { |
3513 | int ret; | |
3514 | struct msi_msg msg; | |
3515 | ||
c8bc6f3c | 3516 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3517 | if (ret < 0) |
3518 | return ret; | |
3519 | ||
3145e941 | 3520 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3521 | write_msi_msg(irq, &msg); |
3522 | ||
54168ed7 IM |
3523 | if (irq_remapped(irq)) { |
3524 | struct irq_desc *desc = irq_to_desc(irq); | |
3525 | /* | |
3526 | * irq migration in process context | |
3527 | */ | |
3528 | desc->status |= IRQ_MOVE_PCNTXT; | |
3529 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3530 | } else | |
54168ed7 | 3531 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3532 | |
c81bba49 YL |
3533 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3534 | ||
1d025192 YL |
3535 | return 0; |
3536 | } | |
3537 | ||
047c8fdb YL |
3538 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3539 | { | |
54168ed7 IM |
3540 | unsigned int irq; |
3541 | int ret, sub_handle; | |
0b8f1efa | 3542 | struct msi_desc *msidesc; |
54168ed7 | 3543 | unsigned int irq_want; |
1cc18521 | 3544 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3545 | int index = 0; |
d047f53a | 3546 | int node; |
54168ed7 | 3547 | |
1c8d7b0a MW |
3548 | /* x86 doesn't support multiple MSI yet */ |
3549 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3550 | return 1; | |
3551 | ||
d047f53a | 3552 | node = dev_to_node(&dev->dev); |
be5d5350 | 3553 | irq_want = nr_irqs_gsi; |
54168ed7 | 3554 | sub_handle = 0; |
0b8f1efa | 3555 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3556 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3557 | if (irq == 0) |
3558 | return -1; | |
f1ee5548 | 3559 | irq_want = irq + 1; |
54168ed7 IM |
3560 | if (!intr_remapping_enabled) |
3561 | goto no_ir; | |
3562 | ||
3563 | if (!sub_handle) { | |
3564 | /* | |
3565 | * allocate the consecutive block of IRTE's | |
3566 | * for 'nvec' | |
3567 | */ | |
3568 | index = msi_alloc_irte(dev, irq, nvec); | |
3569 | if (index < 0) { | |
3570 | ret = index; | |
3571 | goto error; | |
3572 | } | |
3573 | } else { | |
3574 | iommu = map_dev_to_ir(dev); | |
3575 | if (!iommu) { | |
3576 | ret = -ENOENT; | |
3577 | goto error; | |
3578 | } | |
3579 | /* | |
3580 | * setup the mapping between the irq and the IRTE | |
3581 | * base index, the sub_handle pointing to the | |
3582 | * appropriate interrupt remap table entry. | |
3583 | */ | |
3584 | set_irte_irq(irq, iommu, index, sub_handle); | |
3585 | } | |
3586 | no_ir: | |
0b8f1efa | 3587 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3588 | if (ret < 0) |
3589 | goto error; | |
3590 | sub_handle++; | |
3591 | } | |
3592 | return 0; | |
047c8fdb YL |
3593 | |
3594 | error: | |
54168ed7 IM |
3595 | destroy_irq(irq); |
3596 | return ret; | |
047c8fdb YL |
3597 | } |
3598 | ||
3b7d1921 EB |
3599 | void arch_teardown_msi_irq(unsigned int irq) |
3600 | { | |
f7feaca7 | 3601 | destroy_irq(irq); |
3b7d1921 EB |
3602 | } |
3603 | ||
9d783ba0 | 3604 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3605 | #ifdef CONFIG_SMP |
d5dedd45 | 3606 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3607 | { |
3145e941 | 3608 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3609 | struct irq_cfg *cfg; |
3610 | struct msi_msg msg; | |
3611 | unsigned int dest; | |
54168ed7 | 3612 | |
18374d89 | 3613 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3614 | return -1; |
54168ed7 | 3615 | |
3145e941 | 3616 | cfg = desc->chip_data; |
54168ed7 IM |
3617 | |
3618 | dmar_msi_read(irq, &msg); | |
3619 | ||
3620 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3621 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3622 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3623 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3624 | ||
3625 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3626 | |
3627 | return 0; | |
54168ed7 | 3628 | } |
3145e941 | 3629 | |
54168ed7 IM |
3630 | #endif /* CONFIG_SMP */ |
3631 | ||
8f7007aa | 3632 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3633 | .name = "DMAR_MSI", |
3634 | .unmask = dmar_msi_unmask, | |
3635 | .mask = dmar_msi_mask, | |
3636 | .ack = ack_apic_edge, | |
3637 | #ifdef CONFIG_SMP | |
3638 | .set_affinity = dmar_msi_set_affinity, | |
3639 | #endif | |
3640 | .retrigger = ioapic_retrigger_irq, | |
3641 | }; | |
3642 | ||
3643 | int arch_setup_dmar_msi(unsigned int irq) | |
3644 | { | |
3645 | int ret; | |
3646 | struct msi_msg msg; | |
2d3fcc1c | 3647 | |
c8bc6f3c | 3648 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3649 | if (ret < 0) |
3650 | return ret; | |
3651 | dmar_msi_write(irq, &msg); | |
3652 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3653 | "edge"); | |
3654 | return 0; | |
3655 | } | |
3656 | #endif | |
3657 | ||
58ac1e76 | 3658 | #ifdef CONFIG_HPET_TIMER |
3659 | ||
3660 | #ifdef CONFIG_SMP | |
d5dedd45 | 3661 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3662 | { |
3145e941 | 3663 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3664 | struct irq_cfg *cfg; |
58ac1e76 | 3665 | struct msi_msg msg; |
3666 | unsigned int dest; | |
58ac1e76 | 3667 | |
18374d89 | 3668 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3669 | return -1; |
58ac1e76 | 3670 | |
3145e941 | 3671 | cfg = desc->chip_data; |
58ac1e76 | 3672 | |
3673 | hpet_msi_read(irq, &msg); | |
3674 | ||
3675 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3676 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3677 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3678 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3679 | ||
3680 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3681 | |
3682 | return 0; | |
58ac1e76 | 3683 | } |
3145e941 | 3684 | |
58ac1e76 | 3685 | #endif /* CONFIG_SMP */ |
3686 | ||
c8bc6f3c SS |
3687 | static struct irq_chip ir_hpet_msi_type = { |
3688 | .name = "IR-HPET_MSI", | |
3689 | .unmask = hpet_msi_unmask, | |
3690 | .mask = hpet_msi_mask, | |
3691 | #ifdef CONFIG_INTR_REMAP | |
3692 | .ack = ir_ack_apic_edge, | |
3693 | #ifdef CONFIG_SMP | |
3694 | .set_affinity = ir_set_msi_irq_affinity, | |
3695 | #endif | |
3696 | #endif | |
3697 | .retrigger = ioapic_retrigger_irq, | |
3698 | }; | |
3699 | ||
1cc18521 | 3700 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3701 | .name = "HPET_MSI", |
3702 | .unmask = hpet_msi_unmask, | |
3703 | .mask = hpet_msi_mask, | |
3704 | .ack = ack_apic_edge, | |
3705 | #ifdef CONFIG_SMP | |
3706 | .set_affinity = hpet_msi_set_affinity, | |
3707 | #endif | |
3708 | .retrigger = ioapic_retrigger_irq, | |
3709 | }; | |
3710 | ||
c8bc6f3c | 3711 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3712 | { |
3713 | int ret; | |
3714 | struct msi_msg msg; | |
6ec3cfec | 3715 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3716 | |
c8bc6f3c SS |
3717 | if (intr_remapping_enabled) { |
3718 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3719 | int index; | |
3720 | ||
3721 | if (!iommu) | |
3722 | return -1; | |
3723 | ||
3724 | index = alloc_irte(iommu, irq, 1); | |
3725 | if (index < 0) | |
3726 | return -1; | |
3727 | } | |
3728 | ||
3729 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3730 | if (ret < 0) |
3731 | return ret; | |
3732 | ||
3733 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3734 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3735 | if (irq_remapped(irq)) |
3736 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3737 | handle_edge_irq, "edge"); | |
3738 | else | |
3739 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3740 | handle_edge_irq, "edge"); | |
c81bba49 | 3741 | |
58ac1e76 | 3742 | return 0; |
3743 | } | |
3744 | #endif | |
3745 | ||
54168ed7 | 3746 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3747 | /* |
3748 | * Hypertransport interrupt support | |
3749 | */ | |
3750 | #ifdef CONFIG_HT_IRQ | |
3751 | ||
3752 | #ifdef CONFIG_SMP | |
3753 | ||
497c9a19 | 3754 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3755 | { |
ec68307c EB |
3756 | struct ht_irq_msg msg; |
3757 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3758 | |
497c9a19 | 3759 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3760 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3761 | |
497c9a19 | 3762 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3763 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3764 | |
ec68307c | 3765 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3766 | } |
3767 | ||
d5dedd45 | 3768 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3769 | { |
3145e941 | 3770 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3771 | struct irq_cfg *cfg; |
8b955b0d | 3772 | unsigned int dest; |
8b955b0d | 3773 | |
18374d89 | 3774 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3775 | return -1; |
8b955b0d | 3776 | |
3145e941 | 3777 | cfg = desc->chip_data; |
8b955b0d | 3778 | |
497c9a19 | 3779 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3780 | |
3781 | return 0; | |
8b955b0d | 3782 | } |
3145e941 | 3783 | |
8b955b0d EB |
3784 | #endif |
3785 | ||
c37e108d | 3786 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3787 | .name = "PCI-HT", |
3788 | .mask = mask_ht_irq, | |
3789 | .unmask = unmask_ht_irq, | |
1d025192 | 3790 | .ack = ack_apic_edge, |
8b955b0d EB |
3791 | #ifdef CONFIG_SMP |
3792 | .set_affinity = set_ht_irq_affinity, | |
3793 | #endif | |
3794 | .retrigger = ioapic_retrigger_irq, | |
3795 | }; | |
3796 | ||
3797 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3798 | { | |
497c9a19 YL |
3799 | struct irq_cfg *cfg; |
3800 | int err; | |
8b955b0d | 3801 | |
f1182638 JB |
3802 | if (disable_apic) |
3803 | return -ENXIO; | |
3804 | ||
3145e941 | 3805 | cfg = irq_cfg(irq); |
fe402e1f | 3806 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3807 | if (!err) { |
ec68307c | 3808 | struct ht_irq_msg msg; |
8b955b0d | 3809 | unsigned dest; |
8b955b0d | 3810 | |
debccb3e IM |
3811 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3812 | apic->target_cpus()); | |
8b955b0d | 3813 | |
ec68307c | 3814 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3815 | |
ec68307c EB |
3816 | msg.address_lo = |
3817 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3818 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3819 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3820 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3821 | HT_IRQ_LOW_DM_PHYSICAL : |
3822 | HT_IRQ_LOW_DM_LOGICAL) | | |
3823 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3824 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3825 | HT_IRQ_LOW_MT_FIXED : |
3826 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3827 | HT_IRQ_LOW_IRQ_MASKED; | |
3828 | ||
ec68307c | 3829 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3830 | |
a460e745 IM |
3831 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3832 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3833 | |
3834 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3835 | } |
497c9a19 | 3836 | return err; |
8b955b0d EB |
3837 | } |
3838 | #endif /* CONFIG_HT_IRQ */ | |
3839 | ||
9d6a4d08 YL |
3840 | int __init io_apic_get_redir_entries (int ioapic) |
3841 | { | |
3842 | union IO_APIC_reg_01 reg_01; | |
3843 | unsigned long flags; | |
3844 | ||
dade7716 | 3845 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3846 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3847 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3848 | |
4b6b19a1 EB |
3849 | /* The register returns the maximum index redir index |
3850 | * supported, which is one less than the total number of redir | |
3851 | * entries. | |
3852 | */ | |
3853 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3854 | } |
3855 | ||
be5d5350 | 3856 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3857 | { |
4afc51a8 | 3858 | int nr; |
be5d5350 | 3859 | |
a4384df3 | 3860 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3861 | if (nr > nr_irqs_gsi) |
be5d5350 | 3862 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3863 | |
3864 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3865 | } |
3866 | ||
4a046d17 YL |
3867 | #ifdef CONFIG_SPARSE_IRQ |
3868 | int __init arch_probe_nr_irqs(void) | |
3869 | { | |
3870 | int nr; | |
3871 | ||
f1ee5548 YL |
3872 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3873 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3874 | |
f1ee5548 YL |
3875 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3876 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3877 | /* | |
3878 | * for MSI and HT dyn irq | |
3879 | */ | |
3880 | nr += nr_irqs_gsi * 16; | |
3881 | #endif | |
3882 | if (nr < nr_irqs) | |
4a046d17 YL |
3883 | nr_irqs = nr; |
3884 | ||
3885 | return 0; | |
3886 | } | |
3887 | #endif | |
3888 | ||
e5198075 YL |
3889 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3890 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3891 | { |
3892 | struct irq_desc *desc; | |
3893 | struct irq_cfg *cfg; | |
3894 | int node; | |
e5198075 YL |
3895 | int ioapic, pin; |
3896 | int trigger, polarity; | |
5ef21837 | 3897 | |
e5198075 | 3898 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3899 | if (!IO_APIC_IRQ(irq)) { |
3900 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3901 | ioapic); | |
3902 | return -EINVAL; | |
3903 | } | |
3904 | ||
3905 | if (dev) | |
3906 | node = dev_to_node(dev); | |
3907 | else | |
3908 | node = cpu_to_node(boot_cpu_id); | |
3909 | ||
3910 | desc = irq_to_desc_alloc_node(irq, node); | |
3911 | if (!desc) { | |
3912 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3913 | return 0; | |
3914 | } | |
3915 | ||
e5198075 YL |
3916 | pin = irq_attr->ioapic_pin; |
3917 | trigger = irq_attr->trigger; | |
3918 | polarity = irq_attr->polarity; | |
3919 | ||
5ef21837 YL |
3920 | /* |
3921 | * IRQs < 16 are already in the irq_2_pin[] map | |
3922 | */ | |
b81bb373 | 3923 | if (irq >= legacy_pic->nr_legacy_irqs) { |
5ef21837 | 3924 | cfg = desc->chip_data; |
f3d1915a CG |
3925 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3926 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3927 | pin, irq); | |
3928 | return 0; | |
3929 | } | |
5ef21837 YL |
3930 | } |
3931 | ||
e5198075 | 3932 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3933 | |
3934 | return 0; | |
3935 | } | |
3936 | ||
e5198075 YL |
3937 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3938 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3939 | { |
e5198075 | 3940 | int ioapic, pin; |
5ef21837 YL |
3941 | /* |
3942 | * Avoid pin reprogramming. PRTs typically include entries | |
3943 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3944 | * we only program the IOAPIC on the first. | |
3945 | */ | |
e5198075 YL |
3946 | ioapic = irq_attr->ioapic; |
3947 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3948 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3949 | pr_debug("Pin %d-%d already programmed\n", | |
3950 | mp_ioapics[ioapic].apicid, pin); | |
3951 | return 0; | |
3952 | } | |
3953 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3954 | ||
e5198075 | 3955 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3956 | } |
3957 | ||
2a4ab640 FT |
3958 | u8 __init io_apic_unique_id(u8 id) |
3959 | { | |
3960 | #ifdef CONFIG_X86_32 | |
3961 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3962 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3963 | return io_apic_get_unique_id(nr_ioapics, id); | |
3964 | else | |
3965 | return id; | |
3966 | #else | |
3967 | int i; | |
3968 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3969 | |
2a4ab640 FT |
3970 | bitmap_zero(used, 256); |
3971 | for (i = 0; i < nr_ioapics; i++) { | |
3972 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3973 | __set_bit(ia->apicid, used); | |
3974 | } | |
3975 | if (!test_bit(id, used)) | |
3976 | return id; | |
3977 | return find_first_zero_bit(used, 256); | |
3978 | #endif | |
3979 | } | |
1da177e4 | 3980 | |
54168ed7 | 3981 | #ifdef CONFIG_X86_32 |
36062448 | 3982 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3983 | { |
3984 | union IO_APIC_reg_00 reg_00; | |
3985 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3986 | physid_mask_t tmp; | |
3987 | unsigned long flags; | |
3988 | int i = 0; | |
3989 | ||
3990 | /* | |
36062448 PC |
3991 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3992 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3993 | * supports up to 16 on one shared APIC bus. |
36062448 | 3994 | * |
1da177e4 LT |
3995 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3996 | * advantage of new APIC bus architecture. | |
3997 | */ | |
3998 | ||
3999 | if (physids_empty(apic_id_map)) | |
7abc0753 | 4000 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 4001 | |
dade7716 | 4002 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4003 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 4004 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4005 | |
4006 | if (apic_id >= get_physical_broadcast()) { | |
4007 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
4008 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
4009 | apic_id = reg_00.bits.ID; | |
4010 | } | |
4011 | ||
4012 | /* | |
36062448 | 4013 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
4014 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
4015 | */ | |
7abc0753 | 4016 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
4017 | |
4018 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 4019 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
4020 | break; |
4021 | } | |
4022 | ||
4023 | if (i == get_physical_broadcast()) | |
4024 | panic("Max apic_id exceeded!\n"); | |
4025 | ||
4026 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
4027 | "trying %d\n", ioapic, apic_id, i); | |
4028 | ||
4029 | apic_id = i; | |
36062448 | 4030 | } |
1da177e4 | 4031 | |
7abc0753 | 4032 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
4033 | physids_or(apic_id_map, apic_id_map, tmp); |
4034 | ||
4035 | if (reg_00.bits.ID != apic_id) { | |
4036 | reg_00.bits.ID = apic_id; | |
4037 | ||
dade7716 | 4038 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
4039 | io_apic_write(ioapic, 0, reg_00.raw); |
4040 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 4041 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4042 | |
4043 | /* Sanity check */ | |
6070f9ec AD |
4044 | if (reg_00.bits.ID != apic_id) { |
4045 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4046 | return -1; | |
4047 | } | |
1da177e4 LT |
4048 | } |
4049 | ||
4050 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4051 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4052 | ||
4053 | return apic_id; | |
4054 | } | |
58f892e0 | 4055 | #endif |
1da177e4 | 4056 | |
36062448 | 4057 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4058 | { |
4059 | union IO_APIC_reg_01 reg_01; | |
4060 | unsigned long flags; | |
4061 | ||
dade7716 | 4062 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4063 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4064 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4065 | |
4066 | return reg_01.bits.version; | |
4067 | } | |
4068 | ||
9a0a91bb | 4069 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 4070 | { |
9a0a91bb | 4071 | int ioapic, pin, idx; |
61fd47e0 SL |
4072 | |
4073 | if (skip_ioapic_setup) | |
4074 | return -1; | |
4075 | ||
9a0a91bb EB |
4076 | ioapic = mp_find_ioapic(gsi); |
4077 | if (ioapic < 0) | |
61fd47e0 SL |
4078 | return -1; |
4079 | ||
9a0a91bb EB |
4080 | pin = mp_find_ioapic_pin(ioapic, gsi); |
4081 | if (pin < 0) | |
4082 | return -1; | |
4083 | ||
4084 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
4085 | if (idx < 0) | |
61fd47e0 SL |
4086 | return -1; |
4087 | ||
9a0a91bb EB |
4088 | *trigger = irq_trigger(idx); |
4089 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
4090 | return 0; |
4091 | } | |
4092 | ||
497c9a19 YL |
4093 | /* |
4094 | * This function currently is only a helper for the i386 smp boot process where | |
4095 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4096 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4097 | */ |
4098 | #ifdef CONFIG_SMP | |
4099 | void __init setup_ioapic_dest(void) | |
4100 | { | |
fad53995 | 4101 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4102 | struct irq_desc *desc; |
22f65d31 | 4103 | const struct cpumask *mask; |
497c9a19 YL |
4104 | |
4105 | if (skip_ioapic_setup == 1) | |
4106 | return; | |
4107 | ||
fad53995 | 4108 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4109 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4110 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4111 | if (irq_entry == -1) | |
4112 | continue; | |
4113 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4114 | |
fad53995 EB |
4115 | if ((ioapic > 0) && (irq > 16)) |
4116 | continue; | |
4117 | ||
b9c61b70 | 4118 | desc = irq_to_desc(irq); |
6c2e9403 | 4119 | |
b9c61b70 YL |
4120 | /* |
4121 | * Honour affinities which have been set in early boot | |
4122 | */ | |
4123 | if (desc->status & | |
4124 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4125 | mask = desc->affinity; | |
4126 | else | |
4127 | mask = apic->target_cpus(); | |
497c9a19 | 4128 | |
b9c61b70 YL |
4129 | if (intr_remapping_enabled) |
4130 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4131 | else | |
4132 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4133 | } |
b9c61b70 | 4134 | |
497c9a19 YL |
4135 | } |
4136 | #endif | |
4137 | ||
54168ed7 IM |
4138 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4139 | ||
4140 | static struct resource *ioapic_resources; | |
4141 | ||
ffc43836 | 4142 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4143 | { |
4144 | unsigned long n; | |
4145 | struct resource *res; | |
4146 | char *mem; | |
4147 | int i; | |
4148 | ||
4149 | if (nr_ioapics <= 0) | |
4150 | return NULL; | |
4151 | ||
4152 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4153 | n *= nr_ioapics; | |
4154 | ||
4155 | mem = alloc_bootmem(n); | |
4156 | res = (void *)mem; | |
4157 | ||
ffc43836 | 4158 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4159 | |
ffc43836 CG |
4160 | for (i = 0; i < nr_ioapics; i++) { |
4161 | res[i].name = mem; | |
4162 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4163 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4164 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4165 | } |
4166 | ||
4167 | ioapic_resources = res; | |
4168 | ||
4169 | return res; | |
4170 | } | |
54168ed7 | 4171 | |
f3294a33 YL |
4172 | void __init ioapic_init_mappings(void) |
4173 | { | |
4174 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4175 | struct resource *ioapic_res; |
d6c88a50 | 4176 | int i; |
f3294a33 | 4177 | |
ffc43836 | 4178 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4179 | for (i = 0; i < nr_ioapics; i++) { |
4180 | if (smp_found_config) { | |
b5ba7e6d | 4181 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4182 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4183 | if (!ioapic_phys) { |
4184 | printk(KERN_ERR | |
4185 | "WARNING: bogus zero IO-APIC " | |
4186 | "address found in MPTABLE, " | |
4187 | "disabling IO/APIC support!\n"); | |
4188 | smp_found_config = 0; | |
4189 | skip_ioapic_setup = 1; | |
4190 | goto fake_ioapic_page; | |
4191 | } | |
54168ed7 | 4192 | #endif |
f3294a33 | 4193 | } else { |
54168ed7 | 4194 | #ifdef CONFIG_X86_32 |
f3294a33 | 4195 | fake_ioapic_page: |
54168ed7 | 4196 | #endif |
e79c65a9 | 4197 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4198 | ioapic_phys = __pa(ioapic_phys); |
4199 | } | |
4200 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4201 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4202 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4203 | ioapic_phys); | |
f3294a33 | 4204 | idx++; |
54168ed7 | 4205 | |
ffc43836 | 4206 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4207 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4208 | ioapic_res++; |
f3294a33 YL |
4209 | } |
4210 | } | |
4211 | ||
857fdc53 | 4212 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4213 | { |
4214 | int i; | |
4215 | struct resource *r = ioapic_resources; | |
4216 | ||
4217 | if (!r) { | |
857fdc53 | 4218 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4219 | printk(KERN_ERR |
4220 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4221 | return; |
54168ed7 IM |
4222 | } |
4223 | ||
4224 | for (i = 0; i < nr_ioapics; i++) { | |
4225 | insert_resource(&iomem_resource, r); | |
4226 | r++; | |
4227 | } | |
54168ed7 | 4228 | } |
2a4ab640 | 4229 | |
eddb0c55 | 4230 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4231 | { |
4232 | int i = 0; | |
4233 | ||
4234 | /* Find the IOAPIC that manages this GSI. */ | |
4235 | for (i = 0; i < nr_ioapics; i++) { | |
4236 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4237 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4238 | return i; | |
4239 | } | |
54168ed7 | 4240 | |
2a4ab640 FT |
4241 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4242 | return -1; | |
4243 | } | |
4244 | ||
eddb0c55 | 4245 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4246 | { |
4247 | if (WARN_ON(ioapic == -1)) | |
4248 | return -1; | |
4249 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4250 | return -1; | |
4251 | ||
4252 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4253 | } | |
4254 | ||
4255 | static int bad_ioapic(unsigned long address) | |
4256 | { | |
4257 | if (nr_ioapics >= MAX_IO_APICS) { | |
4258 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4259 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4260 | return 1; | |
4261 | } | |
4262 | if (!address) { | |
4263 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4264 | " found in table, skipping!\n"); | |
4265 | return 1; | |
4266 | } | |
54168ed7 IM |
4267 | return 0; |
4268 | } | |
4269 | ||
2a4ab640 FT |
4270 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4271 | { | |
4272 | int idx = 0; | |
7716a5c4 | 4273 | int entries; |
2a4ab640 FT |
4274 | |
4275 | if (bad_ioapic(address)) | |
4276 | return; | |
4277 | ||
4278 | idx = nr_ioapics; | |
4279 | ||
4280 | mp_ioapics[idx].type = MP_IOAPIC; | |
4281 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4282 | mp_ioapics[idx].apicaddr = address; | |
4283 | ||
4284 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4285 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4286 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4287 | ||
4288 | /* | |
4289 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4290 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4291 | */ | |
7716a5c4 | 4292 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4293 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4294 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4295 | ||
4296 | /* | |
4297 | * The number of IO-APIC IRQ registers (== #pins): | |
4298 | */ | |
4299 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4300 | |
a4384df3 EB |
4301 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4302 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4303 | |
4304 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4305 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4306 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4307 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4308 | ||
4309 | nr_ioapics++; | |
4310 | } | |
05ddafb1 JP |
4311 | |
4312 | /* Enable IOAPIC early just for system timer */ | |
4313 | void __init pre_init_apic_IRQ0(void) | |
4314 | { | |
4315 | struct irq_cfg *cfg; | |
4316 | struct irq_desc *desc; | |
4317 | ||
4318 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4319 | #ifndef CONFIG_SMP | |
4320 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4321 | #endif | |
4322 | desc = irq_to_desc_alloc_node(0, 0); | |
4323 | ||
4324 | setup_local_APIC(); | |
4325 | ||
4326 | cfg = irq_cfg(0); | |
4327 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4328 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4329 | ||
4330 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4331 | } |