Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 TG |
76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
77 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 78 | |
b69c6c3b SS |
79 | static struct ioapic { |
80 | /* | |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_registers; | |
84 | } ioapics[MAX_IO_APICS]; | |
1da177e4 | 85 | |
9f640ccb | 86 | /* I/O APIC entries */ |
b5ba7e6d | 87 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
88 | int nr_ioapics; |
89 | ||
2a4ab640 FT |
90 | /* IO APIC gsi routing info */ |
91 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
92 | ||
a4384df3 EB |
93 | /* The one past the highest gsi number used */ |
94 | u32 gsi_top; | |
5777372a | 95 | |
584f734d | 96 | /* MP IRQ source entries */ |
c2c21745 | 97 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
98 | |
99 | /* # of MP IRQ source entries */ | |
100 | int mp_irq_entries; | |
101 | ||
bc07844a TG |
102 | /* GSI interrupts */ |
103 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
104 | ||
4c79185c | 105 | /* |
31dce14a | 106 | * Saved I/O APIC state during suspend/resume, or while enabling intr-remap. |
4c79185c SS |
107 | */ |
108 | static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS]; | |
109 | ||
8732fc4b AS |
110 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
111 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
112 | #endif | |
113 | ||
114 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
115 | ||
efa2559f YL |
116 | int skip_ioapic_setup; |
117 | ||
7167d08e HK |
118 | /** |
119 | * disable_ioapic_support() - disables ioapic support at runtime | |
120 | */ | |
121 | void disable_ioapic_support(void) | |
65a4e574 IM |
122 | { |
123 | #ifdef CONFIG_PCI | |
124 | noioapicquirk = 1; | |
125 | noioapicreroute = -1; | |
126 | #endif | |
127 | skip_ioapic_setup = 1; | |
128 | } | |
129 | ||
54168ed7 | 130 | static int __init parse_noapic(char *str) |
efa2559f YL |
131 | { |
132 | /* disable IO-APIC */ | |
7167d08e | 133 | disable_ioapic_support(); |
efa2559f YL |
134 | return 0; |
135 | } | |
136 | early_param("noapic", parse_noapic); | |
66759a01 | 137 | |
20443598 SAS |
138 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
139 | struct io_apic_irq_attr *attr); | |
710dcda6 | 140 | |
2d8009ba FT |
141 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
142 | void mp_save_irq(struct mpc_intsrc *m) | |
143 | { | |
144 | int i; | |
145 | ||
146 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
147 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
148 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
149 | m->srcbusirq, m->dstapic, m->dstirq); | |
150 | ||
151 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 152 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
153 | return; |
154 | } | |
155 | ||
0e3fa13f | 156 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
157 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
158 | panic("Max # of irq sources exceeded!!\n"); | |
159 | } | |
160 | ||
0b8f1efa YL |
161 | struct irq_pin_list { |
162 | int apic, pin; | |
163 | struct irq_pin_list *next; | |
164 | }; | |
165 | ||
7e495529 | 166 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 167 | { |
2ee39065 | 168 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
169 | } |
170 | ||
2d8009ba | 171 | |
a1420f39 | 172 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 173 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 174 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 175 | #else |
97943390 | 176 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 177 | #endif |
a1420f39 | 178 | |
13a0c3c2 | 179 | int __init arch_early_irq_init(void) |
8f09cd20 | 180 | { |
0b8f1efa | 181 | struct irq_cfg *cfg; |
60c69948 | 182 | int count, node, i; |
d6c88a50 | 183 | |
1f91233c JP |
184 | if (!legacy_pic->nr_legacy_irqs) { |
185 | nr_irqs_gsi = 0; | |
186 | io_apic_irqs = ~0UL; | |
187 | } | |
188 | ||
4c79185c SS |
189 | for (i = 0; i < nr_ioapics; i++) { |
190 | ioapic_saved_data[i] = | |
191 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
b69c6c3b | 192 | ioapics[i].nr_registers, GFP_KERNEL); |
4c79185c SS |
193 | if (!ioapic_saved_data[i]) |
194 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); | |
195 | } | |
196 | ||
0b8f1efa YL |
197 | cfg = irq_cfgx; |
198 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 199 | node = cpu_to_node(0); |
8f09cd20 | 200 | |
fbc6bff0 TG |
201 | /* Make sure the legacy interrupts are marked in the bitmap */ |
202 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
203 | ||
0b8f1efa | 204 | for (i = 0; i < count; i++) { |
2c778651 | 205 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
206 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
207 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
208 | /* |
209 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
210 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
211 | */ | |
54b56170 | 212 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
213 | cfg[i].vector = IRQ0_VECTOR + i; |
214 | cpumask_set_cpu(0, cfg[i].domain); | |
215 | } | |
0b8f1efa | 216 | } |
13a0c3c2 YL |
217 | |
218 | return 0; | |
0b8f1efa | 219 | } |
8f09cd20 | 220 | |
0b8f1efa | 221 | #ifdef CONFIG_SPARSE_IRQ |
48b26501 | 222 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 223 | { |
2c778651 | 224 | return irq_get_chip_data(irq); |
8f09cd20 | 225 | } |
d6c88a50 | 226 | |
f981a3dc | 227 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 228 | { |
0b8f1efa | 229 | struct irq_cfg *cfg; |
0f978f45 | 230 | |
2ee39065 | 231 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
232 | if (!cfg) |
233 | return NULL; | |
2ee39065 | 234 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 235 | goto out_cfg; |
2ee39065 | 236 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 237 | goto out_domain; |
0b8f1efa | 238 | return cfg; |
6e2fff50 TG |
239 | out_domain: |
240 | free_cpumask_var(cfg->domain); | |
241 | out_cfg: | |
242 | kfree(cfg); | |
243 | return NULL; | |
8f09cd20 YL |
244 | } |
245 | ||
f981a3dc | 246 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 247 | { |
fbc6bff0 TG |
248 | if (!cfg) |
249 | return; | |
2c778651 | 250 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
251 | free_cpumask_var(cfg->domain); |
252 | free_cpumask_var(cfg->old_domain); | |
253 | kfree(cfg); | |
254 | } | |
255 | ||
0b8f1efa | 256 | #else |
08c33db6 | 257 | |
9338ad6f | 258 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
259 | { |
260 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 261 | } |
1da177e4 | 262 | |
f981a3dc | 263 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
08c33db6 TG |
264 | { |
265 | return irq_cfgx + irq; | |
266 | } | |
267 | ||
f981a3dc | 268 | static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } |
08c33db6 | 269 | |
0b8f1efa YL |
270 | #endif |
271 | ||
08c33db6 TG |
272 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
273 | { | |
274 | int res = irq_alloc_desc_at(at, node); | |
275 | struct irq_cfg *cfg; | |
276 | ||
277 | if (res < 0) { | |
278 | if (res != -EEXIST) | |
279 | return NULL; | |
2c778651 | 280 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
281 | if (cfg) |
282 | return cfg; | |
283 | } | |
284 | ||
f981a3dc | 285 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 286 | if (cfg) |
2c778651 | 287 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
288 | else |
289 | irq_free_desc(at); | |
290 | return cfg; | |
291 | } | |
292 | ||
293 | static int alloc_irq_from(unsigned int from, int node) | |
294 | { | |
295 | return irq_alloc_desc_from(from, node); | |
296 | } | |
297 | ||
298 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
299 | { | |
f981a3dc | 300 | free_irq_cfg(at, cfg); |
08c33db6 TG |
301 | irq_free_desc(at); |
302 | } | |
303 | ||
130fe05d LT |
304 | struct io_apic { |
305 | unsigned int index; | |
306 | unsigned int unused[3]; | |
307 | unsigned int data; | |
0280f7c4 SS |
308 | unsigned int unused2[11]; |
309 | unsigned int eoi; | |
130fe05d LT |
310 | }; |
311 | ||
312 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
313 | { | |
314 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 315 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
316 | } |
317 | ||
0280f7c4 SS |
318 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
319 | { | |
320 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
321 | writel(vector, &io_apic->eoi); | |
322 | } | |
323 | ||
130fe05d LT |
324 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
325 | { | |
326 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
327 | writel(reg, &io_apic->index); | |
328 | return readl(&io_apic->data); | |
329 | } | |
330 | ||
331 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
332 | { | |
333 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
334 | writel(reg, &io_apic->index); | |
335 | writel(value, &io_apic->data); | |
336 | } | |
337 | ||
338 | /* | |
339 | * Re-write a value: to be used for read-modify-write | |
340 | * cycles where the read already set up the index register. | |
341 | * | |
342 | * Older SiS APIC requires we rewrite the index register | |
343 | */ | |
344 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
345 | { | |
54168ed7 | 346 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
347 | |
348 | if (sis_apic_bug) | |
349 | writel(reg, &io_apic->index); | |
130fe05d LT |
350 | writel(value, &io_apic->data); |
351 | } | |
352 | ||
3145e941 | 353 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
354 | { |
355 | struct irq_pin_list *entry; | |
356 | unsigned long flags; | |
047c8fdb | 357 | |
dade7716 | 358 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 359 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
360 | unsigned int reg; |
361 | int pin; | |
362 | ||
047c8fdb YL |
363 | pin = entry->pin; |
364 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
365 | /* Is the remote IRR bit set? */ | |
366 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 367 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
368 | return true; |
369 | } | |
047c8fdb | 370 | } |
dade7716 | 371 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
372 | |
373 | return false; | |
374 | } | |
047c8fdb | 375 | |
cf4c6a2f AK |
376 | union entry_union { |
377 | struct { u32 w1, w2; }; | |
378 | struct IO_APIC_route_entry entry; | |
379 | }; | |
380 | ||
381 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
382 | { | |
383 | union entry_union eu; | |
384 | unsigned long flags; | |
dade7716 | 385 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
386 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
387 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 388 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
389 | return eu.entry; |
390 | } | |
391 | ||
f9dadfa7 LT |
392 | /* |
393 | * When we write a new IO APIC routing entry, we need to write the high | |
394 | * word first! If the mask bit in the low word is clear, we will enable | |
395 | * the interrupt, and we need to make sure the entry is fully populated | |
396 | * before that happens. | |
397 | */ | |
d15512f4 AK |
398 | static void |
399 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 400 | { |
50a8d4d2 F |
401 | union entry_union eu = {{0, 0}}; |
402 | ||
cf4c6a2f | 403 | eu.entry = e; |
f9dadfa7 LT |
404 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
405 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
406 | } |
407 | ||
1a8ce7ff | 408 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
409 | { |
410 | unsigned long flags; | |
dade7716 | 411 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 412 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 413 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
414 | } |
415 | ||
416 | /* | |
417 | * When we mask an IO APIC routing entry, we need to write the low | |
418 | * word first, in order to set the mask bit before we change the | |
419 | * high bits! | |
420 | */ | |
421 | static void ioapic_mask_entry(int apic, int pin) | |
422 | { | |
423 | unsigned long flags; | |
424 | union entry_union eu = { .entry.mask = 1 }; | |
425 | ||
dade7716 | 426 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
427 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
428 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 429 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
430 | } |
431 | ||
1da177e4 LT |
432 | /* |
433 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
434 | * shared ISA-space IRQs, so we have to support them. We are super | |
435 | * fast in the common case, and fast for shared ISA-space IRQs. | |
436 | */ | |
f3d1915a | 437 | static int |
7e495529 | 438 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 439 | { |
2977fb3f | 440 | struct irq_pin_list **last, *entry; |
0f978f45 | 441 | |
2977fb3f CG |
442 | /* don't allow duplicates */ |
443 | last = &cfg->irq_2_pin; | |
444 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 445 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 446 | return 0; |
2977fb3f | 447 | last = &entry->next; |
1da177e4 | 448 | } |
0f978f45 | 449 | |
7e495529 | 450 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 451 | if (!entry) { |
f3d1915a CG |
452 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
453 | node, apic, pin); | |
454 | return -ENOMEM; | |
a7428cd2 | 455 | } |
1da177e4 LT |
456 | entry->apic = apic; |
457 | entry->pin = pin; | |
875e68ec | 458 | |
2977fb3f | 459 | *last = entry; |
f3d1915a CG |
460 | return 0; |
461 | } | |
462 | ||
463 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
464 | { | |
7e495529 | 465 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 466 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
467 | } |
468 | ||
469 | /* | |
470 | * Reroute an IRQ to a different pin. | |
471 | */ | |
85ac16d0 | 472 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
473 | int oldapic, int oldpin, |
474 | int newapic, int newpin) | |
1da177e4 | 475 | { |
535b6429 | 476 | struct irq_pin_list *entry; |
1da177e4 | 477 | |
2977fb3f | 478 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
479 | if (entry->apic == oldapic && entry->pin == oldpin) { |
480 | entry->apic = newapic; | |
481 | entry->pin = newpin; | |
0f978f45 | 482 | /* every one is different, right? */ |
4eea6fff | 483 | return; |
0f978f45 | 484 | } |
1da177e4 | 485 | } |
0f978f45 | 486 | |
4eea6fff JF |
487 | /* old apic/pin didn't exist, so just add new ones */ |
488 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
489 | } |
490 | ||
c29d9db3 SS |
491 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
492 | int mask_and, int mask_or, | |
493 | void (*final)(struct irq_pin_list *entry)) | |
494 | { | |
495 | unsigned int reg, pin; | |
496 | ||
497 | pin = entry->pin; | |
498 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
499 | reg &= mask_and; | |
500 | reg |= mask_or; | |
501 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
502 | if (final) | |
503 | final(entry); | |
504 | } | |
505 | ||
2f210deb JF |
506 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
507 | int mask_and, int mask_or, | |
508 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 509 | { |
87783be4 | 510 | struct irq_pin_list *entry; |
047c8fdb | 511 | |
c29d9db3 SS |
512 | for_each_irq_pin(entry, cfg->irq_2_pin) |
513 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
514 | } | |
515 | ||
516 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
517 | { | |
518 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
519 | IO_APIC_REDIR_MASKED, NULL); | |
520 | } | |
521 | ||
522 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
523 | { | |
524 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
525 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 526 | } |
047c8fdb | 527 | |
7f3e632f | 528 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 529 | { |
87783be4 CG |
530 | /* |
531 | * Synchronize the IO-APIC and the CPU by doing | |
532 | * a dummy read from the IO-APIC | |
533 | */ | |
534 | struct io_apic __iomem *io_apic; | |
535 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 536 | readl(&io_apic->data); |
1da177e4 LT |
537 | } |
538 | ||
dd5f15e5 | 539 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 540 | { |
dd5f15e5 TG |
541 | unsigned long flags; |
542 | ||
543 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 544 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 545 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 546 | } |
1da177e4 | 547 | |
90297c5f | 548 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 549 | { |
90297c5f | 550 | mask_ioapic(data->chip_data); |
dd5f15e5 | 551 | } |
3145e941 | 552 | |
dd5f15e5 TG |
553 | static void __unmask_ioapic(struct irq_cfg *cfg) |
554 | { | |
555 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
556 | } |
557 | ||
dd5f15e5 | 558 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
559 | { |
560 | unsigned long flags; | |
561 | ||
dade7716 | 562 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 563 | __unmask_ioapic(cfg); |
dade7716 | 564 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
565 | } |
566 | ||
90297c5f | 567 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 568 | { |
90297c5f | 569 | unmask_ioapic(data->chip_data); |
3145e941 YL |
570 | } |
571 | ||
1da177e4 LT |
572 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
573 | { | |
574 | struct IO_APIC_route_entry entry; | |
36062448 | 575 | |
1da177e4 | 576 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 577 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
578 | if (entry.delivery_mode == dest_SMI) |
579 | return; | |
1da177e4 LT |
580 | /* |
581 | * Disable it in the IO-APIC irq-routing table: | |
582 | */ | |
f9dadfa7 | 583 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
584 | } |
585 | ||
54168ed7 | 586 | static void clear_IO_APIC (void) |
1da177e4 LT |
587 | { |
588 | int apic, pin; | |
589 | ||
590 | for (apic = 0; apic < nr_ioapics; apic++) | |
b69c6c3b | 591 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
1da177e4 LT |
592 | clear_IO_APIC_pin(apic, pin); |
593 | } | |
594 | ||
54168ed7 | 595 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
596 | /* |
597 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
598 | * specific CPU-side IRQs. | |
599 | */ | |
600 | ||
601 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
602 | static int pirq_entries[MAX_PIRQS] = { |
603 | [0 ... MAX_PIRQS - 1] = -1 | |
604 | }; | |
1da177e4 | 605 | |
1da177e4 LT |
606 | static int __init ioapic_pirq_setup(char *str) |
607 | { | |
608 | int i, max; | |
609 | int ints[MAX_PIRQS+1]; | |
610 | ||
611 | get_options(str, ARRAY_SIZE(ints), ints); | |
612 | ||
1da177e4 LT |
613 | apic_printk(APIC_VERBOSE, KERN_INFO |
614 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
615 | max = MAX_PIRQS; | |
616 | if (ints[0] < MAX_PIRQS) | |
617 | max = ints[0]; | |
618 | ||
619 | for (i = 0; i < max; i++) { | |
620 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
621 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
622 | /* | |
623 | * PIRQs are mapped upside down, usually. | |
624 | */ | |
625 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
626 | } | |
627 | return 1; | |
628 | } | |
629 | ||
630 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
631 | #endif /* CONFIG_X86_32 */ |
632 | ||
54168ed7 | 633 | /* |
05c3dc2c | 634 | * Saves all the IO-APIC RTE's |
54168ed7 | 635 | */ |
31dce14a | 636 | int save_ioapic_entries(void) |
54168ed7 | 637 | { |
54168ed7 | 638 | int apic, pin; |
31dce14a | 639 | int err = 0; |
54168ed7 IM |
640 | |
641 | for (apic = 0; apic < nr_ioapics; apic++) { | |
31dce14a SS |
642 | if (!ioapic_saved_data[apic]) { |
643 | err = -ENOMEM; | |
644 | continue; | |
645 | } | |
54168ed7 | 646 | |
b69c6c3b | 647 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
31dce14a | 648 | ioapic_saved_data[apic][pin] = |
54168ed7 | 649 | ioapic_read_entry(apic, pin); |
b24696bc | 650 | } |
5ffa4eb2 | 651 | |
31dce14a | 652 | return err; |
54168ed7 IM |
653 | } |
654 | ||
b24696bc FY |
655 | /* |
656 | * Mask all IO APIC entries. | |
657 | */ | |
31dce14a | 658 | void mask_ioapic_entries(void) |
05c3dc2c SS |
659 | { |
660 | int apic, pin; | |
661 | ||
662 | for (apic = 0; apic < nr_ioapics; apic++) { | |
31dce14a SS |
663 | if (!ioapic_saved_data[apic]) |
664 | continue; | |
b24696bc | 665 | |
b69c6c3b | 666 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
05c3dc2c SS |
667 | struct IO_APIC_route_entry entry; |
668 | ||
31dce14a | 669 | entry = ioapic_saved_data[apic][pin]; |
05c3dc2c SS |
670 | if (!entry.mask) { |
671 | entry.mask = 1; | |
672 | ioapic_write_entry(apic, pin, entry); | |
673 | } | |
674 | } | |
675 | } | |
676 | } | |
677 | ||
b24696bc | 678 | /* |
31dce14a | 679 | * Restore IO APIC entries which was saved in ioapic_saved_data |
b24696bc | 680 | */ |
31dce14a | 681 | int restore_ioapic_entries(void) |
54168ed7 IM |
682 | { |
683 | int apic, pin; | |
684 | ||
5ffa4eb2 | 685 | for (apic = 0; apic < nr_ioapics; apic++) { |
31dce14a SS |
686 | if (!ioapic_saved_data[apic]) |
687 | continue; | |
b24696bc | 688 | |
b69c6c3b | 689 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
54168ed7 | 690 | ioapic_write_entry(apic, pin, |
31dce14a | 691 | ioapic_saved_data[apic][pin]); |
5ffa4eb2 | 692 | } |
b24696bc | 693 | return 0; |
54168ed7 IM |
694 | } |
695 | ||
1da177e4 LT |
696 | /* |
697 | * Find the IRQ entry number of a certain pin. | |
698 | */ | |
699 | static int find_irq_entry(int apic, int pin, int type) | |
700 | { | |
701 | int i; | |
702 | ||
703 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
704 | if (mp_irqs[i].irqtype == type && |
705 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
706 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
707 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
708 | return i; |
709 | ||
710 | return -1; | |
711 | } | |
712 | ||
713 | /* | |
714 | * Find the pin to which IRQ[irq] (ISA) is connected | |
715 | */ | |
fcfd636a | 716 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
717 | { |
718 | int i; | |
719 | ||
720 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 721 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 722 | |
d27e2b8e | 723 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
724 | (mp_irqs[i].irqtype == type) && |
725 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 726 | |
c2c21745 | 727 | return mp_irqs[i].dstirq; |
1da177e4 LT |
728 | } |
729 | return -1; | |
730 | } | |
731 | ||
fcfd636a EB |
732 | static int __init find_isa_irq_apic(int irq, int type) |
733 | { | |
734 | int i; | |
735 | ||
736 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 737 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 738 | |
73b2961b | 739 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
740 | (mp_irqs[i].irqtype == type) && |
741 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
742 | break; |
743 | } | |
744 | if (i < mp_irq_entries) { | |
745 | int apic; | |
54168ed7 | 746 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 747 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
748 | return apic; |
749 | } | |
750 | } | |
751 | ||
752 | return -1; | |
753 | } | |
754 | ||
c0a282c2 | 755 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
756 | /* |
757 | * EISA Edge/Level control register, ELCR | |
758 | */ | |
759 | static int EISA_ELCR(unsigned int irq) | |
760 | { | |
b81bb373 | 761 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
762 | unsigned int port = 0x4d0 + (irq >> 3); |
763 | return (inb(port) >> (irq & 7)) & 1; | |
764 | } | |
765 | apic_printk(APIC_VERBOSE, KERN_INFO | |
766 | "Broken MPtable reports ISA irq %d\n", irq); | |
767 | return 0; | |
768 | } | |
54168ed7 | 769 | |
c0a282c2 | 770 | #endif |
1da177e4 | 771 | |
6728801d AS |
772 | /* ISA interrupts are always polarity zero edge triggered, |
773 | * when listed as conforming in the MP table. */ | |
774 | ||
775 | #define default_ISA_trigger(idx) (0) | |
776 | #define default_ISA_polarity(idx) (0) | |
777 | ||
1da177e4 LT |
778 | /* EISA interrupts are always polarity zero and can be edge or level |
779 | * trigger depending on the ELCR value. If an interrupt is listed as | |
780 | * EISA conforming in the MP table, that means its trigger type must | |
781 | * be read in from the ELCR */ | |
782 | ||
c2c21745 | 783 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 784 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
785 | |
786 | /* PCI interrupts are always polarity one level triggered, | |
787 | * when listed as conforming in the MP table. */ | |
788 | ||
789 | #define default_PCI_trigger(idx) (1) | |
790 | #define default_PCI_polarity(idx) (1) | |
791 | ||
792 | /* MCA interrupts are always polarity zero level triggered, | |
793 | * when listed as conforming in the MP table. */ | |
794 | ||
795 | #define default_MCA_trigger(idx) (1) | |
6728801d | 796 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 797 | |
b77cf6a8 | 798 | static int irq_polarity(int idx) |
1da177e4 | 799 | { |
c2c21745 | 800 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
801 | int polarity; |
802 | ||
803 | /* | |
804 | * Determine IRQ line polarity (high active or low active): | |
805 | */ | |
c2c21745 | 806 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 807 | { |
54168ed7 IM |
808 | case 0: /* conforms, ie. bus-type dependent polarity */ |
809 | if (test_bit(bus, mp_bus_not_pci)) | |
810 | polarity = default_ISA_polarity(idx); | |
811 | else | |
812 | polarity = default_PCI_polarity(idx); | |
813 | break; | |
814 | case 1: /* high active */ | |
815 | { | |
816 | polarity = 0; | |
817 | break; | |
818 | } | |
819 | case 2: /* reserved */ | |
820 | { | |
821 | printk(KERN_WARNING "broken BIOS!!\n"); | |
822 | polarity = 1; | |
823 | break; | |
824 | } | |
825 | case 3: /* low active */ | |
826 | { | |
827 | polarity = 1; | |
828 | break; | |
829 | } | |
830 | default: /* invalid */ | |
831 | { | |
832 | printk(KERN_WARNING "broken BIOS!!\n"); | |
833 | polarity = 1; | |
834 | break; | |
835 | } | |
1da177e4 LT |
836 | } |
837 | return polarity; | |
838 | } | |
839 | ||
b77cf6a8 | 840 | static int irq_trigger(int idx) |
1da177e4 | 841 | { |
c2c21745 | 842 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
843 | int trigger; |
844 | ||
845 | /* | |
846 | * Determine IRQ trigger mode (edge or level sensitive): | |
847 | */ | |
c2c21745 | 848 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 849 | { |
54168ed7 IM |
850 | case 0: /* conforms, ie. bus-type dependent */ |
851 | if (test_bit(bus, mp_bus_not_pci)) | |
852 | trigger = default_ISA_trigger(idx); | |
853 | else | |
854 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 855 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
856 | switch (mp_bus_id_to_type[bus]) { |
857 | case MP_BUS_ISA: /* ISA pin */ | |
858 | { | |
859 | /* set before the switch */ | |
860 | break; | |
861 | } | |
862 | case MP_BUS_EISA: /* EISA pin */ | |
863 | { | |
864 | trigger = default_EISA_trigger(idx); | |
865 | break; | |
866 | } | |
867 | case MP_BUS_PCI: /* PCI pin */ | |
868 | { | |
869 | /* set before the switch */ | |
870 | break; | |
871 | } | |
872 | case MP_BUS_MCA: /* MCA pin */ | |
873 | { | |
874 | trigger = default_MCA_trigger(idx); | |
875 | break; | |
876 | } | |
877 | default: | |
878 | { | |
879 | printk(KERN_WARNING "broken BIOS!!\n"); | |
880 | trigger = 1; | |
881 | break; | |
882 | } | |
883 | } | |
884 | #endif | |
1da177e4 | 885 | break; |
54168ed7 | 886 | case 1: /* edge */ |
1da177e4 | 887 | { |
54168ed7 | 888 | trigger = 0; |
1da177e4 LT |
889 | break; |
890 | } | |
54168ed7 | 891 | case 2: /* reserved */ |
1da177e4 | 892 | { |
54168ed7 IM |
893 | printk(KERN_WARNING "broken BIOS!!\n"); |
894 | trigger = 1; | |
1da177e4 LT |
895 | break; |
896 | } | |
54168ed7 | 897 | case 3: /* level */ |
1da177e4 | 898 | { |
54168ed7 | 899 | trigger = 1; |
1da177e4 LT |
900 | break; |
901 | } | |
54168ed7 | 902 | default: /* invalid */ |
1da177e4 LT |
903 | { |
904 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 905 | trigger = 0; |
1da177e4 LT |
906 | break; |
907 | } | |
908 | } | |
909 | return trigger; | |
910 | } | |
911 | ||
1da177e4 LT |
912 | static int pin_2_irq(int idx, int apic, int pin) |
913 | { | |
d464207c | 914 | int irq; |
c2c21745 | 915 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
916 | |
917 | /* | |
918 | * Debugging check, we are in big trouble if this message pops up! | |
919 | */ | |
c2c21745 | 920 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
921 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
922 | ||
54168ed7 | 923 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 924 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 925 | } else { |
d464207c | 926 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
927 | |
928 | if (gsi >= NR_IRQS_LEGACY) | |
929 | irq = gsi; | |
930 | else | |
a4384df3 | 931 | irq = gsi_top + gsi; |
1da177e4 LT |
932 | } |
933 | ||
54168ed7 | 934 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
935 | /* |
936 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
937 | */ | |
938 | if ((pin >= 16) && (pin <= 23)) { | |
939 | if (pirq_entries[pin-16] != -1) { | |
940 | if (!pirq_entries[pin-16]) { | |
941 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
942 | "disabling PIRQ%d\n", pin-16); | |
943 | } else { | |
944 | irq = pirq_entries[pin-16]; | |
945 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
946 | "using PIRQ%d -> IRQ %d\n", | |
947 | pin-16, irq); | |
948 | } | |
949 | } | |
950 | } | |
54168ed7 IM |
951 | #endif |
952 | ||
1da177e4 LT |
953 | return irq; |
954 | } | |
955 | ||
e20c06fd YL |
956 | /* |
957 | * Find a specific PCI IRQ entry. | |
958 | * Not an __init, possibly needed by modules | |
959 | */ | |
960 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 961 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
962 | { |
963 | int apic, i, best_guess = -1; | |
964 | ||
965 | apic_printk(APIC_DEBUG, | |
966 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
967 | bus, slot, pin); | |
968 | if (test_bit(bus, mp_bus_not_pci)) { | |
969 | apic_printk(APIC_VERBOSE, | |
970 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
971 | return -1; | |
972 | } | |
973 | for (i = 0; i < mp_irq_entries; i++) { | |
974 | int lbus = mp_irqs[i].srcbus; | |
975 | ||
976 | for (apic = 0; apic < nr_ioapics; apic++) | |
977 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
978 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
979 | break; | |
980 | ||
981 | if (!test_bit(lbus, mp_bus_not_pci) && | |
982 | !mp_irqs[i].irqtype && | |
983 | (bus == lbus) && | |
984 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
985 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
986 | ||
987 | if (!(apic || IO_APIC_IRQ(irq))) | |
988 | continue; | |
989 | ||
990 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
991 | set_io_apic_irq_attr(irq_attr, apic, |
992 | mp_irqs[i].dstirq, | |
993 | irq_trigger(i), | |
994 | irq_polarity(i)); | |
e20c06fd YL |
995 | return irq; |
996 | } | |
997 | /* | |
998 | * Use the first all-but-pin matching entry as a | |
999 | * best-guess fuzzy result for broken mptables. | |
1000 | */ | |
1001 | if (best_guess < 0) { | |
e5198075 YL |
1002 | set_io_apic_irq_attr(irq_attr, apic, |
1003 | mp_irqs[i].dstirq, | |
1004 | irq_trigger(i), | |
1005 | irq_polarity(i)); | |
e20c06fd YL |
1006 | best_guess = irq; |
1007 | } | |
1008 | } | |
1009 | } | |
1010 | return best_guess; | |
1011 | } | |
1012 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1013 | ||
497c9a19 YL |
1014 | void lock_vector_lock(void) |
1015 | { | |
1016 | /* Used to the online set of cpus does not change | |
1017 | * during assign_irq_vector. | |
1018 | */ | |
dade7716 | 1019 | raw_spin_lock(&vector_lock); |
497c9a19 | 1020 | } |
1da177e4 | 1021 | |
497c9a19 | 1022 | void unlock_vector_lock(void) |
1da177e4 | 1023 | { |
dade7716 | 1024 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1025 | } |
1da177e4 | 1026 | |
e7986739 MT |
1027 | static int |
1028 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1029 | { |
047c8fdb YL |
1030 | /* |
1031 | * NOTE! The local APIC isn't very good at handling | |
1032 | * multiple interrupts at the same interrupt level. | |
1033 | * As the interrupt level is determined by taking the | |
1034 | * vector number and shifting that right by 4, we | |
1035 | * want to spread these out a bit so that they don't | |
1036 | * all fall in the same interrupt level. | |
1037 | * | |
1038 | * Also, we've got to be careful not to trash gate | |
1039 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1040 | */ | |
6579b474 | 1041 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1042 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1043 | unsigned int old_vector; |
22f65d31 MT |
1044 | int cpu, err; |
1045 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1046 | |
23359a88 | 1047 | if (cfg->move_in_progress) |
54168ed7 | 1048 | return -EBUSY; |
0a1ad60d | 1049 | |
22f65d31 MT |
1050 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1051 | return -ENOMEM; | |
ace80ab7 | 1052 | |
54168ed7 IM |
1053 | old_vector = cfg->vector; |
1054 | if (old_vector) { | |
22f65d31 MT |
1055 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1056 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1057 | if (!cpumask_empty(tmp_mask)) { | |
1058 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1059 | return 0; |
22f65d31 | 1060 | } |
54168ed7 | 1061 | } |
497c9a19 | 1062 | |
e7986739 | 1063 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1064 | err = -ENOSPC; |
1065 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1066 | int new_cpu; |
1067 | int vector, offset; | |
497c9a19 | 1068 | |
e2d40b18 | 1069 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1070 | |
54168ed7 IM |
1071 | vector = current_vector; |
1072 | offset = current_offset; | |
497c9a19 | 1073 | next: |
54168ed7 IM |
1074 | vector += 8; |
1075 | if (vector >= first_system_vector) { | |
e7986739 | 1076 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1077 | offset = (offset + 1) % 8; |
6579b474 | 1078 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1079 | } |
1080 | if (unlikely(current_vector == vector)) | |
1081 | continue; | |
b77b881f YL |
1082 | |
1083 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1084 | goto next; |
b77b881f | 1085 | |
22f65d31 | 1086 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1087 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1088 | goto next; | |
1089 | /* Found one! */ | |
1090 | current_vector = vector; | |
1091 | current_offset = offset; | |
1092 | if (old_vector) { | |
1093 | cfg->move_in_progress = 1; | |
22f65d31 | 1094 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1095 | } |
22f65d31 | 1096 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1097 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1098 | cfg->vector = vector; | |
22f65d31 MT |
1099 | cpumask_copy(cfg->domain, tmp_mask); |
1100 | err = 0; | |
1101 | break; | |
54168ed7 | 1102 | } |
22f65d31 MT |
1103 | free_cpumask_var(tmp_mask); |
1104 | return err; | |
497c9a19 YL |
1105 | } |
1106 | ||
9338ad6f | 1107 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1108 | { |
1109 | int err; | |
ace80ab7 | 1110 | unsigned long flags; |
ace80ab7 | 1111 | |
dade7716 | 1112 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1113 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1114 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1115 | return err; |
1116 | } | |
1117 | ||
3145e941 | 1118 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1119 | { |
497c9a19 YL |
1120 | int cpu, vector; |
1121 | ||
497c9a19 YL |
1122 | BUG_ON(!cfg->vector); |
1123 | ||
1124 | vector = cfg->vector; | |
22f65d31 | 1125 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1126 | per_cpu(vector_irq, cpu)[vector] = -1; |
1127 | ||
1128 | cfg->vector = 0; | |
22f65d31 | 1129 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1130 | |
1131 | if (likely(!cfg->move_in_progress)) | |
1132 | return; | |
22f65d31 | 1133 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1134 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1135 | vector++) { | |
1136 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1137 | continue; | |
1138 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1139 | break; | |
1140 | } | |
1141 | } | |
1142 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1143 | } |
1144 | ||
1145 | void __setup_vector_irq(int cpu) | |
1146 | { | |
1147 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1148 | int irq, vector; |
1149 | struct irq_cfg *cfg; | |
1150 | ||
9d133e5d SS |
1151 | /* |
1152 | * vector_lock will make sure that we don't run into irq vector | |
1153 | * assignments that might be happening on another cpu in parallel, | |
1154 | * while we setup our initial vector to irq mappings. | |
1155 | */ | |
dade7716 | 1156 | raw_spin_lock(&vector_lock); |
497c9a19 | 1157 | /* Mark the inuse vectors */ |
ad9f4334 | 1158 | for_each_active_irq(irq) { |
2c778651 | 1159 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1160 | if (!cfg) |
1161 | continue; | |
36e9e1ea SS |
1162 | /* |
1163 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1164 | * will be part of the irq_cfg's domain. | |
1165 | */ | |
1166 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1167 | cpumask_set_cpu(cpu, cfg->domain); | |
1168 | ||
22f65d31 | 1169 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1170 | continue; |
1171 | vector = cfg->vector; | |
497c9a19 YL |
1172 | per_cpu(vector_irq, cpu)[vector] = irq; |
1173 | } | |
1174 | /* Mark the free vectors */ | |
1175 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1176 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1177 | if (irq < 0) | |
1178 | continue; | |
1179 | ||
1180 | cfg = irq_cfg(irq); | |
22f65d31 | 1181 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1182 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1183 | } |
dade7716 | 1184 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1185 | } |
3fde6900 | 1186 | |
f5b9ed7a | 1187 | static struct irq_chip ioapic_chip; |
54168ed7 | 1188 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1189 | |
047c8fdb | 1190 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1191 | static inline int IO_APIC_irq_trigger(int irq) |
1192 | { | |
d6c88a50 | 1193 | int apic, idx, pin; |
1d025192 | 1194 | |
d6c88a50 | 1195 | for (apic = 0; apic < nr_ioapics; apic++) { |
b69c6c3b | 1196 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
d6c88a50 TG |
1197 | idx = find_irq_entry(apic, pin, mp_INT); |
1198 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1199 | return irq_trigger(idx); | |
1200 | } | |
1201 | } | |
1202 | /* | |
54168ed7 IM |
1203 | * nonexistent IRQs are edge default |
1204 | */ | |
d6c88a50 | 1205 | return 0; |
1d025192 | 1206 | } |
047c8fdb YL |
1207 | #else |
1208 | static inline int IO_APIC_irq_trigger(int irq) | |
1209 | { | |
54168ed7 | 1210 | return 1; |
047c8fdb YL |
1211 | } |
1212 | #endif | |
1d025192 | 1213 | |
1a0e62a4 TG |
1214 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1215 | unsigned long trigger) | |
1da177e4 | 1216 | { |
c60eaf25 TG |
1217 | struct irq_chip *chip = &ioapic_chip; |
1218 | irq_flow_handler_t hdl; | |
1219 | bool fasteoi; | |
199751d7 | 1220 | |
6ebcc00e | 1221 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1222 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1223 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1224 | fasteoi = true; |
1225 | } else { | |
60c69948 | 1226 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1227 | fasteoi = false; |
1228 | } | |
047c8fdb | 1229 | |
1a0e62a4 | 1230 | if (irq_remapped(cfg)) { |
60c69948 | 1231 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
1232 | chip = &ir_ioapic_chip; |
1233 | fasteoi = trigger != 0; | |
54168ed7 | 1234 | } |
29b61be6 | 1235 | |
c60eaf25 TG |
1236 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1237 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1238 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1239 | } |
1240 | ||
1a8ce7ff TG |
1241 | static int setup_ioapic_entry(int apic_id, int irq, |
1242 | struct IO_APIC_route_entry *entry, | |
1243 | unsigned int destination, int trigger, | |
1244 | int polarity, int vector, int pin) | |
1da177e4 | 1245 | { |
497c9a19 YL |
1246 | /* |
1247 | * add it to the IO-APIC irq-routing table: | |
1248 | */ | |
1249 | memset(entry,0,sizeof(*entry)); | |
1250 | ||
54168ed7 | 1251 | if (intr_remapping_enabled) { |
c8d46cf0 | 1252 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1253 | struct irte irte; |
1254 | struct IR_IO_APIC_route_entry *ir_entry = | |
1255 | (struct IR_IO_APIC_route_entry *) entry; | |
1256 | int index; | |
1257 | ||
1258 | if (!iommu) | |
c8d46cf0 | 1259 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1260 | |
1261 | index = alloc_irte(iommu, irq, 1); | |
1262 | if (index < 0) | |
c8d46cf0 | 1263 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1264 | |
62a92f4c | 1265 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1266 | |
f007e99c WH |
1267 | /* Set source-id of interrupt request */ |
1268 | set_ioapic_sid(&irte, apic_id); | |
1269 | ||
54168ed7 IM |
1270 | modify_irte(irq, &irte); |
1271 | ||
1272 | ir_entry->index2 = (index >> 15) & 0x1; | |
1273 | ir_entry->zero = 0; | |
1274 | ir_entry->format = 1; | |
1275 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1276 | /* |
1277 | * IO-APIC RTE will be configured with virtual vector. | |
1278 | * irq handler will do the explicit EOI to the io-apic. | |
1279 | */ | |
1280 | ir_entry->vector = pin; | |
29b61be6 | 1281 | } else { |
9b5bc8dc IM |
1282 | entry->delivery_mode = apic->irq_delivery_mode; |
1283 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1284 | entry->dest = destination; |
0280f7c4 | 1285 | entry->vector = vector; |
54168ed7 | 1286 | } |
497c9a19 | 1287 | |
54168ed7 | 1288 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1289 | entry->trigger = trigger; |
1290 | entry->polarity = polarity; | |
497c9a19 YL |
1291 | |
1292 | /* Mask level triggered irqs. | |
1293 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1294 | */ | |
1295 | if (trigger) | |
1296 | entry->mask = 1; | |
497c9a19 YL |
1297 | return 0; |
1298 | } | |
1299 | ||
60c69948 TG |
1300 | static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, |
1301 | struct irq_cfg *cfg, int trigger, int polarity) | |
497c9a19 | 1302 | { |
1da177e4 | 1303 | struct IO_APIC_route_entry entry; |
22f65d31 | 1304 | unsigned int dest; |
497c9a19 YL |
1305 | |
1306 | if (!IO_APIC_IRQ(irq)) | |
1307 | return; | |
69c89efb SS |
1308 | /* |
1309 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1310 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1311 | * the cfg->domain. | |
1312 | */ | |
28c6a0ba | 1313 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1314 | apic->vector_allocation_domain(0, cfg->domain); |
1315 | ||
fe402e1f | 1316 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1317 | return; |
1318 | ||
debccb3e | 1319 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1320 | |
1321 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1322 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1323 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1324 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1325 | irq, trigger, polarity); |
1326 | ||
1327 | ||
c8d46cf0 | 1328 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1329 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1330 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1331 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1332 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1333 | return; |
1334 | } | |
1335 | ||
1a0e62a4 | 1336 | ioapic_register_intr(irq, cfg, trigger); |
b81bb373 | 1337 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1338 | legacy_pic->mask(irq); |
497c9a19 | 1339 | |
c8d46cf0 | 1340 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1341 | } |
1342 | ||
b9c61b70 YL |
1343 | static struct { |
1344 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1345 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1346 | ||
c8d6b8fe TG |
1347 | static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) |
1348 | { | |
1349 | if (idx != -1) | |
1350 | return false; | |
1351 | ||
1352 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
1353 | mp_ioapics[apic_id].apicid, pin); | |
1354 | return true; | |
1355 | } | |
1356 | ||
ed972ccf | 1357 | static void __init __io_apic_setup_irqs(unsigned int apic_id) |
497c9a19 | 1358 | { |
ed972ccf | 1359 | int idx, node = cpu_to_node(0); |
2d57e37d | 1360 | struct io_apic_irq_attr attr; |
ed972ccf | 1361 | unsigned int pin, irq; |
1da177e4 | 1362 | |
b69c6c3b | 1363 | for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) { |
b9c61b70 | 1364 | idx = find_irq_entry(apic_id, pin, mp_INT); |
c8d6b8fe | 1365 | if (io_apic_pin_not_connected(idx, apic_id, pin)) |
b9c61b70 | 1366 | continue; |
33a201fa | 1367 | |
b9c61b70 | 1368 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1369 | |
fad53995 EB |
1370 | if ((apic_id > 0) && (irq > 16)) |
1371 | continue; | |
1372 | ||
b9c61b70 YL |
1373 | /* |
1374 | * Skip the timer IRQ if there's a quirk handler | |
1375 | * installed and if it returns 1: | |
1376 | */ | |
1377 | if (apic->multi_timer_check && | |
2d57e37d | 1378 | apic->multi_timer_check(apic_id, irq)) |
b9c61b70 | 1379 | continue; |
36062448 | 1380 | |
2d57e37d TG |
1381 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1382 | irq_polarity(idx)); | |
fbc6bff0 | 1383 | |
2d57e37d | 1384 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1385 | } |
1da177e4 LT |
1386 | } |
1387 | ||
ed972ccf TG |
1388 | static void __init setup_IO_APIC_irqs(void) |
1389 | { | |
1390 | unsigned int apic_id; | |
1391 | ||
1392 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1393 | ||
1394 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) | |
1395 | __io_apic_setup_irqs(apic_id); | |
1396 | } | |
1397 | ||
18dce6ba YL |
1398 | /* |
1399 | * for the gsit that is not in first ioapic | |
1400 | * but could not use acpi_register_gsi() | |
1401 | * like some special sci in IBM x3330 | |
1402 | */ | |
1403 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1404 | { | |
fbc6bff0 | 1405 | int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1406 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1407 | |
1408 | /* | |
1409 | * Convert 'gsi' to 'ioapic.pin'. | |
1410 | */ | |
1411 | apic_id = mp_find_ioapic(gsi); | |
1412 | if (apic_id < 0) | |
1413 | return; | |
1414 | ||
1415 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1416 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1417 | if (idx == -1) | |
1418 | return; | |
1419 | ||
1420 | irq = pin_2_irq(idx, apic_id, pin); | |
fe6dab4e YL |
1421 | |
1422 | /* Only handle the non legacy irqs on secondary ioapics */ | |
1423 | if (apic_id == 0 || irq < NR_IRQS_LEGACY) | |
18dce6ba | 1424 | return; |
fe6dab4e | 1425 | |
da1ad9d7 TG |
1426 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1427 | irq_polarity(idx)); | |
1428 | ||
710dcda6 | 1429 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1430 | } |
1431 | ||
1da177e4 | 1432 | /* |
f7633ce5 | 1433 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1434 | */ |
c8d46cf0 | 1435 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1436 | int vector) |
1da177e4 LT |
1437 | { |
1438 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1439 | |
54168ed7 IM |
1440 | if (intr_remapping_enabled) |
1441 | return; | |
54168ed7 | 1442 | |
36062448 | 1443 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1444 | |
1445 | /* | |
1446 | * We use logical delivery to get the timer IRQ | |
1447 | * to the first CPU. | |
1448 | */ | |
9b5bc8dc | 1449 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1450 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1451 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1452 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1453 | entry.polarity = 0; |
1454 | entry.trigger = 0; | |
1455 | entry.vector = vector; | |
1456 | ||
1457 | /* | |
1458 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1459 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1460 | */ |
2c778651 TG |
1461 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1462 | "edge"); | |
1da177e4 LT |
1463 | |
1464 | /* | |
1465 | * Add it to the IO-APIC irq-routing table: | |
1466 | */ | |
c8d46cf0 | 1467 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1468 | } |
1469 | ||
32f71aff MR |
1470 | |
1471 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1472 | { |
1473 | int apic, i; | |
1474 | union IO_APIC_reg_00 reg_00; | |
1475 | union IO_APIC_reg_01 reg_01; | |
1476 | union IO_APIC_reg_02 reg_02; | |
1477 | union IO_APIC_reg_03 reg_03; | |
1478 | unsigned long flags; | |
0f978f45 | 1479 | struct irq_cfg *cfg; |
8f09cd20 | 1480 | unsigned int irq; |
1da177e4 | 1481 | |
36062448 | 1482 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1483 | for (i = 0; i < nr_ioapics; i++) |
1484 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b69c6c3b | 1485 | mp_ioapics[i].apicid, ioapics[i].nr_registers); |
1da177e4 LT |
1486 | |
1487 | /* | |
1488 | * We are a bit conservative about what we expect. We have to | |
1489 | * know about every hardware change ASAP. | |
1490 | */ | |
1491 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1492 | ||
1493 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1494 | ||
dade7716 | 1495 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1496 | reg_00.raw = io_apic_read(apic, 0); |
1497 | reg_01.raw = io_apic_read(apic, 1); | |
1498 | if (reg_01.bits.version >= 0x10) | |
1499 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1500 | if (reg_01.bits.version >= 0x20) |
1501 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1502 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1503 | |
54168ed7 | 1504 | printk("\n"); |
b5ba7e6d | 1505 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1506 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1507 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1508 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1509 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1510 | |
54168ed7 | 1511 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1512 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1513 | |
1514 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1515 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1516 | |
1517 | /* | |
1518 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1519 | * but the value of reg_02 is read as the previous read register | |
1520 | * value, so ignore it if reg_02 == reg_01. | |
1521 | */ | |
1522 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1523 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1524 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1525 | } |
1526 | ||
1527 | /* | |
1528 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1529 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1530 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1531 | */ | |
1532 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1533 | reg_03.raw != reg_01.raw) { | |
1534 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1535 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1536 | } |
1537 | ||
1538 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1539 | ||
d83e94ac | 1540 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1541 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1542 | |
1543 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1544 | struct IO_APIC_route_entry entry; | |
1545 | ||
cf4c6a2f | 1546 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1547 | |
54168ed7 IM |
1548 | printk(KERN_DEBUG " %02x %03X ", |
1549 | i, | |
1550 | entry.dest | |
1551 | ); | |
1da177e4 LT |
1552 | |
1553 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1554 | entry.mask, | |
1555 | entry.trigger, | |
1556 | entry.irr, | |
1557 | entry.polarity, | |
1558 | entry.delivery_status, | |
1559 | entry.dest_mode, | |
1560 | entry.delivery_mode, | |
1561 | entry.vector | |
1562 | ); | |
1563 | } | |
1564 | } | |
1da177e4 | 1565 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1566 | for_each_active_irq(irq) { |
0b8f1efa YL |
1567 | struct irq_pin_list *entry; |
1568 | ||
2c778651 | 1569 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1570 | if (!cfg) |
1571 | continue; | |
0b8f1efa | 1572 | entry = cfg->irq_2_pin; |
0f978f45 | 1573 | if (!entry) |
1da177e4 | 1574 | continue; |
8f09cd20 | 1575 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1576 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1577 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1578 | printk("\n"); |
1579 | } | |
1580 | ||
1581 | printk(KERN_INFO ".................................... done.\n"); | |
1582 | ||
1583 | return; | |
1584 | } | |
1585 | ||
251e1e44 | 1586 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1587 | { |
251e1e44 | 1588 | int i; |
1da177e4 | 1589 | |
251e1e44 IM |
1590 | printk(KERN_DEBUG); |
1591 | ||
1592 | for (i = 0; i < 8; i++) | |
1593 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1594 | ||
1595 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1596 | } |
1597 | ||
32f71aff | 1598 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1599 | { |
97a52714 | 1600 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1601 | u64 icr; |
1da177e4 | 1602 | |
251e1e44 | 1603 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1604 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1605 | v = apic_read(APIC_ID); |
54168ed7 | 1606 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1607 | v = apic_read(APIC_LVR); |
1608 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1609 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1610 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1611 | |
1612 | v = apic_read(APIC_TASKPRI); | |
1613 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1614 | ||
54168ed7 | 1615 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1616 | if (!APIC_XAPIC(ver)) { |
1617 | v = apic_read(APIC_ARBPRI); | |
1618 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1619 | v & APIC_ARBPRI_MASK); | |
1620 | } | |
1da177e4 LT |
1621 | v = apic_read(APIC_PROCPRI); |
1622 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1623 | } | |
1624 | ||
a11b5abe YL |
1625 | /* |
1626 | * Remote read supported only in the 82489DX and local APIC for | |
1627 | * Pentium processors. | |
1628 | */ | |
1629 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1630 | v = apic_read(APIC_RRR); | |
1631 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1632 | } | |
1633 | ||
1da177e4 LT |
1634 | v = apic_read(APIC_LDR); |
1635 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1636 | if (!x2apic_enabled()) { |
1637 | v = apic_read(APIC_DFR); | |
1638 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1639 | } | |
1da177e4 LT |
1640 | v = apic_read(APIC_SPIV); |
1641 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1642 | ||
1643 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1644 | print_APIC_field(APIC_ISR); |
1da177e4 | 1645 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1646 | print_APIC_field(APIC_TMR); |
1da177e4 | 1647 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1648 | print_APIC_field(APIC_IRR); |
1da177e4 | 1649 | |
54168ed7 IM |
1650 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1651 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1652 | apic_write(APIC_ESR, 0); |
54168ed7 | 1653 | |
1da177e4 LT |
1654 | v = apic_read(APIC_ESR); |
1655 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1656 | } | |
1657 | ||
7ab6af7a | 1658 | icr = apic_icr_read(); |
0c425cec IM |
1659 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1660 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1661 | |
1662 | v = apic_read(APIC_LVTT); | |
1663 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1664 | ||
1665 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1666 | v = apic_read(APIC_LVTPC); | |
1667 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1668 | } | |
1669 | v = apic_read(APIC_LVT0); | |
1670 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1671 | v = apic_read(APIC_LVT1); | |
1672 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1673 | ||
1674 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1675 | v = apic_read(APIC_LVTERR); | |
1676 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1677 | } | |
1678 | ||
1679 | v = apic_read(APIC_TMICT); | |
1680 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1681 | v = apic_read(APIC_TMCCT); | |
1682 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1683 | v = apic_read(APIC_TDCR); | |
1684 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1685 | |
1686 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1687 | v = apic_read(APIC_EFEAT); | |
1688 | maxlvt = (v >> 16) & 0xff; | |
1689 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1690 | v = apic_read(APIC_ECTRL); | |
1691 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1692 | for (i = 0; i < maxlvt; i++) { | |
1693 | v = apic_read(APIC_EILVTn(i)); | |
1694 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1695 | } | |
1696 | } | |
1da177e4 LT |
1697 | printk("\n"); |
1698 | } | |
1699 | ||
2626eb2b | 1700 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1701 | { |
ffd5aae7 YL |
1702 | int cpu; |
1703 | ||
2626eb2b CG |
1704 | if (!maxcpu) |
1705 | return; | |
1706 | ||
ffd5aae7 | 1707 | preempt_disable(); |
2626eb2b CG |
1708 | for_each_online_cpu(cpu) { |
1709 | if (cpu >= maxcpu) | |
1710 | break; | |
ffd5aae7 | 1711 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1712 | } |
ffd5aae7 | 1713 | preempt_enable(); |
1da177e4 LT |
1714 | } |
1715 | ||
32f71aff | 1716 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1717 | { |
1da177e4 LT |
1718 | unsigned int v; |
1719 | unsigned long flags; | |
1720 | ||
b81bb373 | 1721 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1722 | return; |
1723 | ||
1724 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1725 | ||
5619c280 | 1726 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1727 | |
1728 | v = inb(0xa1) << 8 | inb(0x21); | |
1729 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1730 | ||
1731 | v = inb(0xa0) << 8 | inb(0x20); | |
1732 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1733 | ||
54168ed7 IM |
1734 | outb(0x0b,0xa0); |
1735 | outb(0x0b,0x20); | |
1da177e4 | 1736 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1737 | outb(0x0a,0xa0); |
1738 | outb(0x0a,0x20); | |
1da177e4 | 1739 | |
5619c280 | 1740 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1741 | |
1742 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1743 | ||
1744 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1745 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1746 | } | |
1747 | ||
2626eb2b CG |
1748 | static int __initdata show_lapic = 1; |
1749 | static __init int setup_show_lapic(char *arg) | |
1750 | { | |
1751 | int num = -1; | |
1752 | ||
1753 | if (strcmp(arg, "all") == 0) { | |
1754 | show_lapic = CONFIG_NR_CPUS; | |
1755 | } else { | |
1756 | get_option(&arg, &num); | |
1757 | if (num >= 0) | |
1758 | show_lapic = num; | |
1759 | } | |
1760 | ||
1761 | return 1; | |
1762 | } | |
1763 | __setup("show_lapic=", setup_show_lapic); | |
1764 | ||
1765 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1766 | { |
2626eb2b CG |
1767 | if (apic_verbosity == APIC_QUIET) |
1768 | return 0; | |
1769 | ||
32f71aff | 1770 | print_PIC(); |
4797f6b0 YL |
1771 | |
1772 | /* don't print out if apic is not there */ | |
8312136f | 1773 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1774 | return 0; |
1775 | ||
2626eb2b | 1776 | print_local_APICs(show_lapic); |
32f71aff MR |
1777 | print_IO_APIC(); |
1778 | ||
1779 | return 0; | |
1780 | } | |
1781 | ||
2626eb2b | 1782 | fs_initcall(print_ICs); |
32f71aff | 1783 | |
1da177e4 | 1784 | |
efa2559f YL |
1785 | /* Where if anywhere is the i8259 connect in external int mode */ |
1786 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1787 | ||
54168ed7 | 1788 | void __init enable_IO_APIC(void) |
1da177e4 | 1789 | { |
fcfd636a | 1790 | int i8259_apic, i8259_pin; |
54168ed7 | 1791 | int apic; |
bc07844a | 1792 | |
b81bb373 | 1793 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1794 | return; |
1795 | ||
54168ed7 | 1796 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1797 | int pin; |
1798 | /* See if any of the pins is in ExtINT mode */ | |
b69c6c3b | 1799 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
fcfd636a | 1800 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1801 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1802 | |
fcfd636a EB |
1803 | /* If the interrupt line is enabled and in ExtInt mode |
1804 | * I have found the pin where the i8259 is connected. | |
1805 | */ | |
1806 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1807 | ioapic_i8259.apic = apic; | |
1808 | ioapic_i8259.pin = pin; | |
1809 | goto found_i8259; | |
1810 | } | |
1811 | } | |
1812 | } | |
1813 | found_i8259: | |
1814 | /* Look to see what if the MP table has reported the ExtINT */ | |
1815 | /* If we could not find the appropriate pin by looking at the ioapic | |
1816 | * the i8259 probably is not connected the ioapic but give the | |
1817 | * mptable a chance anyway. | |
1818 | */ | |
1819 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1820 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1821 | /* Trust the MP table if nothing is setup in the hardware */ | |
1822 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1823 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1824 | ioapic_i8259.pin = i8259_pin; | |
1825 | ioapic_i8259.apic = i8259_apic; | |
1826 | } | |
1827 | /* Complain if the MP table and the hardware disagree */ | |
1828 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1829 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1830 | { | |
1831 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1832 | } |
1833 | ||
1834 | /* | |
1835 | * Do not trust the IO-APIC being empty at bootup | |
1836 | */ | |
1837 | clear_IO_APIC(); | |
1838 | } | |
1839 | ||
1840 | /* | |
1841 | * Not an __init, needed by the reboot code | |
1842 | */ | |
1843 | void disable_IO_APIC(void) | |
1844 | { | |
1845 | /* | |
1846 | * Clear the IO-APIC before rebooting: | |
1847 | */ | |
1848 | clear_IO_APIC(); | |
1849 | ||
b81bb373 | 1850 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1851 | return; |
1852 | ||
650927ef | 1853 | /* |
0b968d23 | 1854 | * If the i8259 is routed through an IOAPIC |
650927ef | 1855 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1856 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1857 | * |
1858 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1859 | * as virtual wire B is little complex (need to configure both | |
0d2eb44f | 1860 | * IOAPIC RTE as well as interrupt-remapping table entry). |
7c6d9f97 | 1861 | * As this gets called during crash dump, keep this simple for now. |
650927ef | 1862 | */ |
7c6d9f97 | 1863 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1864 | struct IO_APIC_route_entry entry; |
650927ef EB |
1865 | |
1866 | memset(&entry, 0, sizeof(entry)); | |
1867 | entry.mask = 0; /* Enabled */ | |
1868 | entry.trigger = 0; /* Edge */ | |
1869 | entry.irr = 0; | |
1870 | entry.polarity = 0; /* High */ | |
1871 | entry.delivery_status = 0; | |
1872 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1873 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1874 | entry.vector = 0; |
54168ed7 | 1875 | entry.dest = read_apic_id(); |
650927ef EB |
1876 | |
1877 | /* | |
1878 | * Add it to the IO-APIC irq-routing table: | |
1879 | */ | |
cf4c6a2f | 1880 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1881 | } |
54168ed7 | 1882 | |
7c6d9f97 SS |
1883 | /* |
1884 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1885 | */ | |
8312136f | 1886 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1887 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1888 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1889 | } |
1890 | ||
54168ed7 | 1891 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1892 | /* |
1893 | * function to set the IO-APIC physical IDs based on the | |
1894 | * values stored in the MPC table. | |
1895 | * | |
1896 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1897 | */ | |
a38c5380 | 1898 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1899 | { |
1900 | union IO_APIC_reg_00 reg_00; | |
1901 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1902 | int apic_id; |
1da177e4 LT |
1903 | int i; |
1904 | unsigned char old_id; | |
1905 | unsigned long flags; | |
1906 | ||
1907 | /* | |
1908 | * This is broken; anything with a real cpu count has to | |
1909 | * circumvent this idiocy regardless. | |
1910 | */ | |
7abc0753 | 1911 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1912 | |
1913 | /* | |
1914 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1915 | */ | |
c8d46cf0 | 1916 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
1917 | |
1918 | /* Read the register 0 value */ | |
dade7716 | 1919 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1920 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1921 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1922 | |
c8d46cf0 | 1923 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 1924 | |
c8d46cf0 | 1925 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 1926 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 1927 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1928 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1929 | reg_00.bits.ID); | |
c8d46cf0 | 1930 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
1931 | } |
1932 | ||
1da177e4 LT |
1933 | /* |
1934 | * Sanity check, is the ID really free? Every APIC in a | |
1935 | * system must have a unique ID or we get lots of nice | |
1936 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1937 | */ | |
7abc0753 | 1938 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 1939 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 1940 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 1941 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1942 | for (i = 0; i < get_physical_broadcast(); i++) |
1943 | if (!physid_isset(i, phys_id_present_map)) | |
1944 | break; | |
1945 | if (i >= get_physical_broadcast()) | |
1946 | panic("Max APIC ID exceeded!\n"); | |
1947 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1948 | i); | |
1949 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 1950 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
1951 | } else { |
1952 | physid_mask_t tmp; | |
7abc0753 | 1953 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
1954 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1955 | "phys_id_present_map\n", | |
c8d46cf0 | 1956 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1957 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1958 | } | |
1959 | ||
1da177e4 LT |
1960 | /* |
1961 | * We need to adjust the IRQ routing table | |
1962 | * if the ID changed. | |
1963 | */ | |
c8d46cf0 | 1964 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 1965 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1966 | if (mp_irqs[i].dstapic == old_id) |
1967 | mp_irqs[i].dstapic | |
c8d46cf0 | 1968 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
1969 | |
1970 | /* | |
60d79fd9 YL |
1971 | * Update the ID register according to the right value |
1972 | * from the MPC table if they are different. | |
36062448 | 1973 | */ |
60d79fd9 YL |
1974 | if (mp_ioapics[apic_id].apicid == reg_00.bits.ID) |
1975 | continue; | |
1976 | ||
1da177e4 LT |
1977 | apic_printk(APIC_VERBOSE, KERN_INFO |
1978 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 1979 | mp_ioapics[apic_id].apicid); |
1da177e4 | 1980 | |
c8d46cf0 | 1981 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 1982 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1983 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 1984 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1985 | |
1986 | /* | |
1987 | * Sanity check | |
1988 | */ | |
dade7716 | 1989 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1990 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1991 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 1992 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
1993 | printk("could not set ID!\n"); |
1994 | else | |
1995 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1996 | } | |
1997 | } | |
a38c5380 SAS |
1998 | |
1999 | void __init setup_ioapic_ids_from_mpc(void) | |
2000 | { | |
2001 | ||
2002 | if (acpi_ioapic) | |
2003 | return; | |
2004 | /* | |
2005 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2006 | * no meaning without the serial APIC bus. | |
2007 | */ | |
2008 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2009 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2010 | return; | |
2011 | setup_ioapic_ids_from_mpc_nocheck(); | |
2012 | } | |
54168ed7 | 2013 | #endif |
1da177e4 | 2014 | |
7ce0bcfd | 2015 | int no_timer_check __initdata; |
8542b200 ZA |
2016 | |
2017 | static int __init notimercheck(char *s) | |
2018 | { | |
2019 | no_timer_check = 1; | |
2020 | return 1; | |
2021 | } | |
2022 | __setup("no_timer_check", notimercheck); | |
2023 | ||
1da177e4 LT |
2024 | /* |
2025 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2026 | * about the timer IRQ. We do the following to work around the situation: | |
2027 | * | |
2028 | * - timer IRQ defaults to IO-APIC IRQ | |
2029 | * - if this function detects that timer IRQs are defunct, then we fall | |
2030 | * back to ISA timer IRQs | |
2031 | */ | |
f0a7a5c9 | 2032 | static int __init timer_irq_works(void) |
1da177e4 LT |
2033 | { |
2034 | unsigned long t1 = jiffies; | |
4aae0702 | 2035 | unsigned long flags; |
1da177e4 | 2036 | |
8542b200 ZA |
2037 | if (no_timer_check) |
2038 | return 1; | |
2039 | ||
4aae0702 | 2040 | local_save_flags(flags); |
1da177e4 LT |
2041 | local_irq_enable(); |
2042 | /* Let ten ticks pass... */ | |
2043 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2044 | local_irq_restore(flags); |
1da177e4 LT |
2045 | |
2046 | /* | |
2047 | * Expect a few ticks at least, to be sure some possible | |
2048 | * glue logic does not lock up after one or two first | |
2049 | * ticks in a non-ExtINT mode. Also the local APIC | |
2050 | * might have cached one ExtINT interrupt. Finally, at | |
2051 | * least one tick may be lost due to delays. | |
2052 | */ | |
54168ed7 IM |
2053 | |
2054 | /* jiffies wrap? */ | |
1d16b53e | 2055 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2056 | return 1; |
1da177e4 LT |
2057 | return 0; |
2058 | } | |
2059 | ||
2060 | /* | |
2061 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2062 | * number of pending IRQ events unhandled. These cases are very rare, | |
2063 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2064 | * better to do it this way as thus we do not have to be aware of | |
2065 | * 'pending' interrupts in the IRQ path, except at this point. | |
2066 | */ | |
2067 | /* | |
2068 | * Edge triggered needs to resend any interrupt | |
2069 | * that was delayed but this is now handled in the device | |
2070 | * independent code. | |
2071 | */ | |
2072 | ||
2073 | /* | |
2074 | * Starting up a edge-triggered IO-APIC interrupt is | |
2075 | * nasty - we need to make sure that we get the edge. | |
2076 | * If it is already asserted for some reason, we need | |
2077 | * return 1 to indicate that is was pending. | |
2078 | * | |
2079 | * This is not complete - we should be able to fake | |
2080 | * an edge even if it isn't on the 8259A... | |
2081 | */ | |
54168ed7 | 2082 | |
61a38ce3 | 2083 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2084 | { |
61a38ce3 | 2085 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2086 | unsigned long flags; |
2087 | ||
dade7716 | 2088 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2089 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2090 | legacy_pic->mask(irq); |
b81bb373 | 2091 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2092 | was_pending = 1; |
2093 | } | |
61a38ce3 | 2094 | __unmask_ioapic(data->chip_data); |
dade7716 | 2095 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2096 | |
2097 | return was_pending; | |
2098 | } | |
2099 | ||
90297c5f | 2100 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2101 | { |
90297c5f | 2102 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2103 | unsigned long flags; |
2104 | ||
dade7716 | 2105 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2106 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2107 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2108 | |
2109 | return 1; | |
2110 | } | |
497c9a19 | 2111 | |
54168ed7 IM |
2112 | /* |
2113 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2114 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2115 | * handled with the level-triggered descriptor, but that one has slightly | |
2116 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2117 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2118 | * races. | |
2119 | */ | |
497c9a19 | 2120 | |
54168ed7 | 2121 | #ifdef CONFIG_SMP |
9338ad6f | 2122 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2123 | { |
2124 | cpumask_var_t cleanup_mask; | |
2125 | ||
2126 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2127 | unsigned int i; | |
e85abf8f GH |
2128 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2129 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2130 | } else { | |
2131 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2132 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2133 | free_cpumask_var(cleanup_mask); | |
2134 | } | |
2135 | cfg->move_in_progress = 0; | |
2136 | } | |
2137 | ||
4420471f | 2138 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2139 | { |
2140 | int apic, pin; | |
2141 | struct irq_pin_list *entry; | |
2142 | u8 vector = cfg->vector; | |
2143 | ||
2977fb3f | 2144 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2145 | unsigned int reg; |
2146 | ||
e85abf8f GH |
2147 | apic = entry->apic; |
2148 | pin = entry->pin; | |
2149 | /* | |
2150 | * With interrupt-remapping, destination information comes | |
2151 | * from interrupt-remapping table entry. | |
2152 | */ | |
1a0730d6 | 2153 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2154 | io_apic_write(apic, 0x11 + pin*2, dest); |
2155 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2156 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2157 | reg |= vector; | |
2158 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2159 | } |
2160 | } | |
2161 | ||
2162 | /* | |
f7e909ea | 2163 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2164 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2165 | * leaves data->affinity untouched. |
e85abf8f | 2166 | */ |
f7e909ea TG |
2167 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2168 | unsigned int *dest_id) | |
e85abf8f | 2169 | { |
f7e909ea | 2170 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2171 | |
2172 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2173 | return -1; |
e85abf8f | 2174 | |
f7e909ea | 2175 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2176 | return -1; |
e85abf8f | 2177 | |
f7e909ea | 2178 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2179 | |
f7e909ea | 2180 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2181 | return 0; |
e85abf8f GH |
2182 | } |
2183 | ||
4420471f | 2184 | static int |
f7e909ea TG |
2185 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2186 | bool force) | |
e85abf8f | 2187 | { |
f7e909ea | 2188 | unsigned int dest, irq = data->irq; |
e85abf8f | 2189 | unsigned long flags; |
f7e909ea | 2190 | int ret; |
e85abf8f | 2191 | |
dade7716 | 2192 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2193 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2194 | if (!ret) { |
e85abf8f GH |
2195 | /* Only the high 8 bits are valid. */ |
2196 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2197 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2198 | } |
dade7716 | 2199 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2200 | return ret; |
e85abf8f GH |
2201 | } |
2202 | ||
54168ed7 | 2203 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2204 | |
54168ed7 IM |
2205 | /* |
2206 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2207 | * | |
0280f7c4 SS |
2208 | * For both level and edge triggered, irq migration is a simple atomic |
2209 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2210 | * |
0280f7c4 SS |
2211 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2212 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2213 | * Real vector that is used for interrupting cpu will be coming from | |
2214 | * the interrupt-remapping table entry. | |
54168ed7 | 2215 | */ |
d5dedd45 | 2216 | static int |
f19f5ecc TG |
2217 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2218 | bool force) | |
497c9a19 | 2219 | { |
f19f5ecc TG |
2220 | struct irq_cfg *cfg = data->chip_data; |
2221 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2222 | struct irte irte; |
497c9a19 | 2223 | |
22f65d31 | 2224 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2225 | return -EINVAL; |
497c9a19 | 2226 | |
54168ed7 | 2227 | if (get_irte(irq, &irte)) |
f19f5ecc | 2228 | return -EBUSY; |
497c9a19 | 2229 | |
3145e941 | 2230 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2231 | return -EBUSY; |
54168ed7 | 2232 | |
debccb3e | 2233 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2234 | |
54168ed7 IM |
2235 | irte.vector = cfg->vector; |
2236 | irte.dest_id = IRTE_DEST(dest); | |
2237 | ||
2238 | /* | |
2239 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2240 | */ | |
2241 | modify_irte(irq, &irte); | |
2242 | ||
22f65d31 MT |
2243 | if (cfg->move_in_progress) |
2244 | send_cleanup_vector(cfg); | |
54168ed7 | 2245 | |
f19f5ecc | 2246 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2247 | return 0; |
54168ed7 IM |
2248 | } |
2249 | ||
29b61be6 | 2250 | #else |
f19f5ecc TG |
2251 | static inline int |
2252 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2253 | bool force) | |
29b61be6 | 2254 | { |
d5dedd45 | 2255 | return 0; |
29b61be6 | 2256 | } |
54168ed7 IM |
2257 | #endif |
2258 | ||
2259 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2260 | { | |
2261 | unsigned vector, me; | |
8f2466f4 | 2262 | |
54168ed7 | 2263 | ack_APIC_irq(); |
54168ed7 | 2264 | exit_idle(); |
54168ed7 IM |
2265 | irq_enter(); |
2266 | ||
2267 | me = smp_processor_id(); | |
2268 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2269 | unsigned int irq; | |
68a8ca59 | 2270 | unsigned int irr; |
54168ed7 IM |
2271 | struct irq_desc *desc; |
2272 | struct irq_cfg *cfg; | |
0a3aee0d | 2273 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2274 | |
0b8f1efa YL |
2275 | if (irq == -1) |
2276 | continue; | |
2277 | ||
54168ed7 IM |
2278 | desc = irq_to_desc(irq); |
2279 | if (!desc) | |
2280 | continue; | |
2281 | ||
2282 | cfg = irq_cfg(irq); | |
239007b8 | 2283 | raw_spin_lock(&desc->lock); |
54168ed7 | 2284 | |
7f41c2e1 SS |
2285 | /* |
2286 | * Check if the irq migration is in progress. If so, we | |
2287 | * haven't received the cleanup request yet for this irq. | |
2288 | */ | |
2289 | if (cfg->move_in_progress) | |
2290 | goto unlock; | |
2291 | ||
22f65d31 | 2292 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2293 | goto unlock; |
2294 | ||
68a8ca59 SS |
2295 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2296 | /* | |
2297 | * Check if the vector that needs to be cleanedup is | |
2298 | * registered at the cpu's IRR. If so, then this is not | |
2299 | * the best time to clean it up. Lets clean it up in the | |
2300 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2301 | * to myself. | |
2302 | */ | |
2303 | if (irr & (1 << (vector % 32))) { | |
2304 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2305 | goto unlock; | |
2306 | } | |
0a3aee0d | 2307 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2308 | unlock: |
239007b8 | 2309 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2310 | } |
2311 | ||
2312 | irq_exit(); | |
2313 | } | |
2314 | ||
dd5f15e5 | 2315 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2316 | { |
a5e74b84 | 2317 | unsigned me; |
54168ed7 | 2318 | |
fcef5911 | 2319 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2320 | return; |
2321 | ||
54168ed7 | 2322 | me = smp_processor_id(); |
10b888d6 | 2323 | |
fcef5911 | 2324 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2325 | send_cleanup_vector(cfg); |
497c9a19 | 2326 | } |
a5e74b84 | 2327 | |
dd5f15e5 | 2328 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2329 | { |
dd5f15e5 | 2330 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2331 | } |
2332 | ||
2333 | void irq_force_complete_move(int irq) | |
2334 | { | |
2c778651 | 2335 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2336 | |
bbd391a1 PB |
2337 | if (!cfg) |
2338 | return; | |
2339 | ||
dd5f15e5 | 2340 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2341 | } |
497c9a19 | 2342 | #else |
dd5f15e5 | 2343 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2344 | #endif |
3145e941 | 2345 | |
90297c5f | 2346 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2347 | { |
90297c5f | 2348 | irq_complete_move(data->chip_data); |
08221110 | 2349 | irq_move_irq(data); |
1d025192 YL |
2350 | ack_APIC_irq(); |
2351 | } | |
2352 | ||
3eb2cce8 | 2353 | atomic_t irq_mis_count; |
3eb2cce8 | 2354 | |
c29d9db3 SS |
2355 | /* |
2356 | * IO-APIC versions below 0x20 don't support EOI register. | |
2357 | * For the record, here is the information about various versions: | |
2358 | * 0Xh 82489DX | |
2359 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2360 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2361 | * 30h-FFh Reserved | |
2362 | * | |
2363 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2364 | * version as 0x2. This is an error with documentation and these ICH chips | |
2365 | * use io-apic's of version 0x20. | |
2366 | * | |
2367 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2368 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2369 | * mode to edge and then back to level, with RTE being masked during this. | |
2370 | */ | |
dd5f15e5 | 2371 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2372 | { |
2373 | struct irq_pin_list *entry; | |
dd5f15e5 | 2374 | unsigned long flags; |
b3ec0a37 | 2375 | |
dd5f15e5 | 2376 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2377 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2378 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2379 | /* | |
2380 | * Intr-remapping uses pin number as the virtual vector | |
2381 | * in the RTE. Actual vector is programmed in | |
2382 | * intr-remapping table entry. Hence for the io-apic | |
2383 | * EOI we use the pin number. | |
2384 | */ | |
1a0730d6 | 2385 | if (irq_remapped(cfg)) |
c29d9db3 SS |
2386 | io_apic_eoi(entry->apic, entry->pin); |
2387 | else | |
2388 | io_apic_eoi(entry->apic, cfg->vector); | |
2389 | } else { | |
2390 | __mask_and_edge_IO_APIC_irq(entry); | |
2391 | __unmask_and_level_IO_APIC_irq(entry); | |
2392 | } | |
b3ec0a37 | 2393 | } |
dade7716 | 2394 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2395 | } |
2396 | ||
90297c5f | 2397 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2398 | { |
90297c5f TG |
2399 | struct irq_cfg *cfg = data->chip_data; |
2400 | int i, do_unmask_irq = 0, irq = data->irq; | |
3eb2cce8 | 2401 | unsigned long v; |
047c8fdb | 2402 | |
dd5f15e5 | 2403 | irq_complete_move(cfg); |
047c8fdb | 2404 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2405 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2406 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
54168ed7 | 2407 | do_unmask_irq = 1; |
dd5f15e5 | 2408 | mask_ioapic(cfg); |
54168ed7 | 2409 | } |
047c8fdb YL |
2410 | #endif |
2411 | ||
3eb2cce8 | 2412 | /* |
916a0fe7 JF |
2413 | * It appears there is an erratum which affects at least version 0x11 |
2414 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2415 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2416 | * erroneously delivered as edge-triggered one but the respective IRR | |
2417 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2418 | * message but it will never arrive and further interrupts are blocked | |
2419 | * from the source. The exact reason is so far unknown, but the | |
2420 | * phenomenon was observed when two consecutive interrupt requests | |
2421 | * from a given source get delivered to the same CPU and the source is | |
2422 | * temporarily disabled in between. | |
2423 | * | |
2424 | * A workaround is to simulate an EOI message manually. We achieve it | |
2425 | * by setting the trigger mode to edge and then to level when the edge | |
2426 | * trigger mode gets detected in the TMR of a local APIC for a | |
2427 | * level-triggered interrupt. We mask the source for the time of the | |
2428 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2429 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2430 | * |
2431 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2432 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2433 | * destination that is handling the corresponding interrupt. This | |
2434 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2435 | * level-triggered io-apic interrupt will be seen as an edge | |
2436 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2437 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2438 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2439 | * supporting EOI register, we do an explicit EOI to clear the | |
2440 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2441 | * we use the above logic (mask+edge followed by unmask+level) from | |
2442 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2443 | */ |
3145e941 | 2444 | i = cfg->vector; |
3eb2cce8 | 2445 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2446 | |
54168ed7 IM |
2447 | /* |
2448 | * We must acknowledge the irq before we move it or the acknowledge will | |
2449 | * not propagate properly. | |
2450 | */ | |
2451 | ack_APIC_irq(); | |
2452 | ||
1c83995b SS |
2453 | /* |
2454 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2455 | * message via io-apic EOI register write or simulating it using | |
2456 | * mask+edge followed by unnask+level logic) manually when the | |
2457 | * level triggered interrupt is seen as the edge triggered interrupt | |
2458 | * at the cpu. | |
2459 | */ | |
ca64c47c MR |
2460 | if (!(v & (1 << (i & 0x1f)))) { |
2461 | atomic_inc(&irq_mis_count); | |
2462 | ||
dd5f15e5 | 2463 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2464 | } |
2465 | ||
54168ed7 IM |
2466 | /* Now we can move and renable the irq */ |
2467 | if (unlikely(do_unmask_irq)) { | |
2468 | /* Only migrate the irq if the ack has been received. | |
2469 | * | |
2470 | * On rare occasions the broadcast level triggered ack gets | |
2471 | * delayed going to ioapics, and if we reprogram the | |
2472 | * vector while Remote IRR is still set the irq will never | |
2473 | * fire again. | |
2474 | * | |
2475 | * To prevent this scenario we read the Remote IRR bit | |
2476 | * of the ioapic. This has two effects. | |
2477 | * - On any sane system the read of the ioapic will | |
2478 | * flush writes (and acks) going to the ioapic from | |
2479 | * this cpu. | |
2480 | * - We get to see if the ACK has actually been delivered. | |
2481 | * | |
2482 | * Based on failed experiments of reprogramming the | |
2483 | * ioapic entry from outside of irq context starting | |
2484 | * with masking the ioapic entry and then polling until | |
2485 | * Remote IRR was clear before reprogramming the | |
2486 | * ioapic I don't trust the Remote IRR bit to be | |
2487 | * completey accurate. | |
2488 | * | |
2489 | * However there appears to be no other way to plug | |
2490 | * this race, so if the Remote IRR bit is not | |
2491 | * accurate and is causing problems then it is a hardware bug | |
2492 | * and you can go talk to the chipset vendor about it. | |
2493 | */ | |
3145e941 | 2494 | if (!io_apic_level_ack_pending(cfg)) |
08221110 | 2495 | irq_move_masked_irq(data); |
dd5f15e5 | 2496 | unmask_ioapic(cfg); |
54168ed7 | 2497 | } |
3eb2cce8 | 2498 | } |
1d025192 | 2499 | |
d0b03bd1 | 2500 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2501 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2502 | { |
5d0ae2db | 2503 | ack_APIC_irq(); |
d0b03bd1 HW |
2504 | } |
2505 | ||
90297c5f | 2506 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2507 | { |
5d0ae2db | 2508 | ack_APIC_irq(); |
90297c5f | 2509 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2510 | } |
2511 | #endif /* CONFIG_INTR_REMAP */ | |
2512 | ||
f5b9ed7a | 2513 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2514 | .name = "IO-APIC", |
2515 | .irq_startup = startup_ioapic_irq, | |
2516 | .irq_mask = mask_ioapic_irq, | |
2517 | .irq_unmask = unmask_ioapic_irq, | |
2518 | .irq_ack = ack_apic_edge, | |
2519 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2520 | #ifdef CONFIG_SMP |
f7e909ea | 2521 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2522 | #endif |
f7e909ea | 2523 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2524 | }; |
2525 | ||
54168ed7 | 2526 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
f19f5ecc TG |
2527 | .name = "IR-IO-APIC", |
2528 | .irq_startup = startup_ioapic_irq, | |
2529 | .irq_mask = mask_ioapic_irq, | |
2530 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2531 | #ifdef CONFIG_INTR_REMAP |
f19f5ecc TG |
2532 | .irq_ack = ir_ack_apic_edge, |
2533 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2534 | #ifdef CONFIG_SMP |
f19f5ecc | 2535 | .irq_set_affinity = ir_ioapic_set_affinity, |
a1e38ca5 | 2536 | #endif |
54168ed7 | 2537 | #endif |
f19f5ecc | 2538 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2539 | }; |
1da177e4 LT |
2540 | |
2541 | static inline void init_IO_APIC_traps(void) | |
2542 | { | |
da51a821 | 2543 | struct irq_cfg *cfg; |
ad9f4334 | 2544 | unsigned int irq; |
1da177e4 LT |
2545 | |
2546 | /* | |
2547 | * NOTE! The local APIC isn't very good at handling | |
2548 | * multiple interrupts at the same interrupt level. | |
2549 | * As the interrupt level is determined by taking the | |
2550 | * vector number and shifting that right by 4, we | |
2551 | * want to spread these out a bit so that they don't | |
2552 | * all fall in the same interrupt level. | |
2553 | * | |
2554 | * Also, we've got to be careful not to trash gate | |
2555 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2556 | */ | |
ad9f4334 | 2557 | for_each_active_irq(irq) { |
2c778651 | 2558 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2559 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2560 | /* |
2561 | * Hmm.. We don't have an entry for this, | |
2562 | * so default to an old-fashioned 8259 | |
2563 | * interrupt if we can.. | |
2564 | */ | |
b81bb373 JP |
2565 | if (irq < legacy_pic->nr_legacy_irqs) |
2566 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2567 | else |
1da177e4 | 2568 | /* Strange. Oh, well.. */ |
2c778651 | 2569 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2570 | } |
2571 | } | |
2572 | } | |
2573 | ||
f5b9ed7a IM |
2574 | /* |
2575 | * The local APIC irq-chip implementation: | |
2576 | */ | |
1da177e4 | 2577 | |
90297c5f | 2578 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2579 | { |
2580 | unsigned long v; | |
2581 | ||
2582 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2583 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2584 | } |
2585 | ||
90297c5f | 2586 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2587 | { |
f5b9ed7a | 2588 | unsigned long v; |
1da177e4 | 2589 | |
f5b9ed7a | 2590 | v = apic_read(APIC_LVT0); |
593f4a78 | 2591 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2592 | } |
1da177e4 | 2593 | |
90297c5f | 2594 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2595 | { |
2596 | ack_APIC_irq(); | |
2597 | } | |
2598 | ||
f5b9ed7a | 2599 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2600 | .name = "local-APIC", |
90297c5f TG |
2601 | .irq_mask = mask_lapic_irq, |
2602 | .irq_unmask = unmask_lapic_irq, | |
2603 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2604 | }; |
2605 | ||
60c69948 | 2606 | static void lapic_register_intr(int irq) |
c88ac1df | 2607 | { |
60c69948 | 2608 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2609 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2610 | "edge"); |
c88ac1df MR |
2611 | } |
2612 | ||
1da177e4 LT |
2613 | /* |
2614 | * This looks a bit hackish but it's about the only one way of sending | |
2615 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2616 | * not support the ExtINT mode, unfortunately. We need to send these | |
2617 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2618 | * 8259A interrupt line asserted until INTA. --macro | |
2619 | */ | |
28acf285 | 2620 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2621 | { |
fcfd636a | 2622 | int apic, pin, i; |
1da177e4 LT |
2623 | struct IO_APIC_route_entry entry0, entry1; |
2624 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2625 | |
fcfd636a | 2626 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2627 | if (pin == -1) { |
2628 | WARN_ON_ONCE(1); | |
2629 | return; | |
2630 | } | |
fcfd636a | 2631 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2632 | if (apic == -1) { |
2633 | WARN_ON_ONCE(1); | |
1da177e4 | 2634 | return; |
956fb531 | 2635 | } |
1da177e4 | 2636 | |
cf4c6a2f | 2637 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2638 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2639 | |
2640 | memset(&entry1, 0, sizeof(entry1)); | |
2641 | ||
2642 | entry1.dest_mode = 0; /* physical delivery */ | |
2643 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2644 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2645 | entry1.delivery_mode = dest_ExtINT; |
2646 | entry1.polarity = entry0.polarity; | |
2647 | entry1.trigger = 0; | |
2648 | entry1.vector = 0; | |
2649 | ||
cf4c6a2f | 2650 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2651 | |
2652 | save_control = CMOS_READ(RTC_CONTROL); | |
2653 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2654 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2655 | RTC_FREQ_SELECT); | |
2656 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2657 | ||
2658 | i = 100; | |
2659 | while (i-- > 0) { | |
2660 | mdelay(10); | |
2661 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2662 | i -= 10; | |
2663 | } | |
2664 | ||
2665 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2666 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2667 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2668 | |
cf4c6a2f | 2669 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2670 | } |
2671 | ||
efa2559f | 2672 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2673 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2674 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2675 | { |
2676 | disable_timer_pin_1 = 1; | |
2677 | return 0; | |
2678 | } | |
54168ed7 | 2679 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2680 | |
2681 | int timer_through_8259 __initdata; | |
2682 | ||
1da177e4 LT |
2683 | /* |
2684 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2685 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2686 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2687 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2688 | * |
2689 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2690 | */ |
8542b200 | 2691 | static inline void __init check_timer(void) |
1da177e4 | 2692 | { |
2c778651 | 2693 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2694 | int node = cpu_to_node(0); |
fcfd636a | 2695 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2696 | unsigned long flags; |
047c8fdb | 2697 | int no_pin1 = 0; |
4aae0702 IM |
2698 | |
2699 | local_irq_save(flags); | |
d4d25dec | 2700 | |
1da177e4 LT |
2701 | /* |
2702 | * get/set the timer IRQ vector: | |
2703 | */ | |
4305df94 | 2704 | legacy_pic->mask(0); |
fe402e1f | 2705 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2706 | |
2707 | /* | |
d11d5794 MR |
2708 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2709 | * wire has to be disabled in the local APIC. Also | |
2710 | * timer interrupts need to be acknowledged manually in | |
2711 | * the 8259A for the i82489DX when using the NMI | |
2712 | * watchdog as that APIC treats NMIs as level-triggered. | |
2713 | * The AEOI mode will finish them in the 8259A | |
2714 | * automatically. | |
1da177e4 | 2715 | */ |
593f4a78 | 2716 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2717 | legacy_pic->init(1); |
1da177e4 | 2718 | |
fcfd636a EB |
2719 | pin1 = find_isa_irq_pin(0, mp_INT); |
2720 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2721 | pin2 = ioapic_i8259.pin; | |
2722 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2723 | |
49a66a0b MR |
2724 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2725 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2726 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2727 | |
691874fa MR |
2728 | /* |
2729 | * Some BIOS writers are clueless and report the ExtINTA | |
2730 | * I/O APIC input from the cascaded 8259A as the timer | |
2731 | * interrupt input. So just in case, if only one pin | |
2732 | * was found above, try it both directly and through the | |
2733 | * 8259A. | |
2734 | */ | |
2735 | if (pin1 == -1) { | |
54168ed7 IM |
2736 | if (intr_remapping_enabled) |
2737 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2738 | pin1 = pin2; |
2739 | apic1 = apic2; | |
2740 | no_pin1 = 1; | |
2741 | } else if (pin2 == -1) { | |
2742 | pin2 = pin1; | |
2743 | apic2 = apic1; | |
2744 | } | |
2745 | ||
1da177e4 LT |
2746 | if (pin1 != -1) { |
2747 | /* | |
2748 | * Ok, does IRQ0 through the IOAPIC work? | |
2749 | */ | |
691874fa | 2750 | if (no_pin1) { |
85ac16d0 | 2751 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2752 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2753 | } else { |
60c69948 | 2754 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2755 | * leave it unmasked. |
2756 | * so only need to unmask if it is level-trigger | |
2757 | * do we really have level trigger timer? | |
2758 | */ | |
2759 | int idx; | |
2760 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2761 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2762 | unmask_ioapic(cfg); |
691874fa | 2763 | } |
1da177e4 | 2764 | if (timer_irq_works()) { |
66759a01 CE |
2765 | if (disable_timer_pin_1 > 0) |
2766 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2767 | goto out; |
1da177e4 | 2768 | } |
54168ed7 IM |
2769 | if (intr_remapping_enabled) |
2770 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2771 | local_irq_disable(); |
fcfd636a | 2772 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2773 | if (!no_pin1) |
49a66a0b MR |
2774 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2775 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2776 | |
49a66a0b MR |
2777 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2778 | "(IRQ0) through the 8259A ...\n"); | |
2779 | apic_printk(APIC_QUIET, KERN_INFO | |
2780 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2781 | /* |
2782 | * legacy devices should be connected to IO APIC #0 | |
2783 | */ | |
85ac16d0 | 2784 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2785 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2786 | legacy_pic->unmask(0); |
1da177e4 | 2787 | if (timer_irq_works()) { |
49a66a0b | 2788 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2789 | timer_through_8259 = 1; |
4aae0702 | 2790 | goto out; |
1da177e4 LT |
2791 | } |
2792 | /* | |
2793 | * Cleanup, just in case ... | |
2794 | */ | |
f72dccac | 2795 | local_irq_disable(); |
4305df94 | 2796 | legacy_pic->mask(0); |
fcfd636a | 2797 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2798 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2799 | } |
1da177e4 | 2800 | |
49a66a0b MR |
2801 | apic_printk(APIC_QUIET, KERN_INFO |
2802 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2803 | |
60c69948 | 2804 | lapic_register_intr(0); |
497c9a19 | 2805 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2806 | legacy_pic->unmask(0); |
1da177e4 LT |
2807 | |
2808 | if (timer_irq_works()) { | |
49a66a0b | 2809 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2810 | goto out; |
1da177e4 | 2811 | } |
f72dccac | 2812 | local_irq_disable(); |
4305df94 | 2813 | legacy_pic->mask(0); |
497c9a19 | 2814 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2815 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2816 | |
49a66a0b MR |
2817 | apic_printk(APIC_QUIET, KERN_INFO |
2818 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2819 | |
b81bb373 JP |
2820 | legacy_pic->init(0); |
2821 | legacy_pic->make_irq(0); | |
593f4a78 | 2822 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2823 | |
2824 | unlock_ExtINT_logic(); | |
2825 | ||
2826 | if (timer_irq_works()) { | |
49a66a0b | 2827 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2828 | goto out; |
1da177e4 | 2829 | } |
f72dccac | 2830 | local_irq_disable(); |
49a66a0b | 2831 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2832 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2833 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2834 | out: |
2835 | local_irq_restore(flags); | |
1da177e4 LT |
2836 | } |
2837 | ||
2838 | /* | |
af174783 MR |
2839 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2840 | * to devices. However there may be an I/O APIC pin available for | |
2841 | * this interrupt regardless. The pin may be left unconnected, but | |
2842 | * typically it will be reused as an ExtINT cascade interrupt for | |
2843 | * the master 8259A. In the MPS case such a pin will normally be | |
2844 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2845 | * there is no provision for ExtINT interrupts, and in the absence | |
2846 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2847 | * interrupt, that is edge-triggered and unmasked by default. We | |
2848 | * used to do this, but it caused problems on some systems because | |
2849 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2850 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2851 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2852 | * the I/O APIC in all cases now. No actual device should request | |
2853 | * it anyway. --macro | |
1da177e4 | 2854 | */ |
bc07844a | 2855 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2856 | |
2857 | void __init setup_IO_APIC(void) | |
2858 | { | |
54168ed7 | 2859 | |
54168ed7 IM |
2860 | /* |
2861 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2862 | */ | |
b81bb373 | 2863 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2864 | |
54168ed7 | 2865 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2866 | /* |
54168ed7 IM |
2867 | * Set up IO-APIC IRQ routing. |
2868 | */ | |
de934103 TG |
2869 | x86_init.mpparse.setup_ioapic_ids(); |
2870 | ||
1da177e4 LT |
2871 | sync_Arb_IDs(); |
2872 | setup_IO_APIC_irqs(); | |
2873 | init_IO_APIC_traps(); | |
b81bb373 | 2874 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2875 | check_timer(); |
1da177e4 LT |
2876 | } |
2877 | ||
2878 | /* | |
0d2eb44f | 2879 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2880 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2881 | */ |
36062448 | 2882 | |
1da177e4 LT |
2883 | static int __init io_apic_bug_finalize(void) |
2884 | { | |
d6c88a50 TG |
2885 | if (sis_apic_bug == -1) |
2886 | sis_apic_bug = 0; | |
2887 | return 0; | |
1da177e4 LT |
2888 | } |
2889 | ||
2890 | late_initcall(io_apic_bug_finalize); | |
2891 | ||
15bac20b | 2892 | static void resume_ioapic_id(int ioapic_id) |
1da177e4 | 2893 | { |
1da177e4 LT |
2894 | unsigned long flags; |
2895 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2896 | |
1da177e4 | 2897 | |
dade7716 | 2898 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f3c6ea1b RW |
2899 | reg_00.raw = io_apic_read(ioapic_id, 0); |
2900 | if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) { | |
2901 | reg_00.bits.ID = mp_ioapics[ioapic_id].apicid; | |
2902 | io_apic_write(ioapic_id, 0, reg_00.raw); | |
1da177e4 | 2903 | } |
dade7716 | 2904 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2905 | } |
1da177e4 | 2906 | |
f3c6ea1b RW |
2907 | static void ioapic_resume(void) |
2908 | { | |
2909 | int ioapic_id; | |
2910 | ||
2911 | for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--) | |
15bac20b SS |
2912 | resume_ioapic_id(ioapic_id); |
2913 | ||
2914 | restore_ioapic_entries(); | |
1da177e4 LT |
2915 | } |
2916 | ||
f3c6ea1b | 2917 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2918 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2919 | .resume = ioapic_resume, |
2920 | }; | |
2921 | ||
f3c6ea1b | 2922 | static int __init ioapic_init_ops(void) |
1da177e4 | 2923 | { |
f3c6ea1b RW |
2924 | register_syscore_ops(&ioapic_syscore_ops); |
2925 | ||
1da177e4 LT |
2926 | return 0; |
2927 | } | |
2928 | ||
f3c6ea1b | 2929 | device_initcall(ioapic_init_ops); |
1da177e4 | 2930 | |
3fc471ed | 2931 | /* |
95d77884 | 2932 | * Dynamic irq allocate and deallocation |
3fc471ed | 2933 | */ |
fbc6bff0 | 2934 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 2935 | { |
fbc6bff0 | 2936 | struct irq_cfg *cfg; |
3fc471ed | 2937 | unsigned long flags; |
fbc6bff0 TG |
2938 | unsigned int ret = 0; |
2939 | int irq; | |
d047f53a | 2940 | |
fbc6bff0 TG |
2941 | if (from < nr_irqs_gsi) |
2942 | from = nr_irqs_gsi; | |
d047f53a | 2943 | |
fbc6bff0 TG |
2944 | irq = alloc_irq_from(from, node); |
2945 | if (irq < 0) | |
2946 | return 0; | |
2947 | cfg = alloc_irq_cfg(irq, node); | |
2948 | if (!cfg) { | |
2949 | free_irq_at(irq, NULL); | |
2950 | return 0; | |
ace80ab7 | 2951 | } |
3fc471ed | 2952 | |
fbc6bff0 TG |
2953 | raw_spin_lock_irqsave(&vector_lock, flags); |
2954 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
2955 | ret = irq; | |
2956 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2957 | |
fbc6bff0 | 2958 | if (ret) { |
2c778651 | 2959 | irq_set_chip_data(irq, cfg); |
fbc6bff0 TG |
2960 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
2961 | } else { | |
2962 | free_irq_at(irq, cfg); | |
2963 | } | |
2964 | return ret; | |
3fc471ed EB |
2965 | } |
2966 | ||
199751d7 YL |
2967 | int create_irq(void) |
2968 | { | |
f6e9456c | 2969 | int node = cpu_to_node(0); |
be5d5350 | 2970 | unsigned int irq_want; |
54168ed7 IM |
2971 | int irq; |
2972 | ||
be5d5350 | 2973 | irq_want = nr_irqs_gsi; |
d047f53a | 2974 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
2975 | |
2976 | if (irq == 0) | |
2977 | irq = -1; | |
2978 | ||
2979 | return irq; | |
199751d7 YL |
2980 | } |
2981 | ||
3fc471ed EB |
2982 | void destroy_irq(unsigned int irq) |
2983 | { | |
2c778651 | 2984 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 2985 | unsigned long flags; |
3fc471ed | 2986 | |
fbc6bff0 | 2987 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 2988 | |
7b79462a | 2989 | if (irq_remapped(cfg)) |
9717967c | 2990 | free_irte(irq); |
dade7716 | 2991 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 2992 | __clear_irq_vector(irq, cfg); |
dade7716 | 2993 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 2994 | free_irq_at(irq, cfg); |
3fc471ed | 2995 | } |
3fc471ed | 2996 | |
2d3fcc1c | 2997 | /* |
27b46d76 | 2998 | * MSI message composition |
2d3fcc1c EB |
2999 | */ |
3000 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3001 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3002 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3003 | { |
497c9a19 YL |
3004 | struct irq_cfg *cfg; |
3005 | int err; | |
2d3fcc1c EB |
3006 | unsigned dest; |
3007 | ||
f1182638 JB |
3008 | if (disable_apic) |
3009 | return -ENXIO; | |
3010 | ||
3145e941 | 3011 | cfg = irq_cfg(irq); |
fe402e1f | 3012 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3013 | if (err) |
3014 | return err; | |
2d3fcc1c | 3015 | |
debccb3e | 3016 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3017 | |
1a0e62a4 | 3018 | if (irq_remapped(cfg)) { |
54168ed7 IM |
3019 | struct irte irte; |
3020 | int ir_index; | |
3021 | u16 sub_handle; | |
3022 | ||
3023 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3024 | BUG_ON(ir_index == -1); | |
3025 | ||
62a92f4c | 3026 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3027 | |
f007e99c | 3028 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3029 | if (pdev) |
3030 | set_msi_sid(&irte, pdev); | |
3031 | else | |
3032 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3033 | |
54168ed7 IM |
3034 | modify_irte(irq, &irte); |
3035 | ||
3036 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3037 | msg->data = sub_handle; | |
3038 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3039 | MSI_ADDR_IR_SHV | | |
3040 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3041 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3042 | } else { |
9d783ba0 SS |
3043 | if (x2apic_enabled()) |
3044 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3045 | MSI_ADDR_EXT_DEST_ID(dest); | |
3046 | else | |
3047 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3048 | ||
54168ed7 IM |
3049 | msg->address_lo = |
3050 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3051 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3052 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3053 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3054 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3055 | MSI_ADDR_REDIRECTION_CPU: |
3056 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3057 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3058 | |
54168ed7 IM |
3059 | msg->data = |
3060 | MSI_DATA_TRIGGER_EDGE | | |
3061 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3062 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3063 | MSI_DATA_DELIVERY_FIXED: |
3064 | MSI_DATA_DELIVERY_LOWPRI) | | |
3065 | MSI_DATA_VECTOR(cfg->vector); | |
3066 | } | |
497c9a19 | 3067 | return err; |
2d3fcc1c EB |
3068 | } |
3069 | ||
3b7d1921 | 3070 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3071 | static int |
3072 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3073 | { |
5346b2a7 | 3074 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3075 | struct msi_msg msg; |
3076 | unsigned int dest; | |
3b7d1921 | 3077 | |
5346b2a7 | 3078 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3079 | return -1; |
2d3fcc1c | 3080 | |
5346b2a7 | 3081 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3082 | |
3083 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3084 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3085 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3086 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3087 | ||
5346b2a7 | 3088 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3089 | |
3090 | return 0; | |
2d3fcc1c | 3091 | } |
54168ed7 IM |
3092 | #ifdef CONFIG_INTR_REMAP |
3093 | /* | |
3094 | * Migrate the MSI irq to another cpumask. This migration is | |
3095 | * done in the process context using interrupt-remapping hardware. | |
3096 | */ | |
d5dedd45 | 3097 | static int |
b5d1c465 TG |
3098 | ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3099 | bool force) | |
54168ed7 | 3100 | { |
b5d1c465 TG |
3101 | struct irq_cfg *cfg = data->chip_data; |
3102 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3103 | struct irte irte; |
54168ed7 IM |
3104 | |
3105 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3106 | return -1; |
54168ed7 | 3107 | |
b5d1c465 | 3108 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3109 | return -1; |
54168ed7 | 3110 | |
54168ed7 IM |
3111 | irte.vector = cfg->vector; |
3112 | irte.dest_id = IRTE_DEST(dest); | |
3113 | ||
3114 | /* | |
3115 | * atomically update the IRTE with the new destination and vector. | |
3116 | */ | |
3117 | modify_irte(irq, &irte); | |
3118 | ||
3119 | /* | |
3120 | * After this point, all the interrupts will start arriving | |
3121 | * at the new destination. So, time to cleanup the previous | |
3122 | * vector allocation. | |
3123 | */ | |
22f65d31 MT |
3124 | if (cfg->move_in_progress) |
3125 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3126 | |
3127 | return 0; | |
54168ed7 | 3128 | } |
3145e941 | 3129 | |
54168ed7 | 3130 | #endif |
3b7d1921 | 3131 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3132 | |
3b7d1921 EB |
3133 | /* |
3134 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3135 | * which implement the MSI or MSI-X Capability Structure. | |
3136 | */ | |
3137 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3138 | .name = "PCI-MSI", |
3139 | .irq_unmask = unmask_msi_irq, | |
3140 | .irq_mask = mask_msi_irq, | |
3141 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3142 | #ifdef CONFIG_SMP |
5346b2a7 | 3143 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3144 | #endif |
5346b2a7 | 3145 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3146 | }; |
3147 | ||
54168ed7 | 3148 | static struct irq_chip msi_ir_chip = { |
b5d1c465 TG |
3149 | .name = "IR-PCI-MSI", |
3150 | .irq_unmask = unmask_msi_irq, | |
3151 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3152 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3153 | .irq_ack = ir_ack_apic_edge, |
54168ed7 | 3154 | #ifdef CONFIG_SMP |
b5d1c465 | 3155 | .irq_set_affinity = ir_msi_set_affinity, |
a1e38ca5 | 3156 | #endif |
54168ed7 | 3157 | #endif |
b5d1c465 | 3158 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3159 | }; |
3160 | ||
3161 | /* | |
3162 | * Map the PCI dev to the corresponding remapping hardware unit | |
3163 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3164 | * in it. | |
3165 | */ | |
3166 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3167 | { | |
3168 | struct intel_iommu *iommu; | |
3169 | int index; | |
3170 | ||
3171 | iommu = map_dev_to_ir(dev); | |
3172 | if (!iommu) { | |
3173 | printk(KERN_ERR | |
3174 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3175 | return -ENOENT; | |
3176 | } | |
3177 | ||
3178 | index = alloc_irte(iommu, irq, nvec); | |
3179 | if (index < 0) { | |
3180 | printk(KERN_ERR | |
3181 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3182 | pci_name(dev)); |
54168ed7 IM |
3183 | return -ENOSPC; |
3184 | } | |
3185 | return index; | |
3186 | } | |
1d025192 | 3187 | |
3145e941 | 3188 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3189 | { |
c60eaf25 | 3190 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3191 | struct msi_msg msg; |
60c69948 | 3192 | int ret; |
1d025192 | 3193 | |
c8bc6f3c | 3194 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3195 | if (ret < 0) |
3196 | return ret; | |
3197 | ||
2c778651 | 3198 | irq_set_msi_desc(irq, msidesc); |
1d025192 YL |
3199 | write_msi_msg(irq, &msg); |
3200 | ||
2c778651 | 3201 | if (irq_remapped(irq_get_chip_data(irq))) { |
60c69948 | 3202 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
3203 | chip = &msi_ir_chip; |
3204 | } | |
3205 | ||
3206 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3207 | |
c81bba49 YL |
3208 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3209 | ||
1d025192 YL |
3210 | return 0; |
3211 | } | |
3212 | ||
294ee6f8 | 3213 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3214 | { |
60c69948 TG |
3215 | int node, ret, sub_handle, index = 0; |
3216 | unsigned int irq, irq_want; | |
0b8f1efa | 3217 | struct msi_desc *msidesc; |
1cc18521 | 3218 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3219 | |
1c8d7b0a MW |
3220 | /* x86 doesn't support multiple MSI yet */ |
3221 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3222 | return 1; | |
3223 | ||
d047f53a | 3224 | node = dev_to_node(&dev->dev); |
be5d5350 | 3225 | irq_want = nr_irqs_gsi; |
54168ed7 | 3226 | sub_handle = 0; |
0b8f1efa | 3227 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3228 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3229 | if (irq == 0) |
3230 | return -1; | |
f1ee5548 | 3231 | irq_want = irq + 1; |
54168ed7 IM |
3232 | if (!intr_remapping_enabled) |
3233 | goto no_ir; | |
3234 | ||
3235 | if (!sub_handle) { | |
3236 | /* | |
3237 | * allocate the consecutive block of IRTE's | |
3238 | * for 'nvec' | |
3239 | */ | |
3240 | index = msi_alloc_irte(dev, irq, nvec); | |
3241 | if (index < 0) { | |
3242 | ret = index; | |
3243 | goto error; | |
3244 | } | |
3245 | } else { | |
3246 | iommu = map_dev_to_ir(dev); | |
3247 | if (!iommu) { | |
3248 | ret = -ENOENT; | |
3249 | goto error; | |
3250 | } | |
3251 | /* | |
3252 | * setup the mapping between the irq and the IRTE | |
3253 | * base index, the sub_handle pointing to the | |
3254 | * appropriate interrupt remap table entry. | |
3255 | */ | |
3256 | set_irte_irq(irq, iommu, index, sub_handle); | |
3257 | } | |
3258 | no_ir: | |
0b8f1efa | 3259 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3260 | if (ret < 0) |
3261 | goto error; | |
3262 | sub_handle++; | |
3263 | } | |
3264 | return 0; | |
047c8fdb YL |
3265 | |
3266 | error: | |
54168ed7 IM |
3267 | destroy_irq(irq); |
3268 | return ret; | |
047c8fdb YL |
3269 | } |
3270 | ||
294ee6f8 | 3271 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3272 | { |
f7feaca7 | 3273 | destroy_irq(irq); |
3b7d1921 EB |
3274 | } |
3275 | ||
9d783ba0 | 3276 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3277 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3278 | static int |
3279 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3280 | bool force) | |
54168ed7 | 3281 | { |
fe52b2d2 TG |
3282 | struct irq_cfg *cfg = data->chip_data; |
3283 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3284 | struct msi_msg msg; |
54168ed7 | 3285 | |
fe52b2d2 | 3286 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3287 | return -1; |
54168ed7 | 3288 | |
54168ed7 IM |
3289 | dmar_msi_read(irq, &msg); |
3290 | ||
3291 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3292 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3293 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3294 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3295 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3296 | |
3297 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3298 | |
3299 | return 0; | |
54168ed7 | 3300 | } |
3145e941 | 3301 | |
54168ed7 IM |
3302 | #endif /* CONFIG_SMP */ |
3303 | ||
8f7007aa | 3304 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3305 | .name = "DMAR_MSI", |
3306 | .irq_unmask = dmar_msi_unmask, | |
3307 | .irq_mask = dmar_msi_mask, | |
3308 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3309 | #ifdef CONFIG_SMP |
fe52b2d2 | 3310 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3311 | #endif |
fe52b2d2 | 3312 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3313 | }; |
3314 | ||
3315 | int arch_setup_dmar_msi(unsigned int irq) | |
3316 | { | |
3317 | int ret; | |
3318 | struct msi_msg msg; | |
2d3fcc1c | 3319 | |
c8bc6f3c | 3320 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3321 | if (ret < 0) |
3322 | return ret; | |
3323 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3324 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3325 | "edge"); | |
54168ed7 IM |
3326 | return 0; |
3327 | } | |
3328 | #endif | |
3329 | ||
58ac1e76 | 3330 | #ifdef CONFIG_HPET_TIMER |
3331 | ||
3332 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3333 | static int hpet_msi_set_affinity(struct irq_data *data, |
3334 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3335 | { |
d0fbca8f | 3336 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3337 | struct msi_msg msg; |
3338 | unsigned int dest; | |
58ac1e76 | 3339 | |
0e09ddf2 | 3340 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3341 | return -1; |
58ac1e76 | 3342 | |
d0fbca8f | 3343 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3344 | |
3345 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3346 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3347 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3348 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3349 | ||
d0fbca8f | 3350 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3351 | |
3352 | return 0; | |
58ac1e76 | 3353 | } |
3145e941 | 3354 | |
58ac1e76 | 3355 | #endif /* CONFIG_SMP */ |
3356 | ||
c8bc6f3c | 3357 | static struct irq_chip ir_hpet_msi_type = { |
b5d1c465 TG |
3358 | .name = "IR-HPET_MSI", |
3359 | .irq_unmask = hpet_msi_unmask, | |
3360 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3361 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3362 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c | 3363 | #ifdef CONFIG_SMP |
b5d1c465 | 3364 | .irq_set_affinity = ir_msi_set_affinity, |
c8bc6f3c SS |
3365 | #endif |
3366 | #endif | |
b5d1c465 | 3367 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3368 | }; |
3369 | ||
1cc18521 | 3370 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3371 | .name = "HPET_MSI", |
d0fbca8f TG |
3372 | .irq_unmask = hpet_msi_unmask, |
3373 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3374 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3375 | #ifdef CONFIG_SMP |
d0fbca8f | 3376 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3377 | #endif |
90297c5f | 3378 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3379 | }; |
3380 | ||
c8bc6f3c | 3381 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3382 | { |
c60eaf25 | 3383 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3384 | struct msi_msg msg; |
d0fbca8f | 3385 | int ret; |
58ac1e76 | 3386 | |
c8bc6f3c SS |
3387 | if (intr_remapping_enabled) { |
3388 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3389 | int index; | |
3390 | ||
3391 | if (!iommu) | |
3392 | return -1; | |
3393 | ||
3394 | index = alloc_irte(iommu, irq, 1); | |
3395 | if (index < 0) | |
3396 | return -1; | |
3397 | } | |
3398 | ||
3399 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3400 | if (ret < 0) |
3401 | return ret; | |
3402 | ||
2c778651 | 3403 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3404 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2c778651 | 3405 | if (irq_remapped(irq_get_chip_data(irq))) |
c60eaf25 | 3406 | chip = &ir_hpet_msi_type; |
c81bba49 | 3407 | |
c60eaf25 | 3408 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3409 | return 0; |
3410 | } | |
3411 | #endif | |
3412 | ||
54168ed7 | 3413 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3414 | /* |
3415 | * Hypertransport interrupt support | |
3416 | */ | |
3417 | #ifdef CONFIG_HT_IRQ | |
3418 | ||
3419 | #ifdef CONFIG_SMP | |
3420 | ||
497c9a19 | 3421 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3422 | { |
ec68307c EB |
3423 | struct ht_irq_msg msg; |
3424 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3425 | |
497c9a19 | 3426 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3427 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3428 | |
497c9a19 | 3429 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3430 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3431 | |
ec68307c | 3432 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3433 | } |
3434 | ||
be5b7bf7 TG |
3435 | static int |
3436 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3437 | { |
be5b7bf7 | 3438 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3439 | unsigned int dest; |
8b955b0d | 3440 | |
be5b7bf7 | 3441 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3442 | return -1; |
8b955b0d | 3443 | |
be5b7bf7 | 3444 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3445 | return 0; |
8b955b0d | 3446 | } |
3145e941 | 3447 | |
8b955b0d EB |
3448 | #endif |
3449 | ||
c37e108d | 3450 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3451 | .name = "PCI-HT", |
3452 | .irq_mask = mask_ht_irq, | |
3453 | .irq_unmask = unmask_ht_irq, | |
3454 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3455 | #ifdef CONFIG_SMP |
be5b7bf7 | 3456 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3457 | #endif |
be5b7bf7 | 3458 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3459 | }; |
3460 | ||
3461 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3462 | { | |
497c9a19 YL |
3463 | struct irq_cfg *cfg; |
3464 | int err; | |
8b955b0d | 3465 | |
f1182638 JB |
3466 | if (disable_apic) |
3467 | return -ENXIO; | |
3468 | ||
3145e941 | 3469 | cfg = irq_cfg(irq); |
fe402e1f | 3470 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3471 | if (!err) { |
ec68307c | 3472 | struct ht_irq_msg msg; |
8b955b0d | 3473 | unsigned dest; |
8b955b0d | 3474 | |
debccb3e IM |
3475 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3476 | apic->target_cpus()); | |
8b955b0d | 3477 | |
ec68307c | 3478 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3479 | |
ec68307c EB |
3480 | msg.address_lo = |
3481 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3482 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3483 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3484 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3485 | HT_IRQ_LOW_DM_PHYSICAL : |
3486 | HT_IRQ_LOW_DM_LOGICAL) | | |
3487 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3488 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3489 | HT_IRQ_LOW_MT_FIXED : |
3490 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3491 | HT_IRQ_LOW_IRQ_MASKED; | |
3492 | ||
ec68307c | 3493 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3494 | |
2c778651 | 3495 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
a460e745 | 3496 | handle_edge_irq, "edge"); |
c81bba49 YL |
3497 | |
3498 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3499 | } |
497c9a19 | 3500 | return err; |
8b955b0d EB |
3501 | } |
3502 | #endif /* CONFIG_HT_IRQ */ | |
3503 | ||
20443598 | 3504 | static int |
ff973d04 TG |
3505 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3506 | { | |
3507 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3508 | int ret; | |
3509 | ||
3510 | if (!cfg) | |
3511 | return -EINVAL; | |
3512 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3513 | if (!ret) | |
3514 | setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, | |
3515 | attr->trigger, attr->polarity); | |
3516 | return ret; | |
3517 | } | |
3518 | ||
20443598 SAS |
3519 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3520 | struct io_apic_irq_attr *attr) | |
710dcda6 TG |
3521 | { |
3522 | unsigned int id = attr->ioapic, pin = attr->ioapic_pin; | |
3523 | int ret; | |
3524 | ||
3525 | /* Avoid redundant programming */ | |
3526 | if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) { | |
3527 | pr_debug("Pin %d-%d already programmed\n", | |
3528 | mp_ioapics[id].apicid, pin); | |
3529 | return 0; | |
3530 | } | |
3531 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3532 | if (!ret) | |
3533 | set_bit(pin, mp_ioapic_routing[id].pin_programmed); | |
3534 | return ret; | |
3535 | } | |
3536 | ||
41098ffe | 3537 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3538 | { |
3539 | union IO_APIC_reg_01 reg_01; | |
3540 | unsigned long flags; | |
3541 | ||
dade7716 | 3542 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3543 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3544 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3545 | |
4b6b19a1 EB |
3546 | /* The register returns the maximum index redir index |
3547 | * supported, which is one less than the total number of redir | |
3548 | * entries. | |
3549 | */ | |
3550 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3551 | } |
3552 | ||
23f9b267 | 3553 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3554 | { |
4afc51a8 | 3555 | int nr; |
be5d5350 | 3556 | |
a4384df3 | 3557 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3558 | if (nr > nr_irqs_gsi) |
be5d5350 | 3559 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3560 | |
3561 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3562 | } |
3563 | ||
7b586d71 JF |
3564 | int get_nr_irqs_gsi(void) |
3565 | { | |
3566 | return nr_irqs_gsi; | |
3567 | } | |
3568 | ||
4a046d17 YL |
3569 | #ifdef CONFIG_SPARSE_IRQ |
3570 | int __init arch_probe_nr_irqs(void) | |
3571 | { | |
3572 | int nr; | |
3573 | ||
f1ee5548 YL |
3574 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3575 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3576 | |
f1ee5548 YL |
3577 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3578 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3579 | /* | |
3580 | * for MSI and HT dyn irq | |
3581 | */ | |
3582 | nr += nr_irqs_gsi * 16; | |
3583 | #endif | |
3584 | if (nr < nr_irqs) | |
4a046d17 YL |
3585 | nr_irqs = nr; |
3586 | ||
b683de2b | 3587 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3588 | } |
3589 | #endif | |
3590 | ||
710dcda6 TG |
3591 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3592 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3593 | { |
5ef21837 YL |
3594 | int node; |
3595 | ||
3596 | if (!IO_APIC_IRQ(irq)) { | |
3597 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3598 | irq_attr->ioapic); |
5ef21837 YL |
3599 | return -EINVAL; |
3600 | } | |
3601 | ||
e0799c04 | 3602 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3603 | |
710dcda6 | 3604 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3605 | } |
3606 | ||
54168ed7 | 3607 | #ifdef CONFIG_X86_32 |
41098ffe | 3608 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3609 | { |
3610 | union IO_APIC_reg_00 reg_00; | |
3611 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3612 | physid_mask_t tmp; | |
3613 | unsigned long flags; | |
3614 | int i = 0; | |
3615 | ||
3616 | /* | |
36062448 PC |
3617 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3618 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3619 | * supports up to 16 on one shared APIC bus. |
36062448 | 3620 | * |
1da177e4 LT |
3621 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3622 | * advantage of new APIC bus architecture. | |
3623 | */ | |
3624 | ||
3625 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3626 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3627 | |
dade7716 | 3628 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3629 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3630 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3631 | |
3632 | if (apic_id >= get_physical_broadcast()) { | |
3633 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3634 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3635 | apic_id = reg_00.bits.ID; | |
3636 | } | |
3637 | ||
3638 | /* | |
36062448 | 3639 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3640 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3641 | */ | |
7abc0753 | 3642 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3643 | |
3644 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3645 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3646 | break; |
3647 | } | |
3648 | ||
3649 | if (i == get_physical_broadcast()) | |
3650 | panic("Max apic_id exceeded!\n"); | |
3651 | ||
3652 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3653 | "trying %d\n", ioapic, apic_id, i); | |
3654 | ||
3655 | apic_id = i; | |
36062448 | 3656 | } |
1da177e4 | 3657 | |
7abc0753 | 3658 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3659 | physids_or(apic_id_map, apic_id_map, tmp); |
3660 | ||
3661 | if (reg_00.bits.ID != apic_id) { | |
3662 | reg_00.bits.ID = apic_id; | |
3663 | ||
dade7716 | 3664 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3665 | io_apic_write(ioapic, 0, reg_00.raw); |
3666 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3667 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3668 | |
3669 | /* Sanity check */ | |
6070f9ec AD |
3670 | if (reg_00.bits.ID != apic_id) { |
3671 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3672 | return -1; | |
3673 | } | |
1da177e4 LT |
3674 | } |
3675 | ||
3676 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3677 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3678 | ||
3679 | return apic_id; | |
3680 | } | |
41098ffe TG |
3681 | |
3682 | static u8 __init io_apic_unique_id(u8 id) | |
3683 | { | |
3684 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3685 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3686 | return io_apic_get_unique_id(nr_ioapics, id); | |
3687 | else | |
3688 | return id; | |
3689 | } | |
3690 | #else | |
3691 | static u8 __init io_apic_unique_id(u8 id) | |
3692 | { | |
3693 | int i; | |
3694 | DECLARE_BITMAP(used, 256); | |
3695 | ||
3696 | bitmap_zero(used, 256); | |
3697 | for (i = 0; i < nr_ioapics; i++) { | |
3698 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3699 | __set_bit(ia->apicid, used); | |
3700 | } | |
3701 | if (!test_bit(id, used)) | |
3702 | return id; | |
3703 | return find_first_zero_bit(used, 256); | |
3704 | } | |
58f892e0 | 3705 | #endif |
1da177e4 | 3706 | |
41098ffe | 3707 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3708 | { |
3709 | union IO_APIC_reg_01 reg_01; | |
3710 | unsigned long flags; | |
3711 | ||
dade7716 | 3712 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3713 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3714 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3715 | |
3716 | return reg_01.bits.version; | |
3717 | } | |
3718 | ||
9a0a91bb | 3719 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3720 | { |
9a0a91bb | 3721 | int ioapic, pin, idx; |
61fd47e0 SL |
3722 | |
3723 | if (skip_ioapic_setup) | |
3724 | return -1; | |
3725 | ||
9a0a91bb EB |
3726 | ioapic = mp_find_ioapic(gsi); |
3727 | if (ioapic < 0) | |
61fd47e0 SL |
3728 | return -1; |
3729 | ||
9a0a91bb EB |
3730 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3731 | if (pin < 0) | |
3732 | return -1; | |
3733 | ||
3734 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3735 | if (idx < 0) | |
61fd47e0 SL |
3736 | return -1; |
3737 | ||
9a0a91bb EB |
3738 | *trigger = irq_trigger(idx); |
3739 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3740 | return 0; |
3741 | } | |
3742 | ||
497c9a19 YL |
3743 | /* |
3744 | * This function currently is only a helper for the i386 smp boot process where | |
3745 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3746 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3747 | */ |
3748 | #ifdef CONFIG_SMP | |
3749 | void __init setup_ioapic_dest(void) | |
3750 | { | |
fad53995 | 3751 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3752 | const struct cpumask *mask; |
5451ddc5 | 3753 | struct irq_data *idata; |
497c9a19 YL |
3754 | |
3755 | if (skip_ioapic_setup == 1) | |
3756 | return; | |
3757 | ||
fad53995 | 3758 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b69c6c3b | 3759 | for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { |
b9c61b70 YL |
3760 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3761 | if (irq_entry == -1) | |
3762 | continue; | |
3763 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3764 | |
fad53995 EB |
3765 | if ((ioapic > 0) && (irq > 16)) |
3766 | continue; | |
3767 | ||
5451ddc5 | 3768 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3769 | |
b9c61b70 YL |
3770 | /* |
3771 | * Honour affinities which have been set in early boot | |
3772 | */ | |
5451ddc5 TG |
3773 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3774 | mask = idata->affinity; | |
b9c61b70 YL |
3775 | else |
3776 | mask = apic->target_cpus(); | |
497c9a19 | 3777 | |
b9c61b70 | 3778 | if (intr_remapping_enabled) |
5451ddc5 | 3779 | ir_ioapic_set_affinity(idata, mask, false); |
b9c61b70 | 3780 | else |
5451ddc5 | 3781 | ioapic_set_affinity(idata, mask, false); |
497c9a19 | 3782 | } |
b9c61b70 | 3783 | |
497c9a19 YL |
3784 | } |
3785 | #endif | |
3786 | ||
54168ed7 IM |
3787 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3788 | ||
3789 | static struct resource *ioapic_resources; | |
3790 | ||
ffc43836 | 3791 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3792 | { |
3793 | unsigned long n; | |
3794 | struct resource *res; | |
3795 | char *mem; | |
3796 | int i; | |
3797 | ||
3798 | if (nr_ioapics <= 0) | |
3799 | return NULL; | |
3800 | ||
3801 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3802 | n *= nr_ioapics; | |
3803 | ||
3804 | mem = alloc_bootmem(n); | |
3805 | res = (void *)mem; | |
3806 | ||
ffc43836 | 3807 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3808 | |
ffc43836 CG |
3809 | for (i = 0; i < nr_ioapics; i++) { |
3810 | res[i].name = mem; | |
3811 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3812 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3813 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3814 | } |
3815 | ||
3816 | ioapic_resources = res; | |
3817 | ||
3818 | return res; | |
3819 | } | |
54168ed7 | 3820 | |
23f9b267 | 3821 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3822 | { |
3823 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3824 | struct resource *ioapic_res; |
d6c88a50 | 3825 | int i; |
f3294a33 | 3826 | |
ffc43836 | 3827 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3828 | for (i = 0; i < nr_ioapics; i++) { |
3829 | if (smp_found_config) { | |
b5ba7e6d | 3830 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 3831 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3832 | if (!ioapic_phys) { |
3833 | printk(KERN_ERR | |
3834 | "WARNING: bogus zero IO-APIC " | |
3835 | "address found in MPTABLE, " | |
3836 | "disabling IO/APIC support!\n"); | |
3837 | smp_found_config = 0; | |
3838 | skip_ioapic_setup = 1; | |
3839 | goto fake_ioapic_page; | |
3840 | } | |
54168ed7 | 3841 | #endif |
f3294a33 | 3842 | } else { |
54168ed7 | 3843 | #ifdef CONFIG_X86_32 |
f3294a33 | 3844 | fake_ioapic_page: |
54168ed7 | 3845 | #endif |
e79c65a9 | 3846 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3847 | ioapic_phys = __pa(ioapic_phys); |
3848 | } | |
3849 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3850 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3851 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3852 | ioapic_phys); | |
f3294a33 | 3853 | idx++; |
54168ed7 | 3854 | |
ffc43836 | 3855 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3856 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3857 | ioapic_res++; |
f3294a33 | 3858 | } |
23f9b267 TG |
3859 | |
3860 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3861 | } |
3862 | ||
857fdc53 | 3863 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3864 | { |
3865 | int i; | |
3866 | struct resource *r = ioapic_resources; | |
3867 | ||
3868 | if (!r) { | |
857fdc53 | 3869 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3870 | printk(KERN_ERR |
3871 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3872 | return; |
54168ed7 IM |
3873 | } |
3874 | ||
3875 | for (i = 0; i < nr_ioapics; i++) { | |
3876 | insert_resource(&iomem_resource, r); | |
3877 | r++; | |
3878 | } | |
54168ed7 | 3879 | } |
2a4ab640 | 3880 | |
eddb0c55 | 3881 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3882 | { |
3883 | int i = 0; | |
3884 | ||
678301ec PB |
3885 | if (nr_ioapics == 0) |
3886 | return -1; | |
3887 | ||
2a4ab640 FT |
3888 | /* Find the IOAPIC that manages this GSI. */ |
3889 | for (i = 0; i < nr_ioapics; i++) { | |
3890 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
3891 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
3892 | return i; | |
3893 | } | |
54168ed7 | 3894 | |
2a4ab640 FT |
3895 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3896 | return -1; | |
3897 | } | |
3898 | ||
eddb0c55 | 3899 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
3900 | { |
3901 | if (WARN_ON(ioapic == -1)) | |
3902 | return -1; | |
3903 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
3904 | return -1; | |
3905 | ||
3906 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
3907 | } | |
3908 | ||
41098ffe | 3909 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3910 | { |
3911 | if (nr_ioapics >= MAX_IO_APICS) { | |
45e8234c | 3912 | printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded " |
2a4ab640 FT |
3913 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); |
3914 | return 1; | |
3915 | } | |
3916 | if (!address) { | |
3917 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
3918 | " found in table, skipping!\n"); | |
3919 | return 1; | |
3920 | } | |
54168ed7 IM |
3921 | return 0; |
3922 | } | |
3923 | ||
2a4ab640 FT |
3924 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3925 | { | |
3926 | int idx = 0; | |
7716a5c4 | 3927 | int entries; |
2a4ab640 FT |
3928 | |
3929 | if (bad_ioapic(address)) | |
3930 | return; | |
3931 | ||
3932 | idx = nr_ioapics; | |
3933 | ||
3934 | mp_ioapics[idx].type = MP_IOAPIC; | |
3935 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
3936 | mp_ioapics[idx].apicaddr = address; | |
3937 | ||
3938 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
3939 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
3940 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
3941 | ||
3942 | /* | |
3943 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3944 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3945 | */ | |
7716a5c4 | 3946 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 3947 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
3948 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
3949 | ||
3950 | /* | |
3951 | * The number of IO-APIC IRQ registers (== #pins): | |
3952 | */ | |
b69c6c3b | 3953 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3954 | |
a4384df3 EB |
3955 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
3956 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
3957 | |
3958 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
3959 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
3960 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
3961 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
3962 | ||
3963 | nr_ioapics++; | |
3964 | } | |
05ddafb1 JP |
3965 | |
3966 | /* Enable IOAPIC early just for system timer */ | |
3967 | void __init pre_init_apic_IRQ0(void) | |
3968 | { | |
f880ec78 | 3969 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
3970 | |
3971 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
3972 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
3973 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
3974 | &phys_cpu_present_map); | |
05ddafb1 | 3975 | #endif |
05ddafb1 JP |
3976 | setup_local_APIC(); |
3977 | ||
f880ec78 | 3978 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
3979 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
3980 | "edge"); | |
05ddafb1 | 3981 | } |