Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 TG |
76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
77 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 78 | |
b69c6c3b SS |
79 | static struct ioapic { |
80 | /* | |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_registers; | |
57a6f740 SS |
84 | /* |
85 | * Saved state during suspend/resume, or while enabling intr-remap. | |
86 | */ | |
87 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
88 | /* I/O APIC config */ |
89 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
90 | /* IO APIC gsi routing info */ |
91 | struct mp_ioapic_gsi gsi_config; | |
8f18c971 | 92 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
b69c6c3b | 93 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 94 | |
6f50d45f | 95 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 96 | |
6f50d45f | 97 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 98 | { |
6f50d45f | 99 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
100 | } |
101 | ||
6f50d45f | 102 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 103 | { |
6f50d45f | 104 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
105 | } |
106 | ||
6f50d45f | 107 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 108 | { |
6f50d45f | 109 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 110 | } |
9f640ccb | 111 | |
c040aaeb | 112 | int nr_ioapics; |
2a4ab640 | 113 | |
a4384df3 EB |
114 | /* The one past the highest gsi number used */ |
115 | u32 gsi_top; | |
5777372a | 116 | |
584f734d | 117 | /* MP IRQ source entries */ |
c2c21745 | 118 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
119 | |
120 | /* # of MP IRQ source entries */ | |
121 | int mp_irq_entries; | |
122 | ||
bc07844a TG |
123 | /* GSI interrupts */ |
124 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
125 | ||
8732fc4b AS |
126 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
127 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
128 | #endif | |
129 | ||
130 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
131 | ||
efa2559f YL |
132 | int skip_ioapic_setup; |
133 | ||
7167d08e HK |
134 | /** |
135 | * disable_ioapic_support() - disables ioapic support at runtime | |
136 | */ | |
137 | void disable_ioapic_support(void) | |
65a4e574 IM |
138 | { |
139 | #ifdef CONFIG_PCI | |
140 | noioapicquirk = 1; | |
141 | noioapicreroute = -1; | |
142 | #endif | |
143 | skip_ioapic_setup = 1; | |
144 | } | |
145 | ||
54168ed7 | 146 | static int __init parse_noapic(char *str) |
efa2559f YL |
147 | { |
148 | /* disable IO-APIC */ | |
7167d08e | 149 | disable_ioapic_support(); |
efa2559f YL |
150 | return 0; |
151 | } | |
152 | early_param("noapic", parse_noapic); | |
66759a01 | 153 | |
20443598 SAS |
154 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
155 | struct io_apic_irq_attr *attr); | |
710dcda6 | 156 | |
2d8009ba FT |
157 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
158 | void mp_save_irq(struct mpc_intsrc *m) | |
159 | { | |
160 | int i; | |
161 | ||
162 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
163 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
164 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
165 | m->srcbusirq, m->dstapic, m->dstirq); | |
166 | ||
167 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 168 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
169 | return; |
170 | } | |
171 | ||
0e3fa13f | 172 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
173 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
174 | panic("Max # of irq sources exceeded!!\n"); | |
175 | } | |
176 | ||
0b8f1efa YL |
177 | struct irq_pin_list { |
178 | int apic, pin; | |
179 | struct irq_pin_list *next; | |
180 | }; | |
181 | ||
7e495529 | 182 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 183 | { |
2ee39065 | 184 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
185 | } |
186 | ||
2d8009ba | 187 | |
a1420f39 | 188 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
97943390 | 189 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
a1420f39 | 190 | |
13a0c3c2 | 191 | int __init arch_early_irq_init(void) |
8f09cd20 | 192 | { |
0b8f1efa | 193 | struct irq_cfg *cfg; |
60c69948 | 194 | int count, node, i; |
d6c88a50 | 195 | |
bb84ac2d | 196 | if (!legacy_pic->nr_legacy_irqs) |
1f91233c | 197 | io_apic_irqs = ~0UL; |
1f91233c | 198 | |
4c79185c | 199 | for (i = 0; i < nr_ioapics; i++) { |
57a6f740 | 200 | ioapics[i].saved_registers = |
4c79185c | 201 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 202 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 203 | if (!ioapics[i].saved_registers) |
4c79185c SS |
204 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
205 | } | |
206 | ||
0b8f1efa YL |
207 | cfg = irq_cfgx; |
208 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 209 | node = cpu_to_node(0); |
8f09cd20 | 210 | |
fbc6bff0 TG |
211 | /* Make sure the legacy interrupts are marked in the bitmap */ |
212 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
213 | ||
0b8f1efa | 214 | for (i = 0; i < count; i++) { |
2c778651 | 215 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
216 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
217 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
218 | /* |
219 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
220 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
221 | */ | |
54b56170 | 222 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
223 | cfg[i].vector = IRQ0_VECTOR + i; |
224 | cpumask_set_cpu(0, cfg[i].domain); | |
225 | } | |
0b8f1efa | 226 | } |
13a0c3c2 YL |
227 | |
228 | return 0; | |
0b8f1efa | 229 | } |
8f09cd20 | 230 | |
48b26501 | 231 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 232 | { |
2c778651 | 233 | return irq_get_chip_data(irq); |
8f09cd20 | 234 | } |
d6c88a50 | 235 | |
f981a3dc | 236 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 237 | { |
0b8f1efa | 238 | struct irq_cfg *cfg; |
0f978f45 | 239 | |
2ee39065 | 240 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
241 | if (!cfg) |
242 | return NULL; | |
2ee39065 | 243 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 244 | goto out_cfg; |
2ee39065 | 245 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 246 | goto out_domain; |
0b8f1efa | 247 | return cfg; |
6e2fff50 TG |
248 | out_domain: |
249 | free_cpumask_var(cfg->domain); | |
250 | out_cfg: | |
251 | kfree(cfg); | |
252 | return NULL; | |
8f09cd20 YL |
253 | } |
254 | ||
f981a3dc | 255 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 256 | { |
fbc6bff0 TG |
257 | if (!cfg) |
258 | return; | |
2c778651 | 259 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
260 | free_cpumask_var(cfg->domain); |
261 | free_cpumask_var(cfg->old_domain); | |
262 | kfree(cfg); | |
263 | } | |
264 | ||
08c33db6 TG |
265 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
266 | { | |
267 | int res = irq_alloc_desc_at(at, node); | |
268 | struct irq_cfg *cfg; | |
269 | ||
270 | if (res < 0) { | |
271 | if (res != -EEXIST) | |
272 | return NULL; | |
2c778651 | 273 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
274 | if (cfg) |
275 | return cfg; | |
276 | } | |
277 | ||
f981a3dc | 278 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 279 | if (cfg) |
2c778651 | 280 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
281 | else |
282 | irq_free_desc(at); | |
283 | return cfg; | |
284 | } | |
285 | ||
286 | static int alloc_irq_from(unsigned int from, int node) | |
287 | { | |
288 | return irq_alloc_desc_from(from, node); | |
289 | } | |
290 | ||
291 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
292 | { | |
f981a3dc | 293 | free_irq_cfg(at, cfg); |
08c33db6 TG |
294 | irq_free_desc(at); |
295 | } | |
296 | ||
130fe05d LT |
297 | struct io_apic { |
298 | unsigned int index; | |
299 | unsigned int unused[3]; | |
300 | unsigned int data; | |
0280f7c4 SS |
301 | unsigned int unused2[11]; |
302 | unsigned int eoi; | |
130fe05d LT |
303 | }; |
304 | ||
305 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
306 | { | |
307 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 308 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
309 | } |
310 | ||
0280f7c4 SS |
311 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
312 | { | |
313 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
314 | writel(vector, &io_apic->eoi); | |
315 | } | |
316 | ||
130fe05d LT |
317 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
318 | { | |
319 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
320 | writel(reg, &io_apic->index); | |
321 | return readl(&io_apic->data); | |
322 | } | |
323 | ||
324 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
325 | { | |
326 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
327 | writel(reg, &io_apic->index); | |
328 | writel(value, &io_apic->data); | |
329 | } | |
330 | ||
331 | /* | |
332 | * Re-write a value: to be used for read-modify-write | |
333 | * cycles where the read already set up the index register. | |
334 | * | |
335 | * Older SiS APIC requires we rewrite the index register | |
336 | */ | |
337 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
338 | { | |
54168ed7 | 339 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
340 | |
341 | if (sis_apic_bug) | |
342 | writel(reg, &io_apic->index); | |
130fe05d LT |
343 | writel(value, &io_apic->data); |
344 | } | |
345 | ||
3145e941 | 346 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
347 | { |
348 | struct irq_pin_list *entry; | |
349 | unsigned long flags; | |
047c8fdb | 350 | |
dade7716 | 351 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 352 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
353 | unsigned int reg; |
354 | int pin; | |
355 | ||
047c8fdb YL |
356 | pin = entry->pin; |
357 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
358 | /* Is the remote IRR bit set? */ | |
359 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 360 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
361 | return true; |
362 | } | |
047c8fdb | 363 | } |
dade7716 | 364 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
365 | |
366 | return false; | |
367 | } | |
047c8fdb | 368 | |
cf4c6a2f AK |
369 | union entry_union { |
370 | struct { u32 w1, w2; }; | |
371 | struct IO_APIC_route_entry entry; | |
372 | }; | |
373 | ||
e57253a8 SS |
374 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
375 | { | |
376 | union entry_union eu; | |
377 | ||
378 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
379 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
380 | return eu.entry; | |
381 | } | |
382 | ||
cf4c6a2f AK |
383 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
384 | { | |
385 | union entry_union eu; | |
386 | unsigned long flags; | |
dade7716 | 387 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 388 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 389 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
390 | return eu.entry; |
391 | } | |
392 | ||
f9dadfa7 LT |
393 | /* |
394 | * When we write a new IO APIC routing entry, we need to write the high | |
395 | * word first! If the mask bit in the low word is clear, we will enable | |
396 | * the interrupt, and we need to make sure the entry is fully populated | |
397 | * before that happens. | |
398 | */ | |
d15512f4 AK |
399 | static void |
400 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 401 | { |
50a8d4d2 F |
402 | union entry_union eu = {{0, 0}}; |
403 | ||
cf4c6a2f | 404 | eu.entry = e; |
f9dadfa7 LT |
405 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
406 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
407 | } |
408 | ||
1a8ce7ff | 409 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
410 | { |
411 | unsigned long flags; | |
dade7716 | 412 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 413 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 414 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
415 | } |
416 | ||
417 | /* | |
418 | * When we mask an IO APIC routing entry, we need to write the low | |
419 | * word first, in order to set the mask bit before we change the | |
420 | * high bits! | |
421 | */ | |
422 | static void ioapic_mask_entry(int apic, int pin) | |
423 | { | |
424 | unsigned long flags; | |
425 | union entry_union eu = { .entry.mask = 1 }; | |
426 | ||
dade7716 | 427 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
428 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
429 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 430 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
431 | } |
432 | ||
1da177e4 LT |
433 | /* |
434 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
435 | * shared ISA-space IRQs, so we have to support them. We are super | |
436 | * fast in the common case, and fast for shared ISA-space IRQs. | |
437 | */ | |
f3d1915a | 438 | static int |
7e495529 | 439 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 440 | { |
2977fb3f | 441 | struct irq_pin_list **last, *entry; |
0f978f45 | 442 | |
2977fb3f CG |
443 | /* don't allow duplicates */ |
444 | last = &cfg->irq_2_pin; | |
445 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 446 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 447 | return 0; |
2977fb3f | 448 | last = &entry->next; |
1da177e4 | 449 | } |
0f978f45 | 450 | |
7e495529 | 451 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 452 | if (!entry) { |
f3d1915a CG |
453 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
454 | node, apic, pin); | |
455 | return -ENOMEM; | |
a7428cd2 | 456 | } |
1da177e4 LT |
457 | entry->apic = apic; |
458 | entry->pin = pin; | |
875e68ec | 459 | |
2977fb3f | 460 | *last = entry; |
f3d1915a CG |
461 | return 0; |
462 | } | |
463 | ||
464 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
465 | { | |
7e495529 | 466 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 467 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
468 | } |
469 | ||
470 | /* | |
471 | * Reroute an IRQ to a different pin. | |
472 | */ | |
85ac16d0 | 473 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
474 | int oldapic, int oldpin, |
475 | int newapic, int newpin) | |
1da177e4 | 476 | { |
535b6429 | 477 | struct irq_pin_list *entry; |
1da177e4 | 478 | |
2977fb3f | 479 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
480 | if (entry->apic == oldapic && entry->pin == oldpin) { |
481 | entry->apic = newapic; | |
482 | entry->pin = newpin; | |
0f978f45 | 483 | /* every one is different, right? */ |
4eea6fff | 484 | return; |
0f978f45 | 485 | } |
1da177e4 | 486 | } |
0f978f45 | 487 | |
4eea6fff JF |
488 | /* old apic/pin didn't exist, so just add new ones */ |
489 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
490 | } |
491 | ||
c29d9db3 SS |
492 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
493 | int mask_and, int mask_or, | |
494 | void (*final)(struct irq_pin_list *entry)) | |
495 | { | |
496 | unsigned int reg, pin; | |
497 | ||
498 | pin = entry->pin; | |
499 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
500 | reg &= mask_and; | |
501 | reg |= mask_or; | |
502 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
503 | if (final) | |
504 | final(entry); | |
505 | } | |
506 | ||
2f210deb JF |
507 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
508 | int mask_and, int mask_or, | |
509 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 510 | { |
87783be4 | 511 | struct irq_pin_list *entry; |
047c8fdb | 512 | |
c29d9db3 SS |
513 | for_each_irq_pin(entry, cfg->irq_2_pin) |
514 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
515 | } | |
516 | ||
7f3e632f | 517 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 518 | { |
87783be4 CG |
519 | /* |
520 | * Synchronize the IO-APIC and the CPU by doing | |
521 | * a dummy read from the IO-APIC | |
522 | */ | |
523 | struct io_apic __iomem *io_apic; | |
524 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 525 | readl(&io_apic->data); |
1da177e4 LT |
526 | } |
527 | ||
dd5f15e5 | 528 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 529 | { |
dd5f15e5 TG |
530 | unsigned long flags; |
531 | ||
532 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 533 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 534 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 535 | } |
1da177e4 | 536 | |
90297c5f | 537 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 538 | { |
90297c5f | 539 | mask_ioapic(data->chip_data); |
dd5f15e5 | 540 | } |
3145e941 | 541 | |
dd5f15e5 TG |
542 | static void __unmask_ioapic(struct irq_cfg *cfg) |
543 | { | |
544 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
545 | } |
546 | ||
dd5f15e5 | 547 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
548 | { |
549 | unsigned long flags; | |
550 | ||
dade7716 | 551 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 552 | __unmask_ioapic(cfg); |
dade7716 | 553 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
554 | } |
555 | ||
90297c5f | 556 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 557 | { |
90297c5f | 558 | unmask_ioapic(data->chip_data); |
3145e941 YL |
559 | } |
560 | ||
c0205701 SS |
561 | /* |
562 | * IO-APIC versions below 0x20 don't support EOI register. | |
563 | * For the record, here is the information about various versions: | |
564 | * 0Xh 82489DX | |
565 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
566 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
567 | * 30h-FFh Reserved | |
568 | * | |
569 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
570 | * version as 0x2. This is an error with documentation and these ICH chips | |
571 | * use io-apic's of version 0x20. | |
572 | * | |
573 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
574 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
575 | * mode to edge and then back to level, with RTE being masked during this. | |
576 | */ | |
577 | static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg) | |
578 | { | |
579 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
580 | /* | |
581 | * Intr-remapping uses pin number as the virtual vector | |
582 | * in the RTE. Actual vector is programmed in | |
583 | * intr-remapping table entry. Hence for the io-apic | |
584 | * EOI we use the pin number. | |
585 | */ | |
586 | if (cfg && irq_remapped(cfg)) | |
587 | io_apic_eoi(apic, pin); | |
588 | else | |
589 | io_apic_eoi(apic, vector); | |
590 | } else { | |
591 | struct IO_APIC_route_entry entry, entry1; | |
592 | ||
593 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
594 | ||
595 | /* | |
596 | * Mask the entry and change the trigger mode to edge. | |
597 | */ | |
598 | entry1.mask = 1; | |
599 | entry1.trigger = IOAPIC_EDGE; | |
600 | ||
601 | __ioapic_write_entry(apic, pin, entry1); | |
602 | ||
603 | /* | |
604 | * Restore the previous level triggered entry. | |
605 | */ | |
606 | __ioapic_write_entry(apic, pin, entry); | |
607 | } | |
608 | } | |
609 | ||
610 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) | |
611 | { | |
612 | struct irq_pin_list *entry; | |
613 | unsigned long flags; | |
614 | ||
615 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
616 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
617 | __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg); | |
618 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
619 | } | |
620 | ||
1da177e4 LT |
621 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
622 | { | |
623 | struct IO_APIC_route_entry entry; | |
36062448 | 624 | |
1da177e4 | 625 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 626 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
627 | if (entry.delivery_mode == dest_SMI) |
628 | return; | |
1e75b31d | 629 | |
1da177e4 | 630 | /* |
1e75b31d SS |
631 | * Make sure the entry is masked and re-read the contents to check |
632 | * if it is a level triggered pin and if the remote-IRR is set. | |
633 | */ | |
634 | if (!entry.mask) { | |
635 | entry.mask = 1; | |
636 | ioapic_write_entry(apic, pin, entry); | |
637 | entry = ioapic_read_entry(apic, pin); | |
638 | } | |
639 | ||
640 | if (entry.irr) { | |
c0205701 SS |
641 | unsigned long flags; |
642 | ||
1e75b31d SS |
643 | /* |
644 | * Make sure the trigger mode is set to level. Explicit EOI | |
645 | * doesn't clear the remote-IRR if the trigger mode is not | |
646 | * set to level. | |
647 | */ | |
648 | if (!entry.trigger) { | |
649 | entry.trigger = IOAPIC_LEVEL; | |
650 | ioapic_write_entry(apic, pin, entry); | |
651 | } | |
652 | ||
c0205701 SS |
653 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
654 | __eoi_ioapic_pin(apic, pin, entry.vector, NULL); | |
655 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1e75b31d SS |
656 | } |
657 | ||
658 | /* | |
659 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
660 | * bit. | |
1da177e4 | 661 | */ |
f9dadfa7 | 662 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
663 | entry = ioapic_read_entry(apic, pin); |
664 | if (entry.irr) | |
665 | printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n", | |
666 | mpc_ioapic_id(apic), pin); | |
1da177e4 LT |
667 | } |
668 | ||
54168ed7 | 669 | static void clear_IO_APIC (void) |
1da177e4 LT |
670 | { |
671 | int apic, pin; | |
672 | ||
673 | for (apic = 0; apic < nr_ioapics; apic++) | |
b69c6c3b | 674 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
1da177e4 LT |
675 | clear_IO_APIC_pin(apic, pin); |
676 | } | |
677 | ||
54168ed7 | 678 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
679 | /* |
680 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
681 | * specific CPU-side IRQs. | |
682 | */ | |
683 | ||
684 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
685 | static int pirq_entries[MAX_PIRQS] = { |
686 | [0 ... MAX_PIRQS - 1] = -1 | |
687 | }; | |
1da177e4 | 688 | |
1da177e4 LT |
689 | static int __init ioapic_pirq_setup(char *str) |
690 | { | |
691 | int i, max; | |
692 | int ints[MAX_PIRQS+1]; | |
693 | ||
694 | get_options(str, ARRAY_SIZE(ints), ints); | |
695 | ||
1da177e4 LT |
696 | apic_printk(APIC_VERBOSE, KERN_INFO |
697 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
698 | max = MAX_PIRQS; | |
699 | if (ints[0] < MAX_PIRQS) | |
700 | max = ints[0]; | |
701 | ||
702 | for (i = 0; i < max; i++) { | |
703 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
704 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
705 | /* | |
706 | * PIRQs are mapped upside down, usually. | |
707 | */ | |
708 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
709 | } | |
710 | return 1; | |
711 | } | |
712 | ||
713 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
714 | #endif /* CONFIG_X86_32 */ |
715 | ||
54168ed7 | 716 | /* |
05c3dc2c | 717 | * Saves all the IO-APIC RTE's |
54168ed7 | 718 | */ |
31dce14a | 719 | int save_ioapic_entries(void) |
54168ed7 | 720 | { |
54168ed7 | 721 | int apic, pin; |
31dce14a | 722 | int err = 0; |
54168ed7 IM |
723 | |
724 | for (apic = 0; apic < nr_ioapics; apic++) { | |
57a6f740 | 725 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
726 | err = -ENOMEM; |
727 | continue; | |
728 | } | |
54168ed7 | 729 | |
b69c6c3b | 730 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
57a6f740 | 731 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 732 | ioapic_read_entry(apic, pin); |
b24696bc | 733 | } |
5ffa4eb2 | 734 | |
31dce14a | 735 | return err; |
54168ed7 IM |
736 | } |
737 | ||
b24696bc FY |
738 | /* |
739 | * Mask all IO APIC entries. | |
740 | */ | |
31dce14a | 741 | void mask_ioapic_entries(void) |
05c3dc2c SS |
742 | { |
743 | int apic, pin; | |
744 | ||
745 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2f344d2e | 746 | if (!ioapics[apic].saved_registers) |
31dce14a | 747 | continue; |
b24696bc | 748 | |
b69c6c3b | 749 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
05c3dc2c SS |
750 | struct IO_APIC_route_entry entry; |
751 | ||
57a6f740 | 752 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
753 | if (!entry.mask) { |
754 | entry.mask = 1; | |
755 | ioapic_write_entry(apic, pin, entry); | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
760 | ||
b24696bc | 761 | /* |
57a6f740 | 762 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 763 | */ |
31dce14a | 764 | int restore_ioapic_entries(void) |
54168ed7 IM |
765 | { |
766 | int apic, pin; | |
767 | ||
5ffa4eb2 | 768 | for (apic = 0; apic < nr_ioapics; apic++) { |
2f344d2e | 769 | if (!ioapics[apic].saved_registers) |
31dce14a | 770 | continue; |
b24696bc | 771 | |
b69c6c3b | 772 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
54168ed7 | 773 | ioapic_write_entry(apic, pin, |
57a6f740 | 774 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 775 | } |
b24696bc | 776 | return 0; |
54168ed7 IM |
777 | } |
778 | ||
1da177e4 LT |
779 | /* |
780 | * Find the IRQ entry number of a certain pin. | |
781 | */ | |
6f50d45f | 782 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
783 | { |
784 | int i; | |
785 | ||
786 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 787 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 788 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
789 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
790 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
791 | return i; |
792 | ||
793 | return -1; | |
794 | } | |
795 | ||
796 | /* | |
797 | * Find the pin to which IRQ[irq] (ISA) is connected | |
798 | */ | |
fcfd636a | 799 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
800 | { |
801 | int i; | |
802 | ||
803 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 804 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 805 | |
d27e2b8e | 806 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
807 | (mp_irqs[i].irqtype == type) && |
808 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 809 | |
c2c21745 | 810 | return mp_irqs[i].dstirq; |
1da177e4 LT |
811 | } |
812 | return -1; | |
813 | } | |
814 | ||
fcfd636a EB |
815 | static int __init find_isa_irq_apic(int irq, int type) |
816 | { | |
817 | int i; | |
818 | ||
819 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 820 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 821 | |
73b2961b | 822 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
823 | (mp_irqs[i].irqtype == type) && |
824 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
825 | break; |
826 | } | |
6f50d45f | 827 | |
fcfd636a | 828 | if (i < mp_irq_entries) { |
6f50d45f YL |
829 | int ioapic_idx; |
830 | ||
831 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) | |
832 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) | |
833 | return ioapic_idx; | |
fcfd636a EB |
834 | } |
835 | ||
836 | return -1; | |
837 | } | |
838 | ||
c0a282c2 | 839 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
840 | /* |
841 | * EISA Edge/Level control register, ELCR | |
842 | */ | |
843 | static int EISA_ELCR(unsigned int irq) | |
844 | { | |
b81bb373 | 845 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
846 | unsigned int port = 0x4d0 + (irq >> 3); |
847 | return (inb(port) >> (irq & 7)) & 1; | |
848 | } | |
849 | apic_printk(APIC_VERBOSE, KERN_INFO | |
850 | "Broken MPtable reports ISA irq %d\n", irq); | |
851 | return 0; | |
852 | } | |
54168ed7 | 853 | |
c0a282c2 | 854 | #endif |
1da177e4 | 855 | |
6728801d AS |
856 | /* ISA interrupts are always polarity zero edge triggered, |
857 | * when listed as conforming in the MP table. */ | |
858 | ||
859 | #define default_ISA_trigger(idx) (0) | |
860 | #define default_ISA_polarity(idx) (0) | |
861 | ||
1da177e4 LT |
862 | /* EISA interrupts are always polarity zero and can be edge or level |
863 | * trigger depending on the ELCR value. If an interrupt is listed as | |
864 | * EISA conforming in the MP table, that means its trigger type must | |
865 | * be read in from the ELCR */ | |
866 | ||
c2c21745 | 867 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 868 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
869 | |
870 | /* PCI interrupts are always polarity one level triggered, | |
871 | * when listed as conforming in the MP table. */ | |
872 | ||
873 | #define default_PCI_trigger(idx) (1) | |
874 | #define default_PCI_polarity(idx) (1) | |
875 | ||
876 | /* MCA interrupts are always polarity zero level triggered, | |
877 | * when listed as conforming in the MP table. */ | |
878 | ||
879 | #define default_MCA_trigger(idx) (1) | |
6728801d | 880 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 881 | |
b77cf6a8 | 882 | static int irq_polarity(int idx) |
1da177e4 | 883 | { |
c2c21745 | 884 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
885 | int polarity; |
886 | ||
887 | /* | |
888 | * Determine IRQ line polarity (high active or low active): | |
889 | */ | |
c2c21745 | 890 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 891 | { |
54168ed7 IM |
892 | case 0: /* conforms, ie. bus-type dependent polarity */ |
893 | if (test_bit(bus, mp_bus_not_pci)) | |
894 | polarity = default_ISA_polarity(idx); | |
895 | else | |
896 | polarity = default_PCI_polarity(idx); | |
897 | break; | |
898 | case 1: /* high active */ | |
899 | { | |
900 | polarity = 0; | |
901 | break; | |
902 | } | |
903 | case 2: /* reserved */ | |
904 | { | |
905 | printk(KERN_WARNING "broken BIOS!!\n"); | |
906 | polarity = 1; | |
907 | break; | |
908 | } | |
909 | case 3: /* low active */ | |
910 | { | |
911 | polarity = 1; | |
912 | break; | |
913 | } | |
914 | default: /* invalid */ | |
915 | { | |
916 | printk(KERN_WARNING "broken BIOS!!\n"); | |
917 | polarity = 1; | |
918 | break; | |
919 | } | |
1da177e4 LT |
920 | } |
921 | return polarity; | |
922 | } | |
923 | ||
b77cf6a8 | 924 | static int irq_trigger(int idx) |
1da177e4 | 925 | { |
c2c21745 | 926 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
927 | int trigger; |
928 | ||
929 | /* | |
930 | * Determine IRQ trigger mode (edge or level sensitive): | |
931 | */ | |
c2c21745 | 932 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 933 | { |
54168ed7 IM |
934 | case 0: /* conforms, ie. bus-type dependent */ |
935 | if (test_bit(bus, mp_bus_not_pci)) | |
936 | trigger = default_ISA_trigger(idx); | |
937 | else | |
938 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 939 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
940 | switch (mp_bus_id_to_type[bus]) { |
941 | case MP_BUS_ISA: /* ISA pin */ | |
942 | { | |
943 | /* set before the switch */ | |
944 | break; | |
945 | } | |
946 | case MP_BUS_EISA: /* EISA pin */ | |
947 | { | |
948 | trigger = default_EISA_trigger(idx); | |
949 | break; | |
950 | } | |
951 | case MP_BUS_PCI: /* PCI pin */ | |
952 | { | |
953 | /* set before the switch */ | |
954 | break; | |
955 | } | |
956 | case MP_BUS_MCA: /* MCA pin */ | |
957 | { | |
958 | trigger = default_MCA_trigger(idx); | |
959 | break; | |
960 | } | |
961 | default: | |
962 | { | |
963 | printk(KERN_WARNING "broken BIOS!!\n"); | |
964 | trigger = 1; | |
965 | break; | |
966 | } | |
967 | } | |
968 | #endif | |
1da177e4 | 969 | break; |
54168ed7 | 970 | case 1: /* edge */ |
1da177e4 | 971 | { |
54168ed7 | 972 | trigger = 0; |
1da177e4 LT |
973 | break; |
974 | } | |
54168ed7 | 975 | case 2: /* reserved */ |
1da177e4 | 976 | { |
54168ed7 IM |
977 | printk(KERN_WARNING "broken BIOS!!\n"); |
978 | trigger = 1; | |
1da177e4 LT |
979 | break; |
980 | } | |
54168ed7 | 981 | case 3: /* level */ |
1da177e4 | 982 | { |
54168ed7 | 983 | trigger = 1; |
1da177e4 LT |
984 | break; |
985 | } | |
54168ed7 | 986 | default: /* invalid */ |
1da177e4 LT |
987 | { |
988 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 989 | trigger = 0; |
1da177e4 LT |
990 | break; |
991 | } | |
992 | } | |
993 | return trigger; | |
994 | } | |
995 | ||
1da177e4 LT |
996 | static int pin_2_irq(int idx, int apic, int pin) |
997 | { | |
d464207c | 998 | int irq; |
c2c21745 | 999 | int bus = mp_irqs[idx].srcbus; |
c040aaeb | 1000 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
1da177e4 LT |
1001 | |
1002 | /* | |
1003 | * Debugging check, we are in big trouble if this message pops up! | |
1004 | */ | |
c2c21745 | 1005 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1006 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1007 | ||
54168ed7 | 1008 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1009 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1010 | } else { |
c040aaeb | 1011 | u32 gsi = gsi_cfg->gsi_base + pin; |
988856ee EB |
1012 | |
1013 | if (gsi >= NR_IRQS_LEGACY) | |
1014 | irq = gsi; | |
1015 | else | |
a4384df3 | 1016 | irq = gsi_top + gsi; |
1da177e4 LT |
1017 | } |
1018 | ||
54168ed7 | 1019 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1020 | /* |
1021 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1022 | */ | |
1023 | if ((pin >= 16) && (pin <= 23)) { | |
1024 | if (pirq_entries[pin-16] != -1) { | |
1025 | if (!pirq_entries[pin-16]) { | |
1026 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1027 | "disabling PIRQ%d\n", pin-16); | |
1028 | } else { | |
1029 | irq = pirq_entries[pin-16]; | |
1030 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1031 | "using PIRQ%d -> IRQ %d\n", | |
1032 | pin-16, irq); | |
1033 | } | |
1034 | } | |
1035 | } | |
54168ed7 IM |
1036 | #endif |
1037 | ||
1da177e4 LT |
1038 | return irq; |
1039 | } | |
1040 | ||
e20c06fd YL |
1041 | /* |
1042 | * Find a specific PCI IRQ entry. | |
1043 | * Not an __init, possibly needed by modules | |
1044 | */ | |
1045 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1046 | struct io_apic_irq_attr *irq_attr) |
e20c06fd | 1047 | { |
6f50d45f | 1048 | int ioapic_idx, i, best_guess = -1; |
e20c06fd YL |
1049 | |
1050 | apic_printk(APIC_DEBUG, | |
1051 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1052 | bus, slot, pin); | |
1053 | if (test_bit(bus, mp_bus_not_pci)) { | |
1054 | apic_printk(APIC_VERBOSE, | |
1055 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1056 | return -1; | |
1057 | } | |
1058 | for (i = 0; i < mp_irq_entries; i++) { | |
1059 | int lbus = mp_irqs[i].srcbus; | |
1060 | ||
6f50d45f YL |
1061 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1062 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || | |
e20c06fd YL |
1063 | mp_irqs[i].dstapic == MP_APIC_ALL) |
1064 | break; | |
1065 | ||
1066 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1067 | !mp_irqs[i].irqtype && | |
1068 | (bus == lbus) && | |
1069 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
6f50d45f | 1070 | int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); |
e20c06fd | 1071 | |
6f50d45f | 1072 | if (!(ioapic_idx || IO_APIC_IRQ(irq))) |
e20c06fd YL |
1073 | continue; |
1074 | ||
1075 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
6f50d45f | 1076 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1077 | mp_irqs[i].dstirq, |
1078 | irq_trigger(i), | |
1079 | irq_polarity(i)); | |
e20c06fd YL |
1080 | return irq; |
1081 | } | |
1082 | /* | |
1083 | * Use the first all-but-pin matching entry as a | |
1084 | * best-guess fuzzy result for broken mptables. | |
1085 | */ | |
1086 | if (best_guess < 0) { | |
6f50d45f | 1087 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1088 | mp_irqs[i].dstirq, |
1089 | irq_trigger(i), | |
1090 | irq_polarity(i)); | |
e20c06fd YL |
1091 | best_guess = irq; |
1092 | } | |
1093 | } | |
1094 | } | |
1095 | return best_guess; | |
1096 | } | |
1097 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1098 | ||
497c9a19 YL |
1099 | void lock_vector_lock(void) |
1100 | { | |
1101 | /* Used to the online set of cpus does not change | |
1102 | * during assign_irq_vector. | |
1103 | */ | |
dade7716 | 1104 | raw_spin_lock(&vector_lock); |
497c9a19 | 1105 | } |
1da177e4 | 1106 | |
497c9a19 | 1107 | void unlock_vector_lock(void) |
1da177e4 | 1108 | { |
dade7716 | 1109 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1110 | } |
1da177e4 | 1111 | |
e7986739 MT |
1112 | static int |
1113 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1114 | { |
047c8fdb YL |
1115 | /* |
1116 | * NOTE! The local APIC isn't very good at handling | |
1117 | * multiple interrupts at the same interrupt level. | |
1118 | * As the interrupt level is determined by taking the | |
1119 | * vector number and shifting that right by 4, we | |
1120 | * want to spread these out a bit so that they don't | |
1121 | * all fall in the same interrupt level. | |
1122 | * | |
1123 | * Also, we've got to be careful not to trash gate | |
1124 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1125 | */ | |
6579b474 | 1126 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1127 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1128 | unsigned int old_vector; |
22f65d31 MT |
1129 | int cpu, err; |
1130 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1131 | |
23359a88 | 1132 | if (cfg->move_in_progress) |
54168ed7 | 1133 | return -EBUSY; |
0a1ad60d | 1134 | |
22f65d31 MT |
1135 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1136 | return -ENOMEM; | |
ace80ab7 | 1137 | |
54168ed7 IM |
1138 | old_vector = cfg->vector; |
1139 | if (old_vector) { | |
22f65d31 MT |
1140 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1141 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1142 | if (!cpumask_empty(tmp_mask)) { | |
1143 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1144 | return 0; |
22f65d31 | 1145 | } |
54168ed7 | 1146 | } |
497c9a19 | 1147 | |
e7986739 | 1148 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1149 | err = -ENOSPC; |
1150 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1151 | int new_cpu; |
1152 | int vector, offset; | |
497c9a19 | 1153 | |
e2d40b18 | 1154 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1155 | |
54168ed7 IM |
1156 | vector = current_vector; |
1157 | offset = current_offset; | |
497c9a19 | 1158 | next: |
54168ed7 IM |
1159 | vector += 8; |
1160 | if (vector >= first_system_vector) { | |
e7986739 | 1161 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1162 | offset = (offset + 1) % 8; |
6579b474 | 1163 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1164 | } |
1165 | if (unlikely(current_vector == vector)) | |
1166 | continue; | |
b77b881f YL |
1167 | |
1168 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1169 | goto next; |
b77b881f | 1170 | |
22f65d31 | 1171 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1172 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1173 | goto next; | |
1174 | /* Found one! */ | |
1175 | current_vector = vector; | |
1176 | current_offset = offset; | |
1177 | if (old_vector) { | |
1178 | cfg->move_in_progress = 1; | |
22f65d31 | 1179 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1180 | } |
22f65d31 | 1181 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1182 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1183 | cfg->vector = vector; | |
22f65d31 MT |
1184 | cpumask_copy(cfg->domain, tmp_mask); |
1185 | err = 0; | |
1186 | break; | |
54168ed7 | 1187 | } |
22f65d31 MT |
1188 | free_cpumask_var(tmp_mask); |
1189 | return err; | |
497c9a19 YL |
1190 | } |
1191 | ||
9338ad6f | 1192 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1193 | { |
1194 | int err; | |
ace80ab7 | 1195 | unsigned long flags; |
ace80ab7 | 1196 | |
dade7716 | 1197 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1198 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1199 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1200 | return err; |
1201 | } | |
1202 | ||
3145e941 | 1203 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1204 | { |
497c9a19 YL |
1205 | int cpu, vector; |
1206 | ||
497c9a19 YL |
1207 | BUG_ON(!cfg->vector); |
1208 | ||
1209 | vector = cfg->vector; | |
22f65d31 | 1210 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1211 | per_cpu(vector_irq, cpu)[vector] = -1; |
1212 | ||
1213 | cfg->vector = 0; | |
22f65d31 | 1214 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1215 | |
1216 | if (likely(!cfg->move_in_progress)) | |
1217 | return; | |
22f65d31 | 1218 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1219 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1220 | vector++) { | |
1221 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1222 | continue; | |
1223 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1224 | break; | |
1225 | } | |
1226 | } | |
1227 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1228 | } |
1229 | ||
1230 | void __setup_vector_irq(int cpu) | |
1231 | { | |
1232 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1233 | int irq, vector; |
1234 | struct irq_cfg *cfg; | |
1235 | ||
9d133e5d SS |
1236 | /* |
1237 | * vector_lock will make sure that we don't run into irq vector | |
1238 | * assignments that might be happening on another cpu in parallel, | |
1239 | * while we setup our initial vector to irq mappings. | |
1240 | */ | |
dade7716 | 1241 | raw_spin_lock(&vector_lock); |
497c9a19 | 1242 | /* Mark the inuse vectors */ |
ad9f4334 | 1243 | for_each_active_irq(irq) { |
2c778651 | 1244 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1245 | if (!cfg) |
1246 | continue; | |
36e9e1ea SS |
1247 | /* |
1248 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1249 | * will be part of the irq_cfg's domain. | |
1250 | */ | |
1251 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1252 | cpumask_set_cpu(cpu, cfg->domain); | |
1253 | ||
22f65d31 | 1254 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1255 | continue; |
1256 | vector = cfg->vector; | |
497c9a19 YL |
1257 | per_cpu(vector_irq, cpu)[vector] = irq; |
1258 | } | |
1259 | /* Mark the free vectors */ | |
1260 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1261 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1262 | if (irq < 0) | |
1263 | continue; | |
1264 | ||
1265 | cfg = irq_cfg(irq); | |
22f65d31 | 1266 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1267 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1268 | } |
dade7716 | 1269 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1270 | } |
3fde6900 | 1271 | |
f5b9ed7a | 1272 | static struct irq_chip ioapic_chip; |
1da177e4 | 1273 | |
047c8fdb | 1274 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1275 | static inline int IO_APIC_irq_trigger(int irq) |
1276 | { | |
d6c88a50 | 1277 | int apic, idx, pin; |
1d025192 | 1278 | |
d6c88a50 | 1279 | for (apic = 0; apic < nr_ioapics; apic++) { |
b69c6c3b | 1280 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
d6c88a50 TG |
1281 | idx = find_irq_entry(apic, pin, mp_INT); |
1282 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1283 | return irq_trigger(idx); | |
1284 | } | |
1285 | } | |
1286 | /* | |
54168ed7 IM |
1287 | * nonexistent IRQs are edge default |
1288 | */ | |
d6c88a50 | 1289 | return 0; |
1d025192 | 1290 | } |
047c8fdb YL |
1291 | #else |
1292 | static inline int IO_APIC_irq_trigger(int irq) | |
1293 | { | |
54168ed7 | 1294 | return 1; |
047c8fdb YL |
1295 | } |
1296 | #endif | |
1d025192 | 1297 | |
1a0e62a4 TG |
1298 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1299 | unsigned long trigger) | |
1da177e4 | 1300 | { |
c60eaf25 TG |
1301 | struct irq_chip *chip = &ioapic_chip; |
1302 | irq_flow_handler_t hdl; | |
1303 | bool fasteoi; | |
199751d7 | 1304 | |
6ebcc00e | 1305 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1306 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1307 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1308 | fasteoi = true; |
1309 | } else { | |
60c69948 | 1310 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1311 | fasteoi = false; |
1312 | } | |
047c8fdb | 1313 | |
1a0e62a4 | 1314 | if (irq_remapped(cfg)) { |
60c69948 | 1315 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c39d77ff | 1316 | irq_remap_modify_chip_defaults(chip); |
c60eaf25 | 1317 | fasteoi = trigger != 0; |
54168ed7 | 1318 | } |
29b61be6 | 1319 | |
c60eaf25 TG |
1320 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1321 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1322 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1323 | } |
1324 | ||
c5b4712c YL |
1325 | |
1326 | static int setup_ir_ioapic_entry(int irq, | |
1327 | struct IR_IO_APIC_route_entry *entry, | |
1328 | unsigned int destination, int vector, | |
1329 | struct io_apic_irq_attr *attr) | |
1da177e4 | 1330 | { |
c5b4712c YL |
1331 | int index; |
1332 | struct irte irte; | |
6f50d45f YL |
1333 | int ioapic_id = mpc_ioapic_id(attr->ioapic); |
1334 | struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id); | |
497c9a19 | 1335 | |
c5b4712c | 1336 | if (!iommu) { |
6f50d45f | 1337 | pr_warn("No mapping iommu for ioapic %d\n", ioapic_id); |
c5b4712c YL |
1338 | return -ENODEV; |
1339 | } | |
54168ed7 | 1340 | |
c5b4712c YL |
1341 | index = alloc_irte(iommu, irq, 1); |
1342 | if (index < 0) { | |
6f50d45f | 1343 | pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id); |
c5b4712c YL |
1344 | return -ENOMEM; |
1345 | } | |
54168ed7 | 1346 | |
c5b4712c | 1347 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1348 | |
c5b4712c | 1349 | /* Set source-id of interrupt request */ |
6f50d45f | 1350 | set_ioapic_sid(&irte, ioapic_id); |
54168ed7 | 1351 | |
c5b4712c | 1352 | modify_irte(irq, &irte); |
f007e99c | 1353 | |
c5b4712c YL |
1354 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " |
1355 | "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " | |
1356 | "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " | |
1357 | "Avail:%X Vector:%02X Dest:%08X " | |
1358 | "SID:%04X SQ:%X SVT:%X)\n", | |
3a61d7fe | 1359 | attr->ioapic, irte.present, irte.fpd, irte.dst_mode, |
c5b4712c YL |
1360 | irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, |
1361 | irte.avail, irte.vector, irte.dest_id, | |
1362 | irte.sid, irte.sq, irte.svt); | |
54168ed7 | 1363 | |
c5b4712c | 1364 | memset(entry, 0, sizeof(*entry)); |
497c9a19 | 1365 | |
c5b4712c YL |
1366 | entry->index2 = (index >> 15) & 0x1; |
1367 | entry->zero = 0; | |
1368 | entry->format = 1; | |
1369 | entry->index = (index & 0x7fff); | |
1370 | /* | |
1371 | * IO-APIC RTE will be configured with virtual vector. | |
1372 | * irq handler will do the explicit EOI to the io-apic. | |
1373 | */ | |
1374 | entry->vector = attr->ioapic_pin; | |
1375 | entry->mask = 0; /* enable IRQ */ | |
1376 | entry->trigger = attr->trigger; | |
1377 | entry->polarity = attr->polarity; | |
54168ed7 | 1378 | |
497c9a19 YL |
1379 | /* Mask level triggered irqs. |
1380 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1381 | */ | |
c5b4712c | 1382 | if (attr->trigger) |
497c9a19 | 1383 | entry->mask = 1; |
c5b4712c YL |
1384 | |
1385 | return 0; | |
1386 | } | |
497c9a19 | 1387 | |
c5b4712c YL |
1388 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1389 | unsigned int destination, int vector, | |
1390 | struct io_apic_irq_attr *attr) | |
1391 | { | |
1392 | if (intr_remapping_enabled) | |
1393 | return setup_ir_ioapic_entry(irq, | |
1394 | (struct IR_IO_APIC_route_entry *)entry, | |
1395 | destination, vector, attr); | |
497c9a19 | 1396 | |
c5b4712c YL |
1397 | memset(entry, 0, sizeof(*entry)); |
1398 | ||
1399 | entry->delivery_mode = apic->irq_delivery_mode; | |
1400 | entry->dest_mode = apic->irq_dest_mode; | |
1401 | entry->dest = destination; | |
1402 | entry->vector = vector; | |
1403 | entry->mask = 0; /* enable IRQ */ | |
1404 | entry->trigger = attr->trigger; | |
1405 | entry->polarity = attr->polarity; | |
1406 | ||
1407 | /* | |
1408 | * Mask level triggered irqs. | |
497c9a19 YL |
1409 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1410 | */ | |
c5b4712c | 1411 | if (attr->trigger) |
497c9a19 | 1412 | entry->mask = 1; |
c5b4712c | 1413 | |
497c9a19 YL |
1414 | return 0; |
1415 | } | |
1416 | ||
e4aff811 YL |
1417 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1418 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1419 | { |
1da177e4 | 1420 | struct IO_APIC_route_entry entry; |
22f65d31 | 1421 | unsigned int dest; |
497c9a19 YL |
1422 | |
1423 | if (!IO_APIC_IRQ(irq)) | |
1424 | return; | |
69c89efb SS |
1425 | /* |
1426 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1427 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1428 | * the cfg->domain. | |
1429 | */ | |
28c6a0ba | 1430 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1431 | apic->vector_allocation_domain(0, cfg->domain); |
1432 | ||
fe402e1f | 1433 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1434 | return; |
1435 | ||
debccb3e | 1436 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1437 | |
1438 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1439 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1440 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1441 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1442 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1443 | |
c5b4712c YL |
1444 | if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) { |
1445 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1446 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
3145e941 | 1447 | __clear_irq_vector(irq, cfg); |
c5b4712c | 1448 | |
497c9a19 YL |
1449 | return; |
1450 | } | |
1451 | ||
e4aff811 | 1452 | ioapic_register_intr(irq, cfg, attr->trigger); |
b81bb373 | 1453 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1454 | legacy_pic->mask(irq); |
497c9a19 | 1455 | |
e4aff811 | 1456 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1457 | } |
1458 | ||
6f50d45f | 1459 | static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) |
c8d6b8fe TG |
1460 | { |
1461 | if (idx != -1) | |
1462 | return false; | |
1463 | ||
1464 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
6f50d45f | 1465 | mpc_ioapic_id(ioapic_idx), pin); |
c8d6b8fe TG |
1466 | return true; |
1467 | } | |
1468 | ||
6f50d45f | 1469 | static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) |
497c9a19 | 1470 | { |
ed972ccf | 1471 | int idx, node = cpu_to_node(0); |
2d57e37d | 1472 | struct io_apic_irq_attr attr; |
ed972ccf | 1473 | unsigned int pin, irq; |
1da177e4 | 1474 | |
6f50d45f YL |
1475 | for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) { |
1476 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
1477 | if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) | |
b9c61b70 | 1478 | continue; |
33a201fa | 1479 | |
6f50d45f | 1480 | irq = pin_2_irq(idx, ioapic_idx, pin); |
33a201fa | 1481 | |
6f50d45f | 1482 | if ((ioapic_idx > 0) && (irq > 16)) |
fad53995 EB |
1483 | continue; |
1484 | ||
b9c61b70 YL |
1485 | /* |
1486 | * Skip the timer IRQ if there's a quirk handler | |
1487 | * installed and if it returns 1: | |
1488 | */ | |
1489 | if (apic->multi_timer_check && | |
6f50d45f | 1490 | apic->multi_timer_check(ioapic_idx, irq)) |
b9c61b70 | 1491 | continue; |
36062448 | 1492 | |
6f50d45f | 1493 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
2d57e37d | 1494 | irq_polarity(idx)); |
fbc6bff0 | 1495 | |
2d57e37d | 1496 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1497 | } |
1da177e4 LT |
1498 | } |
1499 | ||
ed972ccf TG |
1500 | static void __init setup_IO_APIC_irqs(void) |
1501 | { | |
6f50d45f | 1502 | unsigned int ioapic_idx; |
ed972ccf TG |
1503 | |
1504 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1505 | ||
6f50d45f YL |
1506 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1507 | __io_apic_setup_irqs(ioapic_idx); | |
ed972ccf TG |
1508 | } |
1509 | ||
18dce6ba YL |
1510 | /* |
1511 | * for the gsit that is not in first ioapic | |
1512 | * but could not use acpi_register_gsi() | |
1513 | * like some special sci in IBM x3330 | |
1514 | */ | |
1515 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1516 | { | |
6f50d45f | 1517 | int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1518 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1519 | |
1520 | /* | |
1521 | * Convert 'gsi' to 'ioapic.pin'. | |
1522 | */ | |
6f50d45f YL |
1523 | ioapic_idx = mp_find_ioapic(gsi); |
1524 | if (ioapic_idx < 0) | |
18dce6ba YL |
1525 | return; |
1526 | ||
6f50d45f YL |
1527 | pin = mp_find_ioapic_pin(ioapic_idx, gsi); |
1528 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
18dce6ba YL |
1529 | if (idx == -1) |
1530 | return; | |
1531 | ||
6f50d45f | 1532 | irq = pin_2_irq(idx, ioapic_idx, pin); |
fe6dab4e YL |
1533 | |
1534 | /* Only handle the non legacy irqs on secondary ioapics */ | |
6f50d45f | 1535 | if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY) |
18dce6ba | 1536 | return; |
fe6dab4e | 1537 | |
6f50d45f | 1538 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
da1ad9d7 TG |
1539 | irq_polarity(idx)); |
1540 | ||
710dcda6 | 1541 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1542 | } |
1543 | ||
1da177e4 | 1544 | /* |
f7633ce5 | 1545 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1546 | */ |
6f50d45f YL |
1547 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
1548 | unsigned int pin, int vector) | |
1da177e4 LT |
1549 | { |
1550 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1551 | |
54168ed7 IM |
1552 | if (intr_remapping_enabled) |
1553 | return; | |
54168ed7 | 1554 | |
36062448 | 1555 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1556 | |
1557 | /* | |
1558 | * We use logical delivery to get the timer IRQ | |
1559 | * to the first CPU. | |
1560 | */ | |
9b5bc8dc | 1561 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1562 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1563 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1564 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1565 | entry.polarity = 0; |
1566 | entry.trigger = 0; | |
1567 | entry.vector = vector; | |
1568 | ||
1569 | /* | |
1570 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1571 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1572 | */ |
2c778651 TG |
1573 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1574 | "edge"); | |
1da177e4 LT |
1575 | |
1576 | /* | |
1577 | * Add it to the IO-APIC irq-routing table: | |
1578 | */ | |
6f50d45f | 1579 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1580 | } |
1581 | ||
6f50d45f | 1582 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
1da177e4 | 1583 | { |
cda417dd | 1584 | int i; |
1da177e4 LT |
1585 | union IO_APIC_reg_00 reg_00; |
1586 | union IO_APIC_reg_01 reg_01; | |
1587 | union IO_APIC_reg_02 reg_02; | |
1588 | union IO_APIC_reg_03 reg_03; | |
1589 | unsigned long flags; | |
1da177e4 | 1590 | |
dade7716 | 1591 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1592 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1593 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1594 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1595 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1596 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1597 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1598 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1599 | |
54168ed7 | 1600 | printk("\n"); |
6f50d45f | 1601 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1602 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1603 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1604 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1605 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1606 | |
54168ed7 | 1607 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1608 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1609 | reg_01.bits.entries); | |
1da177e4 LT |
1610 | |
1611 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1612 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1613 | reg_01.bits.version); | |
1da177e4 LT |
1614 | |
1615 | /* | |
1616 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1617 | * but the value of reg_02 is read as the previous read register | |
1618 | * value, so ignore it if reg_02 == reg_01. | |
1619 | */ | |
1620 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1621 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1622 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1623 | } |
1624 | ||
1625 | /* | |
1626 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1627 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1628 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1629 | */ | |
1630 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1631 | reg_03.raw != reg_01.raw) { | |
1632 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1633 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1634 | } |
1635 | ||
1636 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1637 | ||
42f0efc5 NC |
1638 | if (intr_remapping_enabled) { |
1639 | printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR" | |
1640 | " Pol Stat Indx2 Zero Vect:\n"); | |
1641 | } else { | |
1642 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" | |
1643 | " Stat Dmod Deli Vect:\n"); | |
1644 | } | |
1da177e4 LT |
1645 | |
1646 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
42f0efc5 NC |
1647 | if (intr_remapping_enabled) { |
1648 | struct IO_APIC_route_entry entry; | |
1649 | struct IR_IO_APIC_route_entry *ir_entry; | |
1650 | ||
6f50d45f | 1651 | entry = ioapic_read_entry(ioapic_idx, i); |
42f0efc5 NC |
1652 | ir_entry = (struct IR_IO_APIC_route_entry *) &entry; |
1653 | printk(KERN_DEBUG " %02x %04X ", | |
1654 | i, | |
1655 | ir_entry->index | |
1656 | ); | |
1657 | printk("%1d %1d %1d %1d %1d " | |
1658 | "%1d %1d %X %02X\n", | |
1659 | ir_entry->format, | |
1660 | ir_entry->mask, | |
1661 | ir_entry->trigger, | |
1662 | ir_entry->irr, | |
1663 | ir_entry->polarity, | |
1664 | ir_entry->delivery_status, | |
1665 | ir_entry->index2, | |
1666 | ir_entry->zero, | |
1667 | ir_entry->vector | |
1668 | ); | |
1669 | } else { | |
1670 | struct IO_APIC_route_entry entry; | |
1671 | ||
6f50d45f | 1672 | entry = ioapic_read_entry(ioapic_idx, i); |
42f0efc5 NC |
1673 | printk(KERN_DEBUG " %02x %02X ", |
1674 | i, | |
1675 | entry.dest | |
1676 | ); | |
1677 | printk("%1d %1d %1d %1d %1d " | |
1678 | "%1d %1d %02X\n", | |
1679 | entry.mask, | |
1680 | entry.trigger, | |
1681 | entry.irr, | |
1682 | entry.polarity, | |
1683 | entry.delivery_status, | |
1684 | entry.dest_mode, | |
1685 | entry.delivery_mode, | |
1686 | entry.vector | |
1687 | ); | |
1688 | } | |
1da177e4 | 1689 | } |
cda417dd YL |
1690 | } |
1691 | ||
1692 | __apicdebuginit(void) print_IO_APICs(void) | |
1693 | { | |
6f50d45f | 1694 | int ioapic_idx; |
cda417dd YL |
1695 | struct irq_cfg *cfg; |
1696 | unsigned int irq; | |
6fd36ba0 | 1697 | struct irq_chip *chip; |
cda417dd YL |
1698 | |
1699 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
6f50d45f | 1700 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
cda417dd | 1701 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1702 | mpc_ioapic_id(ioapic_idx), |
1703 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1704 | |
1705 | /* | |
1706 | * We are a bit conservative about what we expect. We have to | |
1707 | * know about every hardware change ASAP. | |
1708 | */ | |
1709 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1710 | ||
6f50d45f YL |
1711 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1712 | print_IO_APIC(ioapic_idx); | |
42f0efc5 | 1713 | |
1da177e4 | 1714 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1715 | for_each_active_irq(irq) { |
0b8f1efa YL |
1716 | struct irq_pin_list *entry; |
1717 | ||
6fd36ba0 MN |
1718 | chip = irq_get_chip(irq); |
1719 | if (chip != &ioapic_chip) | |
1720 | continue; | |
1721 | ||
2c778651 | 1722 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1723 | if (!cfg) |
1724 | continue; | |
0b8f1efa | 1725 | entry = cfg->irq_2_pin; |
0f978f45 | 1726 | if (!entry) |
1da177e4 | 1727 | continue; |
8f09cd20 | 1728 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1729 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1730 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1731 | printk("\n"); |
1732 | } | |
1733 | ||
1734 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1735 | } |
1736 | ||
251e1e44 | 1737 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1738 | { |
251e1e44 | 1739 | int i; |
1da177e4 | 1740 | |
251e1e44 IM |
1741 | printk(KERN_DEBUG); |
1742 | ||
1743 | for (i = 0; i < 8; i++) | |
1744 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1745 | ||
1746 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1747 | } |
1748 | ||
32f71aff | 1749 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1750 | { |
97a52714 | 1751 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1752 | u64 icr; |
1da177e4 | 1753 | |
251e1e44 | 1754 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1755 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1756 | v = apic_read(APIC_ID); |
54168ed7 | 1757 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1758 | v = apic_read(APIC_LVR); |
1759 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1760 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1761 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1762 | |
1763 | v = apic_read(APIC_TASKPRI); | |
1764 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1765 | ||
54168ed7 | 1766 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1767 | if (!APIC_XAPIC(ver)) { |
1768 | v = apic_read(APIC_ARBPRI); | |
1769 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1770 | v & APIC_ARBPRI_MASK); | |
1771 | } | |
1da177e4 LT |
1772 | v = apic_read(APIC_PROCPRI); |
1773 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1774 | } | |
1775 | ||
a11b5abe YL |
1776 | /* |
1777 | * Remote read supported only in the 82489DX and local APIC for | |
1778 | * Pentium processors. | |
1779 | */ | |
1780 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1781 | v = apic_read(APIC_RRR); | |
1782 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1783 | } | |
1784 | ||
1da177e4 LT |
1785 | v = apic_read(APIC_LDR); |
1786 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1787 | if (!x2apic_enabled()) { |
1788 | v = apic_read(APIC_DFR); | |
1789 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1790 | } | |
1da177e4 LT |
1791 | v = apic_read(APIC_SPIV); |
1792 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1793 | ||
1794 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1795 | print_APIC_field(APIC_ISR); |
1da177e4 | 1796 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1797 | print_APIC_field(APIC_TMR); |
1da177e4 | 1798 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1799 | print_APIC_field(APIC_IRR); |
1da177e4 | 1800 | |
54168ed7 IM |
1801 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1802 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1803 | apic_write(APIC_ESR, 0); |
54168ed7 | 1804 | |
1da177e4 LT |
1805 | v = apic_read(APIC_ESR); |
1806 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1807 | } | |
1808 | ||
7ab6af7a | 1809 | icr = apic_icr_read(); |
0c425cec IM |
1810 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1811 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1812 | |
1813 | v = apic_read(APIC_LVTT); | |
1814 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1815 | ||
1816 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1817 | v = apic_read(APIC_LVTPC); | |
1818 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1819 | } | |
1820 | v = apic_read(APIC_LVT0); | |
1821 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1822 | v = apic_read(APIC_LVT1); | |
1823 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1824 | ||
1825 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1826 | v = apic_read(APIC_LVTERR); | |
1827 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1828 | } | |
1829 | ||
1830 | v = apic_read(APIC_TMICT); | |
1831 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1832 | v = apic_read(APIC_TMCCT); | |
1833 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1834 | v = apic_read(APIC_TDCR); | |
1835 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1836 | |
1837 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1838 | v = apic_read(APIC_EFEAT); | |
1839 | maxlvt = (v >> 16) & 0xff; | |
1840 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1841 | v = apic_read(APIC_ECTRL); | |
1842 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1843 | for (i = 0; i < maxlvt; i++) { | |
1844 | v = apic_read(APIC_EILVTn(i)); | |
1845 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1846 | } | |
1847 | } | |
1da177e4 LT |
1848 | printk("\n"); |
1849 | } | |
1850 | ||
2626eb2b | 1851 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1852 | { |
ffd5aae7 YL |
1853 | int cpu; |
1854 | ||
2626eb2b CG |
1855 | if (!maxcpu) |
1856 | return; | |
1857 | ||
ffd5aae7 | 1858 | preempt_disable(); |
2626eb2b CG |
1859 | for_each_online_cpu(cpu) { |
1860 | if (cpu >= maxcpu) | |
1861 | break; | |
ffd5aae7 | 1862 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1863 | } |
ffd5aae7 | 1864 | preempt_enable(); |
1da177e4 LT |
1865 | } |
1866 | ||
32f71aff | 1867 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1868 | { |
1da177e4 LT |
1869 | unsigned int v; |
1870 | unsigned long flags; | |
1871 | ||
b81bb373 | 1872 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1873 | return; |
1874 | ||
1875 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1876 | ||
5619c280 | 1877 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1878 | |
1879 | v = inb(0xa1) << 8 | inb(0x21); | |
1880 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1881 | ||
1882 | v = inb(0xa0) << 8 | inb(0x20); | |
1883 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1884 | ||
54168ed7 IM |
1885 | outb(0x0b,0xa0); |
1886 | outb(0x0b,0x20); | |
1da177e4 | 1887 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1888 | outb(0x0a,0xa0); |
1889 | outb(0x0a,0x20); | |
1da177e4 | 1890 | |
5619c280 | 1891 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1892 | |
1893 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1894 | ||
1895 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1896 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1897 | } | |
1898 | ||
2626eb2b CG |
1899 | static int __initdata show_lapic = 1; |
1900 | static __init int setup_show_lapic(char *arg) | |
1901 | { | |
1902 | int num = -1; | |
1903 | ||
1904 | if (strcmp(arg, "all") == 0) { | |
1905 | show_lapic = CONFIG_NR_CPUS; | |
1906 | } else { | |
1907 | get_option(&arg, &num); | |
1908 | if (num >= 0) | |
1909 | show_lapic = num; | |
1910 | } | |
1911 | ||
1912 | return 1; | |
1913 | } | |
1914 | __setup("show_lapic=", setup_show_lapic); | |
1915 | ||
1916 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1917 | { |
2626eb2b CG |
1918 | if (apic_verbosity == APIC_QUIET) |
1919 | return 0; | |
1920 | ||
32f71aff | 1921 | print_PIC(); |
4797f6b0 YL |
1922 | |
1923 | /* don't print out if apic is not there */ | |
8312136f | 1924 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1925 | return 0; |
1926 | ||
2626eb2b | 1927 | print_local_APICs(show_lapic); |
cda417dd | 1928 | print_IO_APICs(); |
32f71aff MR |
1929 | |
1930 | return 0; | |
1931 | } | |
1932 | ||
ded1f6ab | 1933 | late_initcall(print_ICs); |
32f71aff | 1934 | |
1da177e4 | 1935 | |
efa2559f YL |
1936 | /* Where if anywhere is the i8259 connect in external int mode */ |
1937 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1938 | ||
54168ed7 | 1939 | void __init enable_IO_APIC(void) |
1da177e4 | 1940 | { |
fcfd636a | 1941 | int i8259_apic, i8259_pin; |
54168ed7 | 1942 | int apic; |
bc07844a | 1943 | |
b81bb373 | 1944 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1945 | return; |
1946 | ||
54168ed7 | 1947 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1948 | int pin; |
1949 | /* See if any of the pins is in ExtINT mode */ | |
b69c6c3b | 1950 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
fcfd636a | 1951 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1952 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1953 | |
fcfd636a EB |
1954 | /* If the interrupt line is enabled and in ExtInt mode |
1955 | * I have found the pin where the i8259 is connected. | |
1956 | */ | |
1957 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1958 | ioapic_i8259.apic = apic; | |
1959 | ioapic_i8259.pin = pin; | |
1960 | goto found_i8259; | |
1961 | } | |
1962 | } | |
1963 | } | |
1964 | found_i8259: | |
1965 | /* Look to see what if the MP table has reported the ExtINT */ | |
1966 | /* If we could not find the appropriate pin by looking at the ioapic | |
1967 | * the i8259 probably is not connected the ioapic but give the | |
1968 | * mptable a chance anyway. | |
1969 | */ | |
1970 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1971 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1972 | /* Trust the MP table if nothing is setup in the hardware */ | |
1973 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1974 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1975 | ioapic_i8259.pin = i8259_pin; | |
1976 | ioapic_i8259.apic = i8259_apic; | |
1977 | } | |
1978 | /* Complain if the MP table and the hardware disagree */ | |
1979 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1980 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1981 | { | |
1982 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1983 | } |
1984 | ||
1985 | /* | |
1986 | * Do not trust the IO-APIC being empty at bootup | |
1987 | */ | |
1988 | clear_IO_APIC(); | |
1989 | } | |
1990 | ||
1991 | /* | |
1992 | * Not an __init, needed by the reboot code | |
1993 | */ | |
1994 | void disable_IO_APIC(void) | |
1995 | { | |
1996 | /* | |
1997 | * Clear the IO-APIC before rebooting: | |
1998 | */ | |
1999 | clear_IO_APIC(); | |
2000 | ||
b81bb373 | 2001 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
2002 | return; |
2003 | ||
650927ef | 2004 | /* |
0b968d23 | 2005 | * If the i8259 is routed through an IOAPIC |
650927ef | 2006 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2007 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2008 | * |
2009 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2010 | * as virtual wire B is little complex (need to configure both | |
0d2eb44f | 2011 | * IOAPIC RTE as well as interrupt-remapping table entry). |
7c6d9f97 | 2012 | * As this gets called during crash dump, keep this simple for now. |
650927ef | 2013 | */ |
7c6d9f97 | 2014 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2015 | struct IO_APIC_route_entry entry; |
650927ef EB |
2016 | |
2017 | memset(&entry, 0, sizeof(entry)); | |
2018 | entry.mask = 0; /* Enabled */ | |
2019 | entry.trigger = 0; /* Edge */ | |
2020 | entry.irr = 0; | |
2021 | entry.polarity = 0; /* High */ | |
2022 | entry.delivery_status = 0; | |
2023 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2024 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2025 | entry.vector = 0; |
54168ed7 | 2026 | entry.dest = read_apic_id(); |
650927ef EB |
2027 | |
2028 | /* | |
2029 | * Add it to the IO-APIC irq-routing table: | |
2030 | */ | |
cf4c6a2f | 2031 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2032 | } |
54168ed7 | 2033 | |
7c6d9f97 SS |
2034 | /* |
2035 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2036 | */ | |
8312136f | 2037 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2038 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2039 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2040 | } |
2041 | ||
54168ed7 | 2042 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2043 | /* |
2044 | * function to set the IO-APIC physical IDs based on the | |
2045 | * values stored in the MPC table. | |
2046 | * | |
2047 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2048 | */ | |
a38c5380 | 2049 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
2050 | { |
2051 | union IO_APIC_reg_00 reg_00; | |
2052 | physid_mask_t phys_id_present_map; | |
6f50d45f | 2053 | int ioapic_idx; |
1da177e4 LT |
2054 | int i; |
2055 | unsigned char old_id; | |
2056 | unsigned long flags; | |
2057 | ||
2058 | /* | |
2059 | * This is broken; anything with a real cpu count has to | |
2060 | * circumvent this idiocy regardless. | |
2061 | */ | |
7abc0753 | 2062 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2063 | |
2064 | /* | |
2065 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2066 | */ | |
6f50d45f | 2067 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { |
1da177e4 | 2068 | /* Read the register 0 value */ |
dade7716 | 2069 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2070 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2071 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2072 | |
6f50d45f | 2073 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 2074 | |
6f50d45f | 2075 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 2076 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 2077 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2078 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2079 | reg_00.bits.ID); | |
6f50d45f | 2080 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
2081 | } |
2082 | ||
1da177e4 LT |
2083 | /* |
2084 | * Sanity check, is the ID really free? Every APIC in a | |
2085 | * system must have a unique ID or we get lots of nice | |
2086 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2087 | */ | |
7abc0753 | 2088 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 2089 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 2090 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 2091 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2092 | for (i = 0; i < get_physical_broadcast(); i++) |
2093 | if (!physid_isset(i, phys_id_present_map)) | |
2094 | break; | |
2095 | if (i >= get_physical_broadcast()) | |
2096 | panic("Max APIC ID exceeded!\n"); | |
2097 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2098 | i); | |
2099 | physid_set(i, phys_id_present_map); | |
6f50d45f | 2100 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
2101 | } else { |
2102 | physid_mask_t tmp; | |
6f50d45f | 2103 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 2104 | &tmp); |
1da177e4 LT |
2105 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2106 | "phys_id_present_map\n", | |
6f50d45f | 2107 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2108 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2109 | } | |
2110 | ||
1da177e4 LT |
2111 | /* |
2112 | * We need to adjust the IRQ routing table | |
2113 | * if the ID changed. | |
2114 | */ | |
6f50d45f | 2115 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 2116 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2117 | if (mp_irqs[i].dstapic == old_id) |
2118 | mp_irqs[i].dstapic | |
6f50d45f | 2119 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
2120 | |
2121 | /* | |
60d79fd9 YL |
2122 | * Update the ID register according to the right value |
2123 | * from the MPC table if they are different. | |
36062448 | 2124 | */ |
6f50d45f | 2125 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
2126 | continue; |
2127 | ||
1da177e4 LT |
2128 | apic_printk(APIC_VERBOSE, KERN_INFO |
2129 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 2130 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 2131 | |
6f50d45f | 2132 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 2133 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2134 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 2135 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2136 | |
2137 | /* | |
2138 | * Sanity check | |
2139 | */ | |
dade7716 | 2140 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2141 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2142 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 2143 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
1da177e4 LT |
2144 | printk("could not set ID!\n"); |
2145 | else | |
2146 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2147 | } | |
2148 | } | |
a38c5380 SAS |
2149 | |
2150 | void __init setup_ioapic_ids_from_mpc(void) | |
2151 | { | |
2152 | ||
2153 | if (acpi_ioapic) | |
2154 | return; | |
2155 | /* | |
2156 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2157 | * no meaning without the serial APIC bus. | |
2158 | */ | |
2159 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2160 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2161 | return; | |
2162 | setup_ioapic_ids_from_mpc_nocheck(); | |
2163 | } | |
54168ed7 | 2164 | #endif |
1da177e4 | 2165 | |
7ce0bcfd | 2166 | int no_timer_check __initdata; |
8542b200 ZA |
2167 | |
2168 | static int __init notimercheck(char *s) | |
2169 | { | |
2170 | no_timer_check = 1; | |
2171 | return 1; | |
2172 | } | |
2173 | __setup("no_timer_check", notimercheck); | |
2174 | ||
1da177e4 LT |
2175 | /* |
2176 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2177 | * about the timer IRQ. We do the following to work around the situation: | |
2178 | * | |
2179 | * - timer IRQ defaults to IO-APIC IRQ | |
2180 | * - if this function detects that timer IRQs are defunct, then we fall | |
2181 | * back to ISA timer IRQs | |
2182 | */ | |
f0a7a5c9 | 2183 | static int __init timer_irq_works(void) |
1da177e4 LT |
2184 | { |
2185 | unsigned long t1 = jiffies; | |
4aae0702 | 2186 | unsigned long flags; |
1da177e4 | 2187 | |
8542b200 ZA |
2188 | if (no_timer_check) |
2189 | return 1; | |
2190 | ||
4aae0702 | 2191 | local_save_flags(flags); |
1da177e4 LT |
2192 | local_irq_enable(); |
2193 | /* Let ten ticks pass... */ | |
2194 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2195 | local_irq_restore(flags); |
1da177e4 LT |
2196 | |
2197 | /* | |
2198 | * Expect a few ticks at least, to be sure some possible | |
2199 | * glue logic does not lock up after one or two first | |
2200 | * ticks in a non-ExtINT mode. Also the local APIC | |
2201 | * might have cached one ExtINT interrupt. Finally, at | |
2202 | * least one tick may be lost due to delays. | |
2203 | */ | |
54168ed7 IM |
2204 | |
2205 | /* jiffies wrap? */ | |
1d16b53e | 2206 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2207 | return 1; |
1da177e4 LT |
2208 | return 0; |
2209 | } | |
2210 | ||
2211 | /* | |
2212 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2213 | * number of pending IRQ events unhandled. These cases are very rare, | |
2214 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2215 | * better to do it this way as thus we do not have to be aware of | |
2216 | * 'pending' interrupts in the IRQ path, except at this point. | |
2217 | */ | |
2218 | /* | |
2219 | * Edge triggered needs to resend any interrupt | |
2220 | * that was delayed but this is now handled in the device | |
2221 | * independent code. | |
2222 | */ | |
2223 | ||
2224 | /* | |
2225 | * Starting up a edge-triggered IO-APIC interrupt is | |
2226 | * nasty - we need to make sure that we get the edge. | |
2227 | * If it is already asserted for some reason, we need | |
2228 | * return 1 to indicate that is was pending. | |
2229 | * | |
2230 | * This is not complete - we should be able to fake | |
2231 | * an edge even if it isn't on the 8259A... | |
2232 | */ | |
54168ed7 | 2233 | |
61a38ce3 | 2234 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2235 | { |
61a38ce3 | 2236 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2237 | unsigned long flags; |
2238 | ||
dade7716 | 2239 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2240 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2241 | legacy_pic->mask(irq); |
b81bb373 | 2242 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2243 | was_pending = 1; |
2244 | } | |
61a38ce3 | 2245 | __unmask_ioapic(data->chip_data); |
dade7716 | 2246 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2247 | |
2248 | return was_pending; | |
2249 | } | |
2250 | ||
90297c5f | 2251 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2252 | { |
90297c5f | 2253 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2254 | unsigned long flags; |
2255 | ||
dade7716 | 2256 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2257 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2258 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2259 | |
2260 | return 1; | |
2261 | } | |
497c9a19 | 2262 | |
54168ed7 IM |
2263 | /* |
2264 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2265 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2266 | * handled with the level-triggered descriptor, but that one has slightly | |
2267 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2268 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2269 | * races. | |
2270 | */ | |
497c9a19 | 2271 | |
54168ed7 | 2272 | #ifdef CONFIG_SMP |
9338ad6f | 2273 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2274 | { |
2275 | cpumask_var_t cleanup_mask; | |
2276 | ||
2277 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2278 | unsigned int i; | |
e85abf8f GH |
2279 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2280 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2281 | } else { | |
2282 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2283 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2284 | free_cpumask_var(cleanup_mask); | |
2285 | } | |
2286 | cfg->move_in_progress = 0; | |
2287 | } | |
2288 | ||
4420471f | 2289 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2290 | { |
2291 | int apic, pin; | |
2292 | struct irq_pin_list *entry; | |
2293 | u8 vector = cfg->vector; | |
2294 | ||
2977fb3f | 2295 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2296 | unsigned int reg; |
2297 | ||
e85abf8f GH |
2298 | apic = entry->apic; |
2299 | pin = entry->pin; | |
2300 | /* | |
2301 | * With interrupt-remapping, destination information comes | |
2302 | * from interrupt-remapping table entry. | |
2303 | */ | |
1a0730d6 | 2304 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2305 | io_apic_write(apic, 0x11 + pin*2, dest); |
2306 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2307 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2308 | reg |= vector; | |
2309 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2310 | } |
2311 | } | |
2312 | ||
2313 | /* | |
f7e909ea | 2314 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2315 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2316 | * leaves data->affinity untouched. |
e85abf8f | 2317 | */ |
f7e909ea TG |
2318 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2319 | unsigned int *dest_id) | |
e85abf8f | 2320 | { |
f7e909ea | 2321 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2322 | |
2323 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2324 | return -1; |
e85abf8f | 2325 | |
f7e909ea | 2326 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2327 | return -1; |
e85abf8f | 2328 | |
f7e909ea | 2329 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2330 | |
f7e909ea | 2331 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2332 | return 0; |
e85abf8f GH |
2333 | } |
2334 | ||
4420471f | 2335 | static int |
f7e909ea TG |
2336 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2337 | bool force) | |
e85abf8f | 2338 | { |
f7e909ea | 2339 | unsigned int dest, irq = data->irq; |
e85abf8f | 2340 | unsigned long flags; |
f7e909ea | 2341 | int ret; |
e85abf8f | 2342 | |
dade7716 | 2343 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2344 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2345 | if (!ret) { |
e85abf8f GH |
2346 | /* Only the high 8 bits are valid. */ |
2347 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2348 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2349 | } |
dade7716 | 2350 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2351 | return ret; |
e85abf8f GH |
2352 | } |
2353 | ||
d3f13810 | 2354 | #ifdef CONFIG_IRQ_REMAP |
497c9a19 | 2355 | |
54168ed7 IM |
2356 | /* |
2357 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2358 | * | |
0280f7c4 SS |
2359 | * For both level and edge triggered, irq migration is a simple atomic |
2360 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2361 | * |
0280f7c4 SS |
2362 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2363 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2364 | * Real vector that is used for interrupting cpu will be coming from | |
2365 | * the interrupt-remapping table entry. | |
13ea20f7 SS |
2366 | * |
2367 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
2368 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
54168ed7 | 2369 | */ |
d5dedd45 | 2370 | static int |
f19f5ecc TG |
2371 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2372 | bool force) | |
497c9a19 | 2373 | { |
f19f5ecc TG |
2374 | struct irq_cfg *cfg = data->chip_data; |
2375 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2376 | struct irte irte; |
497c9a19 | 2377 | |
22f65d31 | 2378 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2379 | return -EINVAL; |
497c9a19 | 2380 | |
54168ed7 | 2381 | if (get_irte(irq, &irte)) |
f19f5ecc | 2382 | return -EBUSY; |
497c9a19 | 2383 | |
3145e941 | 2384 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2385 | return -EBUSY; |
54168ed7 | 2386 | |
debccb3e | 2387 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2388 | |
54168ed7 IM |
2389 | irte.vector = cfg->vector; |
2390 | irte.dest_id = IRTE_DEST(dest); | |
2391 | ||
2392 | /* | |
13ea20f7 SS |
2393 | * Atomically updates the IRTE with the new destination, vector |
2394 | * and flushes the interrupt entry cache. | |
54168ed7 IM |
2395 | */ |
2396 | modify_irte(irq, &irte); | |
2397 | ||
13ea20f7 SS |
2398 | /* |
2399 | * After this point, all the interrupts will start arriving | |
2400 | * at the new destination. So, time to cleanup the previous | |
2401 | * vector allocation. | |
2402 | */ | |
22f65d31 MT |
2403 | if (cfg->move_in_progress) |
2404 | send_cleanup_vector(cfg); | |
54168ed7 | 2405 | |
f19f5ecc | 2406 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2407 | return 0; |
54168ed7 IM |
2408 | } |
2409 | ||
29b61be6 | 2410 | #else |
f19f5ecc TG |
2411 | static inline int |
2412 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2413 | bool force) | |
29b61be6 | 2414 | { |
d5dedd45 | 2415 | return 0; |
29b61be6 | 2416 | } |
54168ed7 IM |
2417 | #endif |
2418 | ||
2419 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2420 | { | |
2421 | unsigned vector, me; | |
8f2466f4 | 2422 | |
54168ed7 | 2423 | ack_APIC_irq(); |
54168ed7 | 2424 | irq_enter(); |
98ad1cc1 | 2425 | exit_idle(); |
54168ed7 IM |
2426 | |
2427 | me = smp_processor_id(); | |
2428 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2429 | unsigned int irq; | |
68a8ca59 | 2430 | unsigned int irr; |
54168ed7 IM |
2431 | struct irq_desc *desc; |
2432 | struct irq_cfg *cfg; | |
0a3aee0d | 2433 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2434 | |
0b8f1efa YL |
2435 | if (irq == -1) |
2436 | continue; | |
2437 | ||
54168ed7 IM |
2438 | desc = irq_to_desc(irq); |
2439 | if (!desc) | |
2440 | continue; | |
2441 | ||
2442 | cfg = irq_cfg(irq); | |
239007b8 | 2443 | raw_spin_lock(&desc->lock); |
54168ed7 | 2444 | |
7f41c2e1 SS |
2445 | /* |
2446 | * Check if the irq migration is in progress. If so, we | |
2447 | * haven't received the cleanup request yet for this irq. | |
2448 | */ | |
2449 | if (cfg->move_in_progress) | |
2450 | goto unlock; | |
2451 | ||
22f65d31 | 2452 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2453 | goto unlock; |
2454 | ||
68a8ca59 SS |
2455 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2456 | /* | |
2457 | * Check if the vector that needs to be cleanedup is | |
2458 | * registered at the cpu's IRR. If so, then this is not | |
2459 | * the best time to clean it up. Lets clean it up in the | |
2460 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2461 | * to myself. | |
2462 | */ | |
2463 | if (irr & (1 << (vector % 32))) { | |
2464 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2465 | goto unlock; | |
2466 | } | |
0a3aee0d | 2467 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2468 | unlock: |
239007b8 | 2469 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2470 | } |
2471 | ||
2472 | irq_exit(); | |
2473 | } | |
2474 | ||
dd5f15e5 | 2475 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2476 | { |
a5e74b84 | 2477 | unsigned me; |
54168ed7 | 2478 | |
fcef5911 | 2479 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2480 | return; |
2481 | ||
54168ed7 | 2482 | me = smp_processor_id(); |
10b888d6 | 2483 | |
fcef5911 | 2484 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2485 | send_cleanup_vector(cfg); |
497c9a19 | 2486 | } |
a5e74b84 | 2487 | |
dd5f15e5 | 2488 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2489 | { |
dd5f15e5 | 2490 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2491 | } |
2492 | ||
2493 | void irq_force_complete_move(int irq) | |
2494 | { | |
2c778651 | 2495 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2496 | |
bbd391a1 PB |
2497 | if (!cfg) |
2498 | return; | |
2499 | ||
dd5f15e5 | 2500 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2501 | } |
497c9a19 | 2502 | #else |
dd5f15e5 | 2503 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2504 | #endif |
3145e941 | 2505 | |
90297c5f | 2506 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2507 | { |
90297c5f | 2508 | irq_complete_move(data->chip_data); |
08221110 | 2509 | irq_move_irq(data); |
1d025192 YL |
2510 | ack_APIC_irq(); |
2511 | } | |
2512 | ||
3eb2cce8 | 2513 | atomic_t irq_mis_count; |
3eb2cce8 | 2514 | |
90297c5f | 2515 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2516 | { |
90297c5f TG |
2517 | struct irq_cfg *cfg = data->chip_data; |
2518 | int i, do_unmask_irq = 0, irq = data->irq; | |
3eb2cce8 | 2519 | unsigned long v; |
047c8fdb | 2520 | |
dd5f15e5 | 2521 | irq_complete_move(cfg); |
047c8fdb | 2522 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2523 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2524 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
54168ed7 | 2525 | do_unmask_irq = 1; |
dd5f15e5 | 2526 | mask_ioapic(cfg); |
54168ed7 | 2527 | } |
047c8fdb YL |
2528 | #endif |
2529 | ||
3eb2cce8 | 2530 | /* |
916a0fe7 JF |
2531 | * It appears there is an erratum which affects at least version 0x11 |
2532 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2533 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2534 | * erroneously delivered as edge-triggered one but the respective IRR | |
2535 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2536 | * message but it will never arrive and further interrupts are blocked | |
2537 | * from the source. The exact reason is so far unknown, but the | |
2538 | * phenomenon was observed when two consecutive interrupt requests | |
2539 | * from a given source get delivered to the same CPU and the source is | |
2540 | * temporarily disabled in between. | |
2541 | * | |
2542 | * A workaround is to simulate an EOI message manually. We achieve it | |
2543 | * by setting the trigger mode to edge and then to level when the edge | |
2544 | * trigger mode gets detected in the TMR of a local APIC for a | |
2545 | * level-triggered interrupt. We mask the source for the time of the | |
2546 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2547 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2548 | * |
2549 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2550 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2551 | * destination that is handling the corresponding interrupt. This | |
2552 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2553 | * level-triggered io-apic interrupt will be seen as an edge | |
2554 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2555 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2556 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2557 | * supporting EOI register, we do an explicit EOI to clear the | |
2558 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2559 | * we use the above logic (mask+edge followed by unmask+level) from | |
2560 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2561 | */ |
3145e941 | 2562 | i = cfg->vector; |
3eb2cce8 | 2563 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2564 | |
54168ed7 IM |
2565 | /* |
2566 | * We must acknowledge the irq before we move it or the acknowledge will | |
2567 | * not propagate properly. | |
2568 | */ | |
2569 | ack_APIC_irq(); | |
2570 | ||
1c83995b SS |
2571 | /* |
2572 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2573 | * message via io-apic EOI register write or simulating it using | |
2574 | * mask+edge followed by unnask+level logic) manually when the | |
2575 | * level triggered interrupt is seen as the edge triggered interrupt | |
2576 | * at the cpu. | |
2577 | */ | |
ca64c47c MR |
2578 | if (!(v & (1 << (i & 0x1f)))) { |
2579 | atomic_inc(&irq_mis_count); | |
2580 | ||
dd5f15e5 | 2581 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2582 | } |
2583 | ||
54168ed7 IM |
2584 | /* Now we can move and renable the irq */ |
2585 | if (unlikely(do_unmask_irq)) { | |
2586 | /* Only migrate the irq if the ack has been received. | |
2587 | * | |
2588 | * On rare occasions the broadcast level triggered ack gets | |
2589 | * delayed going to ioapics, and if we reprogram the | |
2590 | * vector while Remote IRR is still set the irq will never | |
2591 | * fire again. | |
2592 | * | |
2593 | * To prevent this scenario we read the Remote IRR bit | |
2594 | * of the ioapic. This has two effects. | |
2595 | * - On any sane system the read of the ioapic will | |
2596 | * flush writes (and acks) going to the ioapic from | |
2597 | * this cpu. | |
2598 | * - We get to see if the ACK has actually been delivered. | |
2599 | * | |
2600 | * Based on failed experiments of reprogramming the | |
2601 | * ioapic entry from outside of irq context starting | |
2602 | * with masking the ioapic entry and then polling until | |
2603 | * Remote IRR was clear before reprogramming the | |
2604 | * ioapic I don't trust the Remote IRR bit to be | |
2605 | * completey accurate. | |
2606 | * | |
2607 | * However there appears to be no other way to plug | |
2608 | * this race, so if the Remote IRR bit is not | |
2609 | * accurate and is causing problems then it is a hardware bug | |
2610 | * and you can go talk to the chipset vendor about it. | |
2611 | */ | |
3145e941 | 2612 | if (!io_apic_level_ack_pending(cfg)) |
08221110 | 2613 | irq_move_masked_irq(data); |
dd5f15e5 | 2614 | unmask_ioapic(cfg); |
54168ed7 | 2615 | } |
3eb2cce8 | 2616 | } |
1d025192 | 2617 | |
d3f13810 | 2618 | #ifdef CONFIG_IRQ_REMAP |
90297c5f | 2619 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2620 | { |
5d0ae2db | 2621 | ack_APIC_irq(); |
d0b03bd1 HW |
2622 | } |
2623 | ||
90297c5f | 2624 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2625 | { |
5d0ae2db | 2626 | ack_APIC_irq(); |
90297c5f | 2627 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 | 2628 | } |
c39d77ff SS |
2629 | |
2630 | static void ir_print_prefix(struct irq_data *data, struct seq_file *p) | |
2631 | { | |
2632 | seq_printf(p, " IR-%s", data->chip->name); | |
2633 | } | |
2634 | ||
2635 | static void irq_remap_modify_chip_defaults(struct irq_chip *chip) | |
2636 | { | |
2637 | chip->irq_print_chip = ir_print_prefix; | |
2638 | chip->irq_ack = ir_ack_apic_edge; | |
2639 | chip->irq_eoi = ir_ack_apic_level; | |
2640 | ||
2641 | #ifdef CONFIG_SMP | |
2642 | chip->irq_set_affinity = ir_ioapic_set_affinity; | |
2643 | #endif | |
2644 | } | |
d3f13810 | 2645 | #endif /* CONFIG_IRQ_REMAP */ |
d0b03bd1 | 2646 | |
f5b9ed7a | 2647 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2648 | .name = "IO-APIC", |
2649 | .irq_startup = startup_ioapic_irq, | |
2650 | .irq_mask = mask_ioapic_irq, | |
2651 | .irq_unmask = unmask_ioapic_irq, | |
2652 | .irq_ack = ack_apic_edge, | |
2653 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2654 | #ifdef CONFIG_SMP |
f7e909ea | 2655 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2656 | #endif |
f7e909ea | 2657 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2658 | }; |
2659 | ||
1da177e4 LT |
2660 | static inline void init_IO_APIC_traps(void) |
2661 | { | |
da51a821 | 2662 | struct irq_cfg *cfg; |
ad9f4334 | 2663 | unsigned int irq; |
1da177e4 LT |
2664 | |
2665 | /* | |
2666 | * NOTE! The local APIC isn't very good at handling | |
2667 | * multiple interrupts at the same interrupt level. | |
2668 | * As the interrupt level is determined by taking the | |
2669 | * vector number and shifting that right by 4, we | |
2670 | * want to spread these out a bit so that they don't | |
2671 | * all fall in the same interrupt level. | |
2672 | * | |
2673 | * Also, we've got to be careful not to trash gate | |
2674 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2675 | */ | |
ad9f4334 | 2676 | for_each_active_irq(irq) { |
2c778651 | 2677 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2678 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2679 | /* |
2680 | * Hmm.. We don't have an entry for this, | |
2681 | * so default to an old-fashioned 8259 | |
2682 | * interrupt if we can.. | |
2683 | */ | |
b81bb373 JP |
2684 | if (irq < legacy_pic->nr_legacy_irqs) |
2685 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2686 | else |
1da177e4 | 2687 | /* Strange. Oh, well.. */ |
2c778651 | 2688 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2689 | } |
2690 | } | |
2691 | } | |
2692 | ||
f5b9ed7a IM |
2693 | /* |
2694 | * The local APIC irq-chip implementation: | |
2695 | */ | |
1da177e4 | 2696 | |
90297c5f | 2697 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2698 | { |
2699 | unsigned long v; | |
2700 | ||
2701 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2702 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2703 | } |
2704 | ||
90297c5f | 2705 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2706 | { |
f5b9ed7a | 2707 | unsigned long v; |
1da177e4 | 2708 | |
f5b9ed7a | 2709 | v = apic_read(APIC_LVT0); |
593f4a78 | 2710 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2711 | } |
1da177e4 | 2712 | |
90297c5f | 2713 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2714 | { |
2715 | ack_APIC_irq(); | |
2716 | } | |
2717 | ||
f5b9ed7a | 2718 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2719 | .name = "local-APIC", |
90297c5f TG |
2720 | .irq_mask = mask_lapic_irq, |
2721 | .irq_unmask = unmask_lapic_irq, | |
2722 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2723 | }; |
2724 | ||
60c69948 | 2725 | static void lapic_register_intr(int irq) |
c88ac1df | 2726 | { |
60c69948 | 2727 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2728 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2729 | "edge"); |
c88ac1df MR |
2730 | } |
2731 | ||
1da177e4 LT |
2732 | /* |
2733 | * This looks a bit hackish but it's about the only one way of sending | |
2734 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2735 | * not support the ExtINT mode, unfortunately. We need to send these | |
2736 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2737 | * 8259A interrupt line asserted until INTA. --macro | |
2738 | */ | |
28acf285 | 2739 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2740 | { |
fcfd636a | 2741 | int apic, pin, i; |
1da177e4 LT |
2742 | struct IO_APIC_route_entry entry0, entry1; |
2743 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2744 | |
fcfd636a | 2745 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2746 | if (pin == -1) { |
2747 | WARN_ON_ONCE(1); | |
2748 | return; | |
2749 | } | |
fcfd636a | 2750 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2751 | if (apic == -1) { |
2752 | WARN_ON_ONCE(1); | |
1da177e4 | 2753 | return; |
956fb531 | 2754 | } |
1da177e4 | 2755 | |
cf4c6a2f | 2756 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2757 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2758 | |
2759 | memset(&entry1, 0, sizeof(entry1)); | |
2760 | ||
2761 | entry1.dest_mode = 0; /* physical delivery */ | |
2762 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2763 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2764 | entry1.delivery_mode = dest_ExtINT; |
2765 | entry1.polarity = entry0.polarity; | |
2766 | entry1.trigger = 0; | |
2767 | entry1.vector = 0; | |
2768 | ||
cf4c6a2f | 2769 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2770 | |
2771 | save_control = CMOS_READ(RTC_CONTROL); | |
2772 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2773 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2774 | RTC_FREQ_SELECT); | |
2775 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2776 | ||
2777 | i = 100; | |
2778 | while (i-- > 0) { | |
2779 | mdelay(10); | |
2780 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2781 | i -= 10; | |
2782 | } | |
2783 | ||
2784 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2785 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2786 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2787 | |
cf4c6a2f | 2788 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2789 | } |
2790 | ||
efa2559f | 2791 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2792 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2793 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2794 | { |
2795 | disable_timer_pin_1 = 1; | |
2796 | return 0; | |
2797 | } | |
54168ed7 | 2798 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2799 | |
2800 | int timer_through_8259 __initdata; | |
2801 | ||
1da177e4 LT |
2802 | /* |
2803 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2804 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2805 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2806 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2807 | * |
2808 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2809 | */ |
8542b200 | 2810 | static inline void __init check_timer(void) |
1da177e4 | 2811 | { |
2c778651 | 2812 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2813 | int node = cpu_to_node(0); |
fcfd636a | 2814 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2815 | unsigned long flags; |
047c8fdb | 2816 | int no_pin1 = 0; |
4aae0702 IM |
2817 | |
2818 | local_irq_save(flags); | |
d4d25dec | 2819 | |
1da177e4 LT |
2820 | /* |
2821 | * get/set the timer IRQ vector: | |
2822 | */ | |
4305df94 | 2823 | legacy_pic->mask(0); |
fe402e1f | 2824 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2825 | |
2826 | /* | |
d11d5794 MR |
2827 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2828 | * wire has to be disabled in the local APIC. Also | |
2829 | * timer interrupts need to be acknowledged manually in | |
2830 | * the 8259A for the i82489DX when using the NMI | |
2831 | * watchdog as that APIC treats NMIs as level-triggered. | |
2832 | * The AEOI mode will finish them in the 8259A | |
2833 | * automatically. | |
1da177e4 | 2834 | */ |
593f4a78 | 2835 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2836 | legacy_pic->init(1); |
1da177e4 | 2837 | |
fcfd636a EB |
2838 | pin1 = find_isa_irq_pin(0, mp_INT); |
2839 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2840 | pin2 = ioapic_i8259.pin; | |
2841 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2842 | |
49a66a0b MR |
2843 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2844 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2845 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2846 | |
691874fa MR |
2847 | /* |
2848 | * Some BIOS writers are clueless and report the ExtINTA | |
2849 | * I/O APIC input from the cascaded 8259A as the timer | |
2850 | * interrupt input. So just in case, if only one pin | |
2851 | * was found above, try it both directly and through the | |
2852 | * 8259A. | |
2853 | */ | |
2854 | if (pin1 == -1) { | |
54168ed7 IM |
2855 | if (intr_remapping_enabled) |
2856 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2857 | pin1 = pin2; |
2858 | apic1 = apic2; | |
2859 | no_pin1 = 1; | |
2860 | } else if (pin2 == -1) { | |
2861 | pin2 = pin1; | |
2862 | apic2 = apic1; | |
2863 | } | |
2864 | ||
1da177e4 LT |
2865 | if (pin1 != -1) { |
2866 | /* | |
2867 | * Ok, does IRQ0 through the IOAPIC work? | |
2868 | */ | |
691874fa | 2869 | if (no_pin1) { |
85ac16d0 | 2870 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2871 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2872 | } else { |
60c69948 | 2873 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2874 | * leave it unmasked. |
2875 | * so only need to unmask if it is level-trigger | |
2876 | * do we really have level trigger timer? | |
2877 | */ | |
2878 | int idx; | |
2879 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2880 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2881 | unmask_ioapic(cfg); |
691874fa | 2882 | } |
1da177e4 | 2883 | if (timer_irq_works()) { |
66759a01 CE |
2884 | if (disable_timer_pin_1 > 0) |
2885 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2886 | goto out; |
1da177e4 | 2887 | } |
54168ed7 IM |
2888 | if (intr_remapping_enabled) |
2889 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2890 | local_irq_disable(); |
fcfd636a | 2891 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2892 | if (!no_pin1) |
49a66a0b MR |
2893 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2894 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2895 | |
49a66a0b MR |
2896 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2897 | "(IRQ0) through the 8259A ...\n"); | |
2898 | apic_printk(APIC_QUIET, KERN_INFO | |
2899 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2900 | /* |
2901 | * legacy devices should be connected to IO APIC #0 | |
2902 | */ | |
85ac16d0 | 2903 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2904 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2905 | legacy_pic->unmask(0); |
1da177e4 | 2906 | if (timer_irq_works()) { |
49a66a0b | 2907 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2908 | timer_through_8259 = 1; |
4aae0702 | 2909 | goto out; |
1da177e4 LT |
2910 | } |
2911 | /* | |
2912 | * Cleanup, just in case ... | |
2913 | */ | |
f72dccac | 2914 | local_irq_disable(); |
4305df94 | 2915 | legacy_pic->mask(0); |
fcfd636a | 2916 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2917 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2918 | } |
1da177e4 | 2919 | |
49a66a0b MR |
2920 | apic_printk(APIC_QUIET, KERN_INFO |
2921 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2922 | |
60c69948 | 2923 | lapic_register_intr(0); |
497c9a19 | 2924 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2925 | legacy_pic->unmask(0); |
1da177e4 LT |
2926 | |
2927 | if (timer_irq_works()) { | |
49a66a0b | 2928 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2929 | goto out; |
1da177e4 | 2930 | } |
f72dccac | 2931 | local_irq_disable(); |
4305df94 | 2932 | legacy_pic->mask(0); |
497c9a19 | 2933 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2934 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2935 | |
49a66a0b MR |
2936 | apic_printk(APIC_QUIET, KERN_INFO |
2937 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2938 | |
b81bb373 JP |
2939 | legacy_pic->init(0); |
2940 | legacy_pic->make_irq(0); | |
593f4a78 | 2941 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2942 | |
2943 | unlock_ExtINT_logic(); | |
2944 | ||
2945 | if (timer_irq_works()) { | |
49a66a0b | 2946 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2947 | goto out; |
1da177e4 | 2948 | } |
f72dccac | 2949 | local_irq_disable(); |
49a66a0b | 2950 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
fb209bd8 YL |
2951 | if (x2apic_preenabled) |
2952 | apic_printk(APIC_QUIET, KERN_INFO | |
2953 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2954 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2955 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2956 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2957 | out: |
2958 | local_irq_restore(flags); | |
1da177e4 LT |
2959 | } |
2960 | ||
2961 | /* | |
af174783 MR |
2962 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2963 | * to devices. However there may be an I/O APIC pin available for | |
2964 | * this interrupt regardless. The pin may be left unconnected, but | |
2965 | * typically it will be reused as an ExtINT cascade interrupt for | |
2966 | * the master 8259A. In the MPS case such a pin will normally be | |
2967 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2968 | * there is no provision for ExtINT interrupts, and in the absence | |
2969 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2970 | * interrupt, that is edge-triggered and unmasked by default. We | |
2971 | * used to do this, but it caused problems on some systems because | |
2972 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2973 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2974 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2975 | * the I/O APIC in all cases now. No actual device should request | |
2976 | * it anyway. --macro | |
1da177e4 | 2977 | */ |
bc07844a | 2978 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2979 | |
2980 | void __init setup_IO_APIC(void) | |
2981 | { | |
54168ed7 | 2982 | |
54168ed7 IM |
2983 | /* |
2984 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2985 | */ | |
b81bb373 | 2986 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2987 | |
54168ed7 | 2988 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2989 | /* |
54168ed7 IM |
2990 | * Set up IO-APIC IRQ routing. |
2991 | */ | |
de934103 TG |
2992 | x86_init.mpparse.setup_ioapic_ids(); |
2993 | ||
1da177e4 LT |
2994 | sync_Arb_IDs(); |
2995 | setup_IO_APIC_irqs(); | |
2996 | init_IO_APIC_traps(); | |
b81bb373 | 2997 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2998 | check_timer(); |
1da177e4 LT |
2999 | } |
3000 | ||
3001 | /* | |
0d2eb44f | 3002 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 3003 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 3004 | */ |
36062448 | 3005 | |
1da177e4 LT |
3006 | static int __init io_apic_bug_finalize(void) |
3007 | { | |
d6c88a50 TG |
3008 | if (sis_apic_bug == -1) |
3009 | sis_apic_bug = 0; | |
3010 | return 0; | |
1da177e4 LT |
3011 | } |
3012 | ||
3013 | late_initcall(io_apic_bug_finalize); | |
3014 | ||
6f50d45f | 3015 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 3016 | { |
1da177e4 LT |
3017 | unsigned long flags; |
3018 | union IO_APIC_reg_00 reg_00; | |
36062448 | 3019 | |
dade7716 | 3020 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
3021 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
3022 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
3023 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
3024 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 3025 | } |
dade7716 | 3026 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 3027 | } |
1da177e4 | 3028 | |
f3c6ea1b RW |
3029 | static void ioapic_resume(void) |
3030 | { | |
6f50d45f | 3031 | int ioapic_idx; |
f3c6ea1b | 3032 | |
6f50d45f YL |
3033 | for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--) |
3034 | resume_ioapic_id(ioapic_idx); | |
15bac20b SS |
3035 | |
3036 | restore_ioapic_entries(); | |
1da177e4 LT |
3037 | } |
3038 | ||
f3c6ea1b | 3039 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 3040 | .suspend = save_ioapic_entries, |
1da177e4 LT |
3041 | .resume = ioapic_resume, |
3042 | }; | |
3043 | ||
f3c6ea1b | 3044 | static int __init ioapic_init_ops(void) |
1da177e4 | 3045 | { |
f3c6ea1b RW |
3046 | register_syscore_ops(&ioapic_syscore_ops); |
3047 | ||
1da177e4 LT |
3048 | return 0; |
3049 | } | |
3050 | ||
f3c6ea1b | 3051 | device_initcall(ioapic_init_ops); |
1da177e4 | 3052 | |
3fc471ed | 3053 | /* |
95d77884 | 3054 | * Dynamic irq allocate and deallocation |
3fc471ed | 3055 | */ |
fbc6bff0 | 3056 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 3057 | { |
fbc6bff0 | 3058 | struct irq_cfg *cfg; |
3fc471ed | 3059 | unsigned long flags; |
fbc6bff0 TG |
3060 | unsigned int ret = 0; |
3061 | int irq; | |
d047f53a | 3062 | |
fbc6bff0 TG |
3063 | if (from < nr_irqs_gsi) |
3064 | from = nr_irqs_gsi; | |
d047f53a | 3065 | |
fbc6bff0 TG |
3066 | irq = alloc_irq_from(from, node); |
3067 | if (irq < 0) | |
3068 | return 0; | |
3069 | cfg = alloc_irq_cfg(irq, node); | |
3070 | if (!cfg) { | |
3071 | free_irq_at(irq, NULL); | |
3072 | return 0; | |
ace80ab7 | 3073 | } |
3fc471ed | 3074 | |
fbc6bff0 TG |
3075 | raw_spin_lock_irqsave(&vector_lock, flags); |
3076 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
3077 | ret = irq; | |
3078 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3079 | |
fbc6bff0 | 3080 | if (ret) { |
2c778651 | 3081 | irq_set_chip_data(irq, cfg); |
fbc6bff0 TG |
3082 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
3083 | } else { | |
3084 | free_irq_at(irq, cfg); | |
3085 | } | |
3086 | return ret; | |
3fc471ed EB |
3087 | } |
3088 | ||
199751d7 YL |
3089 | int create_irq(void) |
3090 | { | |
f6e9456c | 3091 | int node = cpu_to_node(0); |
be5d5350 | 3092 | unsigned int irq_want; |
54168ed7 IM |
3093 | int irq; |
3094 | ||
be5d5350 | 3095 | irq_want = nr_irqs_gsi; |
d047f53a | 3096 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3097 | |
3098 | if (irq == 0) | |
3099 | irq = -1; | |
3100 | ||
3101 | return irq; | |
199751d7 YL |
3102 | } |
3103 | ||
3fc471ed EB |
3104 | void destroy_irq(unsigned int irq) |
3105 | { | |
2c778651 | 3106 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 3107 | unsigned long flags; |
3fc471ed | 3108 | |
fbc6bff0 | 3109 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3110 | |
7b79462a | 3111 | if (irq_remapped(cfg)) |
9717967c | 3112 | free_irte(irq); |
dade7716 | 3113 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3114 | __clear_irq_vector(irq, cfg); |
dade7716 | 3115 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3116 | free_irq_at(irq, cfg); |
3fc471ed | 3117 | } |
3fc471ed | 3118 | |
2d3fcc1c | 3119 | /* |
27b46d76 | 3120 | * MSI message composition |
2d3fcc1c EB |
3121 | */ |
3122 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3123 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3124 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3125 | { |
497c9a19 YL |
3126 | struct irq_cfg *cfg; |
3127 | int err; | |
2d3fcc1c EB |
3128 | unsigned dest; |
3129 | ||
f1182638 JB |
3130 | if (disable_apic) |
3131 | return -ENXIO; | |
3132 | ||
3145e941 | 3133 | cfg = irq_cfg(irq); |
fe402e1f | 3134 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3135 | if (err) |
3136 | return err; | |
2d3fcc1c | 3137 | |
debccb3e | 3138 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3139 | |
1a0e62a4 | 3140 | if (irq_remapped(cfg)) { |
54168ed7 IM |
3141 | struct irte irte; |
3142 | int ir_index; | |
3143 | u16 sub_handle; | |
3144 | ||
3145 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3146 | BUG_ON(ir_index == -1); | |
3147 | ||
62a92f4c | 3148 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3149 | |
f007e99c | 3150 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3151 | if (pdev) |
3152 | set_msi_sid(&irte, pdev); | |
3153 | else | |
3154 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3155 | |
54168ed7 IM |
3156 | modify_irte(irq, &irte); |
3157 | ||
3158 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3159 | msg->data = sub_handle; | |
3160 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3161 | MSI_ADDR_IR_SHV | | |
3162 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3163 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3164 | } else { |
9d783ba0 SS |
3165 | if (x2apic_enabled()) |
3166 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3167 | MSI_ADDR_EXT_DEST_ID(dest); | |
3168 | else | |
3169 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3170 | ||
54168ed7 IM |
3171 | msg->address_lo = |
3172 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3173 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3174 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3175 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3176 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3177 | MSI_ADDR_REDIRECTION_CPU: |
3178 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3179 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3180 | |
54168ed7 IM |
3181 | msg->data = |
3182 | MSI_DATA_TRIGGER_EDGE | | |
3183 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3184 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3185 | MSI_DATA_DELIVERY_FIXED: |
3186 | MSI_DATA_DELIVERY_LOWPRI) | | |
3187 | MSI_DATA_VECTOR(cfg->vector); | |
3188 | } | |
497c9a19 | 3189 | return err; |
2d3fcc1c EB |
3190 | } |
3191 | ||
3b7d1921 | 3192 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3193 | static int |
3194 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3195 | { |
5346b2a7 | 3196 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3197 | struct msi_msg msg; |
3198 | unsigned int dest; | |
3b7d1921 | 3199 | |
5346b2a7 | 3200 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3201 | return -1; |
2d3fcc1c | 3202 | |
5346b2a7 | 3203 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3204 | |
3205 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3206 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3207 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3208 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3209 | ||
5346b2a7 | 3210 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3211 | |
3212 | return 0; | |
2d3fcc1c | 3213 | } |
3b7d1921 | 3214 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3215 | |
3b7d1921 EB |
3216 | /* |
3217 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3218 | * which implement the MSI or MSI-X Capability Structure. | |
3219 | */ | |
3220 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3221 | .name = "PCI-MSI", |
3222 | .irq_unmask = unmask_msi_irq, | |
3223 | .irq_mask = mask_msi_irq, | |
3224 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3225 | #ifdef CONFIG_SMP |
5346b2a7 | 3226 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3227 | #endif |
5346b2a7 | 3228 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3229 | }; |
3230 | ||
54168ed7 IM |
3231 | /* |
3232 | * Map the PCI dev to the corresponding remapping hardware unit | |
3233 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3234 | * in it. | |
3235 | */ | |
3236 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3237 | { | |
3238 | struct intel_iommu *iommu; | |
3239 | int index; | |
3240 | ||
3241 | iommu = map_dev_to_ir(dev); | |
3242 | if (!iommu) { | |
3243 | printk(KERN_ERR | |
3244 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3245 | return -ENOENT; | |
3246 | } | |
3247 | ||
3248 | index = alloc_irte(iommu, irq, nvec); | |
3249 | if (index < 0) { | |
3250 | printk(KERN_ERR | |
3251 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3252 | pci_name(dev)); |
54168ed7 IM |
3253 | return -ENOSPC; |
3254 | } | |
3255 | return index; | |
3256 | } | |
1d025192 | 3257 | |
3145e941 | 3258 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3259 | { |
c60eaf25 | 3260 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3261 | struct msi_msg msg; |
60c69948 | 3262 | int ret; |
1d025192 | 3263 | |
c8bc6f3c | 3264 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3265 | if (ret < 0) |
3266 | return ret; | |
3267 | ||
2c778651 | 3268 | irq_set_msi_desc(irq, msidesc); |
1d025192 YL |
3269 | write_msi_msg(irq, &msg); |
3270 | ||
2c778651 | 3271 | if (irq_remapped(irq_get_chip_data(irq))) { |
60c69948 | 3272 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c39d77ff | 3273 | irq_remap_modify_chip_defaults(chip); |
c60eaf25 TG |
3274 | } |
3275 | ||
3276 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3277 | |
c81bba49 YL |
3278 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3279 | ||
1d025192 YL |
3280 | return 0; |
3281 | } | |
3282 | ||
294ee6f8 | 3283 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3284 | { |
60c69948 TG |
3285 | int node, ret, sub_handle, index = 0; |
3286 | unsigned int irq, irq_want; | |
0b8f1efa | 3287 | struct msi_desc *msidesc; |
1cc18521 | 3288 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3289 | |
1c8d7b0a MW |
3290 | /* x86 doesn't support multiple MSI yet */ |
3291 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3292 | return 1; | |
3293 | ||
d047f53a | 3294 | node = dev_to_node(&dev->dev); |
be5d5350 | 3295 | irq_want = nr_irqs_gsi; |
54168ed7 | 3296 | sub_handle = 0; |
0b8f1efa | 3297 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3298 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3299 | if (irq == 0) |
3300 | return -1; | |
f1ee5548 | 3301 | irq_want = irq + 1; |
54168ed7 IM |
3302 | if (!intr_remapping_enabled) |
3303 | goto no_ir; | |
3304 | ||
3305 | if (!sub_handle) { | |
3306 | /* | |
3307 | * allocate the consecutive block of IRTE's | |
3308 | * for 'nvec' | |
3309 | */ | |
3310 | index = msi_alloc_irte(dev, irq, nvec); | |
3311 | if (index < 0) { | |
3312 | ret = index; | |
3313 | goto error; | |
3314 | } | |
3315 | } else { | |
3316 | iommu = map_dev_to_ir(dev); | |
3317 | if (!iommu) { | |
3318 | ret = -ENOENT; | |
3319 | goto error; | |
3320 | } | |
3321 | /* | |
3322 | * setup the mapping between the irq and the IRTE | |
3323 | * base index, the sub_handle pointing to the | |
3324 | * appropriate interrupt remap table entry. | |
3325 | */ | |
3326 | set_irte_irq(irq, iommu, index, sub_handle); | |
3327 | } | |
3328 | no_ir: | |
0b8f1efa | 3329 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3330 | if (ret < 0) |
3331 | goto error; | |
3332 | sub_handle++; | |
3333 | } | |
3334 | return 0; | |
047c8fdb YL |
3335 | |
3336 | error: | |
54168ed7 IM |
3337 | destroy_irq(irq); |
3338 | return ret; | |
047c8fdb YL |
3339 | } |
3340 | ||
294ee6f8 | 3341 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3342 | { |
f7feaca7 | 3343 | destroy_irq(irq); |
3b7d1921 EB |
3344 | } |
3345 | ||
d3f13810 | 3346 | #ifdef CONFIG_DMAR_TABLE |
54168ed7 | 3347 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3348 | static int |
3349 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3350 | bool force) | |
54168ed7 | 3351 | { |
fe52b2d2 TG |
3352 | struct irq_cfg *cfg = data->chip_data; |
3353 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3354 | struct msi_msg msg; |
54168ed7 | 3355 | |
fe52b2d2 | 3356 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3357 | return -1; |
54168ed7 | 3358 | |
54168ed7 IM |
3359 | dmar_msi_read(irq, &msg); |
3360 | ||
3361 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3362 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3363 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3364 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3365 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3366 | |
3367 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3368 | |
3369 | return 0; | |
54168ed7 | 3370 | } |
3145e941 | 3371 | |
54168ed7 IM |
3372 | #endif /* CONFIG_SMP */ |
3373 | ||
8f7007aa | 3374 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3375 | .name = "DMAR_MSI", |
3376 | .irq_unmask = dmar_msi_unmask, | |
3377 | .irq_mask = dmar_msi_mask, | |
3378 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3379 | #ifdef CONFIG_SMP |
fe52b2d2 | 3380 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3381 | #endif |
fe52b2d2 | 3382 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3383 | }; |
3384 | ||
3385 | int arch_setup_dmar_msi(unsigned int irq) | |
3386 | { | |
3387 | int ret; | |
3388 | struct msi_msg msg; | |
2d3fcc1c | 3389 | |
c8bc6f3c | 3390 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3391 | if (ret < 0) |
3392 | return ret; | |
3393 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3394 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3395 | "edge"); | |
54168ed7 IM |
3396 | return 0; |
3397 | } | |
3398 | #endif | |
3399 | ||
58ac1e76 | 3400 | #ifdef CONFIG_HPET_TIMER |
3401 | ||
3402 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3403 | static int hpet_msi_set_affinity(struct irq_data *data, |
3404 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3405 | { |
d0fbca8f | 3406 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3407 | struct msi_msg msg; |
3408 | unsigned int dest; | |
58ac1e76 | 3409 | |
0e09ddf2 | 3410 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3411 | return -1; |
58ac1e76 | 3412 | |
d0fbca8f | 3413 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3414 | |
3415 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3416 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3417 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3418 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3419 | ||
d0fbca8f | 3420 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3421 | |
3422 | return 0; | |
58ac1e76 | 3423 | } |
3145e941 | 3424 | |
58ac1e76 | 3425 | #endif /* CONFIG_SMP */ |
3426 | ||
1cc18521 | 3427 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3428 | .name = "HPET_MSI", |
d0fbca8f TG |
3429 | .irq_unmask = hpet_msi_unmask, |
3430 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3431 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3432 | #ifdef CONFIG_SMP |
d0fbca8f | 3433 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3434 | #endif |
90297c5f | 3435 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3436 | }; |
3437 | ||
c8bc6f3c | 3438 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3439 | { |
c60eaf25 | 3440 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3441 | struct msi_msg msg; |
d0fbca8f | 3442 | int ret; |
58ac1e76 | 3443 | |
c8bc6f3c SS |
3444 | if (intr_remapping_enabled) { |
3445 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3446 | int index; | |
3447 | ||
3448 | if (!iommu) | |
3449 | return -1; | |
3450 | ||
3451 | index = alloc_irte(iommu, irq, 1); | |
3452 | if (index < 0) | |
3453 | return -1; | |
3454 | } | |
3455 | ||
3456 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3457 | if (ret < 0) |
3458 | return ret; | |
3459 | ||
2c778651 | 3460 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3461 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2c778651 | 3462 | if (irq_remapped(irq_get_chip_data(irq))) |
c39d77ff | 3463 | irq_remap_modify_chip_defaults(chip); |
c81bba49 | 3464 | |
c60eaf25 | 3465 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3466 | return 0; |
3467 | } | |
3468 | #endif | |
3469 | ||
54168ed7 | 3470 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3471 | /* |
3472 | * Hypertransport interrupt support | |
3473 | */ | |
3474 | #ifdef CONFIG_HT_IRQ | |
3475 | ||
3476 | #ifdef CONFIG_SMP | |
3477 | ||
497c9a19 | 3478 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3479 | { |
ec68307c EB |
3480 | struct ht_irq_msg msg; |
3481 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3482 | |
497c9a19 | 3483 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3484 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3485 | |
497c9a19 | 3486 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3487 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3488 | |
ec68307c | 3489 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3490 | } |
3491 | ||
be5b7bf7 TG |
3492 | static int |
3493 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3494 | { |
be5b7bf7 | 3495 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3496 | unsigned int dest; |
8b955b0d | 3497 | |
be5b7bf7 | 3498 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3499 | return -1; |
8b955b0d | 3500 | |
be5b7bf7 | 3501 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3502 | return 0; |
8b955b0d | 3503 | } |
3145e941 | 3504 | |
8b955b0d EB |
3505 | #endif |
3506 | ||
c37e108d | 3507 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3508 | .name = "PCI-HT", |
3509 | .irq_mask = mask_ht_irq, | |
3510 | .irq_unmask = unmask_ht_irq, | |
3511 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3512 | #ifdef CONFIG_SMP |
be5b7bf7 | 3513 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3514 | #endif |
be5b7bf7 | 3515 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3516 | }; |
3517 | ||
3518 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3519 | { | |
497c9a19 YL |
3520 | struct irq_cfg *cfg; |
3521 | int err; | |
8b955b0d | 3522 | |
f1182638 JB |
3523 | if (disable_apic) |
3524 | return -ENXIO; | |
3525 | ||
3145e941 | 3526 | cfg = irq_cfg(irq); |
fe402e1f | 3527 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3528 | if (!err) { |
ec68307c | 3529 | struct ht_irq_msg msg; |
8b955b0d | 3530 | unsigned dest; |
8b955b0d | 3531 | |
debccb3e IM |
3532 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3533 | apic->target_cpus()); | |
8b955b0d | 3534 | |
ec68307c | 3535 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3536 | |
ec68307c EB |
3537 | msg.address_lo = |
3538 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3539 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3540 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3541 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3542 | HT_IRQ_LOW_DM_PHYSICAL : |
3543 | HT_IRQ_LOW_DM_LOGICAL) | | |
3544 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3545 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3546 | HT_IRQ_LOW_MT_FIXED : |
3547 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3548 | HT_IRQ_LOW_IRQ_MASKED; | |
3549 | ||
ec68307c | 3550 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3551 | |
2c778651 | 3552 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
a460e745 | 3553 | handle_edge_irq, "edge"); |
c81bba49 YL |
3554 | |
3555 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3556 | } |
497c9a19 | 3557 | return err; |
8b955b0d EB |
3558 | } |
3559 | #endif /* CONFIG_HT_IRQ */ | |
3560 | ||
20443598 | 3561 | static int |
ff973d04 TG |
3562 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3563 | { | |
3564 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3565 | int ret; | |
3566 | ||
3567 | if (!cfg) | |
3568 | return -EINVAL; | |
3569 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3570 | if (!ret) | |
e4aff811 | 3571 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
3572 | return ret; |
3573 | } | |
3574 | ||
20443598 SAS |
3575 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3576 | struct io_apic_irq_attr *attr) | |
710dcda6 | 3577 | { |
6f50d45f | 3578 | unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; |
710dcda6 TG |
3579 | int ret; |
3580 | ||
3581 | /* Avoid redundant programming */ | |
6f50d45f | 3582 | if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { |
710dcda6 | 3583 | pr_debug("Pin %d-%d already programmed\n", |
6f50d45f | 3584 | mpc_ioapic_id(ioapic_idx), pin); |
710dcda6 TG |
3585 | return 0; |
3586 | } | |
3587 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3588 | if (!ret) | |
6f50d45f | 3589 | set_bit(pin, ioapics[ioapic_idx].pin_programmed); |
710dcda6 TG |
3590 | return ret; |
3591 | } | |
3592 | ||
41098ffe | 3593 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3594 | { |
3595 | union IO_APIC_reg_01 reg_01; | |
3596 | unsigned long flags; | |
3597 | ||
dade7716 | 3598 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3599 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3600 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3601 | |
4b6b19a1 EB |
3602 | /* The register returns the maximum index redir index |
3603 | * supported, which is one less than the total number of redir | |
3604 | * entries. | |
3605 | */ | |
3606 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3607 | } |
3608 | ||
23f9b267 | 3609 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3610 | { |
4afc51a8 | 3611 | int nr; |
be5d5350 | 3612 | |
a4384df3 | 3613 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3614 | if (nr > nr_irqs_gsi) |
be5d5350 | 3615 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3616 | |
3617 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3618 | } |
3619 | ||
7b586d71 JF |
3620 | int get_nr_irqs_gsi(void) |
3621 | { | |
3622 | return nr_irqs_gsi; | |
3623 | } | |
3624 | ||
4a046d17 YL |
3625 | int __init arch_probe_nr_irqs(void) |
3626 | { | |
3627 | int nr; | |
3628 | ||
f1ee5548 YL |
3629 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3630 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3631 | |
f1ee5548 YL |
3632 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3633 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3634 | /* | |
3635 | * for MSI and HT dyn irq | |
3636 | */ | |
3637 | nr += nr_irqs_gsi * 16; | |
3638 | #endif | |
3639 | if (nr < nr_irqs) | |
4a046d17 YL |
3640 | nr_irqs = nr; |
3641 | ||
b683de2b | 3642 | return NR_IRQS_LEGACY; |
4a046d17 | 3643 | } |
4a046d17 | 3644 | |
710dcda6 TG |
3645 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3646 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3647 | { |
5ef21837 YL |
3648 | int node; |
3649 | ||
3650 | if (!IO_APIC_IRQ(irq)) { | |
3651 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3652 | irq_attr->ioapic); |
5ef21837 YL |
3653 | return -EINVAL; |
3654 | } | |
3655 | ||
e0799c04 | 3656 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3657 | |
710dcda6 | 3658 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3659 | } |
3660 | ||
54168ed7 | 3661 | #ifdef CONFIG_X86_32 |
41098ffe | 3662 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3663 | { |
3664 | union IO_APIC_reg_00 reg_00; | |
3665 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3666 | physid_mask_t tmp; | |
3667 | unsigned long flags; | |
3668 | int i = 0; | |
3669 | ||
3670 | /* | |
36062448 PC |
3671 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3672 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3673 | * supports up to 16 on one shared APIC bus. |
36062448 | 3674 | * |
1da177e4 LT |
3675 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3676 | * advantage of new APIC bus architecture. | |
3677 | */ | |
3678 | ||
3679 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3680 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3681 | |
dade7716 | 3682 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3683 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3684 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3685 | |
3686 | if (apic_id >= get_physical_broadcast()) { | |
3687 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3688 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3689 | apic_id = reg_00.bits.ID; | |
3690 | } | |
3691 | ||
3692 | /* | |
36062448 | 3693 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3694 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3695 | */ | |
7abc0753 | 3696 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3697 | |
3698 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3699 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3700 | break; |
3701 | } | |
3702 | ||
3703 | if (i == get_physical_broadcast()) | |
3704 | panic("Max apic_id exceeded!\n"); | |
3705 | ||
3706 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3707 | "trying %d\n", ioapic, apic_id, i); | |
3708 | ||
3709 | apic_id = i; | |
36062448 | 3710 | } |
1da177e4 | 3711 | |
7abc0753 | 3712 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3713 | physids_or(apic_id_map, apic_id_map, tmp); |
3714 | ||
3715 | if (reg_00.bits.ID != apic_id) { | |
3716 | reg_00.bits.ID = apic_id; | |
3717 | ||
dade7716 | 3718 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3719 | io_apic_write(ioapic, 0, reg_00.raw); |
3720 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3721 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3722 | |
3723 | /* Sanity check */ | |
6070f9ec AD |
3724 | if (reg_00.bits.ID != apic_id) { |
3725 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3726 | return -1; | |
3727 | } | |
1da177e4 LT |
3728 | } |
3729 | ||
3730 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3731 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3732 | ||
3733 | return apic_id; | |
3734 | } | |
41098ffe TG |
3735 | |
3736 | static u8 __init io_apic_unique_id(u8 id) | |
3737 | { | |
3738 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3739 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3740 | return io_apic_get_unique_id(nr_ioapics, id); | |
3741 | else | |
3742 | return id; | |
3743 | } | |
3744 | #else | |
3745 | static u8 __init io_apic_unique_id(u8 id) | |
3746 | { | |
3747 | int i; | |
3748 | DECLARE_BITMAP(used, 256); | |
3749 | ||
3750 | bitmap_zero(used, 256); | |
3751 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 3752 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3753 | } |
3754 | if (!test_bit(id, used)) | |
3755 | return id; | |
3756 | return find_first_zero_bit(used, 256); | |
3757 | } | |
58f892e0 | 3758 | #endif |
1da177e4 | 3759 | |
41098ffe | 3760 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3761 | { |
3762 | union IO_APIC_reg_01 reg_01; | |
3763 | unsigned long flags; | |
3764 | ||
dade7716 | 3765 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3766 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3767 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3768 | |
3769 | return reg_01.bits.version; | |
3770 | } | |
3771 | ||
9a0a91bb | 3772 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3773 | { |
9a0a91bb | 3774 | int ioapic, pin, idx; |
61fd47e0 SL |
3775 | |
3776 | if (skip_ioapic_setup) | |
3777 | return -1; | |
3778 | ||
9a0a91bb EB |
3779 | ioapic = mp_find_ioapic(gsi); |
3780 | if (ioapic < 0) | |
61fd47e0 SL |
3781 | return -1; |
3782 | ||
9a0a91bb EB |
3783 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3784 | if (pin < 0) | |
3785 | return -1; | |
3786 | ||
3787 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3788 | if (idx < 0) | |
61fd47e0 SL |
3789 | return -1; |
3790 | ||
9a0a91bb EB |
3791 | *trigger = irq_trigger(idx); |
3792 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3793 | return 0; |
3794 | } | |
3795 | ||
497c9a19 YL |
3796 | /* |
3797 | * This function currently is only a helper for the i386 smp boot process where | |
3798 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3799 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3800 | */ |
3801 | #ifdef CONFIG_SMP | |
3802 | void __init setup_ioapic_dest(void) | |
3803 | { | |
fad53995 | 3804 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3805 | const struct cpumask *mask; |
5451ddc5 | 3806 | struct irq_data *idata; |
497c9a19 YL |
3807 | |
3808 | if (skip_ioapic_setup == 1) | |
3809 | return; | |
3810 | ||
fad53995 | 3811 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b69c6c3b | 3812 | for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { |
b9c61b70 YL |
3813 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3814 | if (irq_entry == -1) | |
3815 | continue; | |
3816 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3817 | |
fad53995 EB |
3818 | if ((ioapic > 0) && (irq > 16)) |
3819 | continue; | |
3820 | ||
5451ddc5 | 3821 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3822 | |
b9c61b70 YL |
3823 | /* |
3824 | * Honour affinities which have been set in early boot | |
3825 | */ | |
5451ddc5 TG |
3826 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3827 | mask = idata->affinity; | |
b9c61b70 YL |
3828 | else |
3829 | mask = apic->target_cpus(); | |
497c9a19 | 3830 | |
b9c61b70 | 3831 | if (intr_remapping_enabled) |
5451ddc5 | 3832 | ir_ioapic_set_affinity(idata, mask, false); |
b9c61b70 | 3833 | else |
5451ddc5 | 3834 | ioapic_set_affinity(idata, mask, false); |
497c9a19 | 3835 | } |
b9c61b70 | 3836 | |
497c9a19 YL |
3837 | } |
3838 | #endif | |
3839 | ||
54168ed7 IM |
3840 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3841 | ||
3842 | static struct resource *ioapic_resources; | |
3843 | ||
ffc43836 | 3844 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3845 | { |
3846 | unsigned long n; | |
3847 | struct resource *res; | |
3848 | char *mem; | |
3849 | int i; | |
3850 | ||
3851 | if (nr_ioapics <= 0) | |
3852 | return NULL; | |
3853 | ||
3854 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3855 | n *= nr_ioapics; | |
3856 | ||
3857 | mem = alloc_bootmem(n); | |
3858 | res = (void *)mem; | |
3859 | ||
ffc43836 | 3860 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3861 | |
ffc43836 CG |
3862 | for (i = 0; i < nr_ioapics; i++) { |
3863 | res[i].name = mem; | |
3864 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3865 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3866 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3867 | } |
3868 | ||
3869 | ioapic_resources = res; | |
3870 | ||
3871 | return res; | |
3872 | } | |
54168ed7 | 3873 | |
23f9b267 | 3874 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3875 | { |
3876 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3877 | struct resource *ioapic_res; |
d6c88a50 | 3878 | int i; |
f3294a33 | 3879 | |
ffc43836 | 3880 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3881 | for (i = 0; i < nr_ioapics; i++) { |
3882 | if (smp_found_config) { | |
d5371430 | 3883 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3884 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3885 | if (!ioapic_phys) { |
3886 | printk(KERN_ERR | |
3887 | "WARNING: bogus zero IO-APIC " | |
3888 | "address found in MPTABLE, " | |
3889 | "disabling IO/APIC support!\n"); | |
3890 | smp_found_config = 0; | |
3891 | skip_ioapic_setup = 1; | |
3892 | goto fake_ioapic_page; | |
3893 | } | |
54168ed7 | 3894 | #endif |
f3294a33 | 3895 | } else { |
54168ed7 | 3896 | #ifdef CONFIG_X86_32 |
f3294a33 | 3897 | fake_ioapic_page: |
54168ed7 | 3898 | #endif |
e79c65a9 | 3899 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3900 | ioapic_phys = __pa(ioapic_phys); |
3901 | } | |
3902 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3903 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3904 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3905 | ioapic_phys); | |
f3294a33 | 3906 | idx++; |
54168ed7 | 3907 | |
ffc43836 | 3908 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3909 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3910 | ioapic_res++; |
f3294a33 | 3911 | } |
23f9b267 TG |
3912 | |
3913 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3914 | } |
3915 | ||
857fdc53 | 3916 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3917 | { |
3918 | int i; | |
3919 | struct resource *r = ioapic_resources; | |
3920 | ||
3921 | if (!r) { | |
857fdc53 | 3922 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3923 | printk(KERN_ERR |
3924 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3925 | return; |
54168ed7 IM |
3926 | } |
3927 | ||
3928 | for (i = 0; i < nr_ioapics; i++) { | |
3929 | insert_resource(&iomem_resource, r); | |
3930 | r++; | |
3931 | } | |
54168ed7 | 3932 | } |
2a4ab640 | 3933 | |
eddb0c55 | 3934 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3935 | { |
3936 | int i = 0; | |
3937 | ||
678301ec PB |
3938 | if (nr_ioapics == 0) |
3939 | return -1; | |
3940 | ||
2a4ab640 FT |
3941 | /* Find the IOAPIC that manages this GSI. */ |
3942 | for (i = 0; i < nr_ioapics; i++) { | |
c040aaeb SS |
3943 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
3944 | if ((gsi >= gsi_cfg->gsi_base) | |
3945 | && (gsi <= gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3946 | return i; |
3947 | } | |
54168ed7 | 3948 | |
2a4ab640 FT |
3949 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3950 | return -1; | |
3951 | } | |
3952 | ||
eddb0c55 | 3953 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3954 | { |
c040aaeb SS |
3955 | struct mp_ioapic_gsi *gsi_cfg; |
3956 | ||
2a4ab640 FT |
3957 | if (WARN_ON(ioapic == -1)) |
3958 | return -1; | |
c040aaeb SS |
3959 | |
3960 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3961 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3962 | return -1; |
3963 | ||
c040aaeb | 3964 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3965 | } |
3966 | ||
41098ffe | 3967 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3968 | { |
3969 | if (nr_ioapics >= MAX_IO_APICS) { | |
73d63d03 SS |
3970 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
3971 | MAX_IO_APICS, nr_ioapics); | |
2a4ab640 FT |
3972 | return 1; |
3973 | } | |
3974 | if (!address) { | |
73d63d03 | 3975 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
2a4ab640 FT |
3976 | return 1; |
3977 | } | |
54168ed7 IM |
3978 | return 0; |
3979 | } | |
3980 | ||
73d63d03 SS |
3981 | static __init int bad_ioapic_register(int idx) |
3982 | { | |
3983 | union IO_APIC_reg_00 reg_00; | |
3984 | union IO_APIC_reg_01 reg_01; | |
3985 | union IO_APIC_reg_02 reg_02; | |
3986 | ||
3987 | reg_00.raw = io_apic_read(idx, 0); | |
3988 | reg_01.raw = io_apic_read(idx, 1); | |
3989 | reg_02.raw = io_apic_read(idx, 2); | |
3990 | ||
3991 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3992 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3993 | mpc_ioapic_addr(idx)); | |
3994 | return 1; | |
3995 | } | |
3996 | ||
3997 | return 0; | |
3998 | } | |
3999 | ||
2a4ab640 FT |
4000 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4001 | { | |
4002 | int idx = 0; | |
7716a5c4 | 4003 | int entries; |
c040aaeb | 4004 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
4005 | |
4006 | if (bad_ioapic(address)) | |
4007 | return; | |
4008 | ||
4009 | idx = nr_ioapics; | |
4010 | ||
d5371430 SS |
4011 | ioapics[idx].mp_config.type = MP_IOAPIC; |
4012 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
4013 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
4014 | |
4015 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
4016 | |
4017 | if (bad_ioapic_register(idx)) { | |
4018 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
4019 | return; | |
4020 | } | |
4021 | ||
d5371430 SS |
4022 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
4023 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
4024 | |
4025 | /* | |
4026 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4027 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4028 | */ | |
7716a5c4 | 4029 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
4030 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
4031 | gsi_cfg->gsi_base = gsi_base; | |
4032 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
4033 | |
4034 | /* | |
4035 | * The number of IO-APIC IRQ registers (== #pins): | |
4036 | */ | |
b69c6c3b | 4037 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 4038 | |
c040aaeb SS |
4039 | if (gsi_cfg->gsi_end >= gsi_top) |
4040 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 | 4041 | |
73d63d03 SS |
4042 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
4043 | idx, mpc_ioapic_id(idx), | |
4044 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
4045 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 FT |
4046 | |
4047 | nr_ioapics++; | |
4048 | } | |
05ddafb1 JP |
4049 | |
4050 | /* Enable IOAPIC early just for system timer */ | |
4051 | void __init pre_init_apic_IRQ0(void) | |
4052 | { | |
f880ec78 | 4053 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
4054 | |
4055 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4056 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
4057 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
4058 | &phys_cpu_present_map); | |
05ddafb1 | 4059 | #endif |
05ddafb1 JP |
4060 | setup_local_APIC(); |
4061 | ||
f880ec78 | 4062 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
4063 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
4064 | "edge"); | |
05ddafb1 | 4065 | } |