Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
c8f730b1 | 8 | * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
0b1da1c8 | 28 | |
ac23d4ee JS |
29 | #include <asm/uv/uv_mmrs.h> |
30 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
31 | #include <asm/current.h> |
32 | #include <asm/pgtable.h> | |
7019cc2d | 33 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
34 | #include <asm/uv/uv.h> |
35 | #include <asm/apic.h> | |
36 | #include <asm/ipi.h> | |
37 | #include <asm/smp.h> | |
fd12a0d6 | 38 | #include <asm/x86_init.h> |
818987e9 | 39 | #include <asm/emergency-restart.h> |
ac23d4ee | 40 | |
510b3725 YL |
41 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
42 | ||
841582ea MT |
43 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
44 | ||
1b9b89e7 | 45 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 46 | static u64 gru_start_paddr, gru_end_paddr; |
c8f730b1 | 47 | static union uvh_apicid uvh_apicid; |
7a1110e8 JS |
48 | int uv_min_hub_revision_id; |
49 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
8191c9f6 DS |
50 | unsigned int uv_apicid_hibits; |
51 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
78c06176 | 52 | static DEFINE_SPINLOCK(uv_nmi_lock); |
fd12a0d6 | 53 | |
e6810413 JS |
54 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
55 | { | |
56 | unsigned long val, *mmr; | |
57 | ||
58 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
59 | val = *mmr; | |
60 | early_iounmap(mmr, sizeof(*mmr)); | |
61 | return val; | |
62 | } | |
63 | ||
eb41c8be | 64 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 65 | { |
ccef0864 | 66 | return start >= gru_start_paddr && end <= gru_end_paddr; |
fd12a0d6 JS |
67 | } |
68 | ||
eb41c8be | 69 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
70 | { |
71 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
72 | } | |
1b9b89e7 | 73 | |
d8850ba4 | 74 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
75 | { |
76 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
77 | union uvh_rh_gam_config_mmr_u m_n_config; |
78 | int pnode; | |
7a1110e8 JS |
79 | |
80 | /* Currently, all blades have same revision number */ | |
e6810413 | 81 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 82 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
83 | uv_min_hub_revision_id = node_id.s.revision; |
84 | ||
d8850ba4 JS |
85 | pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); |
86 | return pnode; | |
27229ca6 JS |
87 | } |
88 | ||
0520bd84 | 89 | static void __init early_get_apic_pnode_shift(void) |
c8f730b1 | 90 | { |
e6810413 | 91 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); |
c8f730b1 RA |
92 | if (!uvh_apicid.v) |
93 | /* | |
94 | * Old bios, use default value | |
95 | */ | |
96 | uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; | |
c8f730b1 RA |
97 | } |
98 | ||
8191c9f6 DS |
99 | /* |
100 | * Add an extra bit as dictated by bios to the destination apicid of | |
101 | * interrupts potentially passing through the UV HUB. This prevents | |
102 | * a deadlock between interrupts and IO port operations. | |
103 | */ | |
104 | static void __init uv_set_apicid_hibit(void) | |
105 | { | |
106 | union uvh_lb_target_physical_apic_id_mask_u apicid_mask; | |
8191c9f6 | 107 | |
e6810413 | 108 | apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK); |
8191c9f6 DS |
109 | uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK; |
110 | } | |
111 | ||
52459ab9 | 112 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 113 | { |
d8850ba4 | 114 | int pnodeid; |
1d2c867c | 115 | |
1b9b89e7 | 116 | if (!strcmp(oem_id, "SGI")) { |
d8850ba4 | 117 | pnodeid = early_get_pnodeid(); |
0520bd84 | 118 | early_get_apic_pnode_shift(); |
fd12a0d6 | 119 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
78c06176 | 120 | x86_platform.nmi_init = uv_nmi_init; |
1b9b89e7 YL |
121 | if (!strcmp(oem_table_id, "UVL")) |
122 | uv_system_type = UV_LEGACY_APIC; | |
123 | else if (!strcmp(oem_table_id, "UVX")) | |
124 | uv_system_type = UV_X2APIC; | |
125 | else if (!strcmp(oem_table_id, "UVH")) { | |
0a3aee0d | 126 | __this_cpu_write(x2apic_extra_bits, |
72eb6a79 | 127 | pnodeid << uvh_apicid.s.pnode_shift); |
1b9b89e7 | 128 | uv_system_type = UV_NON_UNIQUE_APIC; |
8191c9f6 | 129 | uv_set_apicid_hibit(); |
1b9b89e7 YL |
130 | return 1; |
131 | } | |
132 | } | |
133 | return 0; | |
134 | } | |
135 | ||
136 | enum uv_system_type get_uv_system_type(void) | |
137 | { | |
138 | return uv_system_type; | |
139 | } | |
140 | ||
141 | int is_uv_system(void) | |
142 | { | |
143 | return uv_system_type != UV_NONE; | |
144 | } | |
8067794b | 145 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 146 | |
ac23d4ee JS |
147 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
148 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
149 | ||
150 | struct uv_blade_info *uv_blade_info; | |
151 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
152 | ||
153 | short *uv_node_to_blade; | |
154 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
155 | ||
156 | short *uv_cpu_to_blade; | |
157 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
158 | ||
159 | short uv_possible_blades; | |
160 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
161 | ||
7019cc2d RA |
162 | unsigned long sn_rtc_cycles_per_second; |
163 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
164 | ||
bcda016e | 165 | static const struct cpumask *uv_target_cpus(void) |
ac23d4ee | 166 | { |
8447b360 | 167 | return cpu_online_mask; |
ac23d4ee JS |
168 | } |
169 | ||
bcda016e | 170 | static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) |
ac23d4ee | 171 | { |
bcda016e MT |
172 | cpumask_clear(retmask); |
173 | cpumask_set_cpu(cpu, retmask); | |
ac23d4ee JS |
174 | } |
175 | ||
667c5296 | 176 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee | 177 | { |
0b1da1c8 | 178 | #ifdef CONFIG_SMP |
ac23d4ee | 179 | unsigned long val; |
9f5314fb | 180 | int pnode; |
ac23d4ee | 181 | |
9f5314fb | 182 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 183 | phys_apicid |= uv_apicid_hibits; |
ac23d4ee JS |
184 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
185 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 186 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 187 | APIC_DM_INIT; |
9f5314fb | 188 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
189 | mdelay(10); |
190 | ||
191 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
192 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 193 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 194 | APIC_DM_STARTUP; |
9f5314fb | 195 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf YL |
196 | |
197 | atomic_set(&init_deasserted, 1); | |
0b1da1c8 | 198 | #endif |
ac23d4ee JS |
199 | return 0; |
200 | } | |
201 | ||
202 | static void uv_send_IPI_one(int cpu, int vector) | |
203 | { | |
66666e50 | 204 | unsigned long apicid; |
9f5314fb | 205 | int pnode; |
ac23d4ee | 206 | |
1e0b5d00 | 207 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 208 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 209 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
210 | } |
211 | ||
bcda016e | 212 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
213 | { |
214 | unsigned int cpu; | |
215 | ||
bcda016e | 216 | for_each_cpu(cpu, mask) |
e7986739 MT |
217 | uv_send_IPI_one(cpu, vector); |
218 | } | |
219 | ||
bcda016e | 220 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 221 | { |
e7986739 | 222 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 223 | unsigned int cpu; |
e7986739 | 224 | |
dac5f412 | 225 | for_each_cpu(cpu, mask) { |
e7986739 | 226 | if (cpu != this_cpu) |
ac23d4ee | 227 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 228 | } |
ac23d4ee JS |
229 | } |
230 | ||
231 | static void uv_send_IPI_allbutself(int vector) | |
232 | { | |
e7986739 | 233 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 234 | unsigned int cpu; |
ac23d4ee | 235 | |
dac5f412 | 236 | for_each_online_cpu(cpu) { |
e7986739 MT |
237 | if (cpu != this_cpu) |
238 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 239 | } |
ac23d4ee JS |
240 | } |
241 | ||
242 | static void uv_send_IPI_all(int vector) | |
243 | { | |
bcda016e | 244 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
245 | } |
246 | ||
247 | static int uv_apic_id_registered(void) | |
248 | { | |
249 | return 1; | |
250 | } | |
251 | ||
277d1f58 | 252 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
253 | { |
254 | } | |
255 | ||
bcda016e | 256 | static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) |
ac23d4ee | 257 | { |
ac23d4ee JS |
258 | /* |
259 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
260 | * May as well be the first. | |
261 | */ | |
debccb3e IM |
262 | int cpu = cpumask_first(cpumask); |
263 | ||
247bc6ca | 264 | if ((unsigned)cpu < nr_cpu_ids) |
8191c9f6 | 265 | return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
ac23d4ee JS |
266 | else |
267 | return BAD_APICID; | |
268 | } | |
269 | ||
debccb3e IM |
270 | static unsigned int |
271 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
272 | const struct cpumask *andmask) | |
95d313cf MT |
273 | { |
274 | int cpu; | |
275 | ||
276 | /* | |
277 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
278 | * May as well be the first. | |
279 | */ | |
debccb3e | 280 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
281 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
282 | break; | |
debccb3e | 283 | } |
8191c9f6 | 284 | return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
95d313cf MT |
285 | } |
286 | ||
ca6c8ed4 | 287 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
288 | { |
289 | unsigned int id; | |
290 | ||
291 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 292 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
293 | |
294 | return id; | |
295 | } | |
296 | ||
1b9b89e7 | 297 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
298 | { |
299 | unsigned long x; | |
300 | ||
301 | /* maskout x2apic_extra_bits ? */ | |
302 | x = id; | |
303 | return x; | |
304 | } | |
305 | ||
306 | static unsigned int uv_read_apic_id(void) | |
307 | { | |
308 | ||
ca6c8ed4 | 309 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
310 | } |
311 | ||
d4c9a9f3 | 312 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 313 | { |
0c81c746 | 314 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
315 | } |
316 | ||
ac23d4ee JS |
317 | static void uv_send_IPI_self(int vector) |
318 | { | |
319 | apic_write(APIC_SELF_IPI, vector); | |
320 | } | |
ac23d4ee | 321 | |
52459ab9 | 322 | struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
323 | |
324 | .name = "UV large system", | |
325 | .probe = NULL, | |
326 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, | |
327 | .apic_id_registered = uv_apic_id_registered, | |
328 | ||
f8987a10 | 329 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 330 | .irq_dest_mode = 0, /* physical */ |
c7967329 IM |
331 | |
332 | .target_cpus = uv_target_cpus, | |
08125d3e | 333 | .disable_esr = 0, |
bdb1a9b6 | 334 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
335 | .check_apicid_used = NULL, |
336 | .check_apicid_present = NULL, | |
337 | ||
c7967329 IM |
338 | .vector_allocation_domain = uv_vector_allocation_domain, |
339 | .init_apic_ldr = uv_init_apic_ldr, | |
340 | ||
341 | .ioapic_phys_id_map = NULL, | |
342 | .setup_apic_routing = NULL, | |
343 | .multi_timer_check = NULL, | |
a21769a4 | 344 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
345 | .apicid_to_cpu_present = NULL, |
346 | .setup_portio_remap = NULL, | |
a27a6210 | 347 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 348 | .enable_apic_mode = NULL, |
d4c9a9f3 | 349 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
350 | .mps_oem_check = NULL, |
351 | ||
ca6c8ed4 | 352 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
353 | .set_apic_id = set_apic_id, |
354 | .apic_id_mask = 0xFFFFFFFFu, | |
355 | ||
356 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | |
357 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, | |
358 | ||
359 | .send_IPI_mask = uv_send_IPI_mask, | |
360 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
361 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
362 | .send_IPI_all = uv_send_IPI_all, | |
363 | .send_IPI_self = uv_send_IPI_self, | |
364 | ||
1f5bcabf | 365 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
abfa584c IM |
366 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
367 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
c7967329 IM |
368 | .wait_for_init_deassert = NULL, |
369 | .smp_callin_clear_local_apic = NULL, | |
c7967329 | 370 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
371 | |
372 | .read = native_apic_msr_read, | |
373 | .write = native_apic_msr_write, | |
374 | .icr_read = native_x2apic_icr_read, | |
375 | .icr_write = native_x2apic_icr_write, | |
376 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
377 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
378 | }; |
379 | ||
9f5314fb | 380 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 381 | { |
16ee8db6 | 382 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
383 | } |
384 | ||
385 | /* | |
386 | * Called on boot cpu. | |
387 | */ | |
9f5314fb JS |
388 | static __init int boot_pnode_to_blade(int pnode) |
389 | { | |
390 | int blade; | |
391 | ||
392 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
393 | if (pnode == uv_blade_info[blade].pnode) | |
394 | return blade; | |
395 | BUG(); | |
396 | } | |
397 | ||
398 | struct redir_addr { | |
399 | unsigned long redirect; | |
400 | unsigned long alias; | |
401 | }; | |
402 | ||
403 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
404 | ||
405 | static __initdata struct redir_addr redir_addrs[] = { | |
62b0cfc2 JS |
406 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, |
407 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, | |
408 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, | |
9f5314fb JS |
409 | }; |
410 | ||
411 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
412 | { | |
62b0cfc2 | 413 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb JS |
414 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
415 | int i; | |
416 | ||
417 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
418 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
036ed8ba | 419 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb JS |
420 | *size = (1UL << alias.s.m_alias); |
421 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
422 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
423 | return; | |
424 | } | |
425 | } | |
036ed8ba | 426 | *base = *size = 0; |
9f5314fb JS |
427 | } |
428 | ||
83f5d894 JS |
429 | enum map_type {map_wb, map_uc}; |
430 | ||
fcfbb2b5 MT |
431 | static __init void map_high(char *id, unsigned long base, int pshift, |
432 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
433 | { |
434 | unsigned long bytes, paddr; | |
435 | ||
fcfbb2b5 MT |
436 | paddr = base << pshift; |
437 | bytes = (1UL << bshift) * (max_pnode + 1); | |
83f5d894 | 438 | printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, |
0b1da1c8 | 439 | paddr + bytes); |
83f5d894 JS |
440 | if (map_type == map_uc) |
441 | init_extra_mapping_uc(paddr, bytes); | |
442 | else | |
443 | init_extra_mapping_wb(paddr, bytes); | |
444 | ||
445 | } | |
446 | static __init void map_gru_high(int max_pnode) | |
447 | { | |
448 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
449 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
450 | ||
451 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
fd12a0d6 | 452 | if (gru.s.enable) { |
fcfbb2b5 | 453 | map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); |
fd12a0d6 JS |
454 | gru_start_paddr = ((u64)gru.s.base << shift); |
455 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); | |
456 | ||
457 | } | |
83f5d894 JS |
458 | } |
459 | ||
daf7b9c9 JS |
460 | static __init void map_mmr_high(int max_pnode) |
461 | { | |
462 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
463 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
464 | ||
465 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
466 | if (mmr.s.enable) | |
fcfbb2b5 | 467 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
daf7b9c9 JS |
468 | } |
469 | ||
83f5d894 JS |
470 | static __init void map_mmioh_high(int max_pnode) |
471 | { | |
472 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
473 | int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
474 | ||
475 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); | |
476 | if (mmioh.s.enable) | |
fcfbb2b5 MT |
477 | map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io, |
478 | max_pnode, map_uc); | |
83f5d894 JS |
479 | } |
480 | ||
918bc960 JS |
481 | static __init void map_low_mmrs(void) |
482 | { | |
483 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
484 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
485 | } | |
486 | ||
7019cc2d RA |
487 | static __init void uv_rtc_init(void) |
488 | { | |
922402f1 RA |
489 | long status; |
490 | u64 ticks_per_sec; | |
7019cc2d | 491 | |
922402f1 RA |
492 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
493 | &ticks_per_sec); | |
494 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
495 | printk(KERN_WARNING |
496 | "unable to determine platform RTC clock frequency, " | |
497 | "guessing.\n"); | |
498 | /* BIOS gives wrong value for clock freq. so guess */ | |
499 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
500 | } else | |
501 | sn_rtc_cycles_per_second = ticks_per_sec; | |
502 | } | |
503 | ||
7f1baa06 MT |
504 | /* |
505 | * percpu heartbeat timer | |
506 | */ | |
507 | static void uv_heartbeat(unsigned long ignored) | |
508 | { | |
509 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
510 | unsigned char bits = uv_hub_info->scir.state; | |
511 | ||
512 | /* flip heartbeat bit */ | |
513 | bits ^= SCIR_CPU_HEARTBEAT; | |
514 | ||
69a72a0e MT |
515 | /* is this cpu idle? */ |
516 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
517 | bits &= ~SCIR_CPU_ACTIVITY; |
518 | else | |
519 | bits |= SCIR_CPU_ACTIVITY; | |
520 | ||
521 | /* update system controller interface reg */ | |
522 | uv_set_scir_bits(bits); | |
523 | ||
524 | /* enable next timer period */ | |
5c333864 | 525 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
526 | } |
527 | ||
528 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
529 | { | |
99659a92 | 530 | while (!uv_cpu_hub_info(cpu)->scir.enabled) { |
7f1baa06 MT |
531 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; |
532 | ||
533 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
534 | setup_timer(timer, uv_heartbeat, cpu); | |
535 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
536 | add_timer_on(timer, cpu); | |
537 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
7f1baa06 | 538 | |
99659a92 RK |
539 | /* also ensure that boot cpu is enabled */ |
540 | cpu = 0; | |
541 | } | |
7f1baa06 MT |
542 | } |
543 | ||
77be80e4 | 544 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
545 | static void __cpuinit uv_heartbeat_disable(int cpu) |
546 | { | |
547 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
548 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
549 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
550 | } | |
551 | uv_set_cpu_scir_bits(cpu, 0xff); | |
552 | } | |
553 | ||
7f1baa06 MT |
554 | /* |
555 | * cpu hotplug notifier | |
556 | */ | |
557 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
558 | unsigned long action, void *hcpu) | |
559 | { | |
560 | long cpu = (long)hcpu; | |
561 | ||
562 | switch (action) { | |
563 | case CPU_ONLINE: | |
564 | uv_heartbeat_enable(cpu); | |
565 | break; | |
566 | case CPU_DOWN_PREPARE: | |
567 | uv_heartbeat_disable(cpu); | |
568 | break; | |
569 | default: | |
570 | break; | |
571 | } | |
572 | return NOTIFY_OK; | |
573 | } | |
574 | ||
575 | static __init void uv_scir_register_cpu_notifier(void) | |
576 | { | |
577 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
578 | } | |
579 | ||
580 | #else /* !CONFIG_HOTPLUG_CPU */ | |
581 | ||
582 | static __init void uv_scir_register_cpu_notifier(void) | |
583 | { | |
584 | } | |
585 | ||
586 | static __init int uv_init_heartbeat(void) | |
587 | { | |
588 | int cpu; | |
589 | ||
590 | if (is_uv_system()) | |
591 | for_each_online_cpu(cpu) | |
592 | uv_heartbeat_enable(cpu); | |
593 | return 0; | |
594 | } | |
595 | ||
596 | late_initcall(uv_init_heartbeat); | |
597 | ||
598 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
599 | ||
841582ea MT |
600 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
601 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
602 | unsigned int command_bits, bool change_bridge) | |
603 | { | |
604 | int domain, bus, rc; | |
605 | ||
606 | PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n", | |
607 | pdev->devfn, decode, command_bits, change_bridge); | |
608 | ||
609 | if (!change_bridge) | |
610 | return 0; | |
611 | ||
612 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
613 | return 0; | |
614 | ||
615 | domain = pci_domain_nr(pdev->bus); | |
616 | bus = pdev->bus->number; | |
617 | ||
618 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
619 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
620 | ||
621 | return rc; | |
622 | } | |
623 | ||
8da077d6 JS |
624 | /* |
625 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 626 | * FIXME: hotplug not supported yet |
8da077d6 JS |
627 | */ |
628 | void __cpuinit uv_cpu_init(void) | |
629 | { | |
630 | /* CPU 0 initilization will be done via uv_system_init. */ | |
631 | if (!uv_blade_info) | |
632 | return; | |
633 | ||
634 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
635 | ||
636 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
637 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
638 | } | |
639 | ||
78c06176 RA |
640 | /* |
641 | * When NMI is received, print a stack trace. | |
642 | */ | |
643 | int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data) | |
644 | { | |
673a6092 | 645 | if (reason != DIE_NMIUNKNOWN) |
78c06176 | 646 | return NOTIFY_OK; |
5edd19af CW |
647 | |
648 | if (in_crash_kexec) | |
649 | /* do nothing if entering the crash kernel */ | |
650 | return NOTIFY_OK; | |
78c06176 RA |
651 | /* |
652 | * Use a lock so only one cpu prints at a time | |
653 | * to prevent intermixed output. | |
654 | */ | |
655 | spin_lock(&uv_nmi_lock); | |
656 | pr_info("NMI stack dump cpu %u:\n", smp_processor_id()); | |
657 | dump_stack(); | |
658 | spin_unlock(&uv_nmi_lock); | |
659 | ||
660 | return NOTIFY_STOP; | |
661 | } | |
662 | ||
663 | static struct notifier_block uv_dump_stack_nmi_nb = { | |
664 | .notifier_call = uv_handle_nmi | |
665 | }; | |
666 | ||
667 | void uv_register_nmi_notifier(void) | |
668 | { | |
669 | if (register_die_notifier(&uv_dump_stack_nmi_nb)) | |
670 | printk(KERN_WARNING "UV NMI handler failed to register\n"); | |
671 | } | |
672 | ||
673 | void uv_nmi_init(void) | |
674 | { | |
675 | unsigned int value; | |
676 | ||
677 | /* | |
678 | * Unmask NMI on all cpus | |
679 | */ | |
680 | value = apic_read(APIC_LVT1) | APIC_DM_NMI; | |
681 | value &= ~APIC_LVT_MASKED; | |
682 | apic_write(APIC_LVT1, value); | |
683 | } | |
c4bd1fda MS |
684 | |
685 | void __init uv_system_init(void) | |
ac23d4ee | 686 | { |
62b0cfc2 | 687 | union uvh_rh_gam_config_mmr_u m_n_config; |
d8850ba4 | 688 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; |
9f5314fb JS |
689 | union uvh_node_id_u node_id; |
690 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
d8850ba4 | 691 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io; |
c4ed3f04 | 692 | int gnode_extra, max_pnode = 0; |
6a891a24 | 693 | unsigned long mmr_base, present, paddr; |
d8850ba4 | 694 | unsigned short pnode_mask, pnode_io_mask; |
ac23d4ee | 695 | |
918bc960 JS |
696 | map_low_mmrs(); |
697 | ||
62b0cfc2 | 698 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); |
9f5314fb JS |
699 | m_val = m_n_config.s.m_skt; |
700 | n_val = m_n_config.s.n_skt; | |
d8850ba4 JS |
701 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); |
702 | n_io = mmioh.s.n_io; | |
ac23d4ee JS |
703 | mmr_base = |
704 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
705 | ~UV_MMR_ENABLE; | |
c4ed3f04 | 706 | pnode_mask = (1 << n_val) - 1; |
d8850ba4 JS |
707 | pnode_io_mask = (1 << n_io) - 1; |
708 | ||
c4ed3f04 JS |
709 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); |
710 | gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; | |
711 | gnode_upper = ((unsigned long)gnode_extra << m_val); | |
d8850ba4 JS |
712 | printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n", |
713 | n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask); | |
c4ed3f04 | 714 | |
ac23d4ee JS |
715 | printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); |
716 | ||
9f5314fb JS |
717 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
718 | uv_possible_blades += | |
719 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
ac23d4ee JS |
720 | printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); |
721 | ||
722 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
ef020ab0 | 723 | uv_blade_info = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 724 | BUG_ON(!uv_blade_info); |
6c7184b7 JS |
725 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
726 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 727 | |
9f5314fb JS |
728 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
729 | ||
ac23d4ee | 730 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 731 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 732 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
733 | memset(uv_node_to_blade, 255, bytes); |
734 | ||
735 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 736 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 737 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
738 | memset(uv_cpu_to_blade, 255, bytes); |
739 | ||
9f5314fb JS |
740 | blade = 0; |
741 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
742 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
743 | for (j = 0; j < 64; j++) { | |
744 | if (!test_bit(j, &present)) | |
745 | continue; | |
d8850ba4 | 746 | pnode = (i * 64 + j) & pnode_mask; |
36ac4b98 | 747 | uv_blade_info[blade].pnode = pnode; |
9f5314fb | 748 | uv_blade_info[blade].nr_possible_cpus = 0; |
ac23d4ee | 749 | uv_blade_info[blade].nr_online_cpus = 0; |
36ac4b98 | 750 | max_pnode = max(pnode, max_pnode); |
9f5314fb | 751 | blade++; |
ac23d4ee | 752 | } |
9f5314fb | 753 | } |
ac23d4ee | 754 | |
7f594232 | 755 | uv_bios_init(); |
b76365a1 RA |
756 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
757 | &sn_region_size, &system_serial_number); | |
7019cc2d RA |
758 | uv_rtc_init(); |
759 | ||
9f5314fb | 760 | for_each_present_cpu(cpu) { |
39d30770 MT |
761 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
762 | ||
9f5314fb | 763 | nid = cpu_to_node(cpu); |
c8f730b1 RA |
764 | /* |
765 | * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); | |
766 | */ | |
d8850ba4 | 767 | uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; |
c8f730b1 | 768 | uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; |
39d30770 | 769 | pnode = uv_apicid_to_pnode(apicid); |
9f5314fb JS |
770 | blade = boot_pnode_to_blade(pnode); |
771 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
772 | uv_blade_info[blade].nr_possible_cpus++; | |
773 | ||
6c7184b7 JS |
774 | /* Any node on the blade, else will contain -1. */ |
775 | uv_blade_info[blade].memory_nid = nid; | |
776 | ||
9f5314fb | 777 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; |
189f67c4 | 778 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb | 779 | uv_cpu_hub_info(cpu)->m_val = m_val; |
036ed8ba | 780 | uv_cpu_hub_info(cpu)->n_val = n_val; |
ac23d4ee JS |
781 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
782 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb | 783 | uv_cpu_hub_info(cpu)->pnode = pnode; |
036ed8ba | 784 | uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; |
9f5314fb | 785 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; |
c4ed3f04 | 786 | uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; |
ac23d4ee | 787 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 788 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
39d30770 | 789 | uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); |
ac23d4ee JS |
790 | uv_node_to_blade[nid] = blade; |
791 | uv_cpu_to_blade[cpu] = blade; | |
ac23d4ee | 792 | } |
83f5d894 | 793 | |
6a891a24 JS |
794 | /* Add blade/pnode info for nodes without cpus */ |
795 | for_each_online_node(nid) { | |
796 | if (uv_node_to_blade[nid] >= 0) | |
797 | continue; | |
798 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
fc61e663 | 799 | paddr = uv_soc_phys_ram_to_gpa(paddr); |
6a891a24 JS |
800 | pnode = (paddr >> m_val) & pnode_mask; |
801 | blade = boot_pnode_to_blade(pnode); | |
802 | uv_node_to_blade[nid] = blade; | |
803 | } | |
804 | ||
83f5d894 | 805 | map_gru_high(max_pnode); |
daf7b9c9 | 806 | map_mmr_high(max_pnode); |
d8850ba4 | 807 | map_mmioh_high(max_pnode & pnode_io_mask); |
ac23d4ee | 808 | |
8da077d6 | 809 | uv_cpu_init(); |
7f1baa06 | 810 | uv_scir_register_cpu_notifier(); |
78c06176 | 811 | uv_register_nmi_notifier(); |
a3d732f9 | 812 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
813 | |
814 | /* register Legacy VGA I/O redirection handler */ | |
815 | pci_register_set_vga_state(uv_set_vga_state); | |
818987e9 CW |
816 | |
817 | /* | |
818 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
819 | * EFI is not enabled in the kdump kernel. | |
820 | */ | |
821 | if (is_kdump_kernel()) | |
822 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 823 | } |