Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
b15cc4a1 | 8 | * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
1b3a5d02 | 28 | #include <linux/reboot.h> |
0b1da1c8 | 29 | |
ac23d4ee JS |
30 | #include <asm/uv/uv_mmrs.h> |
31 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
32 | #include <asm/current.h> |
33 | #include <asm/pgtable.h> | |
7019cc2d | 34 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
35 | #include <asm/uv/uv.h> |
36 | #include <asm/apic.h> | |
37 | #include <asm/ipi.h> | |
38 | #include <asm/smp.h> | |
fd12a0d6 | 39 | #include <asm/x86_init.h> |
1d44e828 JS |
40 | #include <asm/nmi.h> |
41 | ||
42 | /* BMC sets a bit this MMR non-zero before sending an NMI */ | |
43 | #define UVH_NMI_MMR UVH_SCRATCH5 | |
44 | #define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8) | |
45 | #define UV_NMI_PENDING_MASK (1UL << 63) | |
46 | DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count); | |
ac23d4ee | 47 | |
510b3725 YL |
48 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
49 | ||
841582ea MT |
50 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
51 | ||
1b9b89e7 | 52 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 53 | static u64 gru_start_paddr, gru_end_paddr; |
879d5ad0 DS |
54 | static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; |
55 | static u64 gru_dist_lmask, gru_dist_umask; | |
c8f730b1 | 56 | static union uvh_apicid uvh_apicid; |
7a1110e8 JS |
57 | int uv_min_hub_revision_id; |
58 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
8191c9f6 DS |
59 | unsigned int uv_apicid_hibits; |
60 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
78c06176 | 61 | static DEFINE_SPINLOCK(uv_nmi_lock); |
fd12a0d6 | 62 | |
1a8880a1 SS |
63 | static struct apic apic_x2apic_uv_x; |
64 | ||
e6810413 JS |
65 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
66 | { | |
67 | unsigned long val, *mmr; | |
68 | ||
69 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
70 | val = *mmr; | |
71 | early_iounmap(mmr, sizeof(*mmr)); | |
72 | return val; | |
73 | } | |
74 | ||
eb41c8be | 75 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 76 | { |
879d5ad0 DS |
77 | if (gru_dist_base) { |
78 | u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */ | |
79 | u64 sl = start & gru_dist_lmask; /* base offset bits */ | |
80 | u64 eu = end & gru_dist_umask; | |
81 | u64 el = end & gru_dist_lmask; | |
82 | ||
83 | /* Must reside completely within a single GRU range */ | |
84 | return (sl == gru_dist_base && el == gru_dist_base && | |
85 | su >= gru_first_node_paddr && | |
86 | su <= gru_last_node_paddr && | |
87 | eu == su); | |
88 | } else { | |
89 | return start >= gru_start_paddr && end <= gru_end_paddr; | |
90 | } | |
fd12a0d6 JS |
91 | } |
92 | ||
eb41c8be | 93 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
94 | { |
95 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
96 | } | |
1b9b89e7 | 97 | |
d8850ba4 | 98 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
99 | { |
100 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
101 | union uvh_rh_gam_config_mmr_u m_n_config; |
102 | int pnode; | |
7a1110e8 JS |
103 | |
104 | /* Currently, all blades have same revision number */ | |
e6810413 | 105 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 106 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
107 | uv_min_hub_revision_id = node_id.s.revision; |
108 | ||
b15cc4a1 MT |
109 | switch (node_id.s.part_number) { |
110 | case UV2_HUB_PART_NUMBER: | |
111 | case UV2_HUB_PART_NUMBER_X: | |
b495e039 | 112 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; |
b15cc4a1 MT |
113 | break; |
114 | case UV3_HUB_PART_NUMBER: | |
115 | case UV3_HUB_PART_NUMBER_X: | |
116 | uv_min_hub_revision_id += UV3_HUB_REVISION_BASE - 1; | |
117 | break; | |
118 | } | |
2a919596 JS |
119 | |
120 | uv_hub_info->hub_revision = uv_min_hub_revision_id; | |
d8850ba4 JS |
121 | pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); |
122 | return pnode; | |
27229ca6 JS |
123 | } |
124 | ||
0520bd84 | 125 | static void __init early_get_apic_pnode_shift(void) |
c8f730b1 | 126 | { |
e6810413 | 127 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); |
c8f730b1 RA |
128 | if (!uvh_apicid.v) |
129 | /* | |
130 | * Old bios, use default value | |
131 | */ | |
132 | uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; | |
c8f730b1 RA |
133 | } |
134 | ||
8191c9f6 DS |
135 | /* |
136 | * Add an extra bit as dictated by bios to the destination apicid of | |
137 | * interrupts potentially passing through the UV HUB. This prevents | |
138 | * a deadlock between interrupts and IO port operations. | |
139 | */ | |
140 | static void __init uv_set_apicid_hibit(void) | |
141 | { | |
2a919596 | 142 | union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; |
8191c9f6 | 143 | |
2a919596 JS |
144 | if (is_uv1_hub()) { |
145 | apicid_mask.v = | |
146 | uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); | |
147 | uv_apicid_hibits = | |
148 | apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; | |
149 | } | |
8191c9f6 DS |
150 | } |
151 | ||
52459ab9 | 152 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 153 | { |
b15cc4a1 | 154 | int pnodeid, is_uv1, is_uv2, is_uv3; |
1d2c867c | 155 | |
2a919596 JS |
156 | is_uv1 = !strcmp(oem_id, "SGI"); |
157 | is_uv2 = !strcmp(oem_id, "SGI2"); | |
b15cc4a1 MT |
158 | is_uv3 = !strncmp(oem_id, "SGI3", 4); /* there are varieties of UV3 */ |
159 | if (is_uv1 || is_uv2 || is_uv3) { | |
2a919596 | 160 | uv_hub_info->hub_revision = |
b15cc4a1 MT |
161 | (is_uv1 ? UV1_HUB_REVISION_BASE : |
162 | (is_uv2 ? UV2_HUB_REVISION_BASE : | |
163 | UV3_HUB_REVISION_BASE)); | |
d8850ba4 | 164 | pnodeid = early_get_pnodeid(); |
0520bd84 | 165 | early_get_apic_pnode_shift(); |
fd12a0d6 | 166 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
78c06176 | 167 | x86_platform.nmi_init = uv_nmi_init; |
1b9b89e7 YL |
168 | if (!strcmp(oem_table_id, "UVL")) |
169 | uv_system_type = UV_LEGACY_APIC; | |
170 | else if (!strcmp(oem_table_id, "UVX")) | |
171 | uv_system_type = UV_X2APIC; | |
172 | else if (!strcmp(oem_table_id, "UVH")) { | |
0a3aee0d | 173 | __this_cpu_write(x2apic_extra_bits, |
72eb6a79 | 174 | pnodeid << uvh_apicid.s.pnode_shift); |
1b9b89e7 | 175 | uv_system_type = UV_NON_UNIQUE_APIC; |
8191c9f6 | 176 | uv_set_apicid_hibit(); |
1b9b89e7 YL |
177 | return 1; |
178 | } | |
179 | } | |
180 | return 0; | |
181 | } | |
182 | ||
183 | enum uv_system_type get_uv_system_type(void) | |
184 | { | |
185 | return uv_system_type; | |
186 | } | |
187 | ||
188 | int is_uv_system(void) | |
189 | { | |
190 | return uv_system_type != UV_NONE; | |
191 | } | |
8067794b | 192 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 193 | |
ac23d4ee JS |
194 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
195 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
196 | ||
197 | struct uv_blade_info *uv_blade_info; | |
198 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
199 | ||
200 | short *uv_node_to_blade; | |
201 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
202 | ||
203 | short *uv_cpu_to_blade; | |
204 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
205 | ||
206 | short uv_possible_blades; | |
207 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
208 | ||
7019cc2d RA |
209 | unsigned long sn_rtc_cycles_per_second; |
210 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
211 | ||
667c5296 | 212 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee | 213 | { |
0b1da1c8 | 214 | #ifdef CONFIG_SMP |
ac23d4ee | 215 | unsigned long val; |
9f5314fb | 216 | int pnode; |
ac23d4ee | 217 | |
9f5314fb | 218 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 219 | phys_apicid |= uv_apicid_hibits; |
ac23d4ee JS |
220 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
221 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 222 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 223 | APIC_DM_INIT; |
9f5314fb | 224 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
225 | |
226 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
227 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 228 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 229 | APIC_DM_STARTUP; |
9f5314fb | 230 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf YL |
231 | |
232 | atomic_set(&init_deasserted, 1); | |
0b1da1c8 | 233 | #endif |
ac23d4ee JS |
234 | return 0; |
235 | } | |
236 | ||
237 | static void uv_send_IPI_one(int cpu, int vector) | |
238 | { | |
66666e50 | 239 | unsigned long apicid; |
9f5314fb | 240 | int pnode; |
ac23d4ee | 241 | |
1e0b5d00 | 242 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 243 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 244 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
245 | } |
246 | ||
bcda016e | 247 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
248 | { |
249 | unsigned int cpu; | |
250 | ||
bcda016e | 251 | for_each_cpu(cpu, mask) |
e7986739 MT |
252 | uv_send_IPI_one(cpu, vector); |
253 | } | |
254 | ||
bcda016e | 255 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 256 | { |
e7986739 | 257 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 258 | unsigned int cpu; |
e7986739 | 259 | |
dac5f412 | 260 | for_each_cpu(cpu, mask) { |
e7986739 | 261 | if (cpu != this_cpu) |
ac23d4ee | 262 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 263 | } |
ac23d4ee JS |
264 | } |
265 | ||
266 | static void uv_send_IPI_allbutself(int vector) | |
267 | { | |
e7986739 | 268 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 269 | unsigned int cpu; |
ac23d4ee | 270 | |
dac5f412 | 271 | for_each_online_cpu(cpu) { |
e7986739 MT |
272 | if (cpu != this_cpu) |
273 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 274 | } |
ac23d4ee JS |
275 | } |
276 | ||
277 | static void uv_send_IPI_all(int vector) | |
278 | { | |
bcda016e | 279 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
280 | } |
281 | ||
b7157acf SP |
282 | static int uv_apic_id_valid(int apicid) |
283 | { | |
284 | return 1; | |
285 | } | |
286 | ||
ac23d4ee JS |
287 | static int uv_apic_id_registered(void) |
288 | { | |
289 | return 1; | |
290 | } | |
291 | ||
277d1f58 | 292 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
293 | { |
294 | } | |
295 | ||
ff164324 | 296 | static int |
debccb3e | 297 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
298 | const struct cpumask *andmask, |
299 | unsigned int *apicid) | |
95d313cf | 300 | { |
ea3807ea | 301 | int unsigned cpu; |
95d313cf MT |
302 | |
303 | /* | |
304 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
305 | * May as well be the first. | |
306 | */ | |
debccb3e | 307 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
308 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
309 | break; | |
debccb3e | 310 | } |
ff164324 | 311 | |
ea3807ea | 312 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
313 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
314 | return 0; | |
a5a39156 | 315 | } |
ea3807ea AG |
316 | |
317 | return -EINVAL; | |
95d313cf MT |
318 | } |
319 | ||
ca6c8ed4 | 320 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
321 | { |
322 | unsigned int id; | |
323 | ||
324 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 325 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
326 | |
327 | return id; | |
328 | } | |
329 | ||
1b9b89e7 | 330 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
331 | { |
332 | unsigned long x; | |
333 | ||
334 | /* maskout x2apic_extra_bits ? */ | |
335 | x = id; | |
336 | return x; | |
337 | } | |
338 | ||
339 | static unsigned int uv_read_apic_id(void) | |
340 | { | |
341 | ||
ca6c8ed4 | 342 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
343 | } |
344 | ||
d4c9a9f3 | 345 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 346 | { |
0c81c746 | 347 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
348 | } |
349 | ||
ac23d4ee JS |
350 | static void uv_send_IPI_self(int vector) |
351 | { | |
352 | apic_write(APIC_SELF_IPI, vector); | |
353 | } | |
ac23d4ee | 354 | |
9ebd680b SS |
355 | static int uv_probe(void) |
356 | { | |
357 | return apic == &apic_x2apic_uv_x; | |
358 | } | |
359 | ||
1a8880a1 | 360 | static struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
361 | |
362 | .name = "UV large system", | |
9ebd680b | 363 | .probe = uv_probe, |
c7967329 | 364 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
b7157acf | 365 | .apic_id_valid = uv_apic_id_valid, |
c7967329 IM |
366 | .apic_id_registered = uv_apic_id_registered, |
367 | ||
f8987a10 | 368 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 369 | .irq_dest_mode = 0, /* physical */ |
c7967329 | 370 | |
bf721d3a | 371 | .target_cpus = online_target_cpus, |
08125d3e | 372 | .disable_esr = 0, |
bdb1a9b6 | 373 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
374 | .check_apicid_used = NULL, |
375 | .check_apicid_present = NULL, | |
376 | ||
9d8e1066 | 377 | .vector_allocation_domain = default_vector_allocation_domain, |
c7967329 IM |
378 | .init_apic_ldr = uv_init_apic_ldr, |
379 | ||
380 | .ioapic_phys_id_map = NULL, | |
381 | .setup_apic_routing = NULL, | |
382 | .multi_timer_check = NULL, | |
a21769a4 | 383 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
384 | .apicid_to_cpu_present = NULL, |
385 | .setup_portio_remap = NULL, | |
a27a6210 | 386 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 387 | .enable_apic_mode = NULL, |
d4c9a9f3 | 388 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
389 | .mps_oem_check = NULL, |
390 | ||
ca6c8ed4 | 391 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
392 | .set_apic_id = set_apic_id, |
393 | .apic_id_mask = 0xFFFFFFFFu, | |
394 | ||
c7967329 IM |
395 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, |
396 | ||
397 | .send_IPI_mask = uv_send_IPI_mask, | |
398 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
399 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
400 | .send_IPI_all = uv_send_IPI_all, | |
401 | .send_IPI_self = uv_send_IPI_self, | |
402 | ||
1f5bcabf | 403 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
abfa584c IM |
404 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
405 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
c7967329 IM |
406 | .wait_for_init_deassert = NULL, |
407 | .smp_callin_clear_local_apic = NULL, | |
c7967329 | 408 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
409 | |
410 | .read = native_apic_msr_read, | |
411 | .write = native_apic_msr_write, | |
0ab711ae | 412 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
413 | .icr_read = native_x2apic_icr_read, |
414 | .icr_write = native_x2apic_icr_write, | |
415 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
416 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
417 | }; |
418 | ||
9f5314fb | 419 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 420 | { |
16ee8db6 | 421 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
422 | } |
423 | ||
424 | /* | |
425 | * Called on boot cpu. | |
426 | */ | |
9f5314fb JS |
427 | static __init int boot_pnode_to_blade(int pnode) |
428 | { | |
429 | int blade; | |
430 | ||
431 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
432 | if (pnode == uv_blade_info[blade].pnode) | |
433 | return blade; | |
434 | BUG(); | |
435 | } | |
436 | ||
437 | struct redir_addr { | |
438 | unsigned long redirect; | |
439 | unsigned long alias; | |
440 | }; | |
441 | ||
442 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
443 | ||
444 | static __initdata struct redir_addr redir_addrs[] = { | |
62b0cfc2 JS |
445 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, |
446 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, | |
447 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, | |
9f5314fb JS |
448 | }; |
449 | ||
450 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
451 | { | |
62b0cfc2 | 452 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb JS |
453 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
454 | int i; | |
455 | ||
456 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
457 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
036ed8ba | 458 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb JS |
459 | *size = (1UL << alias.s.m_alias); |
460 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
461 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
462 | return; | |
463 | } | |
464 | } | |
036ed8ba | 465 | *base = *size = 0; |
9f5314fb JS |
466 | } |
467 | ||
83f5d894 JS |
468 | enum map_type {map_wb, map_uc}; |
469 | ||
fcfbb2b5 MT |
470 | static __init void map_high(char *id, unsigned long base, int pshift, |
471 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
472 | { |
473 | unsigned long bytes, paddr; | |
474 | ||
fcfbb2b5 MT |
475 | paddr = base << pshift; |
476 | bytes = (1UL << bshift) * (max_pnode + 1); | |
b15cc4a1 MT |
477 | if (!paddr) { |
478 | pr_info("UV: Map %s_HI base address NULL\n", id); | |
479 | return; | |
480 | } | |
879d5ad0 | 481 | pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); |
83f5d894 JS |
482 | if (map_type == map_uc) |
483 | init_extra_mapping_uc(paddr, bytes); | |
484 | else | |
485 | init_extra_mapping_wb(paddr, bytes); | |
83f5d894 | 486 | } |
b15cc4a1 | 487 | |
879d5ad0 DS |
488 | static __init void map_gru_distributed(unsigned long c) |
489 | { | |
490 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
491 | u64 paddr; | |
492 | unsigned long bytes; | |
493 | int nid; | |
494 | ||
495 | gru.v = c; | |
496 | /* only base bits 42:28 relevant in dist mode */ | |
497 | gru_dist_base = gru.v & 0x000007fff0000000UL; | |
498 | if (!gru_dist_base) { | |
499 | pr_info("UV: Map GRU_DIST base address NULL\n"); | |
500 | return; | |
501 | } | |
502 | bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
503 | gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1); | |
504 | gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1); | |
505 | gru_dist_base &= gru_dist_lmask; /* Clear bits above M */ | |
506 | for_each_online_node(nid) { | |
507 | paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) | | |
508 | gru_dist_base; | |
509 | init_extra_mapping_wb(paddr, bytes); | |
510 | gru_first_node_paddr = min(paddr, gru_first_node_paddr); | |
511 | gru_last_node_paddr = max(paddr, gru_last_node_paddr); | |
512 | } | |
513 | /* Save upper (63:M) bits of address only for is_GRU_range */ | |
514 | gru_first_node_paddr &= gru_dist_umask; | |
515 | gru_last_node_paddr &= gru_dist_umask; | |
516 | pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", | |
517 | gru_dist_base, gru_first_node_paddr, gru_last_node_paddr); | |
518 | } | |
519 | ||
83f5d894 JS |
520 | static __init void map_gru_high(int max_pnode) |
521 | { | |
522 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
523 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
524 | ||
525 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
879d5ad0 | 526 | if (!gru.s.enable) { |
b15cc4a1 | 527 | pr_info("UV: GRU disabled\n"); |
879d5ad0 DS |
528 | return; |
529 | } | |
530 | ||
531 | if (is_uv3_hub() && gru.s3.mode) { | |
532 | map_gru_distributed(gru.v); | |
533 | return; | |
fd12a0d6 | 534 | } |
879d5ad0 DS |
535 | map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); |
536 | gru_start_paddr = ((u64)gru.s.base << shift); | |
537 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); | |
83f5d894 JS |
538 | } |
539 | ||
daf7b9c9 JS |
540 | static __init void map_mmr_high(int max_pnode) |
541 | { | |
542 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
543 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
544 | ||
545 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
546 | if (mmr.s.enable) | |
fcfbb2b5 | 547 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
b15cc4a1 MT |
548 | else |
549 | pr_info("UV: MMR disabled\n"); | |
550 | } | |
551 | ||
552 | /* | |
553 | * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY | |
554 | * and REDIRECT MMR regs are exactly the same on UV3. | |
555 | */ | |
556 | struct mmioh_config { | |
557 | unsigned long overlay; | |
558 | unsigned long redirect; | |
559 | char *id; | |
560 | }; | |
561 | ||
562 | static __initdata struct mmioh_config mmiohs[] = { | |
563 | { | |
564 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, | |
565 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, | |
566 | "MMIOH0" | |
567 | }, | |
568 | { | |
569 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, | |
570 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, | |
571 | "MMIOH1" | |
572 | }, | |
573 | }; | |
574 | ||
575 | static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) | |
576 | { | |
577 | union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; | |
578 | unsigned long mmr; | |
579 | unsigned long base; | |
580 | int i, n, shift, m_io, max_io; | |
581 | int nasid, lnasid, fi, li; | |
582 | char *id; | |
583 | ||
584 | id = mmiohs[index].id; | |
585 | overlay.v = uv_read_local_mmr(mmiohs[index].overlay); | |
586 | pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", | |
587 | id, overlay.v, overlay.s3.base, overlay.s3.m_io); | |
588 | if (!overlay.s3.enable) { | |
589 | pr_info("UV: %s disabled\n", id); | |
590 | return; | |
591 | } | |
592 | ||
593 | shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; | |
594 | base = (unsigned long)overlay.s3.base; | |
595 | m_io = overlay.s3.m_io; | |
596 | mmr = mmiohs[index].redirect; | |
597 | n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; | |
598 | min_pnode *= 2; /* convert to NASID */ | |
599 | max_pnode *= 2; | |
600 | max_io = lnasid = fi = li = -1; | |
601 | ||
602 | for (i = 0; i < n; i++) { | |
603 | union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; | |
604 | ||
605 | redirect.v = uv_read_local_mmr(mmr + i * 8); | |
606 | nasid = redirect.s3.nasid; | |
607 | if (nasid < min_pnode || max_pnode < nasid) | |
608 | nasid = -1; /* invalid NASID */ | |
609 | ||
610 | if (nasid == lnasid) { | |
611 | li = i; | |
612 | if (i != n-1) /* last entry check */ | |
613 | continue; | |
614 | } | |
615 | ||
616 | /* check if we have a cached (or last) redirect to print */ | |
617 | if (lnasid != -1 || (i == n-1 && nasid != -1)) { | |
618 | unsigned long addr1, addr2; | |
619 | int f, l; | |
620 | ||
621 | if (lnasid == -1) { | |
622 | f = l = i; | |
623 | lnasid = nasid; | |
624 | } else { | |
625 | f = fi; | |
626 | l = li; | |
627 | } | |
628 | addr1 = (base << shift) + | |
629 | f * (unsigned long)(1 << m_io); | |
630 | addr2 = (base << shift) + | |
631 | (l + 1) * (unsigned long)(1 << m_io); | |
632 | pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", | |
633 | id, fi, li, lnasid, addr1, addr2); | |
634 | if (max_io < l) | |
635 | max_io = l; | |
636 | } | |
637 | fi = li = i; | |
638 | lnasid = nasid; | |
639 | } | |
640 | ||
641 | pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", | |
642 | id, base, shift, m_io, max_io); | |
643 | ||
644 | if (max_io >= 0) | |
645 | map_high(id, base, shift, m_io, max_io, map_uc); | |
daf7b9c9 JS |
646 | } |
647 | ||
b15cc4a1 | 648 | static __init void map_mmioh_high(int min_pnode, int max_pnode) |
83f5d894 JS |
649 | { |
650 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
b15cc4a1 MT |
651 | unsigned long mmr, base; |
652 | int shift, enable, m_io, n_io; | |
83f5d894 | 653 | |
b15cc4a1 MT |
654 | if (is_uv3_hub()) { |
655 | /* Map both MMIOH Regions */ | |
656 | map_mmioh_high_uv3(0, min_pnode, max_pnode); | |
657 | map_mmioh_high_uv3(1, min_pnode, max_pnode); | |
658 | return; | |
2a919596 | 659 | } |
b15cc4a1 MT |
660 | |
661 | if (is_uv1_hub()) { | |
662 | mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
663 | shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
664 | mmioh.v = uv_read_local_mmr(mmr); | |
665 | enable = !!mmioh.s1.enable; | |
666 | base = mmioh.s1.base; | |
667 | m_io = mmioh.s1.m_io; | |
668 | n_io = mmioh.s1.n_io; | |
669 | } else if (is_uv2_hub()) { | |
670 | mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
2a919596 | 671 | shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; |
b15cc4a1 MT |
672 | mmioh.v = uv_read_local_mmr(mmr); |
673 | enable = !!mmioh.s2.enable; | |
674 | base = mmioh.s2.base; | |
675 | m_io = mmioh.s2.m_io; | |
676 | n_io = mmioh.s2.n_io; | |
677 | } else | |
678 | return; | |
679 | ||
680 | if (enable) { | |
681 | max_pnode &= (1 << n_io) - 1; | |
682 | pr_info( | |
683 | "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", | |
684 | base, shift, m_io, n_io, max_pnode); | |
685 | map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); | |
686 | } else { | |
687 | pr_info("UV: MMIOH disabled\n"); | |
2a919596 | 688 | } |
83f5d894 JS |
689 | } |
690 | ||
918bc960 JS |
691 | static __init void map_low_mmrs(void) |
692 | { | |
693 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
694 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
695 | } | |
696 | ||
7019cc2d RA |
697 | static __init void uv_rtc_init(void) |
698 | { | |
922402f1 RA |
699 | long status; |
700 | u64 ticks_per_sec; | |
7019cc2d | 701 | |
922402f1 RA |
702 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
703 | &ticks_per_sec); | |
704 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
705 | printk(KERN_WARNING |
706 | "unable to determine platform RTC clock frequency, " | |
707 | "guessing.\n"); | |
708 | /* BIOS gives wrong value for clock freq. so guess */ | |
709 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
710 | } else | |
711 | sn_rtc_cycles_per_second = ticks_per_sec; | |
712 | } | |
713 | ||
7f1baa06 MT |
714 | /* |
715 | * percpu heartbeat timer | |
716 | */ | |
717 | static void uv_heartbeat(unsigned long ignored) | |
718 | { | |
719 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
720 | unsigned char bits = uv_hub_info->scir.state; | |
721 | ||
722 | /* flip heartbeat bit */ | |
723 | bits ^= SCIR_CPU_HEARTBEAT; | |
724 | ||
69a72a0e MT |
725 | /* is this cpu idle? */ |
726 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
727 | bits &= ~SCIR_CPU_ACTIVITY; |
728 | else | |
729 | bits |= SCIR_CPU_ACTIVITY; | |
730 | ||
731 | /* update system controller interface reg */ | |
732 | uv_set_scir_bits(bits); | |
733 | ||
734 | /* enable next timer period */ | |
5c333864 | 735 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
736 | } |
737 | ||
738 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
739 | { | |
99659a92 | 740 | while (!uv_cpu_hub_info(cpu)->scir.enabled) { |
7f1baa06 MT |
741 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; |
742 | ||
743 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
744 | setup_timer(timer, uv_heartbeat, cpu); | |
745 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
746 | add_timer_on(timer, cpu); | |
747 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
7f1baa06 | 748 | |
99659a92 RK |
749 | /* also ensure that boot cpu is enabled */ |
750 | cpu = 0; | |
751 | } | |
7f1baa06 MT |
752 | } |
753 | ||
77be80e4 | 754 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
755 | static void __cpuinit uv_heartbeat_disable(int cpu) |
756 | { | |
757 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
758 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
759 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
760 | } | |
761 | uv_set_cpu_scir_bits(cpu, 0xff); | |
762 | } | |
763 | ||
7f1baa06 MT |
764 | /* |
765 | * cpu hotplug notifier | |
766 | */ | |
767 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
768 | unsigned long action, void *hcpu) | |
769 | { | |
770 | long cpu = (long)hcpu; | |
771 | ||
772 | switch (action) { | |
773 | case CPU_ONLINE: | |
774 | uv_heartbeat_enable(cpu); | |
775 | break; | |
776 | case CPU_DOWN_PREPARE: | |
777 | uv_heartbeat_disable(cpu); | |
778 | break; | |
779 | default: | |
780 | break; | |
781 | } | |
782 | return NOTIFY_OK; | |
783 | } | |
784 | ||
785 | static __init void uv_scir_register_cpu_notifier(void) | |
786 | { | |
787 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
788 | } | |
789 | ||
790 | #else /* !CONFIG_HOTPLUG_CPU */ | |
791 | ||
792 | static __init void uv_scir_register_cpu_notifier(void) | |
793 | { | |
794 | } | |
795 | ||
796 | static __init int uv_init_heartbeat(void) | |
797 | { | |
798 | int cpu; | |
799 | ||
800 | if (is_uv_system()) | |
801 | for_each_online_cpu(cpu) | |
802 | uv_heartbeat_enable(cpu); | |
803 | return 0; | |
804 | } | |
805 | ||
806 | late_initcall(uv_init_heartbeat); | |
807 | ||
808 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
809 | ||
841582ea MT |
810 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
811 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
7ad35cf2 | 812 | unsigned int command_bits, u32 flags) |
841582ea MT |
813 | { |
814 | int domain, bus, rc; | |
815 | ||
7ad35cf2 DA |
816 | PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", |
817 | pdev->devfn, decode, command_bits, flags); | |
841582ea | 818 | |
7ad35cf2 | 819 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
841582ea MT |
820 | return 0; |
821 | ||
822 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
823 | return 0; | |
824 | ||
825 | domain = pci_domain_nr(pdev->bus); | |
826 | bus = pdev->bus->number; | |
827 | ||
828 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
829 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
830 | ||
831 | return rc; | |
832 | } | |
833 | ||
8da077d6 JS |
834 | /* |
835 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 836 | * FIXME: hotplug not supported yet |
8da077d6 JS |
837 | */ |
838 | void __cpuinit uv_cpu_init(void) | |
839 | { | |
840 | /* CPU 0 initilization will be done via uv_system_init. */ | |
841 | if (!uv_blade_info) | |
842 | return; | |
843 | ||
844 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
845 | ||
846 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
847 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
848 | } | |
849 | ||
78c06176 RA |
850 | /* |
851 | * When NMI is received, print a stack trace. | |
852 | */ | |
9c48f1c6 | 853 | int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) |
78c06176 | 854 | { |
1d44e828 JS |
855 | unsigned long real_uv_nmi; |
856 | int bid; | |
857 | ||
78c06176 | 858 | /* |
1d44e828 JS |
859 | * Each blade has an MMR that indicates when an NMI has been sent |
860 | * to cpus on the blade. If an NMI is detected, atomically | |
861 | * clear the MMR and update a per-blade NMI count used to | |
862 | * cause each cpu on the blade to notice a new NMI. | |
863 | */ | |
864 | bid = uv_numa_blade_id(); | |
865 | real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); | |
866 | ||
867 | if (unlikely(real_uv_nmi)) { | |
868 | spin_lock(&uv_blade_info[bid].nmi_lock); | |
869 | real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); | |
870 | if (real_uv_nmi) { | |
871 | uv_blade_info[bid].nmi_count++; | |
872 | uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK); | |
873 | } | |
874 | spin_unlock(&uv_blade_info[bid].nmi_lock); | |
875 | } | |
876 | ||
877 | if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count)) | |
9c48f1c6 | 878 | return NMI_DONE; |
1d44e828 JS |
879 | |
880 | __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count; | |
881 | ||
882 | /* | |
883 | * Use a lock so only one cpu prints at a time. | |
884 | * This prevents intermixed output. | |
78c06176 RA |
885 | */ |
886 | spin_lock(&uv_nmi_lock); | |
1d44e828 | 887 | pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id()); |
78c06176 RA |
888 | dump_stack(); |
889 | spin_unlock(&uv_nmi_lock); | |
890 | ||
9c48f1c6 | 891 | return NMI_HANDLED; |
78c06176 RA |
892 | } |
893 | ||
78c06176 RA |
894 | void uv_register_nmi_notifier(void) |
895 | { | |
9c48f1c6 | 896 | if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) |
78c06176 RA |
897 | printk(KERN_WARNING "UV NMI handler failed to register\n"); |
898 | } | |
899 | ||
900 | void uv_nmi_init(void) | |
901 | { | |
902 | unsigned int value; | |
903 | ||
904 | /* | |
905 | * Unmask NMI on all cpus | |
906 | */ | |
907 | value = apic_read(APIC_LVT1) | APIC_DM_NMI; | |
908 | value &= ~APIC_LVT_MASKED; | |
909 | apic_write(APIC_LVT1, value); | |
910 | } | |
c4bd1fda MS |
911 | |
912 | void __init uv_system_init(void) | |
ac23d4ee | 913 | { |
62b0cfc2 | 914 | union uvh_rh_gam_config_mmr_u m_n_config; |
9f5314fb JS |
915 | union uvh_node_id_u node_id; |
916 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
b15cc4a1 MT |
917 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; |
918 | int gnode_extra, min_pnode = 999999, max_pnode = -1; | |
6a891a24 | 919 | unsigned long mmr_base, present, paddr; |
b15cc4a1 MT |
920 | unsigned short pnode_mask; |
921 | char *hub = (is_uv1_hub() ? "UV1" : | |
922 | (is_uv2_hub() ? "UV2" : | |
923 | "UV3")); | |
ac23d4ee | 924 | |
b15cc4a1 | 925 | pr_info("UV: Found %s hub\n", hub); |
918bc960 JS |
926 | map_low_mmrs(); |
927 | ||
62b0cfc2 | 928 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); |
9f5314fb JS |
929 | m_val = m_n_config.s.m_skt; |
930 | n_val = m_n_config.s.n_skt; | |
b15cc4a1 | 931 | pnode_mask = (1 << n_val) - 1; |
ac23d4ee JS |
932 | mmr_base = |
933 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
934 | ~UV_MMR_ENABLE; | |
d8850ba4 | 935 | |
c4ed3f04 JS |
936 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); |
937 | gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; | |
938 | gnode_upper = ((unsigned long)gnode_extra << m_val); | |
b15cc4a1 MT |
939 | pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x\n", |
940 | n_val, m_val, pnode_mask, gnode_upper, gnode_extra); | |
c4ed3f04 | 941 | |
b15cc4a1 | 942 | pr_info("UV: global MMR base 0x%lx\n", mmr_base); |
ac23d4ee | 943 | |
9f5314fb JS |
944 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
945 | uv_possible_blades += | |
946 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
da517a08 JS |
947 | |
948 | /* uv_num_possible_blades() is really the hub count */ | |
b15cc4a1 | 949 | pr_info("UV: Found %d blades, %d hubs\n", |
da517a08 JS |
950 | is_uv1_hub() ? uv_num_possible_blades() : |
951 | (uv_num_possible_blades() + 1) / 2, | |
952 | uv_num_possible_blades()); | |
ac23d4ee JS |
953 | |
954 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
1d44e828 | 955 | uv_blade_info = kzalloc(bytes, GFP_KERNEL); |
9a8709d4 | 956 | BUG_ON(!uv_blade_info); |
1d44e828 | 957 | |
6c7184b7 JS |
958 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
959 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 960 | |
9f5314fb JS |
961 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
962 | ||
ac23d4ee | 963 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 964 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 965 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
966 | memset(uv_node_to_blade, 255, bytes); |
967 | ||
968 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 969 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 970 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
971 | memset(uv_cpu_to_blade, 255, bytes); |
972 | ||
9f5314fb JS |
973 | blade = 0; |
974 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
975 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
976 | for (j = 0; j < 64; j++) { | |
977 | if (!test_bit(j, &present)) | |
978 | continue; | |
d8850ba4 | 979 | pnode = (i * 64 + j) & pnode_mask; |
36ac4b98 | 980 | uv_blade_info[blade].pnode = pnode; |
9f5314fb | 981 | uv_blade_info[blade].nr_possible_cpus = 0; |
ac23d4ee | 982 | uv_blade_info[blade].nr_online_cpus = 0; |
1d44e828 | 983 | spin_lock_init(&uv_blade_info[blade].nmi_lock); |
b15cc4a1 | 984 | min_pnode = min(pnode, min_pnode); |
36ac4b98 | 985 | max_pnode = max(pnode, max_pnode); |
9f5314fb | 986 | blade++; |
ac23d4ee | 987 | } |
9f5314fb | 988 | } |
ac23d4ee | 989 | |
7f594232 | 990 | uv_bios_init(); |
b76365a1 RA |
991 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
992 | &sn_region_size, &system_serial_number); | |
7019cc2d RA |
993 | uv_rtc_init(); |
994 | ||
9f5314fb | 995 | for_each_present_cpu(cpu) { |
39d30770 MT |
996 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
997 | ||
9f5314fb | 998 | nid = cpu_to_node(cpu); |
c8f730b1 RA |
999 | /* |
1000 | * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); | |
1001 | */ | |
d8850ba4 | 1002 | uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; |
c8f730b1 | 1003 | uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; |
2a919596 JS |
1004 | uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; |
1005 | ||
6a469e46 JS |
1006 | uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; |
1007 | uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ? | |
1008 | (m_val == 40 ? 40 : 39) : m_val; | |
1009 | ||
39d30770 | 1010 | pnode = uv_apicid_to_pnode(apicid); |
9f5314fb JS |
1011 | blade = boot_pnode_to_blade(pnode); |
1012 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
1013 | uv_blade_info[blade].nr_possible_cpus++; | |
1014 | ||
6c7184b7 JS |
1015 | /* Any node on the blade, else will contain -1. */ |
1016 | uv_blade_info[blade].memory_nid = nid; | |
1017 | ||
9f5314fb | 1018 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; |
189f67c4 | 1019 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb | 1020 | uv_cpu_hub_info(cpu)->m_val = m_val; |
036ed8ba | 1021 | uv_cpu_hub_info(cpu)->n_val = n_val; |
ac23d4ee JS |
1022 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
1023 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb | 1024 | uv_cpu_hub_info(cpu)->pnode = pnode; |
036ed8ba | 1025 | uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; |
9f5314fb | 1026 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; |
c4ed3f04 | 1027 | uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; |
ac23d4ee | 1028 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 1029 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
39d30770 | 1030 | uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); |
ac23d4ee JS |
1031 | uv_node_to_blade[nid] = blade; |
1032 | uv_cpu_to_blade[cpu] = blade; | |
ac23d4ee | 1033 | } |
83f5d894 | 1034 | |
6a891a24 JS |
1035 | /* Add blade/pnode info for nodes without cpus */ |
1036 | for_each_online_node(nid) { | |
1037 | if (uv_node_to_blade[nid] >= 0) | |
1038 | continue; | |
1039 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
6a469e46 | 1040 | pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); |
6a891a24 JS |
1041 | blade = boot_pnode_to_blade(pnode); |
1042 | uv_node_to_blade[nid] = blade; | |
1043 | } | |
1044 | ||
83f5d894 | 1045 | map_gru_high(max_pnode); |
daf7b9c9 | 1046 | map_mmr_high(max_pnode); |
b15cc4a1 | 1047 | map_mmioh_high(min_pnode, max_pnode); |
ac23d4ee | 1048 | |
8da077d6 | 1049 | uv_cpu_init(); |
7f1baa06 | 1050 | uv_scir_register_cpu_notifier(); |
78c06176 | 1051 | uv_register_nmi_notifier(); |
a3d732f9 | 1052 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
1053 | |
1054 | /* register Legacy VGA I/O redirection handler */ | |
1055 | pci_register_set_vga_state(uv_set_vga_state); | |
818987e9 CW |
1056 | |
1057 | /* | |
1058 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
1059 | * EFI is not enabled in the kdump kernel. | |
1060 | */ | |
1061 | if (is_kdump_kernel()) | |
1062 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 1063 | } |
107e0e0c SS |
1064 | |
1065 | apic_driver(apic_x2apic_uv_x); |