Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
696e409d | 39 | #include <linux/edac_mce.h> |
b77e70bf | 40 | #include <linux/irq_work.h> |
e9eee03e | 41 | |
d88203d1 | 42 | #include <asm/processor.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
2aa2b50d IM |
48 | static DEFINE_MUTEX(mce_read_mutex); |
49 | ||
f56e8a07 | 50 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 51 | rcu_dereference_index_check((p), \ |
f56e8a07 PM |
52 | rcu_read_lock_sched_held() || \ |
53 | lockdep_is_held(&mce_read_mutex)) | |
54 | ||
8968f9d3 HS |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/mce.h> | |
57 | ||
4e5b3e69 | 58 | int mce_disabled __read_mostly; |
04b2b1a4 | 59 | |
e9eee03e | 60 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 61 | |
3c079792 AK |
62 | #define SPINUNIT 100 /* 100ns */ |
63 | ||
553f265f AK |
64 | atomic_t mce_entry; |
65 | ||
01ca79f1 AK |
66 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
67 | ||
bd78432c TH |
68 | /* |
69 | * Tolerant levels: | |
70 | * 0: always panic on uncorrected errors, log corrected errors | |
71 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
72 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
73 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
74 | */ | |
4e5b3e69 HS |
75 | static int tolerant __read_mostly = 1; |
76 | static int banks __read_mostly; | |
4e5b3e69 HS |
77 | static int rip_msr __read_mostly; |
78 | static int mce_bootlog __read_mostly = -1; | |
79 | static int monarch_timeout __read_mostly = -1; | |
80 | static int mce_panic_timeout __read_mostly; | |
81 | static int mce_dont_log_ce __read_mostly; | |
82 | int mce_cmci_disabled __read_mostly; | |
83 | int mce_ignore_ce __read_mostly; | |
84 | int mce_ser __read_mostly; | |
a98f0dd3 | 85 | |
cebe1820 AK |
86 | struct mce_bank *mce_banks __read_mostly; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
e02e68d3 | 93 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
94 | static DEFINE_PER_CPU(struct mce, mces_seen); |
95 | static int cpu_missing; | |
96 | ||
fb253195 BP |
97 | /* |
98 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
99 | * MCE errors in a human-readable form. | |
100 | */ | |
101 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
102 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
103 | ||
ee031c31 AK |
104 | /* MCA banks polled by the period polling timer for corrected events */ |
105 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
106 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
107 | }; | |
108 | ||
9b1beaf2 AK |
109 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
110 | ||
b5f2fa4e AK |
111 | /* Do initial initialization of a struct mce */ |
112 | void mce_setup(struct mce *m) | |
113 | { | |
114 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 115 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 116 | rdtscll(m->tsc); |
8ee08347 AK |
117 | /* We hope get_seconds stays lockless */ |
118 | m->time = get_seconds(); | |
119 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
120 | m->cpuid = cpuid_eax(1); | |
121 | #ifdef CONFIG_SMP | |
122 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
123 | #endif | |
124 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
125 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
126 | } |
127 | ||
ea149b36 AK |
128 | DEFINE_PER_CPU(struct mce, injectm); |
129 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
130 | ||
1da177e4 LT |
131 | /* |
132 | * Lockless MCE logging infrastructure. | |
133 | * This avoids deadlocks on printk locks without having to break locks. Also | |
134 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
135 | */ | |
136 | ||
231fd906 | 137 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
138 | .signature = MCE_LOG_SIGNATURE, |
139 | .len = MCE_LOG_LEN, | |
140 | .recordlen = sizeof(struct mce), | |
d88203d1 | 141 | }; |
1da177e4 LT |
142 | |
143 | void mce_log(struct mce *mce) | |
144 | { | |
145 | unsigned next, entry; | |
e9eee03e | 146 | |
8968f9d3 HS |
147 | /* Emit the trace record: */ |
148 | trace_mce_record(mce); | |
149 | ||
1da177e4 | 150 | mce->finished = 0; |
7644143c | 151 | wmb(); |
1da177e4 | 152 | for (;;) { |
f56e8a07 | 153 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 154 | for (;;) { |
696e409d MCC |
155 | /* |
156 | * If edac_mce is enabled, it will check the error type | |
157 | * and will process it, if it is a known error. | |
158 | * Otherwise, the error will be sent through mcelog | |
159 | * interface | |
160 | */ | |
161 | if (edac_mce_parse(mce)) | |
162 | return; | |
163 | ||
e9eee03e IM |
164 | /* |
165 | * When the buffer fills up discard new entries. | |
166 | * Assume that the earlier errors are the more | |
167 | * interesting ones: | |
168 | */ | |
673242c1 | 169 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
170 | set_bit(MCE_OVERFLOW, |
171 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
172 | return; |
173 | } | |
e9eee03e | 174 | /* Old left over entry. Skip: */ |
673242c1 AK |
175 | if (mcelog.entry[entry].finished) { |
176 | entry++; | |
177 | continue; | |
178 | } | |
7644143c | 179 | break; |
1da177e4 | 180 | } |
1da177e4 LT |
181 | smp_rmb(); |
182 | next = entry + 1; | |
183 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
184 | break; | |
185 | } | |
186 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 187 | wmb(); |
1da177e4 | 188 | mcelog.entry[entry].finished = 1; |
7644143c | 189 | wmb(); |
1da177e4 | 190 | |
a0189c70 | 191 | mce->finished = 1; |
1020bcbc | 192 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
193 | } |
194 | ||
77e26cca | 195 | static void print_mce(struct mce *m) |
1da177e4 | 196 | { |
dffa4b2f BP |
197 | int ret = 0; |
198 | ||
a2d7b0d4 | 199 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 200 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 201 | |
65ea5b03 | 202 | if (m->ip) { |
a2d7b0d4 | 203 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
204 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
205 | m->cs, m->ip); | |
206 | ||
1da177e4 | 207 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 208 | print_symbol("{%s}", m->ip); |
f436f8bb | 209 | pr_cont("\n"); |
1da177e4 | 210 | } |
f436f8bb | 211 | |
a2d7b0d4 | 212 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 213 | if (m->addr) |
f436f8bb | 214 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 215 | if (m->misc) |
f436f8bb | 216 | pr_cont("MISC %llx ", m->misc); |
549d042d | 217 | |
f436f8bb | 218 | pr_cont("\n"); |
a2d7b0d4 | 219 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
f436f8bb IM |
220 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); |
221 | ||
222 | /* | |
223 | * Print out human-readable details about the MCE error, | |
fb253195 | 224 | * (if the CPU has an implementation for that) |
f436f8bb | 225 | */ |
dffa4b2f BP |
226 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
227 | if (ret == NOTIFY_STOP) | |
228 | return; | |
229 | ||
230 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
231 | } |
232 | ||
f94b61c2 AK |
233 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
234 | ||
235 | static atomic_t mce_paniced; | |
236 | ||
bf783f9f HY |
237 | static int fake_panic; |
238 | static atomic_t mce_fake_paniced; | |
239 | ||
f94b61c2 AK |
240 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
241 | static void wait_for_panic(void) | |
242 | { | |
243 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 244 | |
f94b61c2 AK |
245 | preempt_disable(); |
246 | local_irq_enable(); | |
247 | while (timeout-- > 0) | |
248 | udelay(1); | |
29b0f591 AK |
249 | if (panic_timeout == 0) |
250 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
251 | panic("Panicing machine check CPU died"); |
252 | } | |
253 | ||
bd19a5e6 | 254 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 255 | { |
482908b4 | 256 | int i, apei_err = 0; |
e02e68d3 | 257 | |
bf783f9f HY |
258 | if (!fake_panic) { |
259 | /* | |
260 | * Make sure only one CPU runs in machine check panic | |
261 | */ | |
262 | if (atomic_inc_return(&mce_paniced) > 1) | |
263 | wait_for_panic(); | |
264 | barrier(); | |
f94b61c2 | 265 | |
bf783f9f HY |
266 | bust_spinlocks(1); |
267 | console_verbose(); | |
268 | } else { | |
269 | /* Don't log too much for fake panic */ | |
270 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
271 | return; | |
272 | } | |
a0189c70 | 273 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 274 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 275 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
276 | if (!(m->status & MCI_STATUS_VAL)) |
277 | continue; | |
482908b4 | 278 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 279 | print_mce(m); |
482908b4 HY |
280 | if (!apei_err) |
281 | apei_err = apei_write_mce(m); | |
282 | } | |
a0189c70 AK |
283 | } |
284 | /* Now print uncorrected but with the final one last */ | |
285 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
286 | struct mce *m = &mcelog.entry[i]; | |
287 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 288 | continue; |
77e26cca HS |
289 | if (!(m->status & MCI_STATUS_UC)) |
290 | continue; | |
482908b4 | 291 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 292 | print_mce(m); |
482908b4 HY |
293 | if (!apei_err) |
294 | apei_err = apei_write_mce(m); | |
295 | } | |
1da177e4 | 296 | } |
482908b4 | 297 | if (final) { |
77e26cca | 298 | print_mce(final); |
482908b4 HY |
299 | if (!apei_err) |
300 | apei_err = apei_write_mce(final); | |
301 | } | |
3c079792 | 302 | if (cpu_missing) |
a2d7b0d4 | 303 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 304 | if (exp) |
a2d7b0d4 | 305 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
306 | if (!fake_panic) { |
307 | if (panic_timeout == 0) | |
308 | panic_timeout = mce_panic_timeout; | |
309 | panic(msg); | |
310 | } else | |
a2d7b0d4 | 311 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 312 | } |
1da177e4 | 313 | |
ea149b36 AK |
314 | /* Support code for software error injection */ |
315 | ||
316 | static int msr_to_offset(u32 msr) | |
317 | { | |
0a3aee0d | 318 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 319 | |
ea149b36 AK |
320 | if (msr == rip_msr) |
321 | return offsetof(struct mce, ip); | |
a2d32bcb | 322 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 323 | return offsetof(struct mce, status); |
a2d32bcb | 324 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 325 | return offsetof(struct mce, addr); |
a2d32bcb | 326 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
327 | return offsetof(struct mce, misc); |
328 | if (msr == MSR_IA32_MCG_STATUS) | |
329 | return offsetof(struct mce, mcgstatus); | |
330 | return -1; | |
331 | } | |
332 | ||
5f8c1a54 AK |
333 | /* MSR access wrappers used for error injection */ |
334 | static u64 mce_rdmsrl(u32 msr) | |
335 | { | |
336 | u64 v; | |
11868a2d | 337 | |
0a3aee0d | 338 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 339 | int offset = msr_to_offset(msr); |
11868a2d | 340 | |
ea149b36 AK |
341 | if (offset < 0) |
342 | return 0; | |
343 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
344 | } | |
11868a2d IM |
345 | |
346 | if (rdmsrl_safe(msr, &v)) { | |
347 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
348 | /* | |
349 | * Return zero in case the access faulted. This should | |
350 | * not happen normally but can happen if the CPU does | |
351 | * something weird, or if the code is buggy. | |
352 | */ | |
353 | v = 0; | |
354 | } | |
355 | ||
5f8c1a54 AK |
356 | return v; |
357 | } | |
358 | ||
359 | static void mce_wrmsrl(u32 msr, u64 v) | |
360 | { | |
0a3aee0d | 361 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 362 | int offset = msr_to_offset(msr); |
11868a2d | 363 | |
ea149b36 AK |
364 | if (offset >= 0) |
365 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
366 | return; | |
367 | } | |
5f8c1a54 AK |
368 | wrmsrl(msr, v); |
369 | } | |
370 | ||
b8325c5b HS |
371 | /* |
372 | * Collect all global (w.r.t. this processor) status about this machine | |
373 | * check into our "mce" struct so that we can use it later to assess | |
374 | * the severity of the problem as we read per-bank specific details. | |
375 | */ | |
376 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
377 | { | |
378 | mce_setup(m); | |
379 | ||
380 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
381 | if (regs) { | |
382 | /* | |
383 | * Get the address of the instruction at the time of | |
384 | * the machine check error. | |
385 | */ | |
386 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
387 | m->ip = regs->ip; | |
388 | m->cs = regs->cs; | |
389 | } | |
390 | /* Use accurate RIP reporting if available. */ | |
391 | if (rip_msr) | |
392 | m->ip = mce_rdmsrl(rip_msr); | |
393 | } | |
394 | } | |
395 | ||
9b1beaf2 AK |
396 | /* |
397 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
398 | * process context work function. This is vastly simplified because there's | |
399 | * only a single reader and a single writer. | |
400 | */ | |
401 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
402 | ||
403 | struct mce_ring { | |
404 | unsigned short start; | |
405 | unsigned short end; | |
406 | unsigned long ring[MCE_RING_SIZE]; | |
407 | }; | |
408 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
409 | ||
410 | /* Runs with CPU affinity in workqueue */ | |
411 | static int mce_ring_empty(void) | |
412 | { | |
413 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
414 | ||
415 | return r->start == r->end; | |
416 | } | |
417 | ||
418 | static int mce_ring_get(unsigned long *pfn) | |
419 | { | |
420 | struct mce_ring *r; | |
421 | int ret = 0; | |
422 | ||
423 | *pfn = 0; | |
424 | get_cpu(); | |
425 | r = &__get_cpu_var(mce_ring); | |
426 | if (r->start == r->end) | |
427 | goto out; | |
428 | *pfn = r->ring[r->start]; | |
429 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
430 | ret = 1; | |
431 | out: | |
432 | put_cpu(); | |
433 | return ret; | |
434 | } | |
435 | ||
436 | /* Always runs in MCE context with preempt off */ | |
437 | static int mce_ring_add(unsigned long pfn) | |
438 | { | |
439 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
440 | unsigned next; | |
441 | ||
442 | next = (r->end + 1) % MCE_RING_SIZE; | |
443 | if (next == r->start) | |
444 | return -1; | |
445 | r->ring[r->end] = pfn; | |
446 | wmb(); | |
447 | r->end = next; | |
448 | return 0; | |
449 | } | |
450 | ||
88ccbedd | 451 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 452 | { |
04b2b1a4 | 453 | if (mce_disabled) |
5b4408fd | 454 | return 0; |
3d1712c9 | 455 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
456 | } |
457 | ||
9b1beaf2 AK |
458 | static void mce_schedule_work(void) |
459 | { | |
460 | if (!mce_ring_empty()) { | |
461 | struct work_struct *work = &__get_cpu_var(mce_work); | |
462 | if (!work_pending(work)) | |
463 | schedule_work(work); | |
464 | } | |
465 | } | |
466 | ||
b77e70bf HS |
467 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
468 | ||
469 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 470 | { |
9ff36ee9 | 471 | mce_notify_irq(); |
9b1beaf2 | 472 | mce_schedule_work(); |
ccc3c319 | 473 | } |
ccc3c319 AK |
474 | |
475 | static void mce_report_event(struct pt_regs *regs) | |
476 | { | |
477 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 478 | mce_notify_irq(); |
9b1beaf2 AK |
479 | /* |
480 | * Triggering the work queue here is just an insurance | |
481 | * policy in case the syscall exit notify handler | |
482 | * doesn't run soon enough or ends up running on the | |
483 | * wrong CPU (can happen when audit sleeps) | |
484 | */ | |
485 | mce_schedule_work(); | |
ccc3c319 AK |
486 | return; |
487 | } | |
488 | ||
b77e70bf | 489 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
490 | } |
491 | ||
ca84f696 AK |
492 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
493 | ||
d88203d1 | 494 | /* |
b79109c3 AK |
495 | * Poll for corrected events or events that happened before reset. |
496 | * Those are just logged through /dev/mcelog. | |
497 | * | |
498 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
499 | * |
500 | * Note: spec recommends to panic for fatal unsignalled | |
501 | * errors here. However this would be quite problematic -- | |
502 | * we would need to reimplement the Monarch handling and | |
503 | * it would mess up the exclusion between exception handler | |
504 | * and poll hander -- * so we skip this for now. | |
505 | * These cases should not happen anyways, or only when the CPU | |
506 | * is already totally * confused. In this case it's likely it will | |
507 | * not fully execute the machine check handler either. | |
b79109c3 | 508 | */ |
ee031c31 | 509 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
510 | { |
511 | struct mce m; | |
512 | int i; | |
513 | ||
402af0d7 | 514 | percpu_inc(mce_poll_count); |
ca84f696 | 515 | |
b8325c5b | 516 | mce_gather_info(&m, NULL); |
b79109c3 | 517 | |
b79109c3 | 518 | for (i = 0; i < banks; i++) { |
cebe1820 | 519 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
520 | continue; |
521 | ||
522 | m.misc = 0; | |
523 | m.addr = 0; | |
524 | m.bank = i; | |
525 | m.tsc = 0; | |
526 | ||
527 | barrier(); | |
a2d32bcb | 528 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
529 | if (!(m.status & MCI_STATUS_VAL)) |
530 | continue; | |
531 | ||
532 | /* | |
ed7290d0 AK |
533 | * Uncorrected or signalled events are handled by the exception |
534 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
535 | * |
536 | * TBD do the same check for MCI_STATUS_EN here? | |
537 | */ | |
ed7290d0 AK |
538 | if (!(flags & MCP_UC) && |
539 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
540 | continue; |
541 | ||
542 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 543 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 544 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 545 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
546 | |
547 | if (!(flags & MCP_TIMESTAMP)) | |
548 | m.tsc = 0; | |
549 | /* | |
550 | * Don't get the IP here because it's unlikely to | |
551 | * have anything to do with the actual error location. | |
552 | */ | |
62fdac59 | 553 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c | 554 | mce_log(&m); |
98a5ae2d | 555 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m); |
5679af4c | 556 | } |
b79109c3 AK |
557 | |
558 | /* | |
559 | * Clear state for this bank. | |
560 | */ | |
a2d32bcb | 561 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
562 | } |
563 | ||
564 | /* | |
565 | * Don't clear MCG_STATUS here because it's only defined for | |
566 | * exceptions. | |
567 | */ | |
88921be3 AK |
568 | |
569 | sync_core(); | |
b79109c3 | 570 | } |
ea149b36 | 571 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 572 | |
bd19a5e6 AK |
573 | /* |
574 | * Do a quick check if any of the events requires a panic. | |
575 | * This decides if we keep the events around or clear them. | |
576 | */ | |
577 | static int mce_no_way_out(struct mce *m, char **msg) | |
578 | { | |
579 | int i; | |
580 | ||
581 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 582 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
583 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
584 | return 1; | |
585 | } | |
586 | return 0; | |
587 | } | |
588 | ||
3c079792 AK |
589 | /* |
590 | * Variable to establish order between CPUs while scanning. | |
591 | * Each CPU spins initially until executing is equal its number. | |
592 | */ | |
593 | static atomic_t mce_executing; | |
594 | ||
595 | /* | |
596 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
597 | */ | |
598 | static atomic_t mce_callin; | |
599 | ||
600 | /* | |
601 | * Check if a timeout waiting for other CPUs happened. | |
602 | */ | |
603 | static int mce_timed_out(u64 *t) | |
604 | { | |
605 | /* | |
606 | * The others already did panic for some reason. | |
607 | * Bail out like in a timeout. | |
608 | * rmb() to tell the compiler that system_state | |
609 | * might have been modified by someone else. | |
610 | */ | |
611 | rmb(); | |
612 | if (atomic_read(&mce_paniced)) | |
613 | wait_for_panic(); | |
614 | if (!monarch_timeout) | |
615 | goto out; | |
616 | if ((s64)*t < SPINUNIT) { | |
617 | /* CHECKME: Make panic default for 1 too? */ | |
618 | if (tolerant < 1) | |
619 | mce_panic("Timeout synchronizing machine check over CPUs", | |
620 | NULL, NULL); | |
621 | cpu_missing = 1; | |
622 | return 1; | |
623 | } | |
624 | *t -= SPINUNIT; | |
625 | out: | |
626 | touch_nmi_watchdog(); | |
627 | return 0; | |
628 | } | |
629 | ||
630 | /* | |
631 | * The Monarch's reign. The Monarch is the CPU who entered | |
632 | * the machine check handler first. It waits for the others to | |
633 | * raise the exception too and then grades them. When any | |
634 | * error is fatal panic. Only then let the others continue. | |
635 | * | |
636 | * The other CPUs entering the MCE handler will be controlled by the | |
637 | * Monarch. They are called Subjects. | |
638 | * | |
639 | * This way we prevent any potential data corruption in a unrecoverable case | |
640 | * and also makes sure always all CPU's errors are examined. | |
641 | * | |
680b6cfd | 642 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
643 | * space (not detected by any CPUs) In this case some external agent wants |
644 | * us to shut down, so panic too. | |
645 | * | |
646 | * The other CPUs might still decide to panic if the handler happens | |
647 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
648 | * state and won't corrupt anything by itself. It's ok to let the others | |
649 | * continue for a bit first. | |
650 | * | |
651 | * All the spin loops have timeouts; when a timeout happens a CPU | |
652 | * typically elects itself to be Monarch. | |
653 | */ | |
654 | static void mce_reign(void) | |
655 | { | |
656 | int cpu; | |
657 | struct mce *m = NULL; | |
658 | int global_worst = 0; | |
659 | char *msg = NULL; | |
660 | char *nmsg = NULL; | |
661 | ||
662 | /* | |
663 | * This CPU is the Monarch and the other CPUs have run | |
664 | * through their handlers. | |
665 | * Grade the severity of the errors of all the CPUs. | |
666 | */ | |
667 | for_each_possible_cpu(cpu) { | |
668 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
669 | &nmsg); | |
670 | if (severity > global_worst) { | |
671 | msg = nmsg; | |
672 | global_worst = severity; | |
673 | m = &per_cpu(mces_seen, cpu); | |
674 | } | |
675 | } | |
676 | ||
677 | /* | |
678 | * Cannot recover? Panic here then. | |
679 | * This dumps all the mces in the log buffer and stops the | |
680 | * other CPUs. | |
681 | */ | |
682 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 683 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
684 | |
685 | /* | |
686 | * For UC somewhere we let the CPU who detects it handle it. | |
687 | * Also must let continue the others, otherwise the handling | |
688 | * CPU could deadlock on a lock. | |
689 | */ | |
690 | ||
691 | /* | |
692 | * No machine check event found. Must be some external | |
693 | * source or one CPU is hung. Panic. | |
694 | */ | |
680b6cfd | 695 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
696 | mce_panic("Machine check from unknown source", NULL, NULL); |
697 | ||
698 | /* | |
699 | * Now clear all the mces_seen so that they don't reappear on | |
700 | * the next mce. | |
701 | */ | |
702 | for_each_possible_cpu(cpu) | |
703 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
704 | } | |
705 | ||
706 | static atomic_t global_nwo; | |
707 | ||
708 | /* | |
709 | * Start of Monarch synchronization. This waits until all CPUs have | |
710 | * entered the exception handler and then determines if any of them | |
711 | * saw a fatal event that requires panic. Then it executes them | |
712 | * in the entry order. | |
713 | * TBD double check parallel CPU hotunplug | |
714 | */ | |
7fb06fc9 | 715 | static int mce_start(int *no_way_out) |
3c079792 | 716 | { |
7fb06fc9 | 717 | int order; |
3c079792 AK |
718 | int cpus = num_online_cpus(); |
719 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
720 | ||
7fb06fc9 HS |
721 | if (!timeout) |
722 | return -1; | |
3c079792 | 723 | |
7fb06fc9 | 724 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
725 | /* |
726 | * global_nwo should be updated before mce_callin | |
727 | */ | |
728 | smp_wmb(); | |
a95436e4 | 729 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
730 | |
731 | /* | |
732 | * Wait for everyone. | |
733 | */ | |
734 | while (atomic_read(&mce_callin) != cpus) { | |
735 | if (mce_timed_out(&timeout)) { | |
736 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 737 | return -1; |
3c079792 AK |
738 | } |
739 | ndelay(SPINUNIT); | |
740 | } | |
741 | ||
184e1fdf HY |
742 | /* |
743 | * mce_callin should be read before global_nwo | |
744 | */ | |
745 | smp_rmb(); | |
3c079792 | 746 | |
7fb06fc9 HS |
747 | if (order == 1) { |
748 | /* | |
749 | * Monarch: Starts executing now, the others wait. | |
750 | */ | |
3c079792 | 751 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
752 | } else { |
753 | /* | |
754 | * Subject: Now start the scanning loop one by one in | |
755 | * the original callin order. | |
756 | * This way when there are any shared banks it will be | |
757 | * only seen by one CPU before cleared, avoiding duplicates. | |
758 | */ | |
759 | while (atomic_read(&mce_executing) < order) { | |
760 | if (mce_timed_out(&timeout)) { | |
761 | atomic_set(&global_nwo, 0); | |
762 | return -1; | |
763 | } | |
764 | ndelay(SPINUNIT); | |
765 | } | |
3c079792 AK |
766 | } |
767 | ||
768 | /* | |
7fb06fc9 | 769 | * Cache the global no_way_out state. |
3c079792 | 770 | */ |
7fb06fc9 HS |
771 | *no_way_out = atomic_read(&global_nwo); |
772 | ||
773 | return order; | |
3c079792 AK |
774 | } |
775 | ||
776 | /* | |
777 | * Synchronize between CPUs after main scanning loop. | |
778 | * This invokes the bulk of the Monarch processing. | |
779 | */ | |
780 | static int mce_end(int order) | |
781 | { | |
782 | int ret = -1; | |
783 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
784 | ||
785 | if (!timeout) | |
786 | goto reset; | |
787 | if (order < 0) | |
788 | goto reset; | |
789 | ||
790 | /* | |
791 | * Allow others to run. | |
792 | */ | |
793 | atomic_inc(&mce_executing); | |
794 | ||
795 | if (order == 1) { | |
796 | /* CHECKME: Can this race with a parallel hotplug? */ | |
797 | int cpus = num_online_cpus(); | |
798 | ||
799 | /* | |
800 | * Monarch: Wait for everyone to go through their scanning | |
801 | * loops. | |
802 | */ | |
803 | while (atomic_read(&mce_executing) <= cpus) { | |
804 | if (mce_timed_out(&timeout)) | |
805 | goto reset; | |
806 | ndelay(SPINUNIT); | |
807 | } | |
808 | ||
809 | mce_reign(); | |
810 | barrier(); | |
811 | ret = 0; | |
812 | } else { | |
813 | /* | |
814 | * Subject: Wait for Monarch to finish. | |
815 | */ | |
816 | while (atomic_read(&mce_executing) != 0) { | |
817 | if (mce_timed_out(&timeout)) | |
818 | goto reset; | |
819 | ndelay(SPINUNIT); | |
820 | } | |
821 | ||
822 | /* | |
823 | * Don't reset anything. That's done by the Monarch. | |
824 | */ | |
825 | return 0; | |
826 | } | |
827 | ||
828 | /* | |
829 | * Reset all global state. | |
830 | */ | |
831 | reset: | |
832 | atomic_set(&global_nwo, 0); | |
833 | atomic_set(&mce_callin, 0); | |
834 | barrier(); | |
835 | ||
836 | /* | |
837 | * Let others run again. | |
838 | */ | |
839 | atomic_set(&mce_executing, 0); | |
840 | return ret; | |
841 | } | |
842 | ||
9b1beaf2 AK |
843 | /* |
844 | * Check if the address reported by the CPU is in a format we can parse. | |
845 | * It would be possible to add code for most other cases, but all would | |
846 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 847 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
848 | */ |
849 | static int mce_usable_address(struct mce *m) | |
850 | { | |
851 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
852 | return 0; | |
2b90e77e | 853 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 854 | return 0; |
2b90e77e | 855 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
856 | return 0; |
857 | return 1; | |
858 | } | |
859 | ||
3c079792 AK |
860 | static void mce_clear_state(unsigned long *toclear) |
861 | { | |
862 | int i; | |
863 | ||
864 | for (i = 0; i < banks; i++) { | |
865 | if (test_bit(i, toclear)) | |
a2d32bcb | 866 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
867 | } |
868 | } | |
869 | ||
b79109c3 AK |
870 | /* |
871 | * The actual machine check handler. This only handles real | |
872 | * exceptions when something got corrupted coming in through int 18. | |
873 | * | |
874 | * This is executed in NMI context not subject to normal locking rules. This | |
875 | * implies that most kernel services cannot be safely used. Don't even | |
876 | * think about putting a printk in there! | |
3c079792 AK |
877 | * |
878 | * On Intel systems this is entered on all CPUs in parallel through | |
879 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
880 | * so be always careful when synchronizing with others. | |
1da177e4 | 881 | */ |
e9eee03e | 882 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 883 | { |
3c079792 | 884 | struct mce m, *final; |
1da177e4 | 885 | int i; |
3c079792 AK |
886 | int worst = 0; |
887 | int severity; | |
888 | /* | |
889 | * Establish sequential order between the CPUs entering the machine | |
890 | * check handler. | |
891 | */ | |
7fb06fc9 | 892 | int order; |
bd78432c TH |
893 | /* |
894 | * If no_way_out gets set, there is no safe way to recover from this | |
895 | * MCE. If tolerant is cranked up, we'll try anyway. | |
896 | */ | |
897 | int no_way_out = 0; | |
898 | /* | |
899 | * If kill_it gets set, there might be a way to recover from this | |
900 | * error. | |
901 | */ | |
902 | int kill_it = 0; | |
b79109c3 | 903 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 904 | char *msg = "Unknown"; |
1da177e4 | 905 | |
553f265f AK |
906 | atomic_inc(&mce_entry); |
907 | ||
402af0d7 | 908 | percpu_inc(mce_exception_count); |
01ca79f1 | 909 | |
b79109c3 | 910 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 911 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 912 | goto out; |
b79109c3 | 913 | if (!banks) |
32561696 | 914 | goto out; |
1da177e4 | 915 | |
b8325c5b | 916 | mce_gather_info(&m, regs); |
b5f2fa4e | 917 | |
3c079792 AK |
918 | final = &__get_cpu_var(mces_seen); |
919 | *final = m; | |
920 | ||
680b6cfd HS |
921 | no_way_out = mce_no_way_out(&m, &msg); |
922 | ||
1da177e4 LT |
923 | barrier(); |
924 | ||
ed7290d0 AK |
925 | /* |
926 | * When no restart IP must always kill or panic. | |
927 | */ | |
928 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
929 | kill_it = 1; | |
930 | ||
3c079792 AK |
931 | /* |
932 | * Go through all the banks in exclusion of the other CPUs. | |
933 | * This way we don't report duplicated events on shared banks | |
934 | * because the first one to see it will clear it. | |
935 | */ | |
7fb06fc9 | 936 | order = mce_start(&no_way_out); |
1da177e4 | 937 | for (i = 0; i < banks; i++) { |
b79109c3 | 938 | __clear_bit(i, toclear); |
cebe1820 | 939 | if (!mce_banks[i].ctl) |
1da177e4 | 940 | continue; |
d88203d1 TG |
941 | |
942 | m.misc = 0; | |
1da177e4 LT |
943 | m.addr = 0; |
944 | m.bank = i; | |
1da177e4 | 945 | |
a2d32bcb | 946 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
947 | if ((m.status & MCI_STATUS_VAL) == 0) |
948 | continue; | |
949 | ||
b79109c3 | 950 | /* |
ed7290d0 AK |
951 | * Non uncorrected or non signaled errors are handled by |
952 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 953 | */ |
ed7290d0 AK |
954 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
955 | !no_way_out) | |
b79109c3 AK |
956 | continue; |
957 | ||
958 | /* | |
959 | * Set taint even when machine check was not enabled. | |
960 | */ | |
961 | add_taint(TAINT_MACHINE_CHECK); | |
962 | ||
ed7290d0 | 963 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 964 | |
ed7290d0 AK |
965 | /* |
966 | * When machine check was for corrected handler don't touch, | |
967 | * unless we're panicing. | |
968 | */ | |
969 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
970 | continue; | |
971 | __set_bit(i, toclear); | |
972 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
973 | /* |
974 | * Machine check event was not enabled. Clear, but | |
975 | * ignore. | |
976 | */ | |
977 | continue; | |
1da177e4 LT |
978 | } |
979 | ||
ed7290d0 AK |
980 | /* |
981 | * Kill on action required. | |
982 | */ | |
983 | if (severity == MCE_AR_SEVERITY) | |
984 | kill_it = 1; | |
985 | ||
1da177e4 | 986 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 987 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 988 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 989 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 990 | |
9b1beaf2 AK |
991 | /* |
992 | * Action optional error. Queue address for later processing. | |
993 | * When the ring overflows we just ignore the AO error. | |
994 | * RED-PEN add some logging mechanism when | |
995 | * usable_address or mce_add_ring fails. | |
996 | * RED-PEN don't ignore overflow for tolerant == 0 | |
997 | */ | |
998 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
999 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1000 | ||
b79109c3 | 1001 | mce_log(&m); |
1da177e4 | 1002 | |
3c079792 AK |
1003 | if (severity > worst) { |
1004 | *final = m; | |
1005 | worst = severity; | |
1da177e4 | 1006 | } |
1da177e4 LT |
1007 | } |
1008 | ||
3c079792 AK |
1009 | if (!no_way_out) |
1010 | mce_clear_state(toclear); | |
1011 | ||
e9eee03e | 1012 | /* |
3c079792 AK |
1013 | * Do most of the synchronization with other CPUs. |
1014 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1015 | */ |
3c079792 AK |
1016 | if (mce_end(order) < 0) |
1017 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1018 | |
1019 | /* | |
1020 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1021 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1022 | * |
1023 | * This is mainly used in the case when the system doesn't | |
1024 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1025 | */ |
1026 | if (no_way_out && tolerant < 3) | |
ac960375 | 1027 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1028 | |
1029 | /* | |
1030 | * If the error seems to be unrecoverable, something should be | |
1031 | * done. Try to kill as little as possible. If we can kill just | |
1032 | * one task, do that. If the user has set the tolerance very | |
1033 | * high, don't try to do anything at all. | |
1034 | */ | |
bd78432c | 1035 | |
ed7290d0 AK |
1036 | if (kill_it && tolerant < 3) |
1037 | force_sig(SIGBUS, current); | |
1da177e4 | 1038 | |
e02e68d3 TH |
1039 | /* notify userspace ASAP */ |
1040 | set_thread_flag(TIF_MCE_NOTIFY); | |
1041 | ||
3c079792 AK |
1042 | if (worst > 0) |
1043 | mce_report_event(regs); | |
5f8c1a54 | 1044 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1045 | out: |
553f265f | 1046 | atomic_dec(&mce_entry); |
88921be3 | 1047 | sync_core(); |
1da177e4 | 1048 | } |
ea149b36 | 1049 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1050 | |
9b1beaf2 AK |
1051 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1052 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1053 | { | |
1054 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1055 | } | |
1056 | ||
1057 | /* | |
1058 | * Called after mce notification in process context. This code | |
1059 | * is allowed to sleep. Call the high level VM handler to process | |
1060 | * any corrupted pages. | |
1061 | * Assume that the work queue code only calls this one at a time | |
1062 | * per CPU. | |
1063 | * Note we don't disable preemption, so this code might run on the wrong | |
1064 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1065 | * This is merely a fast path to expedite processing in some common | |
1066 | * cases. | |
1067 | */ | |
1068 | void mce_notify_process(void) | |
1069 | { | |
1070 | unsigned long pfn; | |
1071 | mce_notify_irq(); | |
1072 | while (mce_ring_get(&pfn)) | |
1073 | memory_failure(pfn, MCE_VECTOR); | |
1074 | } | |
1075 | ||
1076 | static void mce_process_work(struct work_struct *dummy) | |
1077 | { | |
1078 | mce_notify_process(); | |
1079 | } | |
1080 | ||
15d5f839 DZ |
1081 | #ifdef CONFIG_X86_MCE_INTEL |
1082 | /*** | |
1083 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1084 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1085 | * @status: Event status information |
1086 | * | |
1087 | * This function should be called by the thermal interrupt after the | |
1088 | * event has been processed and the decision was made to log the event | |
1089 | * further. | |
1090 | * | |
1091 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1092 | * and historically has been the register value of the | |
1093 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1094 | */ | |
b5f2fa4e | 1095 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1096 | { |
1097 | struct mce m; | |
1098 | ||
b5f2fa4e | 1099 | mce_setup(&m); |
15d5f839 DZ |
1100 | m.bank = MCE_THERMAL_BANK; |
1101 | m.status = status; | |
15d5f839 DZ |
1102 | mce_log(&m); |
1103 | } | |
1104 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1105 | ||
1da177e4 | 1106 | /* |
8a336b0a TH |
1107 | * Periodic polling timer for "silent" machine check errors. If the |
1108 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1109 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1110 | */ |
1da177e4 | 1111 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1112 | |
245b2e70 | 1113 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1114 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1115 | |
5e09954a | 1116 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1117 | { |
52d168e2 | 1118 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1119 | int *n; |
52d168e2 AK |
1120 | |
1121 | WARN_ON(smp_processor_id() != data); | |
1122 | ||
7b543a53 | 1123 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1124 | machine_check_poll(MCP_TIMESTAMP, |
1125 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1126 | } |
1da177e4 LT |
1127 | |
1128 | /* | |
e02e68d3 TH |
1129 | * Alert userspace if needed. If we logged an MCE, reduce the |
1130 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1131 | */ |
245b2e70 | 1132 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1133 | if (mce_notify_irq()) |
6298c512 | 1134 | *n = max(*n/2, HZ/100); |
14a02530 | 1135 | else |
6298c512 | 1136 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1137 | |
6298c512 | 1138 | t->expires = jiffies + *n; |
5be6066a | 1139 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1140 | } |
1141 | ||
9bd98405 AK |
1142 | static void mce_do_trigger(struct work_struct *work) |
1143 | { | |
1020bcbc | 1144 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1145 | } |
1146 | ||
1147 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1148 | ||
e02e68d3 | 1149 | /* |
9bd98405 AK |
1150 | * Notify the user(s) about new machine check events. |
1151 | * Can be called from interrupt context, but not from machine check/NMI | |
1152 | * context. | |
e02e68d3 | 1153 | */ |
9ff36ee9 | 1154 | int mce_notify_irq(void) |
e02e68d3 | 1155 | { |
8457c84d AK |
1156 | /* Not more than two messages every minute */ |
1157 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1158 | ||
e02e68d3 | 1159 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1160 | |
1020bcbc | 1161 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1162 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1163 | |
1164 | /* | |
1165 | * There is no risk of missing notifications because | |
1166 | * work_pending is always cleared before the function is | |
1167 | * executed. | |
1168 | */ | |
1020bcbc | 1169 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1170 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1171 | |
8457c84d | 1172 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1173 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1174 | |
1175 | return 1; | |
1da177e4 | 1176 | } |
e02e68d3 TH |
1177 | return 0; |
1178 | } | |
9ff36ee9 | 1179 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1180 | |
cffd377e | 1181 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1182 | { |
1183 | int i; | |
1184 | ||
1185 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1186 | if (!mce_banks) | |
1187 | return -ENOMEM; | |
1188 | for (i = 0; i < banks; i++) { | |
1189 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1190 | |
cebe1820 AK |
1191 | b->ctl = -1ULL; |
1192 | b->init = 1; | |
1193 | } | |
1194 | return 0; | |
1195 | } | |
1196 | ||
d88203d1 | 1197 | /* |
1da177e4 LT |
1198 | * Initialize Machine Checks for a CPU. |
1199 | */ | |
5e09954a | 1200 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1201 | { |
0d7482e3 | 1202 | unsigned b; |
e9eee03e | 1203 | u64 cap; |
1da177e4 LT |
1204 | |
1205 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1206 | |
1207 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1208 | if (!banks) |
1209 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1210 | |
0d7482e3 AK |
1211 | if (b > MAX_NR_BANKS) { |
1212 | printk(KERN_WARNING | |
1213 | "MCE: Using only %u machine check banks out of %u\n", | |
1214 | MAX_NR_BANKS, b); | |
1215 | b = MAX_NR_BANKS; | |
1216 | } | |
1217 | ||
1218 | /* Don't support asymmetric configurations today */ | |
1219 | WARN_ON(banks != 0 && b != banks); | |
1220 | banks = b; | |
cebe1820 | 1221 | if (!mce_banks) { |
cffd377e | 1222 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1223 | |
cebe1820 AK |
1224 | if (err) |
1225 | return err; | |
1da177e4 | 1226 | } |
0d7482e3 | 1227 | |
94ad8474 | 1228 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1229 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1230 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1231 | |
ed7290d0 AK |
1232 | if (cap & MCG_SER_P) |
1233 | mce_ser = 1; | |
1234 | ||
0d7482e3 AK |
1235 | return 0; |
1236 | } | |
1237 | ||
5e09954a | 1238 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1239 | { |
e9eee03e | 1240 | mce_banks_t all_banks; |
0d7482e3 AK |
1241 | u64 cap; |
1242 | int i; | |
1243 | ||
b79109c3 AK |
1244 | /* |
1245 | * Log the machine checks left over from the previous reset. | |
1246 | */ | |
ee031c31 | 1247 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1248 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1249 | |
1250 | set_in_cr4(X86_CR4_MCE); | |
1251 | ||
0d7482e3 | 1252 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1253 | if (cap & MCG_CTL_P) |
1254 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1255 | ||
1256 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1257 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1258 | |
cebe1820 | 1259 | if (!b->init) |
06b7a7a5 | 1260 | continue; |
a2d32bcb AK |
1261 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1262 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1263 | } |
1da177e4 LT |
1264 | } |
1265 | ||
1266 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1267 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1268 | { |
e412cd25 IM |
1269 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1270 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1271 | return -EOPNOTSUPP; | |
1272 | } | |
1273 | ||
1da177e4 | 1274 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1275 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1276 | if (c->x86 == 15 && banks > 4) { |
1277 | /* | |
1278 | * disable GART TBL walk error reporting, which | |
1279 | * trips off incorrectly with the IOMMU & 3ware | |
1280 | * & Cerberus: | |
1281 | */ | |
cebe1820 | 1282 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1283 | } |
1284 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1285 | /* | |
1286 | * Lots of broken BIOS around that don't clear them | |
1287 | * by default and leave crap in there. Don't log: | |
1288 | */ | |
911f6a7b | 1289 | mce_bootlog = 0; |
e9eee03e | 1290 | } |
2e6f694f AK |
1291 | /* |
1292 | * Various K7s with broken bank 0 around. Always disable | |
1293 | * by default. | |
1294 | */ | |
203abd67 | 1295 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1296 | mce_banks[0].ctl = 0; |
1da177e4 | 1297 | } |
e583538f | 1298 | |
06b7a7a5 AK |
1299 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1300 | /* | |
1301 | * SDM documents that on family 6 bank 0 should not be written | |
1302 | * because it aliases to another special BIOS controlled | |
1303 | * register. | |
1304 | * But it's not aliased anymore on model 0x1a+ | |
1305 | * Don't ignore bank 0 completely because there could be a | |
1306 | * valid event later, merely don't write CTL0. | |
1307 | */ | |
1308 | ||
cebe1820 AK |
1309 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1310 | mce_banks[0].init = 0; | |
3c079792 AK |
1311 | |
1312 | /* | |
1313 | * All newer Intel systems support MCE broadcasting. Enable | |
1314 | * synchronization with a one second timeout. | |
1315 | */ | |
1316 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1317 | monarch_timeout < 0) | |
1318 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1319 | |
e412cd25 IM |
1320 | /* |
1321 | * There are also broken BIOSes on some Pentium M and | |
1322 | * earlier systems: | |
1323 | */ | |
1324 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1325 | mce_bootlog = 0; |
06b7a7a5 | 1326 | } |
3c079792 AK |
1327 | if (monarch_timeout < 0) |
1328 | monarch_timeout = 0; | |
29b0f591 AK |
1329 | if (mce_bootlog != 0) |
1330 | mce_panic_timeout = 30; | |
e412cd25 IM |
1331 | |
1332 | return 0; | |
d88203d1 | 1333 | } |
1da177e4 | 1334 | |
3a97fc34 | 1335 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1336 | { |
1337 | if (c->x86 != 5) | |
3a97fc34 HS |
1338 | return 0; |
1339 | ||
4efc0670 AK |
1340 | switch (c->x86_vendor) { |
1341 | case X86_VENDOR_INTEL: | |
c6978369 | 1342 | intel_p5_mcheck_init(c); |
3a97fc34 | 1343 | return 1; |
4efc0670 AK |
1344 | break; |
1345 | case X86_VENDOR_CENTAUR: | |
1346 | winchip_mcheck_init(c); | |
3a97fc34 | 1347 | return 1; |
4efc0670 AK |
1348 | break; |
1349 | } | |
3a97fc34 HS |
1350 | |
1351 | return 0; | |
4efc0670 AK |
1352 | } |
1353 | ||
5e09954a | 1354 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1355 | { |
1356 | switch (c->x86_vendor) { | |
1357 | case X86_VENDOR_INTEL: | |
1358 | mce_intel_feature_init(c); | |
1359 | break; | |
89b831ef JS |
1360 | case X86_VENDOR_AMD: |
1361 | mce_amd_feature_init(c); | |
1362 | break; | |
1da177e4 LT |
1363 | default: |
1364 | break; | |
1365 | } | |
1366 | } | |
1367 | ||
5e09954a | 1368 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1369 | { |
1370 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1371 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1372 | |
bc09effa JB |
1373 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1374 | ||
62fdac59 HS |
1375 | if (mce_ignore_ce) |
1376 | return; | |
1377 | ||
6298c512 AK |
1378 | *n = check_interval * HZ; |
1379 | if (!*n) | |
52d168e2 | 1380 | return; |
6298c512 | 1381 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1382 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1383 | } |
1384 | ||
9eda8cb3 AK |
1385 | /* Handle unconfigured int18 (should never happen) */ |
1386 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1387 | { | |
1388 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1389 | smp_processor_id()); | |
1390 | } | |
1391 | ||
1392 | /* Call the installed machine check handler for this CPU setup. */ | |
1393 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1394 | unexpected_machine_check; | |
1395 | ||
d88203d1 | 1396 | /* |
1da177e4 | 1397 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1398 | * Must be called with preempt off: |
1da177e4 | 1399 | */ |
5e09954a | 1400 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1401 | { |
4efc0670 AK |
1402 | if (mce_disabled) |
1403 | return; | |
1404 | ||
3a97fc34 HS |
1405 | if (__mcheck_cpu_ancient_init(c)) |
1406 | return; | |
4efc0670 | 1407 | |
5b4408fd | 1408 | if (!mce_available(c)) |
1da177e4 LT |
1409 | return; |
1410 | ||
5e09954a | 1411 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1412 | mce_disabled = 1; |
0d7482e3 AK |
1413 | return; |
1414 | } | |
0d7482e3 | 1415 | |
5d727926 AK |
1416 | machine_check_vector = do_machine_check; |
1417 | ||
5e09954a BP |
1418 | __mcheck_cpu_init_generic(); |
1419 | __mcheck_cpu_init_vendor(c); | |
1420 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1421 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1422 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1423 | } |
1424 | ||
1425 | /* | |
1426 | * Character device to read and clear the MCE log. | |
1427 | */ | |
1428 | ||
f528e7ba | 1429 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1430 | static int open_count; /* #times opened */ |
1431 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1432 | |
1433 | static int mce_open(struct inode *inode, struct file *file) | |
1434 | { | |
1435 | spin_lock(&mce_state_lock); | |
1436 | ||
1437 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1438 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1439 | |
f528e7ba TH |
1440 | return -EBUSY; |
1441 | } | |
1442 | ||
1443 | if (file->f_flags & O_EXCL) | |
1444 | open_exclu = 1; | |
1445 | open_count++; | |
1446 | ||
1447 | spin_unlock(&mce_state_lock); | |
1448 | ||
bd78432c | 1449 | return nonseekable_open(inode, file); |
f528e7ba TH |
1450 | } |
1451 | ||
1452 | static int mce_release(struct inode *inode, struct file *file) | |
1453 | { | |
1454 | spin_lock(&mce_state_lock); | |
1455 | ||
1456 | open_count--; | |
1457 | open_exclu = 0; | |
1458 | ||
1459 | spin_unlock(&mce_state_lock); | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
d88203d1 TG |
1464 | static void collect_tscs(void *data) |
1465 | { | |
1da177e4 | 1466 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1467 | |
1da177e4 | 1468 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1469 | } |
1da177e4 | 1470 | |
482908b4 HY |
1471 | static int mce_apei_read_done; |
1472 | ||
1473 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1474 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1475 | { | |
1476 | int rc; | |
1477 | u64 record_id; | |
1478 | struct mce m; | |
1479 | ||
1480 | if (usize < sizeof(struct mce)) | |
1481 | return -EINVAL; | |
1482 | ||
1483 | rc = apei_read_mce(&m, &record_id); | |
1484 | /* Error or no more MCE record */ | |
1485 | if (rc <= 0) { | |
1486 | mce_apei_read_done = 1; | |
1487 | return rc; | |
1488 | } | |
1489 | rc = -EFAULT; | |
1490 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1491 | return rc; | |
1492 | /* | |
1493 | * In fact, we should have cleared the record after that has | |
1494 | * been flushed to the disk or sent to network in | |
1495 | * /sbin/mcelog, but we have no interface to support that now, | |
1496 | * so just clear it to avoid duplication. | |
1497 | */ | |
1498 | rc = apei_clear_mce(record_id); | |
1499 | if (rc) { | |
1500 | mce_apei_read_done = 1; | |
1501 | return rc; | |
1502 | } | |
1503 | *ubuf += sizeof(struct mce); | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
d88203d1 TG |
1508 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1509 | loff_t *off) | |
1da177e4 | 1510 | { |
e9eee03e | 1511 | char __user *buf = ubuf; |
f0de53bb | 1512 | unsigned long *cpu_tsc; |
ef41df43 | 1513 | unsigned prev, next; |
1da177e4 LT |
1514 | int i, err; |
1515 | ||
6bca67f9 | 1516 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1517 | if (!cpu_tsc) |
1518 | return -ENOMEM; | |
1519 | ||
8c8b8859 | 1520 | mutex_lock(&mce_read_mutex); |
482908b4 HY |
1521 | |
1522 | if (!mce_apei_read_done) { | |
1523 | err = __mce_read_apei(&buf, usize); | |
1524 | if (err || buf != ubuf) | |
1525 | goto out; | |
1526 | } | |
1527 | ||
f56e8a07 | 1528 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1529 | |
1530 | /* Only supports full reads right now */ | |
482908b4 HY |
1531 | err = -EINVAL; |
1532 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1533 | goto out; | |
1da177e4 LT |
1534 | |
1535 | err = 0; | |
ef41df43 HY |
1536 | prev = 0; |
1537 | do { | |
1538 | for (i = prev; i < next; i++) { | |
1539 | unsigned long start = jiffies; | |
559faa6b | 1540 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1541 | |
559faa6b | 1542 | while (!m->finished) { |
ef41df43 | 1543 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1544 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1545 | goto timeout; |
1546 | } | |
1547 | cpu_relax(); | |
673242c1 | 1548 | } |
ef41df43 | 1549 | smp_rmb(); |
559faa6b HS |
1550 | err |= copy_to_user(buf, m, sizeof(*m)); |
1551 | buf += sizeof(*m); | |
ef41df43 HY |
1552 | timeout: |
1553 | ; | |
673242c1 | 1554 | } |
1da177e4 | 1555 | |
ef41df43 HY |
1556 | memset(mcelog.entry + prev, 0, |
1557 | (next - prev) * sizeof(struct mce)); | |
1558 | prev = next; | |
1559 | next = cmpxchg(&mcelog.next, prev, 0); | |
1560 | } while (next != prev); | |
1da177e4 | 1561 | |
b2b18660 | 1562 | synchronize_sched(); |
1da177e4 | 1563 | |
d88203d1 TG |
1564 | /* |
1565 | * Collect entries that were still getting written before the | |
1566 | * synchronize. | |
1567 | */ | |
15c8b6c1 | 1568 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1569 | |
d88203d1 | 1570 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1571 | struct mce *m = &mcelog.entry[i]; |
1572 | ||
1573 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1574 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1575 | smp_rmb(); |
559faa6b HS |
1576 | buf += sizeof(*m); |
1577 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1578 | } |
d88203d1 | 1579 | } |
482908b4 HY |
1580 | |
1581 | if (err) | |
1582 | err = -EFAULT; | |
1583 | ||
1584 | out: | |
8c8b8859 | 1585 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1586 | kfree(cpu_tsc); |
e9eee03e | 1587 | |
482908b4 | 1588 | return err ? err : buf - ubuf; |
1da177e4 LT |
1589 | } |
1590 | ||
e02e68d3 TH |
1591 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1592 | { | |
1593 | poll_wait(file, &mce_wait, wait); | |
a4dd9925 | 1594 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1595 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1596 | if (!mce_apei_read_done && apei_check_mce()) |
1597 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1598 | return 0; |
1599 | } | |
1600 | ||
c68461b6 | 1601 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1602 | { |
1603 | int __user *p = (int __user *)arg; | |
d88203d1 | 1604 | |
1da177e4 | 1605 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1606 | return -EPERM; |
e9eee03e | 1607 | |
1da177e4 | 1608 | switch (cmd) { |
d88203d1 | 1609 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1610 | return put_user(sizeof(struct mce), p); |
1611 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1612 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1613 | case MCE_GETCLEAR_FLAGS: { |
1614 | unsigned flags; | |
d88203d1 TG |
1615 | |
1616 | do { | |
1da177e4 | 1617 | flags = mcelog.flags; |
d88203d1 | 1618 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1619 | |
d88203d1 | 1620 | return put_user(flags, p); |
1da177e4 LT |
1621 | } |
1622 | default: | |
d88203d1 TG |
1623 | return -ENOTTY; |
1624 | } | |
1da177e4 LT |
1625 | } |
1626 | ||
a1ff41bf | 1627 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1628 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1629 | .open = mce_open, |
1630 | .release = mce_release, | |
1631 | .read = mce_read, | |
1632 | .poll = mce_poll, | |
1633 | .unlocked_ioctl = mce_ioctl, | |
6038f373 | 1634 | .llseek = no_llseek, |
1da177e4 | 1635 | }; |
ea149b36 | 1636 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1637 | |
1638 | static struct miscdevice mce_log_device = { | |
1639 | MISC_MCELOG_MINOR, | |
1640 | "mcelog", | |
1641 | &mce_chrdev_ops, | |
1642 | }; | |
1643 | ||
13503fa9 | 1644 | /* |
62fdac59 HS |
1645 | * mce=off Disables machine check |
1646 | * mce=no_cmci Disables CMCI | |
1647 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1648 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1649 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1650 | * monarchtimeout is how long to wait for other CPUs on machine | |
1651 | * check, or 0 to not wait | |
13503fa9 HS |
1652 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1653 | * mce=nobootlog Don't log MCEs from before booting. | |
1654 | */ | |
1da177e4 LT |
1655 | static int __init mcheck_enable(char *str) |
1656 | { | |
e3346fc4 | 1657 | if (*str == 0) { |
4efc0670 | 1658 | enable_p5_mce(); |
e3346fc4 BZ |
1659 | return 1; |
1660 | } | |
4efc0670 AK |
1661 | if (*str == '=') |
1662 | str++; | |
1da177e4 | 1663 | if (!strcmp(str, "off")) |
04b2b1a4 | 1664 | mce_disabled = 1; |
62fdac59 HS |
1665 | else if (!strcmp(str, "no_cmci")) |
1666 | mce_cmci_disabled = 1; | |
1667 | else if (!strcmp(str, "dont_log_ce")) | |
1668 | mce_dont_log_ce = 1; | |
1669 | else if (!strcmp(str, "ignore_ce")) | |
1670 | mce_ignore_ce = 1; | |
13503fa9 HS |
1671 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1672 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1673 | else if (isdigit(str[0])) { |
8c566ef5 | 1674 | get_option(&str, &tolerant); |
3c079792 AK |
1675 | if (*str == ',') { |
1676 | ++str; | |
1677 | get_option(&str, &monarch_timeout); | |
1678 | } | |
1679 | } else { | |
4efc0670 | 1680 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1681 | str); |
1682 | return 0; | |
1683 | } | |
9b41046c | 1684 | return 1; |
1da177e4 | 1685 | } |
4efc0670 | 1686 | __setup("mce", mcheck_enable); |
1da177e4 | 1687 | |
a2202aa2 | 1688 | int __init mcheck_init(void) |
b33a6363 | 1689 | { |
a2202aa2 YW |
1690 | mcheck_intel_therm_init(); |
1691 | ||
b33a6363 BP |
1692 | return 0; |
1693 | } | |
b33a6363 | 1694 | |
d88203d1 | 1695 | /* |
1da177e4 | 1696 | * Sysfs support |
d88203d1 | 1697 | */ |
1da177e4 | 1698 | |
973a2dd1 AK |
1699 | /* |
1700 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1701 | * them later. | |
1702 | */ | |
5e09954a | 1703 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1704 | { |
1705 | int i; | |
1706 | ||
06b7a7a5 | 1707 | for (i = 0; i < banks; i++) { |
cebe1820 | 1708 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1709 | |
cebe1820 | 1710 | if (b->init) |
a2d32bcb | 1711 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1712 | } |
973a2dd1 AK |
1713 | return 0; |
1714 | } | |
1715 | ||
f3c6ea1b | 1716 | static int mce_suspend(void) |
973a2dd1 | 1717 | { |
5e09954a | 1718 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1719 | } |
1720 | ||
f3c6ea1b | 1721 | static void mce_shutdown(void) |
973a2dd1 | 1722 | { |
f3c6ea1b | 1723 | mce_disable_error_reporting(); |
973a2dd1 AK |
1724 | } |
1725 | ||
e9eee03e IM |
1726 | /* |
1727 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1728 | * Only one CPU is active at this time, the others get re-added later using | |
1729 | * CPU hotplug: | |
1730 | */ | |
f3c6ea1b | 1731 | static void mce_resume(void) |
1da177e4 | 1732 | { |
5e09954a | 1733 | __mcheck_cpu_init_generic(); |
7b543a53 | 1734 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
1735 | } |
1736 | ||
f3c6ea1b RW |
1737 | static struct syscore_ops mce_syscore_ops = { |
1738 | .suspend = mce_suspend, | |
1739 | .shutdown = mce_shutdown, | |
1740 | .resume = mce_resume, | |
1741 | }; | |
1742 | ||
52d168e2 AK |
1743 | static void mce_cpu_restart(void *data) |
1744 | { | |
1745 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
7b543a53 | 1746 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 1747 | return; |
5e09954a BP |
1748 | __mcheck_cpu_init_generic(); |
1749 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1750 | } |
1751 | ||
1da177e4 | 1752 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1753 | static void mce_restart(void) |
1754 | { | |
52d168e2 | 1755 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1756 | } |
1757 | ||
9af43b54 HS |
1758 | /* Toggle features for corrected errors */ |
1759 | static void mce_disable_ce(void *all) | |
1760 | { | |
7b543a53 | 1761 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1762 | return; |
1763 | if (all) | |
1764 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1765 | cmci_clear(); | |
1766 | } | |
1767 | ||
1768 | static void mce_enable_ce(void *all) | |
1769 | { | |
7b543a53 | 1770 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1771 | return; |
1772 | cmci_reenable(); | |
1773 | cmci_recheck(); | |
1774 | if (all) | |
5e09954a | 1775 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1776 | } |
1777 | ||
1da177e4 | 1778 | static struct sysdev_class mce_sysclass = { |
e9eee03e | 1779 | .name = "machinecheck", |
1da177e4 LT |
1780 | }; |
1781 | ||
cb491fca | 1782 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1783 | |
1784 | __cpuinitdata | |
1785 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1786 | |
cebe1820 AK |
1787 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1788 | { | |
1789 | return container_of(attr, struct mce_bank, attr); | |
1790 | } | |
0d7482e3 AK |
1791 | |
1792 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1793 | char *buf) | |
1794 | { | |
cebe1820 | 1795 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1796 | } |
1797 | ||
1798 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1799 | const char *buf, size_t size) |
0d7482e3 | 1800 | { |
9319cec8 | 1801 | u64 new; |
e9eee03e | 1802 | |
9319cec8 | 1803 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1804 | return -EINVAL; |
e9eee03e | 1805 | |
cebe1820 | 1806 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1807 | mce_restart(); |
e9eee03e | 1808 | |
9319cec8 | 1809 | return size; |
0d7482e3 | 1810 | } |
a98f0dd3 | 1811 | |
e9eee03e IM |
1812 | static ssize_t |
1813 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1814 | { |
1020bcbc | 1815 | strcpy(buf, mce_helper); |
a98f0dd3 | 1816 | strcat(buf, "\n"); |
1020bcbc | 1817 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1818 | } |
1819 | ||
4a0b2b4d | 1820 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1821 | const char *buf, size_t siz) |
a98f0dd3 AK |
1822 | { |
1823 | char *p; | |
e9eee03e | 1824 | |
1020bcbc HS |
1825 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1826 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1827 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1828 | |
e9084ec9 | 1829 | if (p) |
e9eee03e IM |
1830 | *p = 0; |
1831 | ||
e9084ec9 | 1832 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1833 | } |
1834 | ||
9af43b54 HS |
1835 | static ssize_t set_ignore_ce(struct sys_device *s, |
1836 | struct sysdev_attribute *attr, | |
1837 | const char *buf, size_t size) | |
1838 | { | |
1839 | u64 new; | |
1840 | ||
1841 | if (strict_strtoull(buf, 0, &new) < 0) | |
1842 | return -EINVAL; | |
1843 | ||
1844 | if (mce_ignore_ce ^ !!new) { | |
1845 | if (new) { | |
1846 | /* disable ce features */ | |
1847 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1848 | mce_ignore_ce = 1; | |
1849 | } else { | |
1850 | /* enable ce features */ | |
1851 | mce_ignore_ce = 0; | |
1852 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1853 | } | |
1854 | } | |
1855 | return size; | |
1856 | } | |
1857 | ||
1858 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1859 | struct sysdev_attribute *attr, | |
1860 | const char *buf, size_t size) | |
1861 | { | |
1862 | u64 new; | |
1863 | ||
1864 | if (strict_strtoull(buf, 0, &new) < 0) | |
1865 | return -EINVAL; | |
1866 | ||
1867 | if (mce_cmci_disabled ^ !!new) { | |
1868 | if (new) { | |
1869 | /* disable cmci */ | |
1870 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1871 | mce_cmci_disabled = 1; | |
1872 | } else { | |
1873 | /* enable cmci */ | |
1874 | mce_cmci_disabled = 0; | |
1875 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1876 | } | |
1877 | } | |
1878 | return size; | |
1879 | } | |
1880 | ||
b56f642d AK |
1881 | static ssize_t store_int_with_restart(struct sys_device *s, |
1882 | struct sysdev_attribute *attr, | |
1883 | const char *buf, size_t size) | |
1884 | { | |
1885 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1886 | mce_restart(); | |
1887 | return ret; | |
1888 | } | |
1889 | ||
a98f0dd3 | 1890 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1891 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1892 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1893 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1894 | |
b56f642d AK |
1895 | static struct sysdev_ext_attribute attr_check_interval = { |
1896 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1897 | store_int_with_restart), | |
1898 | &check_interval | |
1899 | }; | |
e9eee03e | 1900 | |
9af43b54 HS |
1901 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1902 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1903 | &mce_ignore_ce | |
1904 | }; | |
1905 | ||
1906 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1907 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1908 | &mce_cmci_disabled |
1909 | }; | |
1910 | ||
cb491fca | 1911 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1912 | &attr_tolerant.attr, |
1913 | &attr_check_interval.attr, | |
1914 | &attr_trigger, | |
3c079792 | 1915 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1916 | &attr_dont_log_ce.attr, |
1917 | &attr_ignore_ce.attr, | |
1918 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1919 | NULL |
1920 | }; | |
1da177e4 | 1921 | |
cb491fca | 1922 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1923 | |
e9eee03e | 1924 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1925 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 | 1926 | { |
f6783c42 | 1927 | struct sys_device *sysdev = &per_cpu(mce_dev, cpu); |
1da177e4 | 1928 | int err; |
b1f49f95 | 1929 | int i, j; |
92cb7612 | 1930 | |
90367556 | 1931 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1932 | return -EIO; |
1933 | ||
f6783c42 HS |
1934 | memset(&sysdev->kobj, 0, sizeof(struct kobject)); |
1935 | sysdev->id = cpu; | |
1936 | sysdev->cls = &mce_sysclass; | |
91c6d400 | 1937 | |
f6783c42 | 1938 | err = sysdev_register(sysdev); |
d435d862 AM |
1939 | if (err) |
1940 | return err; | |
1941 | ||
cb491fca | 1942 | for (i = 0; mce_attrs[i]; i++) { |
f6783c42 | 1943 | err = sysdev_create_file(sysdev, mce_attrs[i]); |
d435d862 AM |
1944 | if (err) |
1945 | goto error; | |
1946 | } | |
b1f49f95 | 1947 | for (j = 0; j < banks; j++) { |
f6783c42 | 1948 | err = sysdev_create_file(sysdev, &mce_banks[j].attr); |
0d7482e3 AK |
1949 | if (err) |
1950 | goto error2; | |
1951 | } | |
cb491fca | 1952 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1953 | |
d435d862 | 1954 | return 0; |
0d7482e3 | 1955 | error2: |
b1f49f95 | 1956 | while (--j >= 0) |
f6783c42 | 1957 | sysdev_remove_file(sysdev, &mce_banks[j].attr); |
d435d862 | 1958 | error: |
cb491fca | 1959 | while (--i >= 0) |
f6783c42 | 1960 | sysdev_remove_file(sysdev, mce_attrs[i]); |
cb491fca | 1961 | |
f6783c42 | 1962 | sysdev_unregister(sysdev); |
d435d862 | 1963 | |
91c6d400 AK |
1964 | return err; |
1965 | } | |
1966 | ||
2d9cd6c2 | 1967 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1968 | { |
f6783c42 | 1969 | struct sys_device *sysdev = &per_cpu(mce_dev, cpu); |
73ca5358 SL |
1970 | int i; |
1971 | ||
cb491fca | 1972 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1973 | return; |
1974 | ||
cb491fca | 1975 | for (i = 0; mce_attrs[i]; i++) |
f6783c42 | 1976 | sysdev_remove_file(sysdev, mce_attrs[i]); |
cb491fca | 1977 | |
0d7482e3 | 1978 | for (i = 0; i < banks; i++) |
f6783c42 | 1979 | sysdev_remove_file(sysdev, &mce_banks[i].attr); |
cb491fca | 1980 | |
f6783c42 | 1981 | sysdev_unregister(sysdev); |
cb491fca | 1982 | cpumask_clear_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1983 | } |
91c6d400 | 1984 | |
d6b75584 | 1985 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 1986 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 1987 | { |
88ccbedd | 1988 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1989 | int i; |
d6b75584 | 1990 | |
7b543a53 | 1991 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 1992 | return; |
767df1bd | 1993 | |
88ccbedd AK |
1994 | if (!(action & CPU_TASKS_FROZEN)) |
1995 | cmci_clear(); | |
06b7a7a5 | 1996 | for (i = 0; i < banks; i++) { |
cebe1820 | 1997 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1998 | |
cebe1820 | 1999 | if (b->init) |
a2d32bcb | 2000 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2001 | } |
d6b75584 AK |
2002 | } |
2003 | ||
767df1bd | 2004 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2005 | { |
88ccbedd | 2006 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2007 | int i; |
d6b75584 | 2008 | |
7b543a53 | 2009 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2010 | return; |
e9eee03e | 2011 | |
88ccbedd AK |
2012 | if (!(action & CPU_TASKS_FROZEN)) |
2013 | cmci_reenable(); | |
06b7a7a5 | 2014 | for (i = 0; i < banks; i++) { |
cebe1820 | 2015 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2016 | |
cebe1820 | 2017 | if (b->init) |
a2d32bcb | 2018 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2019 | } |
d6b75584 AK |
2020 | } |
2021 | ||
91c6d400 | 2022 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2023 | static int __cpuinit |
2024 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2025 | { |
2026 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2027 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2028 | |
2029 | switch (action) { | |
bae19fe0 AH |
2030 | case CPU_ONLINE: |
2031 | case CPU_ONLINE_FROZEN: | |
2032 | mce_create_device(cpu); | |
8735728e RW |
2033 | if (threshold_cpu_callback) |
2034 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2035 | break; |
91c6d400 | 2036 | case CPU_DEAD: |
8bb78442 | 2037 | case CPU_DEAD_FROZEN: |
8735728e RW |
2038 | if (threshold_cpu_callback) |
2039 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
2040 | mce_remove_device(cpu); |
2041 | break; | |
52d168e2 AK |
2042 | case CPU_DOWN_PREPARE: |
2043 | case CPU_DOWN_PREPARE_FROZEN: | |
2044 | del_timer_sync(t); | |
88ccbedd | 2045 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2046 | break; |
2047 | case CPU_DOWN_FAILED: | |
2048 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2049 | if (!mce_ignore_ce && check_interval) { |
2050 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2051 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2052 | add_timer_on(t, cpu); |
2053 | } | |
88ccbedd AK |
2054 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2055 | break; | |
2056 | case CPU_POST_DEAD: | |
2057 | /* intentionally ignoring frozen here */ | |
2058 | cmci_rediscover(cpu); | |
52d168e2 | 2059 | break; |
91c6d400 | 2060 | } |
bae19fe0 | 2061 | return NOTIFY_OK; |
91c6d400 AK |
2062 | } |
2063 | ||
1e35669d | 2064 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2065 | .notifier_call = mce_cpu_callback, |
2066 | }; | |
2067 | ||
cebe1820 | 2068 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2069 | { |
2070 | int i; | |
2071 | ||
0d7482e3 | 2072 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2073 | struct mce_bank *b = &mce_banks[i]; |
2074 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2075 | |
a07e4156 | 2076 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2077 | a->attr.name = b->attrname; |
2078 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2079 | |
2080 | a->attr.mode = 0644; | |
2081 | a->show = show_bank; | |
2082 | a->store = set_bank; | |
0d7482e3 | 2083 | } |
0d7482e3 AK |
2084 | } |
2085 | ||
5e09954a | 2086 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2087 | { |
2088 | int err; | |
2089 | int i = 0; | |
2090 | ||
1da177e4 LT |
2091 | if (!mce_available(&boot_cpu_data)) |
2092 | return -EIO; | |
0d7482e3 | 2093 | |
e92fae06 | 2094 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2095 | |
cebe1820 | 2096 | mce_init_banks(); |
0d7482e3 | 2097 | |
1da177e4 | 2098 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2099 | if (err) |
2100 | return err; | |
91c6d400 AK |
2101 | |
2102 | for_each_online_cpu(i) { | |
d435d862 AM |
2103 | err = mce_create_device(i); |
2104 | if (err) | |
2105 | return err; | |
91c6d400 AK |
2106 | } |
2107 | ||
f3c6ea1b | 2108 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2109 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2110 | misc_register(&mce_log_device); |
e9eee03e | 2111 | |
1da177e4 | 2112 | return err; |
1da177e4 | 2113 | } |
91c6d400 | 2114 | |
5e09954a | 2115 | device_initcall(mcheck_init_device); |
a988d334 | 2116 | |
d7c3c9a6 AK |
2117 | /* |
2118 | * Old style boot options parsing. Only for compatibility. | |
2119 | */ | |
2120 | static int __init mcheck_disable(char *str) | |
2121 | { | |
2122 | mce_disabled = 1; | |
2123 | return 1; | |
2124 | } | |
2125 | __setup("nomce", mcheck_disable); | |
a988d334 | 2126 | |
5be9ed25 HY |
2127 | #ifdef CONFIG_DEBUG_FS |
2128 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2129 | { |
5be9ed25 | 2130 | static struct dentry *dmce; |
a988d334 | 2131 | |
5be9ed25 HY |
2132 | if (!dmce) |
2133 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2134 | |
5be9ed25 HY |
2135 | return dmce; |
2136 | } | |
a988d334 | 2137 | |
bf783f9f HY |
2138 | static void mce_reset(void) |
2139 | { | |
2140 | cpu_missing = 0; | |
2141 | atomic_set(&mce_fake_paniced, 0); | |
2142 | atomic_set(&mce_executing, 0); | |
2143 | atomic_set(&mce_callin, 0); | |
2144 | atomic_set(&global_nwo, 0); | |
2145 | } | |
a988d334 | 2146 | |
bf783f9f HY |
2147 | static int fake_panic_get(void *data, u64 *val) |
2148 | { | |
2149 | *val = fake_panic; | |
2150 | return 0; | |
a988d334 IM |
2151 | } |
2152 | ||
bf783f9f | 2153 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2154 | { |
bf783f9f HY |
2155 | mce_reset(); |
2156 | fake_panic = val; | |
2157 | return 0; | |
a988d334 | 2158 | } |
a988d334 | 2159 | |
bf783f9f HY |
2160 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2161 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2162 | |
5e09954a | 2163 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2164 | { |
bf783f9f HY |
2165 | struct dentry *dmce, *ffake_panic; |
2166 | ||
2167 | dmce = mce_get_debugfs_dir(); | |
2168 | if (!dmce) | |
2169 | return -ENOMEM; | |
2170 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2171 | &fake_panic_fops); | |
2172 | if (!ffake_panic) | |
2173 | return -ENOMEM; | |
2174 | ||
2175 | return 0; | |
d7c3c9a6 | 2176 | } |
5e09954a | 2177 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2178 | #endif |