Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
93b62c3c | 51 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 52 | |
f56e8a07 | 53 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 54 | rcu_dereference_index_check((p), \ |
f56e8a07 | 55 | rcu_read_lock_sched_held() || \ |
93b62c3c | 56 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 57 | |
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
3c079792 AK |
61 | #define SPINUNIT 100 /* 100ns */ |
62 | ||
553f265f AK |
63 | atomic_t mce_entry; |
64 | ||
01ca79f1 AK |
65 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
66 | ||
1462594b | 67 | struct mce_bank *mce_banks __read_mostly; |
cebe1820 | 68 | |
d203f0b8 | 69 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 70 | .bootlog = -1, |
d203f0b8 BP |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
84c2559d BP |
78 | .tolerant = 1, |
79 | .monarch_timeout = -1 | |
d203f0b8 BP |
80 | }; |
81 | ||
1020bcbc HS |
82 | /* User mode helper program triggered by machine check event */ |
83 | static unsigned long mce_need_notify; | |
84 | static char mce_helper[128]; | |
85 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 86 | |
93b62c3c HS |
87 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
88 | ||
3c079792 AK |
89 | static DEFINE_PER_CPU(struct mce, mces_seen); |
90 | static int cpu_missing; | |
91 | ||
ee031c31 AK |
92 | /* MCA banks polled by the period polling timer for corrected events */ |
93 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
94 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
95 | }; | |
96 | ||
9b1beaf2 AK |
97 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
98 | ||
61b0fccd TL |
99 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
100 | ||
3653ada5 BP |
101 | /* |
102 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
103 | * MCE errors in a human-readable form. | |
104 | */ | |
105 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
106 | ||
b5f2fa4e AK |
107 | /* Do initial initialization of a struct mce */ |
108 | void mce_setup(struct mce *m) | |
109 | { | |
110 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 111 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 112 | rdtscll(m->tsc); |
8ee08347 AK |
113 | /* We hope get_seconds stays lockless */ |
114 | m->time = get_seconds(); | |
115 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
116 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 117 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
118 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
119 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
120 | } |
121 | ||
ea149b36 AK |
122 | DEFINE_PER_CPU(struct mce, injectm); |
123 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
124 | ||
1da177e4 LT |
125 | /* |
126 | * Lockless MCE logging infrastructure. | |
127 | * This avoids deadlocks on printk locks without having to break locks. Also | |
128 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
129 | */ | |
130 | ||
231fd906 | 131 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
132 | .signature = MCE_LOG_SIGNATURE, |
133 | .len = MCE_LOG_LEN, | |
134 | .recordlen = sizeof(struct mce), | |
d88203d1 | 135 | }; |
1da177e4 LT |
136 | |
137 | void mce_log(struct mce *mce) | |
138 | { | |
139 | unsigned next, entry; | |
f0cb5452 | 140 | int ret = 0; |
e9eee03e | 141 | |
8968f9d3 HS |
142 | /* Emit the trace record: */ |
143 | trace_mce_record(mce); | |
144 | ||
f0cb5452 BP |
145 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
146 | if (ret == NOTIFY_STOP) | |
147 | return; | |
148 | ||
1da177e4 | 149 | mce->finished = 0; |
7644143c | 150 | wmb(); |
1da177e4 | 151 | for (;;) { |
f56e8a07 | 152 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 153 | for (;;) { |
696e409d | 154 | |
e9eee03e IM |
155 | /* |
156 | * When the buffer fills up discard new entries. | |
157 | * Assume that the earlier errors are the more | |
158 | * interesting ones: | |
159 | */ | |
673242c1 | 160 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
161 | set_bit(MCE_OVERFLOW, |
162 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
163 | return; |
164 | } | |
e9eee03e | 165 | /* Old left over entry. Skip: */ |
673242c1 AK |
166 | if (mcelog.entry[entry].finished) { |
167 | entry++; | |
168 | continue; | |
169 | } | |
7644143c | 170 | break; |
1da177e4 | 171 | } |
1da177e4 LT |
172 | smp_rmb(); |
173 | next = entry + 1; | |
174 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
175 | break; | |
176 | } | |
177 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 178 | wmb(); |
1da177e4 | 179 | mcelog.entry[entry].finished = 1; |
7644143c | 180 | wmb(); |
1da177e4 | 181 | |
a0189c70 | 182 | mce->finished = 1; |
1020bcbc | 183 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
184 | } |
185 | ||
09371957 BP |
186 | static void drain_mcelog_buffer(void) |
187 | { | |
188 | unsigned int next, i, prev = 0; | |
189 | ||
b11e3d78 | 190 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
191 | |
192 | do { | |
193 | struct mce *m; | |
194 | ||
195 | /* drain what was logged during boot */ | |
196 | for (i = prev; i < next; i++) { | |
197 | unsigned long start = jiffies; | |
198 | unsigned retries = 1; | |
199 | ||
200 | m = &mcelog.entry[i]; | |
201 | ||
202 | while (!m->finished) { | |
203 | if (time_after_eq(jiffies, start + 2*retries)) | |
204 | retries++; | |
205 | ||
206 | cpu_relax(); | |
207 | ||
208 | if (!m->finished && retries >= 4) { | |
c767a54b | 209 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
210 | break; |
211 | } | |
212 | } | |
213 | smp_rmb(); | |
214 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
215 | } | |
216 | ||
217 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
218 | prev = next; | |
219 | next = cmpxchg(&mcelog.next, prev, 0); | |
220 | } while (next != prev); | |
221 | } | |
222 | ||
223 | ||
3653ada5 BP |
224 | void mce_register_decode_chain(struct notifier_block *nb) |
225 | { | |
226 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 227 | drain_mcelog_buffer(); |
3653ada5 BP |
228 | } |
229 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
230 | ||
231 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
232 | { | |
233 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
234 | } | |
235 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
236 | ||
77e26cca | 237 | static void print_mce(struct mce *m) |
1da177e4 | 238 | { |
dffa4b2f BP |
239 | int ret = 0; |
240 | ||
a2d7b0d4 | 241 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 242 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 243 | |
65ea5b03 | 244 | if (m->ip) { |
a2d7b0d4 | 245 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
246 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
247 | m->cs, m->ip); | |
248 | ||
1da177e4 | 249 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 250 | print_symbol("{%s}", m->ip); |
f436f8bb | 251 | pr_cont("\n"); |
1da177e4 | 252 | } |
f436f8bb | 253 | |
a2d7b0d4 | 254 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 255 | if (m->addr) |
f436f8bb | 256 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 257 | if (m->misc) |
f436f8bb | 258 | pr_cont("MISC %llx ", m->misc); |
549d042d | 259 | |
f436f8bb | 260 | pr_cont("\n"); |
506ed6b5 AK |
261 | /* |
262 | * Note this output is parsed by external tools and old fields | |
263 | * should not be changed. | |
264 | */ | |
881e23e5 | 265 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
266 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
267 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
268 | |
269 | /* | |
270 | * Print out human-readable details about the MCE error, | |
fb253195 | 271 | * (if the CPU has an implementation for that) |
f436f8bb | 272 | */ |
dffa4b2f BP |
273 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
274 | if (ret == NOTIFY_STOP) | |
275 | return; | |
276 | ||
277 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
278 | } |
279 | ||
f94b61c2 AK |
280 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
281 | ||
282 | static atomic_t mce_paniced; | |
283 | ||
bf783f9f HY |
284 | static int fake_panic; |
285 | static atomic_t mce_fake_paniced; | |
286 | ||
f94b61c2 AK |
287 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
288 | static void wait_for_panic(void) | |
289 | { | |
290 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 291 | |
f94b61c2 AK |
292 | preempt_disable(); |
293 | local_irq_enable(); | |
294 | while (timeout-- > 0) | |
295 | udelay(1); | |
29b0f591 | 296 | if (panic_timeout == 0) |
7af19e4a | 297 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
298 | panic("Panicing machine check CPU died"); |
299 | } | |
300 | ||
bd19a5e6 | 301 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 302 | { |
482908b4 | 303 | int i, apei_err = 0; |
e02e68d3 | 304 | |
bf783f9f HY |
305 | if (!fake_panic) { |
306 | /* | |
307 | * Make sure only one CPU runs in machine check panic | |
308 | */ | |
309 | if (atomic_inc_return(&mce_paniced) > 1) | |
310 | wait_for_panic(); | |
311 | barrier(); | |
f94b61c2 | 312 | |
bf783f9f HY |
313 | bust_spinlocks(1); |
314 | console_verbose(); | |
315 | } else { | |
316 | /* Don't log too much for fake panic */ | |
317 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
318 | return; | |
319 | } | |
a0189c70 | 320 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 321 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 322 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
323 | if (!(m->status & MCI_STATUS_VAL)) |
324 | continue; | |
482908b4 | 325 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 326 | print_mce(m); |
482908b4 HY |
327 | if (!apei_err) |
328 | apei_err = apei_write_mce(m); | |
329 | } | |
a0189c70 AK |
330 | } |
331 | /* Now print uncorrected but with the final one last */ | |
332 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
333 | struct mce *m = &mcelog.entry[i]; | |
334 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 335 | continue; |
77e26cca HS |
336 | if (!(m->status & MCI_STATUS_UC)) |
337 | continue; | |
482908b4 | 338 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 339 | print_mce(m); |
482908b4 HY |
340 | if (!apei_err) |
341 | apei_err = apei_write_mce(m); | |
342 | } | |
1da177e4 | 343 | } |
482908b4 | 344 | if (final) { |
77e26cca | 345 | print_mce(final); |
482908b4 HY |
346 | if (!apei_err) |
347 | apei_err = apei_write_mce(final); | |
348 | } | |
3c079792 | 349 | if (cpu_missing) |
a2d7b0d4 | 350 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 351 | if (exp) |
a2d7b0d4 | 352 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
353 | if (!fake_panic) { |
354 | if (panic_timeout == 0) | |
7af19e4a | 355 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
356 | panic(msg); |
357 | } else | |
a2d7b0d4 | 358 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 359 | } |
1da177e4 | 360 | |
ea149b36 AK |
361 | /* Support code for software error injection */ |
362 | ||
363 | static int msr_to_offset(u32 msr) | |
364 | { | |
0a3aee0d | 365 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 366 | |
84c2559d | 367 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 368 | return offsetof(struct mce, ip); |
a2d32bcb | 369 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 370 | return offsetof(struct mce, status); |
a2d32bcb | 371 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 372 | return offsetof(struct mce, addr); |
a2d32bcb | 373 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
374 | return offsetof(struct mce, misc); |
375 | if (msr == MSR_IA32_MCG_STATUS) | |
376 | return offsetof(struct mce, mcgstatus); | |
377 | return -1; | |
378 | } | |
379 | ||
5f8c1a54 AK |
380 | /* MSR access wrappers used for error injection */ |
381 | static u64 mce_rdmsrl(u32 msr) | |
382 | { | |
383 | u64 v; | |
11868a2d | 384 | |
0a3aee0d | 385 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 386 | int offset = msr_to_offset(msr); |
11868a2d | 387 | |
ea149b36 AK |
388 | if (offset < 0) |
389 | return 0; | |
390 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
391 | } | |
11868a2d IM |
392 | |
393 | if (rdmsrl_safe(msr, &v)) { | |
394 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
395 | /* | |
396 | * Return zero in case the access faulted. This should | |
397 | * not happen normally but can happen if the CPU does | |
398 | * something weird, or if the code is buggy. | |
399 | */ | |
400 | v = 0; | |
401 | } | |
402 | ||
5f8c1a54 AK |
403 | return v; |
404 | } | |
405 | ||
406 | static void mce_wrmsrl(u32 msr, u64 v) | |
407 | { | |
0a3aee0d | 408 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 409 | int offset = msr_to_offset(msr); |
11868a2d | 410 | |
ea149b36 AK |
411 | if (offset >= 0) |
412 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
413 | return; | |
414 | } | |
5f8c1a54 AK |
415 | wrmsrl(msr, v); |
416 | } | |
417 | ||
b8325c5b HS |
418 | /* |
419 | * Collect all global (w.r.t. this processor) status about this machine | |
420 | * check into our "mce" struct so that we can use it later to assess | |
421 | * the severity of the problem as we read per-bank specific details. | |
422 | */ | |
423 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
424 | { | |
425 | mce_setup(m); | |
426 | ||
427 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
428 | if (regs) { | |
429 | /* | |
430 | * Get the address of the instruction at the time of | |
431 | * the machine check error. | |
432 | */ | |
433 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
434 | m->ip = regs->ip; | |
435 | m->cs = regs->cs; | |
a129a7c8 AK |
436 | |
437 | /* | |
438 | * When in VM86 mode make the cs look like ring 3 | |
439 | * always. This is a lie, but it's better than passing | |
440 | * the additional vm86 bit around everywhere. | |
441 | */ | |
442 | if (v8086_mode(regs)) | |
443 | m->cs |= 3; | |
b8325c5b HS |
444 | } |
445 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
446 | if (mca_cfg.rip_msr) |
447 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
448 | } |
449 | } | |
450 | ||
9b1beaf2 AK |
451 | /* |
452 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
453 | * process context work function. This is vastly simplified because there's | |
454 | * only a single reader and a single writer. | |
455 | */ | |
456 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
457 | ||
458 | struct mce_ring { | |
459 | unsigned short start; | |
460 | unsigned short end; | |
461 | unsigned long ring[MCE_RING_SIZE]; | |
462 | }; | |
463 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
464 | ||
465 | /* Runs with CPU affinity in workqueue */ | |
466 | static int mce_ring_empty(void) | |
467 | { | |
468 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
469 | ||
470 | return r->start == r->end; | |
471 | } | |
472 | ||
473 | static int mce_ring_get(unsigned long *pfn) | |
474 | { | |
475 | struct mce_ring *r; | |
476 | int ret = 0; | |
477 | ||
478 | *pfn = 0; | |
479 | get_cpu(); | |
480 | r = &__get_cpu_var(mce_ring); | |
481 | if (r->start == r->end) | |
482 | goto out; | |
483 | *pfn = r->ring[r->start]; | |
484 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
485 | ret = 1; | |
486 | out: | |
487 | put_cpu(); | |
488 | return ret; | |
489 | } | |
490 | ||
491 | /* Always runs in MCE context with preempt off */ | |
492 | static int mce_ring_add(unsigned long pfn) | |
493 | { | |
494 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
495 | unsigned next; | |
496 | ||
497 | next = (r->end + 1) % MCE_RING_SIZE; | |
498 | if (next == r->start) | |
499 | return -1; | |
500 | r->ring[r->end] = pfn; | |
501 | wmb(); | |
502 | r->end = next; | |
503 | return 0; | |
504 | } | |
505 | ||
88ccbedd | 506 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 507 | { |
1462594b | 508 | if (mca_cfg.disabled) |
5b4408fd | 509 | return 0; |
3d1712c9 | 510 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
511 | } |
512 | ||
9b1beaf2 AK |
513 | static void mce_schedule_work(void) |
514 | { | |
515 | if (!mce_ring_empty()) { | |
516 | struct work_struct *work = &__get_cpu_var(mce_work); | |
517 | if (!work_pending(work)) | |
518 | schedule_work(work); | |
519 | } | |
520 | } | |
521 | ||
b77e70bf HS |
522 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
523 | ||
524 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 525 | { |
9ff36ee9 | 526 | mce_notify_irq(); |
9b1beaf2 | 527 | mce_schedule_work(); |
ccc3c319 | 528 | } |
ccc3c319 AK |
529 | |
530 | static void mce_report_event(struct pt_regs *regs) | |
531 | { | |
532 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 533 | mce_notify_irq(); |
9b1beaf2 AK |
534 | /* |
535 | * Triggering the work queue here is just an insurance | |
536 | * policy in case the syscall exit notify handler | |
537 | * doesn't run soon enough or ends up running on the | |
538 | * wrong CPU (can happen when audit sleeps) | |
539 | */ | |
540 | mce_schedule_work(); | |
ccc3c319 AK |
541 | return; |
542 | } | |
543 | ||
b77e70bf | 544 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
545 | } |
546 | ||
85f92694 TL |
547 | /* |
548 | * Read ADDR and MISC registers. | |
549 | */ | |
550 | static void mce_read_aux(struct mce *m, int i) | |
551 | { | |
552 | if (m->status & MCI_STATUS_MISCV) | |
553 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
554 | if (m->status & MCI_STATUS_ADDRV) { | |
555 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
556 | ||
557 | /* | |
558 | * Mask the reported address by the reported granularity. | |
559 | */ | |
1462594b | 560 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
561 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
562 | m->addr >>= shift; | |
563 | m->addr <<= shift; | |
564 | } | |
565 | } | |
566 | } | |
567 | ||
ca84f696 AK |
568 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
569 | ||
d88203d1 | 570 | /* |
b79109c3 AK |
571 | * Poll for corrected events or events that happened before reset. |
572 | * Those are just logged through /dev/mcelog. | |
573 | * | |
574 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
575 | * |
576 | * Note: spec recommends to panic for fatal unsignalled | |
577 | * errors here. However this would be quite problematic -- | |
578 | * we would need to reimplement the Monarch handling and | |
579 | * it would mess up the exclusion between exception handler | |
580 | * and poll hander -- * so we skip this for now. | |
581 | * These cases should not happen anyways, or only when the CPU | |
582 | * is already totally * confused. In this case it's likely it will | |
583 | * not fully execute the machine check handler either. | |
b79109c3 | 584 | */ |
ee031c31 | 585 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
586 | { |
587 | struct mce m; | |
588 | int i; | |
589 | ||
c6ae41e7 | 590 | this_cpu_inc(mce_poll_count); |
ca84f696 | 591 | |
b8325c5b | 592 | mce_gather_info(&m, NULL); |
b79109c3 | 593 | |
d203f0b8 | 594 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 595 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
596 | continue; |
597 | ||
598 | m.misc = 0; | |
599 | m.addr = 0; | |
600 | m.bank = i; | |
601 | m.tsc = 0; | |
602 | ||
603 | barrier(); | |
a2d32bcb | 604 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
605 | if (!(m.status & MCI_STATUS_VAL)) |
606 | continue; | |
607 | ||
608 | /* | |
ed7290d0 AK |
609 | * Uncorrected or signalled events are handled by the exception |
610 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
611 | * |
612 | * TBD do the same check for MCI_STATUS_EN here? | |
613 | */ | |
ed7290d0 | 614 | if (!(flags & MCP_UC) && |
1462594b | 615 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
616 | continue; |
617 | ||
85f92694 | 618 | mce_read_aux(&m, i); |
b79109c3 AK |
619 | |
620 | if (!(flags & MCP_TIMESTAMP)) | |
621 | m.tsc = 0; | |
622 | /* | |
623 | * Don't get the IP here because it's unlikely to | |
624 | * have anything to do with the actual error location. | |
625 | */ | |
d203f0b8 | 626 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 627 | mce_log(&m); |
b79109c3 AK |
628 | |
629 | /* | |
630 | * Clear state for this bank. | |
631 | */ | |
a2d32bcb | 632 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
633 | } |
634 | ||
635 | /* | |
636 | * Don't clear MCG_STATUS here because it's only defined for | |
637 | * exceptions. | |
638 | */ | |
88921be3 AK |
639 | |
640 | sync_core(); | |
b79109c3 | 641 | } |
ea149b36 | 642 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 643 | |
bd19a5e6 AK |
644 | /* |
645 | * Do a quick check if any of the events requires a panic. | |
646 | * This decides if we keep the events around or clear them. | |
647 | */ | |
61b0fccd TL |
648 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
649 | struct pt_regs *regs) | |
bd19a5e6 | 650 | { |
95022b8c | 651 | int i, ret = 0; |
bd19a5e6 | 652 | |
d203f0b8 | 653 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 654 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 655 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 656 | __set_bit(i, validp); |
61b0fccd TL |
657 | if (quirk_no_way_out) |
658 | quirk_no_way_out(i, m, regs); | |
659 | } | |
d203f0b8 | 660 | if (mce_severity(m, mca_cfg.tolerant, msg) >= MCE_PANIC_SEVERITY) |
95022b8c | 661 | ret = 1; |
bd19a5e6 | 662 | } |
95022b8c | 663 | return ret; |
bd19a5e6 AK |
664 | } |
665 | ||
3c079792 AK |
666 | /* |
667 | * Variable to establish order between CPUs while scanning. | |
668 | * Each CPU spins initially until executing is equal its number. | |
669 | */ | |
670 | static atomic_t mce_executing; | |
671 | ||
672 | /* | |
673 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
674 | */ | |
675 | static atomic_t mce_callin; | |
676 | ||
677 | /* | |
678 | * Check if a timeout waiting for other CPUs happened. | |
679 | */ | |
680 | static int mce_timed_out(u64 *t) | |
681 | { | |
682 | /* | |
683 | * The others already did panic for some reason. | |
684 | * Bail out like in a timeout. | |
685 | * rmb() to tell the compiler that system_state | |
686 | * might have been modified by someone else. | |
687 | */ | |
688 | rmb(); | |
689 | if (atomic_read(&mce_paniced)) | |
690 | wait_for_panic(); | |
84c2559d | 691 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
692 | goto out; |
693 | if ((s64)*t < SPINUNIT) { | |
694 | /* CHECKME: Make panic default for 1 too? */ | |
d203f0b8 | 695 | if (mca_cfg.tolerant < 1) |
3c079792 AK |
696 | mce_panic("Timeout synchronizing machine check over CPUs", |
697 | NULL, NULL); | |
698 | cpu_missing = 1; | |
699 | return 1; | |
700 | } | |
701 | *t -= SPINUNIT; | |
702 | out: | |
703 | touch_nmi_watchdog(); | |
704 | return 0; | |
705 | } | |
706 | ||
707 | /* | |
708 | * The Monarch's reign. The Monarch is the CPU who entered | |
709 | * the machine check handler first. It waits for the others to | |
710 | * raise the exception too and then grades them. When any | |
711 | * error is fatal panic. Only then let the others continue. | |
712 | * | |
713 | * The other CPUs entering the MCE handler will be controlled by the | |
714 | * Monarch. They are called Subjects. | |
715 | * | |
716 | * This way we prevent any potential data corruption in a unrecoverable case | |
717 | * and also makes sure always all CPU's errors are examined. | |
718 | * | |
680b6cfd | 719 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
720 | * space (not detected by any CPUs) In this case some external agent wants |
721 | * us to shut down, so panic too. | |
722 | * | |
723 | * The other CPUs might still decide to panic if the handler happens | |
724 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
725 | * state and won't corrupt anything by itself. It's ok to let the others | |
726 | * continue for a bit first. | |
727 | * | |
728 | * All the spin loops have timeouts; when a timeout happens a CPU | |
729 | * typically elects itself to be Monarch. | |
730 | */ | |
731 | static void mce_reign(void) | |
732 | { | |
733 | int cpu; | |
734 | struct mce *m = NULL; | |
735 | int global_worst = 0; | |
736 | char *msg = NULL; | |
737 | char *nmsg = NULL; | |
738 | ||
739 | /* | |
740 | * This CPU is the Monarch and the other CPUs have run | |
741 | * through their handlers. | |
742 | * Grade the severity of the errors of all the CPUs. | |
743 | */ | |
744 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
745 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
746 | mca_cfg.tolerant, | |
3c079792 AK |
747 | &nmsg); |
748 | if (severity > global_worst) { | |
749 | msg = nmsg; | |
750 | global_worst = severity; | |
751 | m = &per_cpu(mces_seen, cpu); | |
752 | } | |
753 | } | |
754 | ||
755 | /* | |
756 | * Cannot recover? Panic here then. | |
757 | * This dumps all the mces in the log buffer and stops the | |
758 | * other CPUs. | |
759 | */ | |
d203f0b8 | 760 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
ac960375 | 761 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
762 | |
763 | /* | |
764 | * For UC somewhere we let the CPU who detects it handle it. | |
765 | * Also must let continue the others, otherwise the handling | |
766 | * CPU could deadlock on a lock. | |
767 | */ | |
768 | ||
769 | /* | |
770 | * No machine check event found. Must be some external | |
771 | * source or one CPU is hung. Panic. | |
772 | */ | |
d203f0b8 | 773 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
3c079792 AK |
774 | mce_panic("Machine check from unknown source", NULL, NULL); |
775 | ||
776 | /* | |
777 | * Now clear all the mces_seen so that they don't reappear on | |
778 | * the next mce. | |
779 | */ | |
780 | for_each_possible_cpu(cpu) | |
781 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
782 | } | |
783 | ||
784 | static atomic_t global_nwo; | |
785 | ||
786 | /* | |
787 | * Start of Monarch synchronization. This waits until all CPUs have | |
788 | * entered the exception handler and then determines if any of them | |
789 | * saw a fatal event that requires panic. Then it executes them | |
790 | * in the entry order. | |
791 | * TBD double check parallel CPU hotunplug | |
792 | */ | |
7fb06fc9 | 793 | static int mce_start(int *no_way_out) |
3c079792 | 794 | { |
7fb06fc9 | 795 | int order; |
3c079792 | 796 | int cpus = num_online_cpus(); |
84c2559d | 797 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 798 | |
7fb06fc9 HS |
799 | if (!timeout) |
800 | return -1; | |
3c079792 | 801 | |
7fb06fc9 | 802 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
803 | /* |
804 | * global_nwo should be updated before mce_callin | |
805 | */ | |
806 | smp_wmb(); | |
a95436e4 | 807 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
808 | |
809 | /* | |
810 | * Wait for everyone. | |
811 | */ | |
812 | while (atomic_read(&mce_callin) != cpus) { | |
813 | if (mce_timed_out(&timeout)) { | |
814 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 815 | return -1; |
3c079792 AK |
816 | } |
817 | ndelay(SPINUNIT); | |
818 | } | |
819 | ||
184e1fdf HY |
820 | /* |
821 | * mce_callin should be read before global_nwo | |
822 | */ | |
823 | smp_rmb(); | |
3c079792 | 824 | |
7fb06fc9 HS |
825 | if (order == 1) { |
826 | /* | |
827 | * Monarch: Starts executing now, the others wait. | |
828 | */ | |
3c079792 | 829 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
830 | } else { |
831 | /* | |
832 | * Subject: Now start the scanning loop one by one in | |
833 | * the original callin order. | |
834 | * This way when there are any shared banks it will be | |
835 | * only seen by one CPU before cleared, avoiding duplicates. | |
836 | */ | |
837 | while (atomic_read(&mce_executing) < order) { | |
838 | if (mce_timed_out(&timeout)) { | |
839 | atomic_set(&global_nwo, 0); | |
840 | return -1; | |
841 | } | |
842 | ndelay(SPINUNIT); | |
843 | } | |
3c079792 AK |
844 | } |
845 | ||
846 | /* | |
7fb06fc9 | 847 | * Cache the global no_way_out state. |
3c079792 | 848 | */ |
7fb06fc9 HS |
849 | *no_way_out = atomic_read(&global_nwo); |
850 | ||
851 | return order; | |
3c079792 AK |
852 | } |
853 | ||
854 | /* | |
855 | * Synchronize between CPUs after main scanning loop. | |
856 | * This invokes the bulk of the Monarch processing. | |
857 | */ | |
858 | static int mce_end(int order) | |
859 | { | |
860 | int ret = -1; | |
84c2559d | 861 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
862 | |
863 | if (!timeout) | |
864 | goto reset; | |
865 | if (order < 0) | |
866 | goto reset; | |
867 | ||
868 | /* | |
869 | * Allow others to run. | |
870 | */ | |
871 | atomic_inc(&mce_executing); | |
872 | ||
873 | if (order == 1) { | |
874 | /* CHECKME: Can this race with a parallel hotplug? */ | |
875 | int cpus = num_online_cpus(); | |
876 | ||
877 | /* | |
878 | * Monarch: Wait for everyone to go through their scanning | |
879 | * loops. | |
880 | */ | |
881 | while (atomic_read(&mce_executing) <= cpus) { | |
882 | if (mce_timed_out(&timeout)) | |
883 | goto reset; | |
884 | ndelay(SPINUNIT); | |
885 | } | |
886 | ||
887 | mce_reign(); | |
888 | barrier(); | |
889 | ret = 0; | |
890 | } else { | |
891 | /* | |
892 | * Subject: Wait for Monarch to finish. | |
893 | */ | |
894 | while (atomic_read(&mce_executing) != 0) { | |
895 | if (mce_timed_out(&timeout)) | |
896 | goto reset; | |
897 | ndelay(SPINUNIT); | |
898 | } | |
899 | ||
900 | /* | |
901 | * Don't reset anything. That's done by the Monarch. | |
902 | */ | |
903 | return 0; | |
904 | } | |
905 | ||
906 | /* | |
907 | * Reset all global state. | |
908 | */ | |
909 | reset: | |
910 | atomic_set(&global_nwo, 0); | |
911 | atomic_set(&mce_callin, 0); | |
912 | barrier(); | |
913 | ||
914 | /* | |
915 | * Let others run again. | |
916 | */ | |
917 | atomic_set(&mce_executing, 0); | |
918 | return ret; | |
919 | } | |
920 | ||
9b1beaf2 AK |
921 | /* |
922 | * Check if the address reported by the CPU is in a format we can parse. | |
923 | * It would be possible to add code for most other cases, but all would | |
924 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 925 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
926 | */ |
927 | static int mce_usable_address(struct mce *m) | |
928 | { | |
929 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
930 | return 0; | |
2b90e77e | 931 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 932 | return 0; |
2b90e77e | 933 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
934 | return 0; |
935 | return 1; | |
936 | } | |
937 | ||
3c079792 AK |
938 | static void mce_clear_state(unsigned long *toclear) |
939 | { | |
940 | int i; | |
941 | ||
d203f0b8 | 942 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 943 | if (test_bit(i, toclear)) |
a2d32bcb | 944 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
945 | } |
946 | } | |
947 | ||
af104e39 TL |
948 | /* |
949 | * Need to save faulting physical address associated with a process | |
950 | * in the machine check handler some place where we can grab it back | |
951 | * later in mce_notify_process() | |
952 | */ | |
953 | #define MCE_INFO_MAX 16 | |
954 | ||
955 | struct mce_info { | |
956 | atomic_t inuse; | |
957 | struct task_struct *t; | |
958 | __u64 paddr; | |
dad1743e | 959 | int restartable; |
af104e39 TL |
960 | } mce_info[MCE_INFO_MAX]; |
961 | ||
dad1743e | 962 | static void mce_save_info(__u64 addr, int c) |
af104e39 TL |
963 | { |
964 | struct mce_info *mi; | |
965 | ||
966 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { | |
967 | if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { | |
968 | mi->t = current; | |
969 | mi->paddr = addr; | |
dad1743e | 970 | mi->restartable = c; |
af104e39 TL |
971 | return; |
972 | } | |
973 | } | |
974 | ||
975 | mce_panic("Too many concurrent recoverable errors", NULL, NULL); | |
976 | } | |
977 | ||
978 | static struct mce_info *mce_find_info(void) | |
979 | { | |
980 | struct mce_info *mi; | |
981 | ||
982 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) | |
983 | if (atomic_read(&mi->inuse) && mi->t == current) | |
984 | return mi; | |
985 | return NULL; | |
986 | } | |
987 | ||
988 | static void mce_clear_info(struct mce_info *mi) | |
989 | { | |
990 | atomic_set(&mi->inuse, 0); | |
991 | } | |
992 | ||
b79109c3 AK |
993 | /* |
994 | * The actual machine check handler. This only handles real | |
995 | * exceptions when something got corrupted coming in through int 18. | |
996 | * | |
997 | * This is executed in NMI context not subject to normal locking rules. This | |
998 | * implies that most kernel services cannot be safely used. Don't even | |
999 | * think about putting a printk in there! | |
3c079792 AK |
1000 | * |
1001 | * On Intel systems this is entered on all CPUs in parallel through | |
1002 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1003 | * so be always careful when synchronizing with others. | |
1da177e4 | 1004 | */ |
e9eee03e | 1005 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1006 | { |
1462594b | 1007 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1008 | struct mce m, *final; |
1da177e4 | 1009 | int i; |
3c079792 AK |
1010 | int worst = 0; |
1011 | int severity; | |
1012 | /* | |
1013 | * Establish sequential order between the CPUs entering the machine | |
1014 | * check handler. | |
1015 | */ | |
7fb06fc9 | 1016 | int order; |
bd78432c TH |
1017 | /* |
1018 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1019 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1020 | */ |
1021 | int no_way_out = 0; | |
1022 | /* | |
1023 | * If kill_it gets set, there might be a way to recover from this | |
1024 | * error. | |
1025 | */ | |
1026 | int kill_it = 0; | |
b79109c3 | 1027 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1028 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1029 | char *msg = "Unknown"; |
1da177e4 | 1030 | |
553f265f AK |
1031 | atomic_inc(&mce_entry); |
1032 | ||
c6ae41e7 | 1033 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1034 | |
1462594b | 1035 | if (!cfg->banks) |
32561696 | 1036 | goto out; |
1da177e4 | 1037 | |
b8325c5b | 1038 | mce_gather_info(&m, regs); |
b5f2fa4e | 1039 | |
3c079792 AK |
1040 | final = &__get_cpu_var(mces_seen); |
1041 | *final = m; | |
1042 | ||
95022b8c | 1043 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1044 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1045 | |
1da177e4 LT |
1046 | barrier(); |
1047 | ||
ed7290d0 | 1048 | /* |
a8c321fb TL |
1049 | * When no restart IP might need to kill or panic. |
1050 | * Assume the worst for now, but if we find the | |
1051 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1052 | */ |
1053 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1054 | kill_it = 1; | |
1055 | ||
3c079792 AK |
1056 | /* |
1057 | * Go through all the banks in exclusion of the other CPUs. | |
1058 | * This way we don't report duplicated events on shared banks | |
1059 | * because the first one to see it will clear it. | |
1060 | */ | |
7fb06fc9 | 1061 | order = mce_start(&no_way_out); |
1462594b | 1062 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1063 | __clear_bit(i, toclear); |
95022b8c TL |
1064 | if (!test_bit(i, valid_banks)) |
1065 | continue; | |
cebe1820 | 1066 | if (!mce_banks[i].ctl) |
1da177e4 | 1067 | continue; |
d88203d1 TG |
1068 | |
1069 | m.misc = 0; | |
1da177e4 LT |
1070 | m.addr = 0; |
1071 | m.bank = i; | |
1da177e4 | 1072 | |
a2d32bcb | 1073 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1074 | if ((m.status & MCI_STATUS_VAL) == 0) |
1075 | continue; | |
1076 | ||
b79109c3 | 1077 | /* |
ed7290d0 AK |
1078 | * Non uncorrected or non signaled errors are handled by |
1079 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1080 | */ |
1462594b | 1081 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1082 | !no_way_out) |
b79109c3 AK |
1083 | continue; |
1084 | ||
1085 | /* | |
1086 | * Set taint even when machine check was not enabled. | |
1087 | */ | |
1088 | add_taint(TAINT_MACHINE_CHECK); | |
1089 | ||
1462594b | 1090 | severity = mce_severity(&m, cfg->tolerant, NULL); |
b79109c3 | 1091 | |
ed7290d0 AK |
1092 | /* |
1093 | * When machine check was for corrected handler don't touch, | |
1094 | * unless we're panicing. | |
1095 | */ | |
1096 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1097 | continue; | |
1098 | __set_bit(i, toclear); | |
1099 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1100 | /* |
1101 | * Machine check event was not enabled. Clear, but | |
1102 | * ignore. | |
1103 | */ | |
1104 | continue; | |
1da177e4 LT |
1105 | } |
1106 | ||
85f92694 | 1107 | mce_read_aux(&m, i); |
1da177e4 | 1108 | |
9b1beaf2 AK |
1109 | /* |
1110 | * Action optional error. Queue address for later processing. | |
1111 | * When the ring overflows we just ignore the AO error. | |
1112 | * RED-PEN add some logging mechanism when | |
1113 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1114 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1115 | */ |
1116 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1117 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1118 | ||
b79109c3 | 1119 | mce_log(&m); |
1da177e4 | 1120 | |
3c079792 AK |
1121 | if (severity > worst) { |
1122 | *final = m; | |
1123 | worst = severity; | |
1da177e4 | 1124 | } |
1da177e4 LT |
1125 | } |
1126 | ||
a8c321fb TL |
1127 | /* mce_clear_state will clear *final, save locally for use later */ |
1128 | m = *final; | |
1129 | ||
3c079792 AK |
1130 | if (!no_way_out) |
1131 | mce_clear_state(toclear); | |
1132 | ||
e9eee03e | 1133 | /* |
3c079792 AK |
1134 | * Do most of the synchronization with other CPUs. |
1135 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1136 | */ |
3c079792 AK |
1137 | if (mce_end(order) < 0) |
1138 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1139 | |
1140 | /* | |
a8c321fb TL |
1141 | * At insane "tolerant" levels we take no action. Otherwise |
1142 | * we only die if we have no other choice. For less serious | |
1143 | * issues we try to recover, or limit damage to the current | |
1144 | * process. | |
bd78432c | 1145 | */ |
1462594b | 1146 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1147 | if (no_way_out) |
1148 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1149 | if (worst == MCE_AR_SEVERITY) { | |
1150 | /* schedule action before return to userland */ | |
dad1743e | 1151 | mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); |
a8c321fb TL |
1152 | set_thread_flag(TIF_MCE_NOTIFY); |
1153 | } else if (kill_it) { | |
1154 | force_sig(SIGBUS, current); | |
1155 | } | |
1156 | } | |
e02e68d3 | 1157 | |
3c079792 AK |
1158 | if (worst > 0) |
1159 | mce_report_event(regs); | |
5f8c1a54 | 1160 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1161 | out: |
553f265f | 1162 | atomic_dec(&mce_entry); |
88921be3 | 1163 | sync_core(); |
1da177e4 | 1164 | } |
ea149b36 | 1165 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1166 | |
cd42f4a3 TL |
1167 | #ifndef CONFIG_MEMORY_FAILURE |
1168 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1169 | { |
a8c321fb TL |
1170 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1171 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1172 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1173 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1174 | pfn); | |
cd42f4a3 TL |
1175 | |
1176 | return 0; | |
9b1beaf2 | 1177 | } |
cd42f4a3 | 1178 | #endif |
9b1beaf2 AK |
1179 | |
1180 | /* | |
a8c321fb TL |
1181 | * Called in process context that interrupted by MCE and marked with |
1182 | * TIF_MCE_NOTIFY, just before returning to erroneous userland. | |
1183 | * This code is allowed to sleep. | |
1184 | * Attempt possible recovery such as calling the high level VM handler to | |
1185 | * process any corrupted pages, and kill/signal current process if required. | |
1186 | * Action required errors are handled here. | |
9b1beaf2 AK |
1187 | */ |
1188 | void mce_notify_process(void) | |
1189 | { | |
1190 | unsigned long pfn; | |
a8c321fb | 1191 | struct mce_info *mi = mce_find_info(); |
6751ed65 | 1192 | int flags = MF_ACTION_REQUIRED; |
a8c321fb TL |
1193 | |
1194 | if (!mi) | |
1195 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | |
1196 | pfn = mi->paddr >> PAGE_SHIFT; | |
1197 | ||
1198 | clear_thread_flag(TIF_MCE_NOTIFY); | |
1199 | ||
1200 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1201 | mi->paddr); | |
dad1743e TL |
1202 | /* |
1203 | * We must call memory_failure() here even if the current process is | |
1204 | * doomed. We still need to mark the page as poisoned and alert any | |
1205 | * other users of the page. | |
1206 | */ | |
6751ed65 TL |
1207 | if (!mi->restartable) |
1208 | flags |= MF_MUST_KILL; | |
1209 | if (memory_failure(pfn, MCE_VECTOR, flags) < 0) { | |
a8c321fb TL |
1210 | pr_err("Memory error not recovered"); |
1211 | force_sig(SIGBUS, current); | |
1212 | } | |
1213 | mce_clear_info(mi); | |
9b1beaf2 AK |
1214 | } |
1215 | ||
a8c321fb TL |
1216 | /* |
1217 | * Action optional processing happens here (picking up | |
1218 | * from the list of faulting pages that do_machine_check() | |
1219 | * placed into the "ring"). | |
1220 | */ | |
9b1beaf2 AK |
1221 | static void mce_process_work(struct work_struct *dummy) |
1222 | { | |
a8c321fb TL |
1223 | unsigned long pfn; |
1224 | ||
1225 | while (mce_ring_get(&pfn)) | |
1226 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1227 | } |
1228 | ||
15d5f839 DZ |
1229 | #ifdef CONFIG_X86_MCE_INTEL |
1230 | /*** | |
1231 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1232 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1233 | * @status: Event status information |
1234 | * | |
1235 | * This function should be called by the thermal interrupt after the | |
1236 | * event has been processed and the decision was made to log the event | |
1237 | * further. | |
1238 | * | |
1239 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1240 | * and historically has been the register value of the | |
1241 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1242 | */ | |
b5f2fa4e | 1243 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1244 | { |
1245 | struct mce m; | |
1246 | ||
b5f2fa4e | 1247 | mce_setup(&m); |
15d5f839 DZ |
1248 | m.bank = MCE_THERMAL_BANK; |
1249 | m.status = status; | |
15d5f839 DZ |
1250 | mce_log(&m); |
1251 | } | |
1252 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1253 | ||
1da177e4 | 1254 | /* |
8a336b0a TH |
1255 | * Periodic polling timer for "silent" machine check errors. If the |
1256 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1257 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1258 | */ |
82f7af09 | 1259 | static unsigned long check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1260 | |
82f7af09 | 1261 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1262 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1263 | |
55babd8f CG |
1264 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1265 | { | |
1266 | return interval; | |
1267 | } | |
1268 | ||
1269 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = | |
1270 | mce_adjust_timer_default; | |
1271 | ||
82f7af09 | 1272 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1273 | { |
82f7af09 TG |
1274 | struct timer_list *t = &__get_cpu_var(mce_timer); |
1275 | unsigned long iv; | |
52d168e2 AK |
1276 | |
1277 | WARN_ON(smp_processor_id() != data); | |
1278 | ||
7b543a53 | 1279 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1280 | machine_check_poll(MCP_TIMESTAMP, |
1281 | &__get_cpu_var(mce_poll_banks)); | |
55babd8f | 1282 | mce_intel_cmci_poll(); |
e9eee03e | 1283 | } |
1da177e4 LT |
1284 | |
1285 | /* | |
e02e68d3 TH |
1286 | * Alert userspace if needed. If we logged an MCE, reduce the |
1287 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1288 | */ |
82f7af09 | 1289 | iv = __this_cpu_read(mce_next_interval); |
55babd8f | 1290 | if (mce_notify_irq()) { |
958fb3c5 | 1291 | iv = max(iv / 2, (unsigned long) HZ/100); |
55babd8f | 1292 | } else { |
82f7af09 | 1293 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
55babd8f CG |
1294 | iv = mce_adjust_timer(iv); |
1295 | } | |
82f7af09 | 1296 | __this_cpu_write(mce_next_interval, iv); |
55babd8f CG |
1297 | /* Might have become 0 after CMCI storm subsided */ |
1298 | if (iv) { | |
1299 | t->expires = jiffies + iv; | |
1300 | add_timer_on(t, smp_processor_id()); | |
1301 | } | |
1302 | } | |
e02e68d3 | 1303 | |
55babd8f CG |
1304 | /* |
1305 | * Ensure that the timer is firing in @interval from now. | |
1306 | */ | |
1307 | void mce_timer_kick(unsigned long interval) | |
1308 | { | |
1309 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1310 | unsigned long when = jiffies + interval; | |
1311 | unsigned long iv = __this_cpu_read(mce_next_interval); | |
1312 | ||
1313 | if (timer_pending(t)) { | |
1314 | if (time_before(when, t->expires)) | |
1315 | mod_timer_pinned(t, when); | |
1316 | } else { | |
1317 | t->expires = round_jiffies(when); | |
1318 | add_timer_on(t, smp_processor_id()); | |
1319 | } | |
1320 | if (interval < iv) | |
1321 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1322 | } |
1323 | ||
9aaef96f HS |
1324 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1325 | static void mce_timer_delete_all(void) | |
1326 | { | |
1327 | int cpu; | |
1328 | ||
1329 | for_each_online_cpu(cpu) | |
1330 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1331 | } | |
1332 | ||
9bd98405 AK |
1333 | static void mce_do_trigger(struct work_struct *work) |
1334 | { | |
1020bcbc | 1335 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1336 | } |
1337 | ||
1338 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1339 | ||
e02e68d3 | 1340 | /* |
9bd98405 AK |
1341 | * Notify the user(s) about new machine check events. |
1342 | * Can be called from interrupt context, but not from machine check/NMI | |
1343 | * context. | |
e02e68d3 | 1344 | */ |
9ff36ee9 | 1345 | int mce_notify_irq(void) |
e02e68d3 | 1346 | { |
8457c84d AK |
1347 | /* Not more than two messages every minute */ |
1348 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1349 | ||
1020bcbc | 1350 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1351 | /* wake processes polling /dev/mcelog */ |
1352 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1353 | |
1354 | /* | |
1355 | * There is no risk of missing notifications because | |
1356 | * work_pending is always cleared before the function is | |
1357 | * executed. | |
1358 | */ | |
1020bcbc | 1359 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1360 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1361 | |
8457c84d | 1362 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1363 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1364 | |
1365 | return 1; | |
1da177e4 | 1366 | } |
e02e68d3 TH |
1367 | return 0; |
1368 | } | |
9ff36ee9 | 1369 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1370 | |
cffd377e | 1371 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1372 | { |
1373 | int i; | |
d203f0b8 | 1374 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1375 | |
d203f0b8 | 1376 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1377 | if (!mce_banks) |
1378 | return -ENOMEM; | |
d203f0b8 BP |
1379 | |
1380 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1381 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1382 | |
cebe1820 AK |
1383 | b->ctl = -1ULL; |
1384 | b->init = 1; | |
1385 | } | |
1386 | return 0; | |
1387 | } | |
1388 | ||
d88203d1 | 1389 | /* |
1da177e4 LT |
1390 | * Initialize Machine Checks for a CPU. |
1391 | */ | |
5e09954a | 1392 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1393 | { |
0d7482e3 | 1394 | unsigned b; |
e9eee03e | 1395 | u64 cap; |
1da177e4 LT |
1396 | |
1397 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1398 | |
1399 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1400 | if (!mca_cfg.banks) |
c767a54b | 1401 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1402 | |
0d7482e3 | 1403 | if (b > MAX_NR_BANKS) { |
c767a54b | 1404 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1405 | MAX_NR_BANKS, b); |
1406 | b = MAX_NR_BANKS; | |
1407 | } | |
1408 | ||
1409 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1410 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1411 | mca_cfg.banks = b; | |
1412 | ||
cebe1820 | 1413 | if (!mce_banks) { |
cffd377e | 1414 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1415 | |
cebe1820 AK |
1416 | if (err) |
1417 | return err; | |
1da177e4 | 1418 | } |
0d7482e3 | 1419 | |
94ad8474 | 1420 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1421 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1422 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1423 | |
ed7290d0 | 1424 | if (cap & MCG_SER_P) |
1462594b | 1425 | mca_cfg.ser = true; |
ed7290d0 | 1426 | |
0d7482e3 AK |
1427 | return 0; |
1428 | } | |
1429 | ||
5e09954a | 1430 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1431 | { |
84c2559d | 1432 | enum mcp_flags m_fl = 0; |
e9eee03e | 1433 | mce_banks_t all_banks; |
0d7482e3 AK |
1434 | u64 cap; |
1435 | int i; | |
1436 | ||
84c2559d BP |
1437 | if (!mca_cfg.bootlog) |
1438 | m_fl = MCP_DONTLOG; | |
1439 | ||
b79109c3 AK |
1440 | /* |
1441 | * Log the machine checks left over from the previous reset. | |
1442 | */ | |
ee031c31 | 1443 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1444 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 LT |
1445 | |
1446 | set_in_cr4(X86_CR4_MCE); | |
1447 | ||
0d7482e3 | 1448 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1449 | if (cap & MCG_CTL_P) |
1450 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1451 | ||
d203f0b8 | 1452 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1453 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1454 | |
cebe1820 | 1455 | if (!b->init) |
06b7a7a5 | 1456 | continue; |
a2d32bcb AK |
1457 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1458 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1459 | } |
1da177e4 LT |
1460 | } |
1461 | ||
61b0fccd TL |
1462 | /* |
1463 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1464 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1465 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1466 | * whether the machine check occurred in kernel or user mode, and also | |
1467 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1468 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1469 | */ | |
1470 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1471 | { | |
1472 | if (bank != 0) | |
1473 | return; | |
1474 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1475 | return; | |
1476 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1477 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1478 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1479 | MCACOD)) != | |
1480 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1481 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1482 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1483 | return; | |
1484 | ||
1485 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1486 | m->ip = regs->ip; | |
1487 | m->cs = regs->cs; | |
1488 | } | |
1489 | ||
1da177e4 | 1490 | /* Add per CPU specific workarounds here */ |
5e09954a | 1491 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1492 | { |
d203f0b8 BP |
1493 | struct mca_config *cfg = &mca_cfg; |
1494 | ||
e412cd25 | 1495 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1496 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1497 | return -EOPNOTSUPP; |
1498 | } | |
1499 | ||
1da177e4 | 1500 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1501 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1502 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1503 | /* |
1504 | * disable GART TBL walk error reporting, which | |
1505 | * trips off incorrectly with the IOMMU & 3ware | |
1506 | * & Cerberus: | |
1507 | */ | |
cebe1820 | 1508 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1509 | } |
84c2559d | 1510 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1511 | /* |
1512 | * Lots of broken BIOS around that don't clear them | |
1513 | * by default and leave crap in there. Don't log: | |
1514 | */ | |
84c2559d | 1515 | cfg->bootlog = 0; |
e9eee03e | 1516 | } |
2e6f694f AK |
1517 | /* |
1518 | * Various K7s with broken bank 0 around. Always disable | |
1519 | * by default. | |
1520 | */ | |
d203f0b8 | 1521 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1522 | mce_banks[0].ctl = 0; |
575203b4 BP |
1523 | |
1524 | /* | |
1525 | * Turn off MC4_MISC thresholding banks on those models since | |
1526 | * they're not supported there. | |
1527 | */ | |
1528 | if (c->x86 == 0x15 && | |
1529 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1530 | int i; | |
1531 | u64 val, hwcr; | |
1532 | bool need_toggle; | |
1533 | u32 msrs[] = { | |
1534 | 0x00000413, /* MC4_MISC0 */ | |
1535 | 0xc0000408, /* MC4_MISC1 */ | |
1536 | }; | |
1537 | ||
1538 | rdmsrl(MSR_K7_HWCR, hwcr); | |
1539 | ||
1540 | /* McStatusWrEn has to be set */ | |
1541 | need_toggle = !(hwcr & BIT(18)); | |
1542 | ||
1543 | if (need_toggle) | |
1544 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
1545 | ||
1546 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | |
1547 | rdmsrl(msrs[i], val); | |
1548 | ||
1549 | /* CntP bit set? */ | |
80f03361 BP |
1550 | if (val & BIT_64(62)) { |
1551 | val &= ~BIT_64(62); | |
1552 | wrmsrl(msrs[i], val); | |
575203b4 BP |
1553 | } |
1554 | } | |
1555 | ||
1556 | /* restore old settings */ | |
1557 | if (need_toggle) | |
1558 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1559 | } | |
1da177e4 | 1560 | } |
e583538f | 1561 | |
06b7a7a5 AK |
1562 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1563 | /* | |
1564 | * SDM documents that on family 6 bank 0 should not be written | |
1565 | * because it aliases to another special BIOS controlled | |
1566 | * register. | |
1567 | * But it's not aliased anymore on model 0x1a+ | |
1568 | * Don't ignore bank 0 completely because there could be a | |
1569 | * valid event later, merely don't write CTL0. | |
1570 | */ | |
1571 | ||
d203f0b8 | 1572 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1573 | mce_banks[0].init = 0; |
3c079792 AK |
1574 | |
1575 | /* | |
1576 | * All newer Intel systems support MCE broadcasting. Enable | |
1577 | * synchronization with a one second timeout. | |
1578 | */ | |
1579 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1580 | cfg->monarch_timeout < 0) |
1581 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1582 | |
e412cd25 IM |
1583 | /* |
1584 | * There are also broken BIOSes on some Pentium M and | |
1585 | * earlier systems: | |
1586 | */ | |
84c2559d BP |
1587 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1588 | cfg->bootlog = 0; | |
61b0fccd TL |
1589 | |
1590 | if (c->x86 == 6 && c->x86_model == 45) | |
1591 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1592 | } |
84c2559d BP |
1593 | if (cfg->monarch_timeout < 0) |
1594 | cfg->monarch_timeout = 0; | |
1595 | if (cfg->bootlog != 0) | |
7af19e4a | 1596 | cfg->panic_timeout = 30; |
e412cd25 IM |
1597 | |
1598 | return 0; | |
d88203d1 | 1599 | } |
1da177e4 | 1600 | |
3a97fc34 | 1601 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1602 | { |
1603 | if (c->x86 != 5) | |
3a97fc34 HS |
1604 | return 0; |
1605 | ||
4efc0670 AK |
1606 | switch (c->x86_vendor) { |
1607 | case X86_VENDOR_INTEL: | |
c6978369 | 1608 | intel_p5_mcheck_init(c); |
3a97fc34 | 1609 | return 1; |
4efc0670 AK |
1610 | break; |
1611 | case X86_VENDOR_CENTAUR: | |
1612 | winchip_mcheck_init(c); | |
3a97fc34 | 1613 | return 1; |
4efc0670 AK |
1614 | break; |
1615 | } | |
3a97fc34 HS |
1616 | |
1617 | return 0; | |
4efc0670 AK |
1618 | } |
1619 | ||
5e09954a | 1620 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1621 | { |
1622 | switch (c->x86_vendor) { | |
1623 | case X86_VENDOR_INTEL: | |
1624 | mce_intel_feature_init(c); | |
55babd8f | 1625 | mce_adjust_timer = mce_intel_adjust_timer; |
1da177e4 | 1626 | break; |
89b831ef JS |
1627 | case X86_VENDOR_AMD: |
1628 | mce_amd_feature_init(c); | |
1629 | break; | |
1da177e4 LT |
1630 | default: |
1631 | break; | |
1632 | } | |
1633 | } | |
1634 | ||
26c3c283 | 1635 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1636 | { |
55babd8f | 1637 | unsigned long iv = mce_adjust_timer(check_interval * HZ); |
52d168e2 | 1638 | |
26c3c283 | 1639 | __this_cpu_write(mce_next_interval, iv); |
bc09effa | 1640 | |
7af19e4a | 1641 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1642 | return; |
1643 | ||
82f7af09 | 1644 | t->expires = round_jiffies(jiffies + iv); |
5be6066a | 1645 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1646 | } |
1647 | ||
26c3c283 TG |
1648 | static void __mcheck_cpu_init_timer(void) |
1649 | { | |
1650 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1651 | unsigned int cpu = smp_processor_id(); | |
1652 | ||
1653 | setup_timer(t, mce_timer_fn, cpu); | |
1654 | mce_start_timer(cpu, t); | |
1655 | } | |
1656 | ||
9eda8cb3 AK |
1657 | /* Handle unconfigured int18 (should never happen) */ |
1658 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1659 | { | |
c767a54b | 1660 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1661 | smp_processor_id()); |
1662 | } | |
1663 | ||
1664 | /* Call the installed machine check handler for this CPU setup. */ | |
1665 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1666 | unexpected_machine_check; | |
1667 | ||
d88203d1 | 1668 | /* |
1da177e4 | 1669 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1670 | * Must be called with preempt off: |
1da177e4 | 1671 | */ |
5e09954a | 1672 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1673 | { |
1462594b | 1674 | if (mca_cfg.disabled) |
4efc0670 AK |
1675 | return; |
1676 | ||
3a97fc34 HS |
1677 | if (__mcheck_cpu_ancient_init(c)) |
1678 | return; | |
4efc0670 | 1679 | |
5b4408fd | 1680 | if (!mce_available(c)) |
1da177e4 LT |
1681 | return; |
1682 | ||
5e09954a | 1683 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1684 | mca_cfg.disabled = true; |
0d7482e3 AK |
1685 | return; |
1686 | } | |
0d7482e3 | 1687 | |
5d727926 AK |
1688 | machine_check_vector = do_machine_check; |
1689 | ||
5e09954a BP |
1690 | __mcheck_cpu_init_generic(); |
1691 | __mcheck_cpu_init_vendor(c); | |
1692 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1693 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1694 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1695 | } |
1696 | ||
1697 | /* | |
93b62c3c | 1698 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1699 | */ |
1700 | ||
93b62c3c HS |
1701 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1702 | static int mce_chrdev_open_count; /* #times opened */ | |
1703 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1704 | |
93b62c3c | 1705 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1706 | { |
93b62c3c | 1707 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1708 | |
93b62c3c HS |
1709 | if (mce_chrdev_open_exclu || |
1710 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1711 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1712 | |
f528e7ba TH |
1713 | return -EBUSY; |
1714 | } | |
1715 | ||
1716 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1717 | mce_chrdev_open_exclu = 1; |
1718 | mce_chrdev_open_count++; | |
f528e7ba | 1719 | |
93b62c3c | 1720 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1721 | |
bd78432c | 1722 | return nonseekable_open(inode, file); |
f528e7ba TH |
1723 | } |
1724 | ||
93b62c3c | 1725 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1726 | { |
93b62c3c | 1727 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1728 | |
93b62c3c HS |
1729 | mce_chrdev_open_count--; |
1730 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1731 | |
93b62c3c | 1732 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1733 | |
1734 | return 0; | |
1735 | } | |
1736 | ||
d88203d1 TG |
1737 | static void collect_tscs(void *data) |
1738 | { | |
1da177e4 | 1739 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1740 | |
1da177e4 | 1741 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1742 | } |
1da177e4 | 1743 | |
482908b4 HY |
1744 | static int mce_apei_read_done; |
1745 | ||
1746 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1747 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1748 | { | |
1749 | int rc; | |
1750 | u64 record_id; | |
1751 | struct mce m; | |
1752 | ||
1753 | if (usize < sizeof(struct mce)) | |
1754 | return -EINVAL; | |
1755 | ||
1756 | rc = apei_read_mce(&m, &record_id); | |
1757 | /* Error or no more MCE record */ | |
1758 | if (rc <= 0) { | |
1759 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1760 | /* |
1761 | * When ERST is disabled, mce_chrdev_read() should return | |
1762 | * "no record" instead of "no device." | |
1763 | */ | |
1764 | if (rc == -ENODEV) | |
1765 | return 0; | |
482908b4 HY |
1766 | return rc; |
1767 | } | |
1768 | rc = -EFAULT; | |
1769 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1770 | return rc; | |
1771 | /* | |
1772 | * In fact, we should have cleared the record after that has | |
1773 | * been flushed to the disk or sent to network in | |
1774 | * /sbin/mcelog, but we have no interface to support that now, | |
1775 | * so just clear it to avoid duplication. | |
1776 | */ | |
1777 | rc = apei_clear_mce(record_id); | |
1778 | if (rc) { | |
1779 | mce_apei_read_done = 1; | |
1780 | return rc; | |
1781 | } | |
1782 | *ubuf += sizeof(struct mce); | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
93b62c3c HS |
1787 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1788 | size_t usize, loff_t *off) | |
1da177e4 | 1789 | { |
e9eee03e | 1790 | char __user *buf = ubuf; |
f0de53bb | 1791 | unsigned long *cpu_tsc; |
ef41df43 | 1792 | unsigned prev, next; |
1da177e4 LT |
1793 | int i, err; |
1794 | ||
6bca67f9 | 1795 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1796 | if (!cpu_tsc) |
1797 | return -ENOMEM; | |
1798 | ||
93b62c3c | 1799 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1800 | |
1801 | if (!mce_apei_read_done) { | |
1802 | err = __mce_read_apei(&buf, usize); | |
1803 | if (err || buf != ubuf) | |
1804 | goto out; | |
1805 | } | |
1806 | ||
f56e8a07 | 1807 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1808 | |
1809 | /* Only supports full reads right now */ | |
482908b4 HY |
1810 | err = -EINVAL; |
1811 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1812 | goto out; | |
1da177e4 LT |
1813 | |
1814 | err = 0; | |
ef41df43 HY |
1815 | prev = 0; |
1816 | do { | |
1817 | for (i = prev; i < next; i++) { | |
1818 | unsigned long start = jiffies; | |
559faa6b | 1819 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1820 | |
559faa6b | 1821 | while (!m->finished) { |
ef41df43 | 1822 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1823 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1824 | goto timeout; |
1825 | } | |
1826 | cpu_relax(); | |
673242c1 | 1827 | } |
ef41df43 | 1828 | smp_rmb(); |
559faa6b HS |
1829 | err |= copy_to_user(buf, m, sizeof(*m)); |
1830 | buf += sizeof(*m); | |
ef41df43 HY |
1831 | timeout: |
1832 | ; | |
673242c1 | 1833 | } |
1da177e4 | 1834 | |
ef41df43 HY |
1835 | memset(mcelog.entry + prev, 0, |
1836 | (next - prev) * sizeof(struct mce)); | |
1837 | prev = next; | |
1838 | next = cmpxchg(&mcelog.next, prev, 0); | |
1839 | } while (next != prev); | |
1da177e4 | 1840 | |
b2b18660 | 1841 | synchronize_sched(); |
1da177e4 | 1842 | |
d88203d1 TG |
1843 | /* |
1844 | * Collect entries that were still getting written before the | |
1845 | * synchronize. | |
1846 | */ | |
15c8b6c1 | 1847 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1848 | |
d88203d1 | 1849 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1850 | struct mce *m = &mcelog.entry[i]; |
1851 | ||
1852 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1853 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1854 | smp_rmb(); |
559faa6b HS |
1855 | buf += sizeof(*m); |
1856 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1857 | } |
d88203d1 | 1858 | } |
482908b4 HY |
1859 | |
1860 | if (err) | |
1861 | err = -EFAULT; | |
1862 | ||
1863 | out: | |
93b62c3c | 1864 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1865 | kfree(cpu_tsc); |
e9eee03e | 1866 | |
482908b4 | 1867 | return err ? err : buf - ubuf; |
1da177e4 LT |
1868 | } |
1869 | ||
93b62c3c | 1870 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1871 | { |
93b62c3c | 1872 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1873 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1874 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1875 | if (!mce_apei_read_done && apei_check_mce()) |
1876 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1877 | return 0; |
1878 | } | |
1879 | ||
93b62c3c HS |
1880 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1881 | unsigned long arg) | |
1da177e4 LT |
1882 | { |
1883 | int __user *p = (int __user *)arg; | |
d88203d1 | 1884 | |
1da177e4 | 1885 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1886 | return -EPERM; |
e9eee03e | 1887 | |
1da177e4 | 1888 | switch (cmd) { |
d88203d1 | 1889 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1890 | return put_user(sizeof(struct mce), p); |
1891 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1892 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1893 | case MCE_GETCLEAR_FLAGS: { |
1894 | unsigned flags; | |
d88203d1 TG |
1895 | |
1896 | do { | |
1da177e4 | 1897 | flags = mcelog.flags; |
d88203d1 | 1898 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1899 | |
d88203d1 | 1900 | return put_user(flags, p); |
1da177e4 LT |
1901 | } |
1902 | default: | |
d88203d1 TG |
1903 | return -ENOTTY; |
1904 | } | |
1da177e4 LT |
1905 | } |
1906 | ||
66f5ddf3 LT |
1907 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1908 | size_t usize, loff_t *off); | |
1909 | ||
1910 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1911 | const char __user *ubuf, | |
1912 | size_t usize, loff_t *off)) | |
1913 | { | |
1914 | mce_write = fn; | |
1915 | } | |
1916 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1917 | ||
1918 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1919 | size_t usize, loff_t *off) | |
1920 | { | |
1921 | if (mce_write) | |
1922 | return mce_write(filp, ubuf, usize, off); | |
1923 | else | |
1924 | return -EINVAL; | |
1925 | } | |
1926 | ||
1927 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1928 | .open = mce_chrdev_open, |
1929 | .release = mce_chrdev_release, | |
1930 | .read = mce_chrdev_read, | |
66f5ddf3 | 1931 | .write = mce_chrdev_write, |
93b62c3c HS |
1932 | .poll = mce_chrdev_poll, |
1933 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1934 | .llseek = no_llseek, | |
1da177e4 LT |
1935 | }; |
1936 | ||
93b62c3c | 1937 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1938 | MISC_MCELOG_MINOR, |
1939 | "mcelog", | |
1940 | &mce_chrdev_ops, | |
1941 | }; | |
1942 | ||
13503fa9 | 1943 | /* |
62fdac59 HS |
1944 | * mce=off Disables machine check |
1945 | * mce=no_cmci Disables CMCI | |
1946 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1947 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1948 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1949 | * monarchtimeout is how long to wait for other CPUs on machine | |
1950 | * check, or 0 to not wait | |
13503fa9 HS |
1951 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1952 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1953 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 1954 | */ |
1da177e4 LT |
1955 | static int __init mcheck_enable(char *str) |
1956 | { | |
d203f0b8 BP |
1957 | struct mca_config *cfg = &mca_cfg; |
1958 | ||
e3346fc4 | 1959 | if (*str == 0) { |
4efc0670 | 1960 | enable_p5_mce(); |
e3346fc4 BZ |
1961 | return 1; |
1962 | } | |
4efc0670 AK |
1963 | if (*str == '=') |
1964 | str++; | |
1da177e4 | 1965 | if (!strcmp(str, "off")) |
1462594b | 1966 | cfg->disabled = true; |
62fdac59 | 1967 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 1968 | cfg->cmci_disabled = true; |
62fdac59 | 1969 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 1970 | cfg->dont_log_ce = true; |
62fdac59 | 1971 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 1972 | cfg->ignore_ce = true; |
13503fa9 | 1973 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 1974 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 1975 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 1976 | cfg->bios_cmci_threshold = true; |
3c079792 | 1977 | else if (isdigit(str[0])) { |
d203f0b8 | 1978 | get_option(&str, &(cfg->tolerant)); |
3c079792 AK |
1979 | if (*str == ',') { |
1980 | ++str; | |
84c2559d | 1981 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 AK |
1982 | } |
1983 | } else { | |
c767a54b | 1984 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
1985 | return 0; |
1986 | } | |
9b41046c | 1987 | return 1; |
1da177e4 | 1988 | } |
4efc0670 | 1989 | __setup("mce", mcheck_enable); |
1da177e4 | 1990 | |
a2202aa2 | 1991 | int __init mcheck_init(void) |
b33a6363 | 1992 | { |
a2202aa2 YW |
1993 | mcheck_intel_therm_init(); |
1994 | ||
b33a6363 BP |
1995 | return 0; |
1996 | } | |
b33a6363 | 1997 | |
d88203d1 | 1998 | /* |
c7cece89 | 1999 | * mce_syscore: PM support |
d88203d1 | 2000 | */ |
1da177e4 | 2001 | |
973a2dd1 AK |
2002 | /* |
2003 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2004 | * them later. | |
2005 | */ | |
5e09954a | 2006 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2007 | { |
2008 | int i; | |
2009 | ||
d203f0b8 | 2010 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2011 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2012 | |
cebe1820 | 2013 | if (b->init) |
a2d32bcb | 2014 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2015 | } |
973a2dd1 AK |
2016 | return 0; |
2017 | } | |
2018 | ||
c7cece89 | 2019 | static int mce_syscore_suspend(void) |
973a2dd1 | 2020 | { |
5e09954a | 2021 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2022 | } |
2023 | ||
c7cece89 | 2024 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2025 | { |
f3c6ea1b | 2026 | mce_disable_error_reporting(); |
973a2dd1 AK |
2027 | } |
2028 | ||
e9eee03e IM |
2029 | /* |
2030 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2031 | * Only one CPU is active at this time, the others get re-added later using | |
2032 | * CPU hotplug: | |
2033 | */ | |
c7cece89 | 2034 | static void mce_syscore_resume(void) |
1da177e4 | 2035 | { |
5e09954a | 2036 | __mcheck_cpu_init_generic(); |
7b543a53 | 2037 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2038 | } |
2039 | ||
f3c6ea1b | 2040 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2041 | .suspend = mce_syscore_suspend, |
2042 | .shutdown = mce_syscore_shutdown, | |
2043 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2044 | }; |
2045 | ||
c7cece89 | 2046 | /* |
8a25a2fd | 2047 | * mce_device: Sysfs support |
c7cece89 HS |
2048 | */ |
2049 | ||
52d168e2 AK |
2050 | static void mce_cpu_restart(void *data) |
2051 | { | |
7b543a53 | 2052 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 2053 | return; |
5e09954a BP |
2054 | __mcheck_cpu_init_generic(); |
2055 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2056 | } |
2057 | ||
1da177e4 | 2058 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2059 | static void mce_restart(void) |
2060 | { | |
9aaef96f | 2061 | mce_timer_delete_all(); |
52d168e2 | 2062 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2063 | } |
2064 | ||
9af43b54 | 2065 | /* Toggle features for corrected errors */ |
9aaef96f | 2066 | static void mce_disable_cmci(void *data) |
9af43b54 | 2067 | { |
7b543a53 | 2068 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 2069 | return; |
9af43b54 HS |
2070 | cmci_clear(); |
2071 | } | |
2072 | ||
2073 | static void mce_enable_ce(void *all) | |
2074 | { | |
7b543a53 | 2075 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2076 | return; |
2077 | cmci_reenable(); | |
2078 | cmci_recheck(); | |
2079 | if (all) | |
5e09954a | 2080 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2081 | } |
2082 | ||
8a25a2fd | 2083 | static struct bus_type mce_subsys = { |
e9eee03e | 2084 | .name = "machinecheck", |
8a25a2fd | 2085 | .dev_name = "machinecheck", |
1da177e4 LT |
2086 | }; |
2087 | ||
d6126ef5 | 2088 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e IM |
2089 | |
2090 | __cpuinitdata | |
2091 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 2092 | |
8a25a2fd | 2093 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2094 | { |
2095 | return container_of(attr, struct mce_bank, attr); | |
2096 | } | |
0d7482e3 | 2097 | |
8a25a2fd | 2098 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2099 | char *buf) |
2100 | { | |
cebe1820 | 2101 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2102 | } |
2103 | ||
8a25a2fd | 2104 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2105 | const char *buf, size_t size) |
0d7482e3 | 2106 | { |
9319cec8 | 2107 | u64 new; |
e9eee03e | 2108 | |
9319cec8 | 2109 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 2110 | return -EINVAL; |
e9eee03e | 2111 | |
cebe1820 | 2112 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2113 | mce_restart(); |
e9eee03e | 2114 | |
9319cec8 | 2115 | return size; |
0d7482e3 | 2116 | } |
a98f0dd3 | 2117 | |
e9eee03e | 2118 | static ssize_t |
8a25a2fd | 2119 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2120 | { |
1020bcbc | 2121 | strcpy(buf, mce_helper); |
a98f0dd3 | 2122 | strcat(buf, "\n"); |
1020bcbc | 2123 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2124 | } |
2125 | ||
8a25a2fd | 2126 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2127 | const char *buf, size_t siz) |
a98f0dd3 AK |
2128 | { |
2129 | char *p; | |
e9eee03e | 2130 | |
1020bcbc HS |
2131 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2132 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2133 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2134 | |
e9084ec9 | 2135 | if (p) |
e9eee03e IM |
2136 | *p = 0; |
2137 | ||
e9084ec9 | 2138 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2139 | } |
2140 | ||
8a25a2fd KS |
2141 | static ssize_t set_ignore_ce(struct device *s, |
2142 | struct device_attribute *attr, | |
9af43b54 HS |
2143 | const char *buf, size_t size) |
2144 | { | |
2145 | u64 new; | |
2146 | ||
2147 | if (strict_strtoull(buf, 0, &new) < 0) | |
2148 | return -EINVAL; | |
2149 | ||
7af19e4a | 2150 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2151 | if (new) { |
2152 | /* disable ce features */ | |
9aaef96f HS |
2153 | mce_timer_delete_all(); |
2154 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2155 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2156 | } else { |
2157 | /* enable ce features */ | |
7af19e4a | 2158 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2159 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2160 | } | |
2161 | } | |
2162 | return size; | |
2163 | } | |
2164 | ||
8a25a2fd KS |
2165 | static ssize_t set_cmci_disabled(struct device *s, |
2166 | struct device_attribute *attr, | |
9af43b54 HS |
2167 | const char *buf, size_t size) |
2168 | { | |
2169 | u64 new; | |
2170 | ||
2171 | if (strict_strtoull(buf, 0, &new) < 0) | |
2172 | return -EINVAL; | |
2173 | ||
7af19e4a | 2174 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2175 | if (new) { |
2176 | /* disable cmci */ | |
9aaef96f | 2177 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2178 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2179 | } else { |
2180 | /* enable cmci */ | |
7af19e4a | 2181 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2182 | on_each_cpu(mce_enable_ce, NULL, 1); |
2183 | } | |
2184 | } | |
2185 | return size; | |
2186 | } | |
2187 | ||
8a25a2fd KS |
2188 | static ssize_t store_int_with_restart(struct device *s, |
2189 | struct device_attribute *attr, | |
b56f642d AK |
2190 | const char *buf, size_t size) |
2191 | { | |
8a25a2fd | 2192 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2193 | mce_restart(); |
2194 | return ret; | |
2195 | } | |
2196 | ||
8a25a2fd | 2197 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2198 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2199 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2200 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2201 | |
8a25a2fd KS |
2202 | static struct dev_ext_attribute dev_attr_check_interval = { |
2203 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2204 | &check_interval |
2205 | }; | |
e9eee03e | 2206 | |
8a25a2fd | 2207 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2208 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2209 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2210 | }; |
2211 | ||
8a25a2fd | 2212 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2213 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2214 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2215 | }; |
2216 | ||
8a25a2fd KS |
2217 | static struct device_attribute *mce_device_attrs[] = { |
2218 | &dev_attr_tolerant.attr, | |
2219 | &dev_attr_check_interval.attr, | |
2220 | &dev_attr_trigger, | |
2221 | &dev_attr_monarch_timeout.attr, | |
2222 | &dev_attr_dont_log_ce.attr, | |
2223 | &dev_attr_ignore_ce.attr, | |
2224 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2225 | NULL |
2226 | }; | |
1da177e4 | 2227 | |
8a25a2fd | 2228 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2229 | |
e032d807 GKH |
2230 | static void mce_device_release(struct device *dev) |
2231 | { | |
2232 | kfree(dev); | |
2233 | } | |
2234 | ||
8a25a2fd KS |
2235 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
2236 | static __cpuinit int mce_device_create(unsigned int cpu) | |
1da177e4 | 2237 | { |
e032d807 | 2238 | struct device *dev; |
1da177e4 | 2239 | int err; |
b1f49f95 | 2240 | int i, j; |
92cb7612 | 2241 | |
90367556 | 2242 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2243 | return -EIO; |
2244 | ||
e032d807 GKH |
2245 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2246 | if (!dev) | |
2247 | return -ENOMEM; | |
8a25a2fd KS |
2248 | dev->id = cpu; |
2249 | dev->bus = &mce_subsys; | |
e032d807 | 2250 | dev->release = &mce_device_release; |
91c6d400 | 2251 | |
8a25a2fd | 2252 | err = device_register(dev); |
d435d862 AM |
2253 | if (err) |
2254 | return err; | |
2255 | ||
8a25a2fd KS |
2256 | for (i = 0; mce_device_attrs[i]; i++) { |
2257 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2258 | if (err) |
2259 | goto error; | |
2260 | } | |
d203f0b8 | 2261 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2262 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2263 | if (err) |
2264 | goto error2; | |
2265 | } | |
8a25a2fd | 2266 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2267 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2268 | |
d435d862 | 2269 | return 0; |
0d7482e3 | 2270 | error2: |
b1f49f95 | 2271 | while (--j >= 0) |
8a25a2fd | 2272 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2273 | error: |
cb491fca | 2274 | while (--i >= 0) |
8a25a2fd | 2275 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2276 | |
8a25a2fd | 2277 | device_unregister(dev); |
d435d862 | 2278 | |
91c6d400 AK |
2279 | return err; |
2280 | } | |
2281 | ||
8a25a2fd | 2282 | static __cpuinit void mce_device_remove(unsigned int cpu) |
91c6d400 | 2283 | { |
d6126ef5 | 2284 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2285 | int i; |
2286 | ||
8a25a2fd | 2287 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2288 | return; |
2289 | ||
8a25a2fd KS |
2290 | for (i = 0; mce_device_attrs[i]; i++) |
2291 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2292 | |
d203f0b8 | 2293 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2294 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2295 | |
8a25a2fd KS |
2296 | device_unregister(dev); |
2297 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2298 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2299 | } |
91c6d400 | 2300 | |
d6b75584 | 2301 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2302 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2303 | { |
88ccbedd | 2304 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2305 | int i; |
d6b75584 | 2306 | |
7b543a53 | 2307 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2308 | return; |
767df1bd | 2309 | |
88ccbedd AK |
2310 | if (!(action & CPU_TASKS_FROZEN)) |
2311 | cmci_clear(); | |
d203f0b8 | 2312 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2313 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2314 | |
cebe1820 | 2315 | if (b->init) |
a2d32bcb | 2316 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2317 | } |
d6b75584 AK |
2318 | } |
2319 | ||
767df1bd | 2320 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2321 | { |
88ccbedd | 2322 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2323 | int i; |
d6b75584 | 2324 | |
7b543a53 | 2325 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2326 | return; |
e9eee03e | 2327 | |
88ccbedd AK |
2328 | if (!(action & CPU_TASKS_FROZEN)) |
2329 | cmci_reenable(); | |
d203f0b8 | 2330 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2331 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2332 | |
cebe1820 | 2333 | if (b->init) |
a2d32bcb | 2334 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2335 | } |
d6b75584 AK |
2336 | } |
2337 | ||
91c6d400 | 2338 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2339 | static int __cpuinit |
2340 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2341 | { |
2342 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2343 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2344 | |
1a65f970 | 2345 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2346 | case CPU_ONLINE: |
8a25a2fd | 2347 | mce_device_create(cpu); |
8735728e RW |
2348 | if (threshold_cpu_callback) |
2349 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2350 | break; |
91c6d400 | 2351 | case CPU_DEAD: |
8735728e RW |
2352 | if (threshold_cpu_callback) |
2353 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2354 | mce_device_remove(cpu); |
55babd8f | 2355 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2356 | break; |
52d168e2 | 2357 | case CPU_DOWN_PREPARE: |
88ccbedd | 2358 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2359 | del_timer_sync(t); |
52d168e2 AK |
2360 | break; |
2361 | case CPU_DOWN_FAILED: | |
88ccbedd | 2362 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2363 | mce_start_timer(cpu, t); |
88ccbedd | 2364 | break; |
1a65f970 TG |
2365 | } |
2366 | ||
2367 | if (action == CPU_POST_DEAD) { | |
88ccbedd AK |
2368 | /* intentionally ignoring frozen here */ |
2369 | cmci_rediscover(cpu); | |
91c6d400 | 2370 | } |
1a65f970 | 2371 | |
bae19fe0 | 2372 | return NOTIFY_OK; |
91c6d400 AK |
2373 | } |
2374 | ||
1e35669d | 2375 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2376 | .notifier_call = mce_cpu_callback, |
2377 | }; | |
2378 | ||
cebe1820 | 2379 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2380 | { |
2381 | int i; | |
2382 | ||
d203f0b8 | 2383 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2384 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2385 | struct device_attribute *a = &b->attr; |
e9eee03e | 2386 | |
a07e4156 | 2387 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2388 | a->attr.name = b->attrname; |
2389 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2390 | |
2391 | a->attr.mode = 0644; | |
2392 | a->show = show_bank; | |
2393 | a->store = set_bank; | |
0d7482e3 | 2394 | } |
0d7482e3 AK |
2395 | } |
2396 | ||
5e09954a | 2397 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2398 | { |
2399 | int err; | |
2400 | int i = 0; | |
2401 | ||
1da177e4 LT |
2402 | if (!mce_available(&boot_cpu_data)) |
2403 | return -EIO; | |
0d7482e3 | 2404 | |
8a25a2fd | 2405 | zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
996867d0 | 2406 | |
cebe1820 | 2407 | mce_init_banks(); |
0d7482e3 | 2408 | |
8a25a2fd | 2409 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 AM |
2410 | if (err) |
2411 | return err; | |
91c6d400 AK |
2412 | |
2413 | for_each_online_cpu(i) { | |
8a25a2fd | 2414 | err = mce_device_create(i); |
d435d862 AM |
2415 | if (err) |
2416 | return err; | |
91c6d400 AK |
2417 | } |
2418 | ||
f3c6ea1b | 2419 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2420 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2421 | |
2422 | /* register character device /dev/mcelog */ | |
2423 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2424 | |
1da177e4 | 2425 | return err; |
1da177e4 | 2426 | } |
cef12ee5 | 2427 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2428 | |
d7c3c9a6 AK |
2429 | /* |
2430 | * Old style boot options parsing. Only for compatibility. | |
2431 | */ | |
2432 | static int __init mcheck_disable(char *str) | |
2433 | { | |
1462594b | 2434 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2435 | return 1; |
2436 | } | |
2437 | __setup("nomce", mcheck_disable); | |
a988d334 | 2438 | |
5be9ed25 HY |
2439 | #ifdef CONFIG_DEBUG_FS |
2440 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2441 | { |
5be9ed25 | 2442 | static struct dentry *dmce; |
a988d334 | 2443 | |
5be9ed25 HY |
2444 | if (!dmce) |
2445 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2446 | |
5be9ed25 HY |
2447 | return dmce; |
2448 | } | |
a988d334 | 2449 | |
bf783f9f HY |
2450 | static void mce_reset(void) |
2451 | { | |
2452 | cpu_missing = 0; | |
2453 | atomic_set(&mce_fake_paniced, 0); | |
2454 | atomic_set(&mce_executing, 0); | |
2455 | atomic_set(&mce_callin, 0); | |
2456 | atomic_set(&global_nwo, 0); | |
2457 | } | |
a988d334 | 2458 | |
bf783f9f HY |
2459 | static int fake_panic_get(void *data, u64 *val) |
2460 | { | |
2461 | *val = fake_panic; | |
2462 | return 0; | |
a988d334 IM |
2463 | } |
2464 | ||
bf783f9f | 2465 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2466 | { |
bf783f9f HY |
2467 | mce_reset(); |
2468 | fake_panic = val; | |
2469 | return 0; | |
a988d334 | 2470 | } |
a988d334 | 2471 | |
bf783f9f HY |
2472 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2473 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2474 | |
5e09954a | 2475 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2476 | { |
bf783f9f HY |
2477 | struct dentry *dmce, *ffake_panic; |
2478 | ||
2479 | dmce = mce_get_debugfs_dir(); | |
2480 | if (!dmce) | |
2481 | return -ENOMEM; | |
2482 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2483 | &fake_panic_fops); | |
2484 | if (!ffake_panic) | |
2485 | return -ENOMEM; | |
2486 | ||
2487 | return 0; | |
d7c3c9a6 | 2488 | } |
5e09954a | 2489 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2490 | #endif |