Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
93b62c3c | 51 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 52 | |
f56e8a07 | 53 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 54 | rcu_dereference_index_check((p), \ |
f56e8a07 | 55 | rcu_read_lock_sched_held() || \ |
93b62c3c | 56 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 57 | |
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
4e5b3e69 | 61 | int mce_disabled __read_mostly; |
04b2b1a4 | 62 | |
3c079792 AK |
63 | #define SPINUNIT 100 /* 100ns */ |
64 | ||
553f265f AK |
65 | atomic_t mce_entry; |
66 | ||
01ca79f1 AK |
67 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
68 | ||
bd78432c TH |
69 | /* |
70 | * Tolerant levels: | |
71 | * 0: always panic on uncorrected errors, log corrected errors | |
72 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
73 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
74 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
75 | */ | |
4e5b3e69 HS |
76 | static int tolerant __read_mostly = 1; |
77 | static int banks __read_mostly; | |
4e5b3e69 HS |
78 | static int rip_msr __read_mostly; |
79 | static int mce_bootlog __read_mostly = -1; | |
80 | static int monarch_timeout __read_mostly = -1; | |
81 | static int mce_panic_timeout __read_mostly; | |
82 | static int mce_dont_log_ce __read_mostly; | |
83 | int mce_cmci_disabled __read_mostly; | |
84 | int mce_ignore_ce __read_mostly; | |
85 | int mce_ser __read_mostly; | |
a98f0dd3 | 86 | |
cebe1820 AK |
87 | struct mce_bank *mce_banks __read_mostly; |
88 | ||
1020bcbc HS |
89 | /* User mode helper program triggered by machine check event */ |
90 | static unsigned long mce_need_notify; | |
91 | static char mce_helper[128]; | |
92 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 93 | |
93b62c3c HS |
94 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
95 | ||
3c079792 AK |
96 | static DEFINE_PER_CPU(struct mce, mces_seen); |
97 | static int cpu_missing; | |
98 | ||
ee031c31 AK |
99 | /* MCA banks polled by the period polling timer for corrected events */ |
100 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
101 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
102 | }; | |
103 | ||
9b1beaf2 AK |
104 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
105 | ||
61b0fccd TL |
106 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
107 | ||
3653ada5 BP |
108 | /* |
109 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
110 | * MCE errors in a human-readable form. | |
111 | */ | |
112 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
113 | ||
b5f2fa4e AK |
114 | /* Do initial initialization of a struct mce */ |
115 | void mce_setup(struct mce *m) | |
116 | { | |
117 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 118 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 119 | rdtscll(m->tsc); |
8ee08347 AK |
120 | /* We hope get_seconds stays lockless */ |
121 | m->time = get_seconds(); | |
122 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
123 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 124 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
125 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
126 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
127 | } |
128 | ||
ea149b36 AK |
129 | DEFINE_PER_CPU(struct mce, injectm); |
130 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
131 | ||
1da177e4 LT |
132 | /* |
133 | * Lockless MCE logging infrastructure. | |
134 | * This avoids deadlocks on printk locks without having to break locks. Also | |
135 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
136 | */ | |
137 | ||
231fd906 | 138 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
139 | .signature = MCE_LOG_SIGNATURE, |
140 | .len = MCE_LOG_LEN, | |
141 | .recordlen = sizeof(struct mce), | |
d88203d1 | 142 | }; |
1da177e4 LT |
143 | |
144 | void mce_log(struct mce *mce) | |
145 | { | |
146 | unsigned next, entry; | |
f0cb5452 | 147 | int ret = 0; |
e9eee03e | 148 | |
8968f9d3 HS |
149 | /* Emit the trace record: */ |
150 | trace_mce_record(mce); | |
151 | ||
f0cb5452 BP |
152 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
153 | if (ret == NOTIFY_STOP) | |
154 | return; | |
155 | ||
1da177e4 | 156 | mce->finished = 0; |
7644143c | 157 | wmb(); |
1da177e4 | 158 | for (;;) { |
f56e8a07 | 159 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 160 | for (;;) { |
696e409d | 161 | |
e9eee03e IM |
162 | /* |
163 | * When the buffer fills up discard new entries. | |
164 | * Assume that the earlier errors are the more | |
165 | * interesting ones: | |
166 | */ | |
673242c1 | 167 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
168 | set_bit(MCE_OVERFLOW, |
169 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
170 | return; |
171 | } | |
e9eee03e | 172 | /* Old left over entry. Skip: */ |
673242c1 AK |
173 | if (mcelog.entry[entry].finished) { |
174 | entry++; | |
175 | continue; | |
176 | } | |
7644143c | 177 | break; |
1da177e4 | 178 | } |
1da177e4 LT |
179 | smp_rmb(); |
180 | next = entry + 1; | |
181 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
182 | break; | |
183 | } | |
184 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 185 | wmb(); |
1da177e4 | 186 | mcelog.entry[entry].finished = 1; |
7644143c | 187 | wmb(); |
1da177e4 | 188 | |
a0189c70 | 189 | mce->finished = 1; |
1020bcbc | 190 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
191 | } |
192 | ||
09371957 BP |
193 | static void drain_mcelog_buffer(void) |
194 | { | |
195 | unsigned int next, i, prev = 0; | |
196 | ||
b11e3d78 | 197 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
198 | |
199 | do { | |
200 | struct mce *m; | |
201 | ||
202 | /* drain what was logged during boot */ | |
203 | for (i = prev; i < next; i++) { | |
204 | unsigned long start = jiffies; | |
205 | unsigned retries = 1; | |
206 | ||
207 | m = &mcelog.entry[i]; | |
208 | ||
209 | while (!m->finished) { | |
210 | if (time_after_eq(jiffies, start + 2*retries)) | |
211 | retries++; | |
212 | ||
213 | cpu_relax(); | |
214 | ||
215 | if (!m->finished && retries >= 4) { | |
c767a54b | 216 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
217 | break; |
218 | } | |
219 | } | |
220 | smp_rmb(); | |
221 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
222 | } | |
223 | ||
224 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
225 | prev = next; | |
226 | next = cmpxchg(&mcelog.next, prev, 0); | |
227 | } while (next != prev); | |
228 | } | |
229 | ||
230 | ||
3653ada5 BP |
231 | void mce_register_decode_chain(struct notifier_block *nb) |
232 | { | |
233 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 234 | drain_mcelog_buffer(); |
3653ada5 BP |
235 | } |
236 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
237 | ||
238 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
239 | { | |
240 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
241 | } | |
242 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
243 | ||
77e26cca | 244 | static void print_mce(struct mce *m) |
1da177e4 | 245 | { |
dffa4b2f BP |
246 | int ret = 0; |
247 | ||
a2d7b0d4 | 248 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 249 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 250 | |
65ea5b03 | 251 | if (m->ip) { |
a2d7b0d4 | 252 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
253 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
254 | m->cs, m->ip); | |
255 | ||
1da177e4 | 256 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 257 | print_symbol("{%s}", m->ip); |
f436f8bb | 258 | pr_cont("\n"); |
1da177e4 | 259 | } |
f436f8bb | 260 | |
a2d7b0d4 | 261 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 262 | if (m->addr) |
f436f8bb | 263 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 264 | if (m->misc) |
f436f8bb | 265 | pr_cont("MISC %llx ", m->misc); |
549d042d | 266 | |
f436f8bb | 267 | pr_cont("\n"); |
506ed6b5 AK |
268 | /* |
269 | * Note this output is parsed by external tools and old fields | |
270 | * should not be changed. | |
271 | */ | |
881e23e5 | 272 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
273 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
274 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
275 | |
276 | /* | |
277 | * Print out human-readable details about the MCE error, | |
fb253195 | 278 | * (if the CPU has an implementation for that) |
f436f8bb | 279 | */ |
dffa4b2f BP |
280 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
281 | if (ret == NOTIFY_STOP) | |
282 | return; | |
283 | ||
284 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
285 | } |
286 | ||
f94b61c2 AK |
287 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
288 | ||
289 | static atomic_t mce_paniced; | |
290 | ||
bf783f9f HY |
291 | static int fake_panic; |
292 | static atomic_t mce_fake_paniced; | |
293 | ||
f94b61c2 AK |
294 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
295 | static void wait_for_panic(void) | |
296 | { | |
297 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 298 | |
f94b61c2 AK |
299 | preempt_disable(); |
300 | local_irq_enable(); | |
301 | while (timeout-- > 0) | |
302 | udelay(1); | |
29b0f591 AK |
303 | if (panic_timeout == 0) |
304 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
305 | panic("Panicing machine check CPU died"); |
306 | } | |
307 | ||
bd19a5e6 | 308 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 309 | { |
482908b4 | 310 | int i, apei_err = 0; |
e02e68d3 | 311 | |
bf783f9f HY |
312 | if (!fake_panic) { |
313 | /* | |
314 | * Make sure only one CPU runs in machine check panic | |
315 | */ | |
316 | if (atomic_inc_return(&mce_paniced) > 1) | |
317 | wait_for_panic(); | |
318 | barrier(); | |
f94b61c2 | 319 | |
bf783f9f HY |
320 | bust_spinlocks(1); |
321 | console_verbose(); | |
322 | } else { | |
323 | /* Don't log too much for fake panic */ | |
324 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
325 | return; | |
326 | } | |
a0189c70 | 327 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 328 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 329 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
330 | if (!(m->status & MCI_STATUS_VAL)) |
331 | continue; | |
482908b4 | 332 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 333 | print_mce(m); |
482908b4 HY |
334 | if (!apei_err) |
335 | apei_err = apei_write_mce(m); | |
336 | } | |
a0189c70 AK |
337 | } |
338 | /* Now print uncorrected but with the final one last */ | |
339 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
340 | struct mce *m = &mcelog.entry[i]; | |
341 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 342 | continue; |
77e26cca HS |
343 | if (!(m->status & MCI_STATUS_UC)) |
344 | continue; | |
482908b4 | 345 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 346 | print_mce(m); |
482908b4 HY |
347 | if (!apei_err) |
348 | apei_err = apei_write_mce(m); | |
349 | } | |
1da177e4 | 350 | } |
482908b4 | 351 | if (final) { |
77e26cca | 352 | print_mce(final); |
482908b4 HY |
353 | if (!apei_err) |
354 | apei_err = apei_write_mce(final); | |
355 | } | |
3c079792 | 356 | if (cpu_missing) |
a2d7b0d4 | 357 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 358 | if (exp) |
a2d7b0d4 | 359 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
360 | if (!fake_panic) { |
361 | if (panic_timeout == 0) | |
362 | panic_timeout = mce_panic_timeout; | |
363 | panic(msg); | |
364 | } else | |
a2d7b0d4 | 365 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 366 | } |
1da177e4 | 367 | |
ea149b36 AK |
368 | /* Support code for software error injection */ |
369 | ||
370 | static int msr_to_offset(u32 msr) | |
371 | { | |
0a3aee0d | 372 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 373 | |
ea149b36 AK |
374 | if (msr == rip_msr) |
375 | return offsetof(struct mce, ip); | |
a2d32bcb | 376 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 377 | return offsetof(struct mce, status); |
a2d32bcb | 378 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 379 | return offsetof(struct mce, addr); |
a2d32bcb | 380 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
381 | return offsetof(struct mce, misc); |
382 | if (msr == MSR_IA32_MCG_STATUS) | |
383 | return offsetof(struct mce, mcgstatus); | |
384 | return -1; | |
385 | } | |
386 | ||
5f8c1a54 AK |
387 | /* MSR access wrappers used for error injection */ |
388 | static u64 mce_rdmsrl(u32 msr) | |
389 | { | |
390 | u64 v; | |
11868a2d | 391 | |
0a3aee0d | 392 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 393 | int offset = msr_to_offset(msr); |
11868a2d | 394 | |
ea149b36 AK |
395 | if (offset < 0) |
396 | return 0; | |
397 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
398 | } | |
11868a2d IM |
399 | |
400 | if (rdmsrl_safe(msr, &v)) { | |
401 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
402 | /* | |
403 | * Return zero in case the access faulted. This should | |
404 | * not happen normally but can happen if the CPU does | |
405 | * something weird, or if the code is buggy. | |
406 | */ | |
407 | v = 0; | |
408 | } | |
409 | ||
5f8c1a54 AK |
410 | return v; |
411 | } | |
412 | ||
413 | static void mce_wrmsrl(u32 msr, u64 v) | |
414 | { | |
0a3aee0d | 415 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 416 | int offset = msr_to_offset(msr); |
11868a2d | 417 | |
ea149b36 AK |
418 | if (offset >= 0) |
419 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
420 | return; | |
421 | } | |
5f8c1a54 AK |
422 | wrmsrl(msr, v); |
423 | } | |
424 | ||
b8325c5b HS |
425 | /* |
426 | * Collect all global (w.r.t. this processor) status about this machine | |
427 | * check into our "mce" struct so that we can use it later to assess | |
428 | * the severity of the problem as we read per-bank specific details. | |
429 | */ | |
430 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
431 | { | |
432 | mce_setup(m); | |
433 | ||
434 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
435 | if (regs) { | |
436 | /* | |
437 | * Get the address of the instruction at the time of | |
438 | * the machine check error. | |
439 | */ | |
440 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
441 | m->ip = regs->ip; | |
442 | m->cs = regs->cs; | |
a129a7c8 AK |
443 | |
444 | /* | |
445 | * When in VM86 mode make the cs look like ring 3 | |
446 | * always. This is a lie, but it's better than passing | |
447 | * the additional vm86 bit around everywhere. | |
448 | */ | |
449 | if (v8086_mode(regs)) | |
450 | m->cs |= 3; | |
b8325c5b HS |
451 | } |
452 | /* Use accurate RIP reporting if available. */ | |
453 | if (rip_msr) | |
454 | m->ip = mce_rdmsrl(rip_msr); | |
455 | } | |
456 | } | |
457 | ||
9b1beaf2 AK |
458 | /* |
459 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
460 | * process context work function. This is vastly simplified because there's | |
461 | * only a single reader and a single writer. | |
462 | */ | |
463 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
464 | ||
465 | struct mce_ring { | |
466 | unsigned short start; | |
467 | unsigned short end; | |
468 | unsigned long ring[MCE_RING_SIZE]; | |
469 | }; | |
470 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
471 | ||
472 | /* Runs with CPU affinity in workqueue */ | |
473 | static int mce_ring_empty(void) | |
474 | { | |
475 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
476 | ||
477 | return r->start == r->end; | |
478 | } | |
479 | ||
480 | static int mce_ring_get(unsigned long *pfn) | |
481 | { | |
482 | struct mce_ring *r; | |
483 | int ret = 0; | |
484 | ||
485 | *pfn = 0; | |
486 | get_cpu(); | |
487 | r = &__get_cpu_var(mce_ring); | |
488 | if (r->start == r->end) | |
489 | goto out; | |
490 | *pfn = r->ring[r->start]; | |
491 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
492 | ret = 1; | |
493 | out: | |
494 | put_cpu(); | |
495 | return ret; | |
496 | } | |
497 | ||
498 | /* Always runs in MCE context with preempt off */ | |
499 | static int mce_ring_add(unsigned long pfn) | |
500 | { | |
501 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
502 | unsigned next; | |
503 | ||
504 | next = (r->end + 1) % MCE_RING_SIZE; | |
505 | if (next == r->start) | |
506 | return -1; | |
507 | r->ring[r->end] = pfn; | |
508 | wmb(); | |
509 | r->end = next; | |
510 | return 0; | |
511 | } | |
512 | ||
88ccbedd | 513 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 514 | { |
04b2b1a4 | 515 | if (mce_disabled) |
5b4408fd | 516 | return 0; |
3d1712c9 | 517 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
518 | } |
519 | ||
9b1beaf2 AK |
520 | static void mce_schedule_work(void) |
521 | { | |
522 | if (!mce_ring_empty()) { | |
523 | struct work_struct *work = &__get_cpu_var(mce_work); | |
524 | if (!work_pending(work)) | |
525 | schedule_work(work); | |
526 | } | |
527 | } | |
528 | ||
b77e70bf HS |
529 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
530 | ||
531 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 532 | { |
9ff36ee9 | 533 | mce_notify_irq(); |
9b1beaf2 | 534 | mce_schedule_work(); |
ccc3c319 | 535 | } |
ccc3c319 AK |
536 | |
537 | static void mce_report_event(struct pt_regs *regs) | |
538 | { | |
539 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 540 | mce_notify_irq(); |
9b1beaf2 AK |
541 | /* |
542 | * Triggering the work queue here is just an insurance | |
543 | * policy in case the syscall exit notify handler | |
544 | * doesn't run soon enough or ends up running on the | |
545 | * wrong CPU (can happen when audit sleeps) | |
546 | */ | |
547 | mce_schedule_work(); | |
ccc3c319 AK |
548 | return; |
549 | } | |
550 | ||
b77e70bf | 551 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
552 | } |
553 | ||
85f92694 TL |
554 | /* |
555 | * Read ADDR and MISC registers. | |
556 | */ | |
557 | static void mce_read_aux(struct mce *m, int i) | |
558 | { | |
559 | if (m->status & MCI_STATUS_MISCV) | |
560 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
561 | if (m->status & MCI_STATUS_ADDRV) { | |
562 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
563 | ||
564 | /* | |
565 | * Mask the reported address by the reported granularity. | |
566 | */ | |
567 | if (mce_ser && (m->status & MCI_STATUS_MISCV)) { | |
568 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); | |
569 | m->addr >>= shift; | |
570 | m->addr <<= shift; | |
571 | } | |
572 | } | |
573 | } | |
574 | ||
ca84f696 AK |
575 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
576 | ||
d88203d1 | 577 | /* |
b79109c3 AK |
578 | * Poll for corrected events or events that happened before reset. |
579 | * Those are just logged through /dev/mcelog. | |
580 | * | |
581 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
582 | * |
583 | * Note: spec recommends to panic for fatal unsignalled | |
584 | * errors here. However this would be quite problematic -- | |
585 | * we would need to reimplement the Monarch handling and | |
586 | * it would mess up the exclusion between exception handler | |
587 | * and poll hander -- * so we skip this for now. | |
588 | * These cases should not happen anyways, or only when the CPU | |
589 | * is already totally * confused. In this case it's likely it will | |
590 | * not fully execute the machine check handler either. | |
b79109c3 | 591 | */ |
ee031c31 | 592 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
593 | { |
594 | struct mce m; | |
595 | int i; | |
596 | ||
c6ae41e7 | 597 | this_cpu_inc(mce_poll_count); |
ca84f696 | 598 | |
b8325c5b | 599 | mce_gather_info(&m, NULL); |
b79109c3 | 600 | |
b79109c3 | 601 | for (i = 0; i < banks; i++) { |
cebe1820 | 602 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
603 | continue; |
604 | ||
605 | m.misc = 0; | |
606 | m.addr = 0; | |
607 | m.bank = i; | |
608 | m.tsc = 0; | |
609 | ||
610 | barrier(); | |
a2d32bcb | 611 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
612 | if (!(m.status & MCI_STATUS_VAL)) |
613 | continue; | |
614 | ||
615 | /* | |
ed7290d0 AK |
616 | * Uncorrected or signalled events are handled by the exception |
617 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
618 | * |
619 | * TBD do the same check for MCI_STATUS_EN here? | |
620 | */ | |
ed7290d0 AK |
621 | if (!(flags & MCP_UC) && |
622 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
623 | continue; |
624 | ||
85f92694 | 625 | mce_read_aux(&m, i); |
b79109c3 AK |
626 | |
627 | if (!(flags & MCP_TIMESTAMP)) | |
628 | m.tsc = 0; | |
629 | /* | |
630 | * Don't get the IP here because it's unlikely to | |
631 | * have anything to do with the actual error location. | |
632 | */ | |
f0cb5452 | 633 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) |
5679af4c | 634 | mce_log(&m); |
b79109c3 AK |
635 | |
636 | /* | |
637 | * Clear state for this bank. | |
638 | */ | |
a2d32bcb | 639 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
640 | } |
641 | ||
642 | /* | |
643 | * Don't clear MCG_STATUS here because it's only defined for | |
644 | * exceptions. | |
645 | */ | |
88921be3 AK |
646 | |
647 | sync_core(); | |
b79109c3 | 648 | } |
ea149b36 | 649 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 650 | |
bd19a5e6 AK |
651 | /* |
652 | * Do a quick check if any of the events requires a panic. | |
653 | * This decides if we keep the events around or clear them. | |
654 | */ | |
61b0fccd TL |
655 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
656 | struct pt_regs *regs) | |
bd19a5e6 | 657 | { |
95022b8c | 658 | int i, ret = 0; |
bd19a5e6 AK |
659 | |
660 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 661 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 662 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 663 | __set_bit(i, validp); |
61b0fccd TL |
664 | if (quirk_no_way_out) |
665 | quirk_no_way_out(i, m, regs); | |
666 | } | |
bd19a5e6 | 667 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
95022b8c | 668 | ret = 1; |
bd19a5e6 | 669 | } |
95022b8c | 670 | return ret; |
bd19a5e6 AK |
671 | } |
672 | ||
3c079792 AK |
673 | /* |
674 | * Variable to establish order between CPUs while scanning. | |
675 | * Each CPU spins initially until executing is equal its number. | |
676 | */ | |
677 | static atomic_t mce_executing; | |
678 | ||
679 | /* | |
680 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
681 | */ | |
682 | static atomic_t mce_callin; | |
683 | ||
684 | /* | |
685 | * Check if a timeout waiting for other CPUs happened. | |
686 | */ | |
687 | static int mce_timed_out(u64 *t) | |
688 | { | |
689 | /* | |
690 | * The others already did panic for some reason. | |
691 | * Bail out like in a timeout. | |
692 | * rmb() to tell the compiler that system_state | |
693 | * might have been modified by someone else. | |
694 | */ | |
695 | rmb(); | |
696 | if (atomic_read(&mce_paniced)) | |
697 | wait_for_panic(); | |
698 | if (!monarch_timeout) | |
699 | goto out; | |
700 | if ((s64)*t < SPINUNIT) { | |
701 | /* CHECKME: Make panic default for 1 too? */ | |
702 | if (tolerant < 1) | |
703 | mce_panic("Timeout synchronizing machine check over CPUs", | |
704 | NULL, NULL); | |
705 | cpu_missing = 1; | |
706 | return 1; | |
707 | } | |
708 | *t -= SPINUNIT; | |
709 | out: | |
710 | touch_nmi_watchdog(); | |
711 | return 0; | |
712 | } | |
713 | ||
714 | /* | |
715 | * The Monarch's reign. The Monarch is the CPU who entered | |
716 | * the machine check handler first. It waits for the others to | |
717 | * raise the exception too and then grades them. When any | |
718 | * error is fatal panic. Only then let the others continue. | |
719 | * | |
720 | * The other CPUs entering the MCE handler will be controlled by the | |
721 | * Monarch. They are called Subjects. | |
722 | * | |
723 | * This way we prevent any potential data corruption in a unrecoverable case | |
724 | * and also makes sure always all CPU's errors are examined. | |
725 | * | |
680b6cfd | 726 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
727 | * space (not detected by any CPUs) In this case some external agent wants |
728 | * us to shut down, so panic too. | |
729 | * | |
730 | * The other CPUs might still decide to panic if the handler happens | |
731 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
732 | * state and won't corrupt anything by itself. It's ok to let the others | |
733 | * continue for a bit first. | |
734 | * | |
735 | * All the spin loops have timeouts; when a timeout happens a CPU | |
736 | * typically elects itself to be Monarch. | |
737 | */ | |
738 | static void mce_reign(void) | |
739 | { | |
740 | int cpu; | |
741 | struct mce *m = NULL; | |
742 | int global_worst = 0; | |
743 | char *msg = NULL; | |
744 | char *nmsg = NULL; | |
745 | ||
746 | /* | |
747 | * This CPU is the Monarch and the other CPUs have run | |
748 | * through their handlers. | |
749 | * Grade the severity of the errors of all the CPUs. | |
750 | */ | |
751 | for_each_possible_cpu(cpu) { | |
752 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
753 | &nmsg); | |
754 | if (severity > global_worst) { | |
755 | msg = nmsg; | |
756 | global_worst = severity; | |
757 | m = &per_cpu(mces_seen, cpu); | |
758 | } | |
759 | } | |
760 | ||
761 | /* | |
762 | * Cannot recover? Panic here then. | |
763 | * This dumps all the mces in the log buffer and stops the | |
764 | * other CPUs. | |
765 | */ | |
766 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 767 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
768 | |
769 | /* | |
770 | * For UC somewhere we let the CPU who detects it handle it. | |
771 | * Also must let continue the others, otherwise the handling | |
772 | * CPU could deadlock on a lock. | |
773 | */ | |
774 | ||
775 | /* | |
776 | * No machine check event found. Must be some external | |
777 | * source or one CPU is hung. Panic. | |
778 | */ | |
680b6cfd | 779 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
780 | mce_panic("Machine check from unknown source", NULL, NULL); |
781 | ||
782 | /* | |
783 | * Now clear all the mces_seen so that they don't reappear on | |
784 | * the next mce. | |
785 | */ | |
786 | for_each_possible_cpu(cpu) | |
787 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
788 | } | |
789 | ||
790 | static atomic_t global_nwo; | |
791 | ||
792 | /* | |
793 | * Start of Monarch synchronization. This waits until all CPUs have | |
794 | * entered the exception handler and then determines if any of them | |
795 | * saw a fatal event that requires panic. Then it executes them | |
796 | * in the entry order. | |
797 | * TBD double check parallel CPU hotunplug | |
798 | */ | |
7fb06fc9 | 799 | static int mce_start(int *no_way_out) |
3c079792 | 800 | { |
7fb06fc9 | 801 | int order; |
3c079792 AK |
802 | int cpus = num_online_cpus(); |
803 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
804 | ||
7fb06fc9 HS |
805 | if (!timeout) |
806 | return -1; | |
3c079792 | 807 | |
7fb06fc9 | 808 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
809 | /* |
810 | * global_nwo should be updated before mce_callin | |
811 | */ | |
812 | smp_wmb(); | |
a95436e4 | 813 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
814 | |
815 | /* | |
816 | * Wait for everyone. | |
817 | */ | |
818 | while (atomic_read(&mce_callin) != cpus) { | |
819 | if (mce_timed_out(&timeout)) { | |
820 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 821 | return -1; |
3c079792 AK |
822 | } |
823 | ndelay(SPINUNIT); | |
824 | } | |
825 | ||
184e1fdf HY |
826 | /* |
827 | * mce_callin should be read before global_nwo | |
828 | */ | |
829 | smp_rmb(); | |
3c079792 | 830 | |
7fb06fc9 HS |
831 | if (order == 1) { |
832 | /* | |
833 | * Monarch: Starts executing now, the others wait. | |
834 | */ | |
3c079792 | 835 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
836 | } else { |
837 | /* | |
838 | * Subject: Now start the scanning loop one by one in | |
839 | * the original callin order. | |
840 | * This way when there are any shared banks it will be | |
841 | * only seen by one CPU before cleared, avoiding duplicates. | |
842 | */ | |
843 | while (atomic_read(&mce_executing) < order) { | |
844 | if (mce_timed_out(&timeout)) { | |
845 | atomic_set(&global_nwo, 0); | |
846 | return -1; | |
847 | } | |
848 | ndelay(SPINUNIT); | |
849 | } | |
3c079792 AK |
850 | } |
851 | ||
852 | /* | |
7fb06fc9 | 853 | * Cache the global no_way_out state. |
3c079792 | 854 | */ |
7fb06fc9 HS |
855 | *no_way_out = atomic_read(&global_nwo); |
856 | ||
857 | return order; | |
3c079792 AK |
858 | } |
859 | ||
860 | /* | |
861 | * Synchronize between CPUs after main scanning loop. | |
862 | * This invokes the bulk of the Monarch processing. | |
863 | */ | |
864 | static int mce_end(int order) | |
865 | { | |
866 | int ret = -1; | |
867 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
868 | ||
869 | if (!timeout) | |
870 | goto reset; | |
871 | if (order < 0) | |
872 | goto reset; | |
873 | ||
874 | /* | |
875 | * Allow others to run. | |
876 | */ | |
877 | atomic_inc(&mce_executing); | |
878 | ||
879 | if (order == 1) { | |
880 | /* CHECKME: Can this race with a parallel hotplug? */ | |
881 | int cpus = num_online_cpus(); | |
882 | ||
883 | /* | |
884 | * Monarch: Wait for everyone to go through their scanning | |
885 | * loops. | |
886 | */ | |
887 | while (atomic_read(&mce_executing) <= cpus) { | |
888 | if (mce_timed_out(&timeout)) | |
889 | goto reset; | |
890 | ndelay(SPINUNIT); | |
891 | } | |
892 | ||
893 | mce_reign(); | |
894 | barrier(); | |
895 | ret = 0; | |
896 | } else { | |
897 | /* | |
898 | * Subject: Wait for Monarch to finish. | |
899 | */ | |
900 | while (atomic_read(&mce_executing) != 0) { | |
901 | if (mce_timed_out(&timeout)) | |
902 | goto reset; | |
903 | ndelay(SPINUNIT); | |
904 | } | |
905 | ||
906 | /* | |
907 | * Don't reset anything. That's done by the Monarch. | |
908 | */ | |
909 | return 0; | |
910 | } | |
911 | ||
912 | /* | |
913 | * Reset all global state. | |
914 | */ | |
915 | reset: | |
916 | atomic_set(&global_nwo, 0); | |
917 | atomic_set(&mce_callin, 0); | |
918 | barrier(); | |
919 | ||
920 | /* | |
921 | * Let others run again. | |
922 | */ | |
923 | atomic_set(&mce_executing, 0); | |
924 | return ret; | |
925 | } | |
926 | ||
9b1beaf2 AK |
927 | /* |
928 | * Check if the address reported by the CPU is in a format we can parse. | |
929 | * It would be possible to add code for most other cases, but all would | |
930 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 931 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
932 | */ |
933 | static int mce_usable_address(struct mce *m) | |
934 | { | |
935 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
936 | return 0; | |
2b90e77e | 937 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 938 | return 0; |
2b90e77e | 939 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
940 | return 0; |
941 | return 1; | |
942 | } | |
943 | ||
3c079792 AK |
944 | static void mce_clear_state(unsigned long *toclear) |
945 | { | |
946 | int i; | |
947 | ||
948 | for (i = 0; i < banks; i++) { | |
949 | if (test_bit(i, toclear)) | |
a2d32bcb | 950 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
951 | } |
952 | } | |
953 | ||
af104e39 TL |
954 | /* |
955 | * Need to save faulting physical address associated with a process | |
956 | * in the machine check handler some place where we can grab it back | |
957 | * later in mce_notify_process() | |
958 | */ | |
959 | #define MCE_INFO_MAX 16 | |
960 | ||
961 | struct mce_info { | |
962 | atomic_t inuse; | |
963 | struct task_struct *t; | |
964 | __u64 paddr; | |
dad1743e | 965 | int restartable; |
af104e39 TL |
966 | } mce_info[MCE_INFO_MAX]; |
967 | ||
dad1743e | 968 | static void mce_save_info(__u64 addr, int c) |
af104e39 TL |
969 | { |
970 | struct mce_info *mi; | |
971 | ||
972 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { | |
973 | if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { | |
974 | mi->t = current; | |
975 | mi->paddr = addr; | |
dad1743e | 976 | mi->restartable = c; |
af104e39 TL |
977 | return; |
978 | } | |
979 | } | |
980 | ||
981 | mce_panic("Too many concurrent recoverable errors", NULL, NULL); | |
982 | } | |
983 | ||
984 | static struct mce_info *mce_find_info(void) | |
985 | { | |
986 | struct mce_info *mi; | |
987 | ||
988 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) | |
989 | if (atomic_read(&mi->inuse) && mi->t == current) | |
990 | return mi; | |
991 | return NULL; | |
992 | } | |
993 | ||
994 | static void mce_clear_info(struct mce_info *mi) | |
995 | { | |
996 | atomic_set(&mi->inuse, 0); | |
997 | } | |
998 | ||
b79109c3 AK |
999 | /* |
1000 | * The actual machine check handler. This only handles real | |
1001 | * exceptions when something got corrupted coming in through int 18. | |
1002 | * | |
1003 | * This is executed in NMI context not subject to normal locking rules. This | |
1004 | * implies that most kernel services cannot be safely used. Don't even | |
1005 | * think about putting a printk in there! | |
3c079792 AK |
1006 | * |
1007 | * On Intel systems this is entered on all CPUs in parallel through | |
1008 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1009 | * so be always careful when synchronizing with others. | |
1da177e4 | 1010 | */ |
e9eee03e | 1011 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1012 | { |
3c079792 | 1013 | struct mce m, *final; |
1da177e4 | 1014 | int i; |
3c079792 AK |
1015 | int worst = 0; |
1016 | int severity; | |
1017 | /* | |
1018 | * Establish sequential order between the CPUs entering the machine | |
1019 | * check handler. | |
1020 | */ | |
7fb06fc9 | 1021 | int order; |
bd78432c TH |
1022 | /* |
1023 | * If no_way_out gets set, there is no safe way to recover from this | |
1024 | * MCE. If tolerant is cranked up, we'll try anyway. | |
1025 | */ | |
1026 | int no_way_out = 0; | |
1027 | /* | |
1028 | * If kill_it gets set, there might be a way to recover from this | |
1029 | * error. | |
1030 | */ | |
1031 | int kill_it = 0; | |
b79109c3 | 1032 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1033 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1034 | char *msg = "Unknown"; |
1da177e4 | 1035 | |
553f265f AK |
1036 | atomic_inc(&mce_entry); |
1037 | ||
c6ae41e7 | 1038 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1039 | |
b79109c3 | 1040 | if (!banks) |
32561696 | 1041 | goto out; |
1da177e4 | 1042 | |
b8325c5b | 1043 | mce_gather_info(&m, regs); |
b5f2fa4e | 1044 | |
3c079792 AK |
1045 | final = &__get_cpu_var(mces_seen); |
1046 | *final = m; | |
1047 | ||
95022b8c | 1048 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1049 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1050 | |
1da177e4 LT |
1051 | barrier(); |
1052 | ||
ed7290d0 | 1053 | /* |
a8c321fb TL |
1054 | * When no restart IP might need to kill or panic. |
1055 | * Assume the worst for now, but if we find the | |
1056 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1057 | */ |
1058 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1059 | kill_it = 1; | |
1060 | ||
3c079792 AK |
1061 | /* |
1062 | * Go through all the banks in exclusion of the other CPUs. | |
1063 | * This way we don't report duplicated events on shared banks | |
1064 | * because the first one to see it will clear it. | |
1065 | */ | |
7fb06fc9 | 1066 | order = mce_start(&no_way_out); |
1da177e4 | 1067 | for (i = 0; i < banks; i++) { |
b79109c3 | 1068 | __clear_bit(i, toclear); |
95022b8c TL |
1069 | if (!test_bit(i, valid_banks)) |
1070 | continue; | |
cebe1820 | 1071 | if (!mce_banks[i].ctl) |
1da177e4 | 1072 | continue; |
d88203d1 TG |
1073 | |
1074 | m.misc = 0; | |
1da177e4 LT |
1075 | m.addr = 0; |
1076 | m.bank = i; | |
1da177e4 | 1077 | |
a2d32bcb | 1078 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1079 | if ((m.status & MCI_STATUS_VAL) == 0) |
1080 | continue; | |
1081 | ||
b79109c3 | 1082 | /* |
ed7290d0 AK |
1083 | * Non uncorrected or non signaled errors are handled by |
1084 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1085 | */ |
ed7290d0 AK |
1086 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
1087 | !no_way_out) | |
b79109c3 AK |
1088 | continue; |
1089 | ||
1090 | /* | |
1091 | * Set taint even when machine check was not enabled. | |
1092 | */ | |
1093 | add_taint(TAINT_MACHINE_CHECK); | |
1094 | ||
ed7290d0 | 1095 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 1096 | |
ed7290d0 AK |
1097 | /* |
1098 | * When machine check was for corrected handler don't touch, | |
1099 | * unless we're panicing. | |
1100 | */ | |
1101 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1102 | continue; | |
1103 | __set_bit(i, toclear); | |
1104 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1105 | /* |
1106 | * Machine check event was not enabled. Clear, but | |
1107 | * ignore. | |
1108 | */ | |
1109 | continue; | |
1da177e4 LT |
1110 | } |
1111 | ||
85f92694 | 1112 | mce_read_aux(&m, i); |
1da177e4 | 1113 | |
9b1beaf2 AK |
1114 | /* |
1115 | * Action optional error. Queue address for later processing. | |
1116 | * When the ring overflows we just ignore the AO error. | |
1117 | * RED-PEN add some logging mechanism when | |
1118 | * usable_address or mce_add_ring fails. | |
1119 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1120 | */ | |
1121 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1122 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1123 | ||
b79109c3 | 1124 | mce_log(&m); |
1da177e4 | 1125 | |
3c079792 AK |
1126 | if (severity > worst) { |
1127 | *final = m; | |
1128 | worst = severity; | |
1da177e4 | 1129 | } |
1da177e4 LT |
1130 | } |
1131 | ||
a8c321fb TL |
1132 | /* mce_clear_state will clear *final, save locally for use later */ |
1133 | m = *final; | |
1134 | ||
3c079792 AK |
1135 | if (!no_way_out) |
1136 | mce_clear_state(toclear); | |
1137 | ||
e9eee03e | 1138 | /* |
3c079792 AK |
1139 | * Do most of the synchronization with other CPUs. |
1140 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1141 | */ |
3c079792 AK |
1142 | if (mce_end(order) < 0) |
1143 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1144 | |
1145 | /* | |
a8c321fb TL |
1146 | * At insane "tolerant" levels we take no action. Otherwise |
1147 | * we only die if we have no other choice. For less serious | |
1148 | * issues we try to recover, or limit damage to the current | |
1149 | * process. | |
bd78432c | 1150 | */ |
a8c321fb TL |
1151 | if (tolerant < 3) { |
1152 | if (no_way_out) | |
1153 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1154 | if (worst == MCE_AR_SEVERITY) { | |
1155 | /* schedule action before return to userland */ | |
dad1743e | 1156 | mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); |
a8c321fb TL |
1157 | set_thread_flag(TIF_MCE_NOTIFY); |
1158 | } else if (kill_it) { | |
1159 | force_sig(SIGBUS, current); | |
1160 | } | |
1161 | } | |
e02e68d3 | 1162 | |
3c079792 AK |
1163 | if (worst > 0) |
1164 | mce_report_event(regs); | |
5f8c1a54 | 1165 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1166 | out: |
553f265f | 1167 | atomic_dec(&mce_entry); |
88921be3 | 1168 | sync_core(); |
1da177e4 | 1169 | } |
ea149b36 | 1170 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1171 | |
cd42f4a3 TL |
1172 | #ifndef CONFIG_MEMORY_FAILURE |
1173 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1174 | { |
a8c321fb TL |
1175 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1176 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1177 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1178 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1179 | pfn); | |
cd42f4a3 TL |
1180 | |
1181 | return 0; | |
9b1beaf2 | 1182 | } |
cd42f4a3 | 1183 | #endif |
9b1beaf2 AK |
1184 | |
1185 | /* | |
a8c321fb TL |
1186 | * Called in process context that interrupted by MCE and marked with |
1187 | * TIF_MCE_NOTIFY, just before returning to erroneous userland. | |
1188 | * This code is allowed to sleep. | |
1189 | * Attempt possible recovery such as calling the high level VM handler to | |
1190 | * process any corrupted pages, and kill/signal current process if required. | |
1191 | * Action required errors are handled here. | |
9b1beaf2 AK |
1192 | */ |
1193 | void mce_notify_process(void) | |
1194 | { | |
1195 | unsigned long pfn; | |
a8c321fb | 1196 | struct mce_info *mi = mce_find_info(); |
6751ed65 | 1197 | int flags = MF_ACTION_REQUIRED; |
a8c321fb TL |
1198 | |
1199 | if (!mi) | |
1200 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | |
1201 | pfn = mi->paddr >> PAGE_SHIFT; | |
1202 | ||
1203 | clear_thread_flag(TIF_MCE_NOTIFY); | |
1204 | ||
1205 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1206 | mi->paddr); | |
dad1743e TL |
1207 | /* |
1208 | * We must call memory_failure() here even if the current process is | |
1209 | * doomed. We still need to mark the page as poisoned and alert any | |
1210 | * other users of the page. | |
1211 | */ | |
6751ed65 TL |
1212 | if (!mi->restartable) |
1213 | flags |= MF_MUST_KILL; | |
1214 | if (memory_failure(pfn, MCE_VECTOR, flags) < 0) { | |
a8c321fb TL |
1215 | pr_err("Memory error not recovered"); |
1216 | force_sig(SIGBUS, current); | |
1217 | } | |
1218 | mce_clear_info(mi); | |
9b1beaf2 AK |
1219 | } |
1220 | ||
a8c321fb TL |
1221 | /* |
1222 | * Action optional processing happens here (picking up | |
1223 | * from the list of faulting pages that do_machine_check() | |
1224 | * placed into the "ring"). | |
1225 | */ | |
9b1beaf2 AK |
1226 | static void mce_process_work(struct work_struct *dummy) |
1227 | { | |
a8c321fb TL |
1228 | unsigned long pfn; |
1229 | ||
1230 | while (mce_ring_get(&pfn)) | |
1231 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1232 | } |
1233 | ||
15d5f839 DZ |
1234 | #ifdef CONFIG_X86_MCE_INTEL |
1235 | /*** | |
1236 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1237 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1238 | * @status: Event status information |
1239 | * | |
1240 | * This function should be called by the thermal interrupt after the | |
1241 | * event has been processed and the decision was made to log the event | |
1242 | * further. | |
1243 | * | |
1244 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1245 | * and historically has been the register value of the | |
1246 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1247 | */ | |
b5f2fa4e | 1248 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1249 | { |
1250 | struct mce m; | |
1251 | ||
b5f2fa4e | 1252 | mce_setup(&m); |
15d5f839 DZ |
1253 | m.bank = MCE_THERMAL_BANK; |
1254 | m.status = status; | |
15d5f839 DZ |
1255 | mce_log(&m); |
1256 | } | |
1257 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1258 | ||
1da177e4 | 1259 | /* |
8a336b0a TH |
1260 | * Periodic polling timer for "silent" machine check errors. If the |
1261 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1262 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1263 | */ |
82f7af09 | 1264 | static unsigned long check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1265 | |
82f7af09 | 1266 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1267 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1268 | |
55babd8f CG |
1269 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1270 | { | |
1271 | return interval; | |
1272 | } | |
1273 | ||
1274 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = | |
1275 | mce_adjust_timer_default; | |
1276 | ||
82f7af09 | 1277 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1278 | { |
82f7af09 TG |
1279 | struct timer_list *t = &__get_cpu_var(mce_timer); |
1280 | unsigned long iv; | |
52d168e2 AK |
1281 | |
1282 | WARN_ON(smp_processor_id() != data); | |
1283 | ||
7b543a53 | 1284 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1285 | machine_check_poll(MCP_TIMESTAMP, |
1286 | &__get_cpu_var(mce_poll_banks)); | |
55babd8f | 1287 | mce_intel_cmci_poll(); |
e9eee03e | 1288 | } |
1da177e4 LT |
1289 | |
1290 | /* | |
e02e68d3 TH |
1291 | * Alert userspace if needed. If we logged an MCE, reduce the |
1292 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1293 | */ |
82f7af09 | 1294 | iv = __this_cpu_read(mce_next_interval); |
55babd8f | 1295 | if (mce_notify_irq()) { |
958fb3c5 | 1296 | iv = max(iv / 2, (unsigned long) HZ/100); |
55babd8f | 1297 | } else { |
82f7af09 | 1298 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
55babd8f CG |
1299 | iv = mce_adjust_timer(iv); |
1300 | } | |
82f7af09 | 1301 | __this_cpu_write(mce_next_interval, iv); |
55babd8f CG |
1302 | /* Might have become 0 after CMCI storm subsided */ |
1303 | if (iv) { | |
1304 | t->expires = jiffies + iv; | |
1305 | add_timer_on(t, smp_processor_id()); | |
1306 | } | |
1307 | } | |
e02e68d3 | 1308 | |
55babd8f CG |
1309 | /* |
1310 | * Ensure that the timer is firing in @interval from now. | |
1311 | */ | |
1312 | void mce_timer_kick(unsigned long interval) | |
1313 | { | |
1314 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1315 | unsigned long when = jiffies + interval; | |
1316 | unsigned long iv = __this_cpu_read(mce_next_interval); | |
1317 | ||
1318 | if (timer_pending(t)) { | |
1319 | if (time_before(when, t->expires)) | |
1320 | mod_timer_pinned(t, when); | |
1321 | } else { | |
1322 | t->expires = round_jiffies(when); | |
1323 | add_timer_on(t, smp_processor_id()); | |
1324 | } | |
1325 | if (interval < iv) | |
1326 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1327 | } |
1328 | ||
9aaef96f HS |
1329 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1330 | static void mce_timer_delete_all(void) | |
1331 | { | |
1332 | int cpu; | |
1333 | ||
1334 | for_each_online_cpu(cpu) | |
1335 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1336 | } | |
1337 | ||
9bd98405 AK |
1338 | static void mce_do_trigger(struct work_struct *work) |
1339 | { | |
1020bcbc | 1340 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1341 | } |
1342 | ||
1343 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1344 | ||
e02e68d3 | 1345 | /* |
9bd98405 AK |
1346 | * Notify the user(s) about new machine check events. |
1347 | * Can be called from interrupt context, but not from machine check/NMI | |
1348 | * context. | |
e02e68d3 | 1349 | */ |
9ff36ee9 | 1350 | int mce_notify_irq(void) |
e02e68d3 | 1351 | { |
8457c84d AK |
1352 | /* Not more than two messages every minute */ |
1353 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1354 | ||
1020bcbc | 1355 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1356 | /* wake processes polling /dev/mcelog */ |
1357 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1358 | |
1359 | /* | |
1360 | * There is no risk of missing notifications because | |
1361 | * work_pending is always cleared before the function is | |
1362 | * executed. | |
1363 | */ | |
1020bcbc | 1364 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1365 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1366 | |
8457c84d | 1367 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1368 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1369 | |
1370 | return 1; | |
1da177e4 | 1371 | } |
e02e68d3 TH |
1372 | return 0; |
1373 | } | |
9ff36ee9 | 1374 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1375 | |
cffd377e | 1376 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1377 | { |
1378 | int i; | |
1379 | ||
1380 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1381 | if (!mce_banks) | |
1382 | return -ENOMEM; | |
1383 | for (i = 0; i < banks; i++) { | |
1384 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1385 | |
cebe1820 AK |
1386 | b->ctl = -1ULL; |
1387 | b->init = 1; | |
1388 | } | |
1389 | return 0; | |
1390 | } | |
1391 | ||
d88203d1 | 1392 | /* |
1da177e4 LT |
1393 | * Initialize Machine Checks for a CPU. |
1394 | */ | |
5e09954a | 1395 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1396 | { |
0d7482e3 | 1397 | unsigned b; |
e9eee03e | 1398 | u64 cap; |
1da177e4 LT |
1399 | |
1400 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1401 | |
1402 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 | 1403 | if (!banks) |
c767a54b | 1404 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1405 | |
0d7482e3 | 1406 | if (b > MAX_NR_BANKS) { |
c767a54b | 1407 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1408 | MAX_NR_BANKS, b); |
1409 | b = MAX_NR_BANKS; | |
1410 | } | |
1411 | ||
1412 | /* Don't support asymmetric configurations today */ | |
1413 | WARN_ON(banks != 0 && b != banks); | |
1414 | banks = b; | |
cebe1820 | 1415 | if (!mce_banks) { |
cffd377e | 1416 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1417 | |
cebe1820 AK |
1418 | if (err) |
1419 | return err; | |
1da177e4 | 1420 | } |
0d7482e3 | 1421 | |
94ad8474 | 1422 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1423 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1424 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1425 | |
ed7290d0 AK |
1426 | if (cap & MCG_SER_P) |
1427 | mce_ser = 1; | |
1428 | ||
0d7482e3 AK |
1429 | return 0; |
1430 | } | |
1431 | ||
5e09954a | 1432 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1433 | { |
e9eee03e | 1434 | mce_banks_t all_banks; |
0d7482e3 AK |
1435 | u64 cap; |
1436 | int i; | |
1437 | ||
b79109c3 AK |
1438 | /* |
1439 | * Log the machine checks left over from the previous reset. | |
1440 | */ | |
ee031c31 | 1441 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1442 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1443 | |
1444 | set_in_cr4(X86_CR4_MCE); | |
1445 | ||
0d7482e3 | 1446 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1447 | if (cap & MCG_CTL_P) |
1448 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1449 | ||
1450 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1451 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1452 | |
cebe1820 | 1453 | if (!b->init) |
06b7a7a5 | 1454 | continue; |
a2d32bcb AK |
1455 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1456 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1457 | } |
1da177e4 LT |
1458 | } |
1459 | ||
61b0fccd TL |
1460 | /* |
1461 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1462 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1463 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1464 | * whether the machine check occurred in kernel or user mode, and also | |
1465 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1466 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1467 | */ | |
1468 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1469 | { | |
1470 | if (bank != 0) | |
1471 | return; | |
1472 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1473 | return; | |
1474 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1475 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1476 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1477 | MCACOD)) != | |
1478 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1479 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1480 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1481 | return; | |
1482 | ||
1483 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1484 | m->ip = regs->ip; | |
1485 | m->cs = regs->cs; | |
1486 | } | |
1487 | ||
1da177e4 | 1488 | /* Add per CPU specific workarounds here */ |
5e09954a | 1489 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1490 | { |
e412cd25 | 1491 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1492 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1493 | return -EOPNOTSUPP; |
1494 | } | |
1495 | ||
1da177e4 | 1496 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1497 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1498 | if (c->x86 == 15 && banks > 4) { |
1499 | /* | |
1500 | * disable GART TBL walk error reporting, which | |
1501 | * trips off incorrectly with the IOMMU & 3ware | |
1502 | * & Cerberus: | |
1503 | */ | |
cebe1820 | 1504 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1505 | } |
1506 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1507 | /* | |
1508 | * Lots of broken BIOS around that don't clear them | |
1509 | * by default and leave crap in there. Don't log: | |
1510 | */ | |
911f6a7b | 1511 | mce_bootlog = 0; |
e9eee03e | 1512 | } |
2e6f694f AK |
1513 | /* |
1514 | * Various K7s with broken bank 0 around. Always disable | |
1515 | * by default. | |
1516 | */ | |
203abd67 | 1517 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1518 | mce_banks[0].ctl = 0; |
575203b4 BP |
1519 | |
1520 | /* | |
1521 | * Turn off MC4_MISC thresholding banks on those models since | |
1522 | * they're not supported there. | |
1523 | */ | |
1524 | if (c->x86 == 0x15 && | |
1525 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1526 | int i; | |
1527 | u64 val, hwcr; | |
1528 | bool need_toggle; | |
1529 | u32 msrs[] = { | |
1530 | 0x00000413, /* MC4_MISC0 */ | |
1531 | 0xc0000408, /* MC4_MISC1 */ | |
1532 | }; | |
1533 | ||
1534 | rdmsrl(MSR_K7_HWCR, hwcr); | |
1535 | ||
1536 | /* McStatusWrEn has to be set */ | |
1537 | need_toggle = !(hwcr & BIT(18)); | |
1538 | ||
1539 | if (need_toggle) | |
1540 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
1541 | ||
1542 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | |
1543 | rdmsrl(msrs[i], val); | |
1544 | ||
1545 | /* CntP bit set? */ | |
80f03361 BP |
1546 | if (val & BIT_64(62)) { |
1547 | val &= ~BIT_64(62); | |
1548 | wrmsrl(msrs[i], val); | |
575203b4 BP |
1549 | } |
1550 | } | |
1551 | ||
1552 | /* restore old settings */ | |
1553 | if (need_toggle) | |
1554 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1555 | } | |
1da177e4 | 1556 | } |
e583538f | 1557 | |
06b7a7a5 AK |
1558 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1559 | /* | |
1560 | * SDM documents that on family 6 bank 0 should not be written | |
1561 | * because it aliases to another special BIOS controlled | |
1562 | * register. | |
1563 | * But it's not aliased anymore on model 0x1a+ | |
1564 | * Don't ignore bank 0 completely because there could be a | |
1565 | * valid event later, merely don't write CTL0. | |
1566 | */ | |
1567 | ||
cebe1820 AK |
1568 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1569 | mce_banks[0].init = 0; | |
3c079792 AK |
1570 | |
1571 | /* | |
1572 | * All newer Intel systems support MCE broadcasting. Enable | |
1573 | * synchronization with a one second timeout. | |
1574 | */ | |
1575 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1576 | monarch_timeout < 0) | |
1577 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1578 | |
e412cd25 IM |
1579 | /* |
1580 | * There are also broken BIOSes on some Pentium M and | |
1581 | * earlier systems: | |
1582 | */ | |
1583 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1584 | mce_bootlog = 0; |
61b0fccd TL |
1585 | |
1586 | if (c->x86 == 6 && c->x86_model == 45) | |
1587 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1588 | } |
3c079792 AK |
1589 | if (monarch_timeout < 0) |
1590 | monarch_timeout = 0; | |
29b0f591 AK |
1591 | if (mce_bootlog != 0) |
1592 | mce_panic_timeout = 30; | |
e412cd25 IM |
1593 | |
1594 | return 0; | |
d88203d1 | 1595 | } |
1da177e4 | 1596 | |
3a97fc34 | 1597 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1598 | { |
1599 | if (c->x86 != 5) | |
3a97fc34 HS |
1600 | return 0; |
1601 | ||
4efc0670 AK |
1602 | switch (c->x86_vendor) { |
1603 | case X86_VENDOR_INTEL: | |
c6978369 | 1604 | intel_p5_mcheck_init(c); |
3a97fc34 | 1605 | return 1; |
4efc0670 AK |
1606 | break; |
1607 | case X86_VENDOR_CENTAUR: | |
1608 | winchip_mcheck_init(c); | |
3a97fc34 | 1609 | return 1; |
4efc0670 AK |
1610 | break; |
1611 | } | |
3a97fc34 HS |
1612 | |
1613 | return 0; | |
4efc0670 AK |
1614 | } |
1615 | ||
5e09954a | 1616 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1617 | { |
1618 | switch (c->x86_vendor) { | |
1619 | case X86_VENDOR_INTEL: | |
1620 | mce_intel_feature_init(c); | |
55babd8f | 1621 | mce_adjust_timer = mce_intel_adjust_timer; |
1da177e4 | 1622 | break; |
89b831ef JS |
1623 | case X86_VENDOR_AMD: |
1624 | mce_amd_feature_init(c); | |
1625 | break; | |
1da177e4 LT |
1626 | default: |
1627 | break; | |
1628 | } | |
1629 | } | |
1630 | ||
26c3c283 | 1631 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1632 | { |
55babd8f | 1633 | unsigned long iv = mce_adjust_timer(check_interval * HZ); |
52d168e2 | 1634 | |
26c3c283 | 1635 | __this_cpu_write(mce_next_interval, iv); |
bc09effa | 1636 | |
26c3c283 | 1637 | if (mce_ignore_ce || !iv) |
62fdac59 HS |
1638 | return; |
1639 | ||
82f7af09 | 1640 | t->expires = round_jiffies(jiffies + iv); |
5be6066a | 1641 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1642 | } |
1643 | ||
26c3c283 TG |
1644 | static void __mcheck_cpu_init_timer(void) |
1645 | { | |
1646 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1647 | unsigned int cpu = smp_processor_id(); | |
1648 | ||
1649 | setup_timer(t, mce_timer_fn, cpu); | |
1650 | mce_start_timer(cpu, t); | |
1651 | } | |
1652 | ||
9eda8cb3 AK |
1653 | /* Handle unconfigured int18 (should never happen) */ |
1654 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1655 | { | |
c767a54b | 1656 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1657 | smp_processor_id()); |
1658 | } | |
1659 | ||
1660 | /* Call the installed machine check handler for this CPU setup. */ | |
1661 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1662 | unexpected_machine_check; | |
1663 | ||
d88203d1 | 1664 | /* |
1da177e4 | 1665 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1666 | * Must be called with preempt off: |
1da177e4 | 1667 | */ |
5e09954a | 1668 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1669 | { |
4efc0670 AK |
1670 | if (mce_disabled) |
1671 | return; | |
1672 | ||
3a97fc34 HS |
1673 | if (__mcheck_cpu_ancient_init(c)) |
1674 | return; | |
4efc0670 | 1675 | |
5b4408fd | 1676 | if (!mce_available(c)) |
1da177e4 LT |
1677 | return; |
1678 | ||
5e09954a | 1679 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1680 | mce_disabled = 1; |
0d7482e3 AK |
1681 | return; |
1682 | } | |
0d7482e3 | 1683 | |
5d727926 AK |
1684 | machine_check_vector = do_machine_check; |
1685 | ||
5e09954a BP |
1686 | __mcheck_cpu_init_generic(); |
1687 | __mcheck_cpu_init_vendor(c); | |
1688 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1689 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1690 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1691 | } |
1692 | ||
1693 | /* | |
93b62c3c | 1694 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1695 | */ |
1696 | ||
93b62c3c HS |
1697 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1698 | static int mce_chrdev_open_count; /* #times opened */ | |
1699 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1700 | |
93b62c3c | 1701 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1702 | { |
93b62c3c | 1703 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1704 | |
93b62c3c HS |
1705 | if (mce_chrdev_open_exclu || |
1706 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1707 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1708 | |
f528e7ba TH |
1709 | return -EBUSY; |
1710 | } | |
1711 | ||
1712 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1713 | mce_chrdev_open_exclu = 1; |
1714 | mce_chrdev_open_count++; | |
f528e7ba | 1715 | |
93b62c3c | 1716 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1717 | |
bd78432c | 1718 | return nonseekable_open(inode, file); |
f528e7ba TH |
1719 | } |
1720 | ||
93b62c3c | 1721 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1722 | { |
93b62c3c | 1723 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1724 | |
93b62c3c HS |
1725 | mce_chrdev_open_count--; |
1726 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1727 | |
93b62c3c | 1728 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1729 | |
1730 | return 0; | |
1731 | } | |
1732 | ||
d88203d1 TG |
1733 | static void collect_tscs(void *data) |
1734 | { | |
1da177e4 | 1735 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1736 | |
1da177e4 | 1737 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1738 | } |
1da177e4 | 1739 | |
482908b4 HY |
1740 | static int mce_apei_read_done; |
1741 | ||
1742 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1743 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1744 | { | |
1745 | int rc; | |
1746 | u64 record_id; | |
1747 | struct mce m; | |
1748 | ||
1749 | if (usize < sizeof(struct mce)) | |
1750 | return -EINVAL; | |
1751 | ||
1752 | rc = apei_read_mce(&m, &record_id); | |
1753 | /* Error or no more MCE record */ | |
1754 | if (rc <= 0) { | |
1755 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1756 | /* |
1757 | * When ERST is disabled, mce_chrdev_read() should return | |
1758 | * "no record" instead of "no device." | |
1759 | */ | |
1760 | if (rc == -ENODEV) | |
1761 | return 0; | |
482908b4 HY |
1762 | return rc; |
1763 | } | |
1764 | rc = -EFAULT; | |
1765 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1766 | return rc; | |
1767 | /* | |
1768 | * In fact, we should have cleared the record after that has | |
1769 | * been flushed to the disk or sent to network in | |
1770 | * /sbin/mcelog, but we have no interface to support that now, | |
1771 | * so just clear it to avoid duplication. | |
1772 | */ | |
1773 | rc = apei_clear_mce(record_id); | |
1774 | if (rc) { | |
1775 | mce_apei_read_done = 1; | |
1776 | return rc; | |
1777 | } | |
1778 | *ubuf += sizeof(struct mce); | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
93b62c3c HS |
1783 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1784 | size_t usize, loff_t *off) | |
1da177e4 | 1785 | { |
e9eee03e | 1786 | char __user *buf = ubuf; |
f0de53bb | 1787 | unsigned long *cpu_tsc; |
ef41df43 | 1788 | unsigned prev, next; |
1da177e4 LT |
1789 | int i, err; |
1790 | ||
6bca67f9 | 1791 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1792 | if (!cpu_tsc) |
1793 | return -ENOMEM; | |
1794 | ||
93b62c3c | 1795 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1796 | |
1797 | if (!mce_apei_read_done) { | |
1798 | err = __mce_read_apei(&buf, usize); | |
1799 | if (err || buf != ubuf) | |
1800 | goto out; | |
1801 | } | |
1802 | ||
f56e8a07 | 1803 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1804 | |
1805 | /* Only supports full reads right now */ | |
482908b4 HY |
1806 | err = -EINVAL; |
1807 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1808 | goto out; | |
1da177e4 LT |
1809 | |
1810 | err = 0; | |
ef41df43 HY |
1811 | prev = 0; |
1812 | do { | |
1813 | for (i = prev; i < next; i++) { | |
1814 | unsigned long start = jiffies; | |
559faa6b | 1815 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1816 | |
559faa6b | 1817 | while (!m->finished) { |
ef41df43 | 1818 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1819 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1820 | goto timeout; |
1821 | } | |
1822 | cpu_relax(); | |
673242c1 | 1823 | } |
ef41df43 | 1824 | smp_rmb(); |
559faa6b HS |
1825 | err |= copy_to_user(buf, m, sizeof(*m)); |
1826 | buf += sizeof(*m); | |
ef41df43 HY |
1827 | timeout: |
1828 | ; | |
673242c1 | 1829 | } |
1da177e4 | 1830 | |
ef41df43 HY |
1831 | memset(mcelog.entry + prev, 0, |
1832 | (next - prev) * sizeof(struct mce)); | |
1833 | prev = next; | |
1834 | next = cmpxchg(&mcelog.next, prev, 0); | |
1835 | } while (next != prev); | |
1da177e4 | 1836 | |
b2b18660 | 1837 | synchronize_sched(); |
1da177e4 | 1838 | |
d88203d1 TG |
1839 | /* |
1840 | * Collect entries that were still getting written before the | |
1841 | * synchronize. | |
1842 | */ | |
15c8b6c1 | 1843 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1844 | |
d88203d1 | 1845 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1846 | struct mce *m = &mcelog.entry[i]; |
1847 | ||
1848 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1849 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1850 | smp_rmb(); |
559faa6b HS |
1851 | buf += sizeof(*m); |
1852 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1853 | } |
d88203d1 | 1854 | } |
482908b4 HY |
1855 | |
1856 | if (err) | |
1857 | err = -EFAULT; | |
1858 | ||
1859 | out: | |
93b62c3c | 1860 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1861 | kfree(cpu_tsc); |
e9eee03e | 1862 | |
482908b4 | 1863 | return err ? err : buf - ubuf; |
1da177e4 LT |
1864 | } |
1865 | ||
93b62c3c | 1866 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1867 | { |
93b62c3c | 1868 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1869 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1870 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1871 | if (!mce_apei_read_done && apei_check_mce()) |
1872 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1873 | return 0; |
1874 | } | |
1875 | ||
93b62c3c HS |
1876 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1877 | unsigned long arg) | |
1da177e4 LT |
1878 | { |
1879 | int __user *p = (int __user *)arg; | |
d88203d1 | 1880 | |
1da177e4 | 1881 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1882 | return -EPERM; |
e9eee03e | 1883 | |
1da177e4 | 1884 | switch (cmd) { |
d88203d1 | 1885 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1886 | return put_user(sizeof(struct mce), p); |
1887 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1888 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1889 | case MCE_GETCLEAR_FLAGS: { |
1890 | unsigned flags; | |
d88203d1 TG |
1891 | |
1892 | do { | |
1da177e4 | 1893 | flags = mcelog.flags; |
d88203d1 | 1894 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1895 | |
d88203d1 | 1896 | return put_user(flags, p); |
1da177e4 LT |
1897 | } |
1898 | default: | |
d88203d1 TG |
1899 | return -ENOTTY; |
1900 | } | |
1da177e4 LT |
1901 | } |
1902 | ||
66f5ddf3 LT |
1903 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1904 | size_t usize, loff_t *off); | |
1905 | ||
1906 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1907 | const char __user *ubuf, | |
1908 | size_t usize, loff_t *off)) | |
1909 | { | |
1910 | mce_write = fn; | |
1911 | } | |
1912 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1913 | ||
1914 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1915 | size_t usize, loff_t *off) | |
1916 | { | |
1917 | if (mce_write) | |
1918 | return mce_write(filp, ubuf, usize, off); | |
1919 | else | |
1920 | return -EINVAL; | |
1921 | } | |
1922 | ||
1923 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1924 | .open = mce_chrdev_open, |
1925 | .release = mce_chrdev_release, | |
1926 | .read = mce_chrdev_read, | |
66f5ddf3 | 1927 | .write = mce_chrdev_write, |
93b62c3c HS |
1928 | .poll = mce_chrdev_poll, |
1929 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1930 | .llseek = no_llseek, | |
1da177e4 LT |
1931 | }; |
1932 | ||
93b62c3c | 1933 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1934 | MISC_MCELOG_MINOR, |
1935 | "mcelog", | |
1936 | &mce_chrdev_ops, | |
1937 | }; | |
1938 | ||
13503fa9 | 1939 | /* |
62fdac59 HS |
1940 | * mce=off Disables machine check |
1941 | * mce=no_cmci Disables CMCI | |
1942 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1943 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1944 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1945 | * monarchtimeout is how long to wait for other CPUs on machine | |
1946 | * check, or 0 to not wait | |
13503fa9 HS |
1947 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1948 | * mce=nobootlog Don't log MCEs from before booting. | |
1949 | */ | |
1da177e4 LT |
1950 | static int __init mcheck_enable(char *str) |
1951 | { | |
e3346fc4 | 1952 | if (*str == 0) { |
4efc0670 | 1953 | enable_p5_mce(); |
e3346fc4 BZ |
1954 | return 1; |
1955 | } | |
4efc0670 AK |
1956 | if (*str == '=') |
1957 | str++; | |
1da177e4 | 1958 | if (!strcmp(str, "off")) |
04b2b1a4 | 1959 | mce_disabled = 1; |
62fdac59 HS |
1960 | else if (!strcmp(str, "no_cmci")) |
1961 | mce_cmci_disabled = 1; | |
1962 | else if (!strcmp(str, "dont_log_ce")) | |
1963 | mce_dont_log_ce = 1; | |
1964 | else if (!strcmp(str, "ignore_ce")) | |
1965 | mce_ignore_ce = 1; | |
13503fa9 HS |
1966 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1967 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1968 | else if (isdigit(str[0])) { |
8c566ef5 | 1969 | get_option(&str, &tolerant); |
3c079792 AK |
1970 | if (*str == ',') { |
1971 | ++str; | |
1972 | get_option(&str, &monarch_timeout); | |
1973 | } | |
1974 | } else { | |
c767a54b | 1975 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
1976 | return 0; |
1977 | } | |
9b41046c | 1978 | return 1; |
1da177e4 | 1979 | } |
4efc0670 | 1980 | __setup("mce", mcheck_enable); |
1da177e4 | 1981 | |
a2202aa2 | 1982 | int __init mcheck_init(void) |
b33a6363 | 1983 | { |
a2202aa2 YW |
1984 | mcheck_intel_therm_init(); |
1985 | ||
b33a6363 BP |
1986 | return 0; |
1987 | } | |
b33a6363 | 1988 | |
d88203d1 | 1989 | /* |
c7cece89 | 1990 | * mce_syscore: PM support |
d88203d1 | 1991 | */ |
1da177e4 | 1992 | |
973a2dd1 AK |
1993 | /* |
1994 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1995 | * them later. | |
1996 | */ | |
5e09954a | 1997 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1998 | { |
1999 | int i; | |
2000 | ||
06b7a7a5 | 2001 | for (i = 0; i < banks; i++) { |
cebe1820 | 2002 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2003 | |
cebe1820 | 2004 | if (b->init) |
a2d32bcb | 2005 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2006 | } |
973a2dd1 AK |
2007 | return 0; |
2008 | } | |
2009 | ||
c7cece89 | 2010 | static int mce_syscore_suspend(void) |
973a2dd1 | 2011 | { |
5e09954a | 2012 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2013 | } |
2014 | ||
c7cece89 | 2015 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2016 | { |
f3c6ea1b | 2017 | mce_disable_error_reporting(); |
973a2dd1 AK |
2018 | } |
2019 | ||
e9eee03e IM |
2020 | /* |
2021 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2022 | * Only one CPU is active at this time, the others get re-added later using | |
2023 | * CPU hotplug: | |
2024 | */ | |
c7cece89 | 2025 | static void mce_syscore_resume(void) |
1da177e4 | 2026 | { |
5e09954a | 2027 | __mcheck_cpu_init_generic(); |
7b543a53 | 2028 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2029 | } |
2030 | ||
f3c6ea1b | 2031 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2032 | .suspend = mce_syscore_suspend, |
2033 | .shutdown = mce_syscore_shutdown, | |
2034 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2035 | }; |
2036 | ||
c7cece89 | 2037 | /* |
8a25a2fd | 2038 | * mce_device: Sysfs support |
c7cece89 HS |
2039 | */ |
2040 | ||
52d168e2 AK |
2041 | static void mce_cpu_restart(void *data) |
2042 | { | |
7b543a53 | 2043 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 2044 | return; |
5e09954a BP |
2045 | __mcheck_cpu_init_generic(); |
2046 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2047 | } |
2048 | ||
1da177e4 | 2049 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2050 | static void mce_restart(void) |
2051 | { | |
9aaef96f | 2052 | mce_timer_delete_all(); |
52d168e2 | 2053 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2054 | } |
2055 | ||
9af43b54 | 2056 | /* Toggle features for corrected errors */ |
9aaef96f | 2057 | static void mce_disable_cmci(void *data) |
9af43b54 | 2058 | { |
7b543a53 | 2059 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 2060 | return; |
9af43b54 HS |
2061 | cmci_clear(); |
2062 | } | |
2063 | ||
2064 | static void mce_enable_ce(void *all) | |
2065 | { | |
7b543a53 | 2066 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2067 | return; |
2068 | cmci_reenable(); | |
2069 | cmci_recheck(); | |
2070 | if (all) | |
5e09954a | 2071 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2072 | } |
2073 | ||
8a25a2fd | 2074 | static struct bus_type mce_subsys = { |
e9eee03e | 2075 | .name = "machinecheck", |
8a25a2fd | 2076 | .dev_name = "machinecheck", |
1da177e4 LT |
2077 | }; |
2078 | ||
d6126ef5 | 2079 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e IM |
2080 | |
2081 | __cpuinitdata | |
2082 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 2083 | |
8a25a2fd | 2084 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2085 | { |
2086 | return container_of(attr, struct mce_bank, attr); | |
2087 | } | |
0d7482e3 | 2088 | |
8a25a2fd | 2089 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2090 | char *buf) |
2091 | { | |
cebe1820 | 2092 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2093 | } |
2094 | ||
8a25a2fd | 2095 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2096 | const char *buf, size_t size) |
0d7482e3 | 2097 | { |
9319cec8 | 2098 | u64 new; |
e9eee03e | 2099 | |
9319cec8 | 2100 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 2101 | return -EINVAL; |
e9eee03e | 2102 | |
cebe1820 | 2103 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2104 | mce_restart(); |
e9eee03e | 2105 | |
9319cec8 | 2106 | return size; |
0d7482e3 | 2107 | } |
a98f0dd3 | 2108 | |
e9eee03e | 2109 | static ssize_t |
8a25a2fd | 2110 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2111 | { |
1020bcbc | 2112 | strcpy(buf, mce_helper); |
a98f0dd3 | 2113 | strcat(buf, "\n"); |
1020bcbc | 2114 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2115 | } |
2116 | ||
8a25a2fd | 2117 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2118 | const char *buf, size_t siz) |
a98f0dd3 AK |
2119 | { |
2120 | char *p; | |
e9eee03e | 2121 | |
1020bcbc HS |
2122 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2123 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2124 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2125 | |
e9084ec9 | 2126 | if (p) |
e9eee03e IM |
2127 | *p = 0; |
2128 | ||
e9084ec9 | 2129 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2130 | } |
2131 | ||
8a25a2fd KS |
2132 | static ssize_t set_ignore_ce(struct device *s, |
2133 | struct device_attribute *attr, | |
9af43b54 HS |
2134 | const char *buf, size_t size) |
2135 | { | |
2136 | u64 new; | |
2137 | ||
2138 | if (strict_strtoull(buf, 0, &new) < 0) | |
2139 | return -EINVAL; | |
2140 | ||
2141 | if (mce_ignore_ce ^ !!new) { | |
2142 | if (new) { | |
2143 | /* disable ce features */ | |
9aaef96f HS |
2144 | mce_timer_delete_all(); |
2145 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
9af43b54 HS |
2146 | mce_ignore_ce = 1; |
2147 | } else { | |
2148 | /* enable ce features */ | |
2149 | mce_ignore_ce = 0; | |
2150 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
2151 | } | |
2152 | } | |
2153 | return size; | |
2154 | } | |
2155 | ||
8a25a2fd KS |
2156 | static ssize_t set_cmci_disabled(struct device *s, |
2157 | struct device_attribute *attr, | |
9af43b54 HS |
2158 | const char *buf, size_t size) |
2159 | { | |
2160 | u64 new; | |
2161 | ||
2162 | if (strict_strtoull(buf, 0, &new) < 0) | |
2163 | return -EINVAL; | |
2164 | ||
2165 | if (mce_cmci_disabled ^ !!new) { | |
2166 | if (new) { | |
2167 | /* disable cmci */ | |
9aaef96f | 2168 | on_each_cpu(mce_disable_cmci, NULL, 1); |
9af43b54 HS |
2169 | mce_cmci_disabled = 1; |
2170 | } else { | |
2171 | /* enable cmci */ | |
2172 | mce_cmci_disabled = 0; | |
2173 | on_each_cpu(mce_enable_ce, NULL, 1); | |
2174 | } | |
2175 | } | |
2176 | return size; | |
2177 | } | |
2178 | ||
8a25a2fd KS |
2179 | static ssize_t store_int_with_restart(struct device *s, |
2180 | struct device_attribute *attr, | |
b56f642d AK |
2181 | const char *buf, size_t size) |
2182 | { | |
8a25a2fd | 2183 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2184 | mce_restart(); |
2185 | return ret; | |
2186 | } | |
2187 | ||
8a25a2fd KS |
2188 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
2189 | static DEVICE_INT_ATTR(tolerant, 0644, tolerant); | |
2190 | static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout); | |
2191 | static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); | |
e9eee03e | 2192 | |
8a25a2fd KS |
2193 | static struct dev_ext_attribute dev_attr_check_interval = { |
2194 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2195 | &check_interval |
2196 | }; | |
e9eee03e | 2197 | |
8a25a2fd KS |
2198 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
2199 | __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce), | |
9af43b54 HS |
2200 | &mce_ignore_ce |
2201 | }; | |
2202 | ||
8a25a2fd KS |
2203 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
2204 | __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled), | |
9af43b54 HS |
2205 | &mce_cmci_disabled |
2206 | }; | |
2207 | ||
8a25a2fd KS |
2208 | static struct device_attribute *mce_device_attrs[] = { |
2209 | &dev_attr_tolerant.attr, | |
2210 | &dev_attr_check_interval.attr, | |
2211 | &dev_attr_trigger, | |
2212 | &dev_attr_monarch_timeout.attr, | |
2213 | &dev_attr_dont_log_ce.attr, | |
2214 | &dev_attr_ignore_ce.attr, | |
2215 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2216 | NULL |
2217 | }; | |
1da177e4 | 2218 | |
8a25a2fd | 2219 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2220 | |
e032d807 GKH |
2221 | static void mce_device_release(struct device *dev) |
2222 | { | |
2223 | kfree(dev); | |
2224 | } | |
2225 | ||
8a25a2fd KS |
2226 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
2227 | static __cpuinit int mce_device_create(unsigned int cpu) | |
1da177e4 | 2228 | { |
e032d807 | 2229 | struct device *dev; |
1da177e4 | 2230 | int err; |
b1f49f95 | 2231 | int i, j; |
92cb7612 | 2232 | |
90367556 | 2233 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2234 | return -EIO; |
2235 | ||
e032d807 GKH |
2236 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2237 | if (!dev) | |
2238 | return -ENOMEM; | |
8a25a2fd KS |
2239 | dev->id = cpu; |
2240 | dev->bus = &mce_subsys; | |
e032d807 | 2241 | dev->release = &mce_device_release; |
91c6d400 | 2242 | |
8a25a2fd | 2243 | err = device_register(dev); |
d435d862 AM |
2244 | if (err) |
2245 | return err; | |
2246 | ||
8a25a2fd KS |
2247 | for (i = 0; mce_device_attrs[i]; i++) { |
2248 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2249 | if (err) |
2250 | goto error; | |
2251 | } | |
b1f49f95 | 2252 | for (j = 0; j < banks; j++) { |
8a25a2fd | 2253 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2254 | if (err) |
2255 | goto error2; | |
2256 | } | |
8a25a2fd | 2257 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2258 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2259 | |
d435d862 | 2260 | return 0; |
0d7482e3 | 2261 | error2: |
b1f49f95 | 2262 | while (--j >= 0) |
8a25a2fd | 2263 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2264 | error: |
cb491fca | 2265 | while (--i >= 0) |
8a25a2fd | 2266 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2267 | |
8a25a2fd | 2268 | device_unregister(dev); |
d435d862 | 2269 | |
91c6d400 AK |
2270 | return err; |
2271 | } | |
2272 | ||
8a25a2fd | 2273 | static __cpuinit void mce_device_remove(unsigned int cpu) |
91c6d400 | 2274 | { |
d6126ef5 | 2275 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2276 | int i; |
2277 | ||
8a25a2fd | 2278 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2279 | return; |
2280 | ||
8a25a2fd KS |
2281 | for (i = 0; mce_device_attrs[i]; i++) |
2282 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2283 | |
0d7482e3 | 2284 | for (i = 0; i < banks; i++) |
8a25a2fd | 2285 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2286 | |
8a25a2fd KS |
2287 | device_unregister(dev); |
2288 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2289 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2290 | } |
91c6d400 | 2291 | |
d6b75584 | 2292 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2293 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2294 | { |
88ccbedd | 2295 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2296 | int i; |
d6b75584 | 2297 | |
7b543a53 | 2298 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2299 | return; |
767df1bd | 2300 | |
88ccbedd AK |
2301 | if (!(action & CPU_TASKS_FROZEN)) |
2302 | cmci_clear(); | |
06b7a7a5 | 2303 | for (i = 0; i < banks; i++) { |
cebe1820 | 2304 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2305 | |
cebe1820 | 2306 | if (b->init) |
a2d32bcb | 2307 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2308 | } |
d6b75584 AK |
2309 | } |
2310 | ||
767df1bd | 2311 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2312 | { |
88ccbedd | 2313 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2314 | int i; |
d6b75584 | 2315 | |
7b543a53 | 2316 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2317 | return; |
e9eee03e | 2318 | |
88ccbedd AK |
2319 | if (!(action & CPU_TASKS_FROZEN)) |
2320 | cmci_reenable(); | |
06b7a7a5 | 2321 | for (i = 0; i < banks; i++) { |
cebe1820 | 2322 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2323 | |
cebe1820 | 2324 | if (b->init) |
a2d32bcb | 2325 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2326 | } |
d6b75584 AK |
2327 | } |
2328 | ||
91c6d400 | 2329 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2330 | static int __cpuinit |
2331 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2332 | { |
2333 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2334 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2335 | |
1a65f970 | 2336 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2337 | case CPU_ONLINE: |
8a25a2fd | 2338 | mce_device_create(cpu); |
8735728e RW |
2339 | if (threshold_cpu_callback) |
2340 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2341 | break; |
91c6d400 | 2342 | case CPU_DEAD: |
8735728e RW |
2343 | if (threshold_cpu_callback) |
2344 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2345 | mce_device_remove(cpu); |
55babd8f | 2346 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2347 | break; |
52d168e2 | 2348 | case CPU_DOWN_PREPARE: |
88ccbedd | 2349 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2350 | del_timer_sync(t); |
52d168e2 AK |
2351 | break; |
2352 | case CPU_DOWN_FAILED: | |
88ccbedd | 2353 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2354 | mce_start_timer(cpu, t); |
88ccbedd | 2355 | break; |
1a65f970 TG |
2356 | } |
2357 | ||
2358 | if (action == CPU_POST_DEAD) { | |
88ccbedd AK |
2359 | /* intentionally ignoring frozen here */ |
2360 | cmci_rediscover(cpu); | |
91c6d400 | 2361 | } |
1a65f970 | 2362 | |
bae19fe0 | 2363 | return NOTIFY_OK; |
91c6d400 AK |
2364 | } |
2365 | ||
1e35669d | 2366 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2367 | .notifier_call = mce_cpu_callback, |
2368 | }; | |
2369 | ||
cebe1820 | 2370 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2371 | { |
2372 | int i; | |
2373 | ||
0d7482e3 | 2374 | for (i = 0; i < banks; i++) { |
cebe1820 | 2375 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2376 | struct device_attribute *a = &b->attr; |
e9eee03e | 2377 | |
a07e4156 | 2378 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2379 | a->attr.name = b->attrname; |
2380 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2381 | |
2382 | a->attr.mode = 0644; | |
2383 | a->show = show_bank; | |
2384 | a->store = set_bank; | |
0d7482e3 | 2385 | } |
0d7482e3 AK |
2386 | } |
2387 | ||
5e09954a | 2388 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2389 | { |
2390 | int err; | |
2391 | int i = 0; | |
2392 | ||
1da177e4 LT |
2393 | if (!mce_available(&boot_cpu_data)) |
2394 | return -EIO; | |
0d7482e3 | 2395 | |
8a25a2fd | 2396 | zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
996867d0 | 2397 | |
cebe1820 | 2398 | mce_init_banks(); |
0d7482e3 | 2399 | |
8a25a2fd | 2400 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 AM |
2401 | if (err) |
2402 | return err; | |
91c6d400 AK |
2403 | |
2404 | for_each_online_cpu(i) { | |
8a25a2fd | 2405 | err = mce_device_create(i); |
d435d862 AM |
2406 | if (err) |
2407 | return err; | |
91c6d400 AK |
2408 | } |
2409 | ||
f3c6ea1b | 2410 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2411 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2412 | |
2413 | /* register character device /dev/mcelog */ | |
2414 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2415 | |
1da177e4 | 2416 | return err; |
1da177e4 | 2417 | } |
cef12ee5 | 2418 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2419 | |
d7c3c9a6 AK |
2420 | /* |
2421 | * Old style boot options parsing. Only for compatibility. | |
2422 | */ | |
2423 | static int __init mcheck_disable(char *str) | |
2424 | { | |
2425 | mce_disabled = 1; | |
2426 | return 1; | |
2427 | } | |
2428 | __setup("nomce", mcheck_disable); | |
a988d334 | 2429 | |
5be9ed25 HY |
2430 | #ifdef CONFIG_DEBUG_FS |
2431 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2432 | { |
5be9ed25 | 2433 | static struct dentry *dmce; |
a988d334 | 2434 | |
5be9ed25 HY |
2435 | if (!dmce) |
2436 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2437 | |
5be9ed25 HY |
2438 | return dmce; |
2439 | } | |
a988d334 | 2440 | |
bf783f9f HY |
2441 | static void mce_reset(void) |
2442 | { | |
2443 | cpu_missing = 0; | |
2444 | atomic_set(&mce_fake_paniced, 0); | |
2445 | atomic_set(&mce_executing, 0); | |
2446 | atomic_set(&mce_callin, 0); | |
2447 | atomic_set(&global_nwo, 0); | |
2448 | } | |
a988d334 | 2449 | |
bf783f9f HY |
2450 | static int fake_panic_get(void *data, u64 *val) |
2451 | { | |
2452 | *val = fake_panic; | |
2453 | return 0; | |
a988d334 IM |
2454 | } |
2455 | ||
bf783f9f | 2456 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2457 | { |
bf783f9f HY |
2458 | mce_reset(); |
2459 | fake_panic = val; | |
2460 | return 0; | |
a988d334 | 2461 | } |
a988d334 | 2462 | |
bf783f9f HY |
2463 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2464 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2465 | |
5e09954a | 2466 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2467 | { |
bf783f9f HY |
2468 | struct dentry *dmce, *ffake_panic; |
2469 | ||
2470 | dmce = mce_get_debugfs_dir(); | |
2471 | if (!dmce) | |
2472 | return -ENOMEM; | |
2473 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2474 | &fake_panic_fops); | |
2475 | if (!ffake_panic) | |
2476 | return -ENOMEM; | |
2477 | ||
2478 | return 0; | |
d7c3c9a6 | 2479 | } |
5e09954a | 2480 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2481 | #endif |