Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
93b62c3c | 51 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 52 | |
f56e8a07 | 53 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 54 | rcu_dereference_index_check((p), \ |
f56e8a07 | 55 | rcu_read_lock_sched_held() || \ |
93b62c3c | 56 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 57 | |
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
3c079792 AK |
61 | #define SPINUNIT 100 /* 100ns */ |
62 | ||
01ca79f1 AK |
63 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
64 | ||
1462594b | 65 | struct mce_bank *mce_banks __read_mostly; |
cebe1820 | 66 | |
d203f0b8 | 67 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 68 | .bootlog = -1, |
d203f0b8 BP |
69 | /* |
70 | * Tolerant levels: | |
71 | * 0: always panic on uncorrected errors, log corrected errors | |
72 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
73 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
74 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
75 | */ | |
84c2559d BP |
76 | .tolerant = 1, |
77 | .monarch_timeout = -1 | |
d203f0b8 BP |
78 | }; |
79 | ||
1020bcbc HS |
80 | /* User mode helper program triggered by machine check event */ |
81 | static unsigned long mce_need_notify; | |
82 | static char mce_helper[128]; | |
83 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 84 | |
93b62c3c HS |
85 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
86 | ||
3c079792 AK |
87 | static DEFINE_PER_CPU(struct mce, mces_seen); |
88 | static int cpu_missing; | |
89 | ||
27f6c573 CG |
90 | /* CMCI storm detection filter */ |
91 | static DEFINE_PER_CPU(unsigned long, mce_polled_error); | |
92 | ||
0644414e NR |
93 | /* |
94 | * MCA banks polled by the period polling timer for corrected events. | |
95 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
96 | */ | |
ee031c31 AK |
97 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
98 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
99 | }; | |
100 | ||
c3d1fb56 NR |
101 | /* |
102 | * MCA banks controlled through firmware first for corrected errors. | |
103 | * This is a global list of banks for which we won't enable CMCI and we | |
104 | * won't poll. Firmware controls these banks and is responsible for | |
105 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
106 | * errors are still notified through a machine check. | |
107 | */ | |
108 | mce_banks_t mce_banks_ce_disabled; | |
109 | ||
9b1beaf2 AK |
110 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
111 | ||
61b0fccd TL |
112 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
113 | ||
3653ada5 BP |
114 | /* |
115 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
116 | * MCE errors in a human-readable form. | |
117 | */ | |
118 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
119 | ||
b5f2fa4e AK |
120 | /* Do initial initialization of a struct mce */ |
121 | void mce_setup(struct mce *m) | |
122 | { | |
123 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 124 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 125 | rdtscll(m->tsc); |
8ee08347 AK |
126 | /* We hope get_seconds stays lockless */ |
127 | m->time = get_seconds(); | |
128 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
129 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 130 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
131 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
132 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
133 | } |
134 | ||
ea149b36 AK |
135 | DEFINE_PER_CPU(struct mce, injectm); |
136 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
137 | ||
1da177e4 LT |
138 | /* |
139 | * Lockless MCE logging infrastructure. | |
140 | * This avoids deadlocks on printk locks without having to break locks. Also | |
141 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
142 | */ | |
143 | ||
231fd906 | 144 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
145 | .signature = MCE_LOG_SIGNATURE, |
146 | .len = MCE_LOG_LEN, | |
147 | .recordlen = sizeof(struct mce), | |
d88203d1 | 148 | }; |
1da177e4 LT |
149 | |
150 | void mce_log(struct mce *mce) | |
151 | { | |
152 | unsigned next, entry; | |
f0cb5452 | 153 | int ret = 0; |
e9eee03e | 154 | |
8968f9d3 HS |
155 | /* Emit the trace record: */ |
156 | trace_mce_record(mce); | |
157 | ||
f0cb5452 BP |
158 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
159 | if (ret == NOTIFY_STOP) | |
160 | return; | |
161 | ||
1da177e4 | 162 | mce->finished = 0; |
7644143c | 163 | wmb(); |
1da177e4 | 164 | for (;;) { |
f56e8a07 | 165 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 166 | for (;;) { |
696e409d | 167 | |
e9eee03e IM |
168 | /* |
169 | * When the buffer fills up discard new entries. | |
170 | * Assume that the earlier errors are the more | |
171 | * interesting ones: | |
172 | */ | |
673242c1 | 173 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
174 | set_bit(MCE_OVERFLOW, |
175 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
176 | return; |
177 | } | |
e9eee03e | 178 | /* Old left over entry. Skip: */ |
673242c1 AK |
179 | if (mcelog.entry[entry].finished) { |
180 | entry++; | |
181 | continue; | |
182 | } | |
7644143c | 183 | break; |
1da177e4 | 184 | } |
1da177e4 LT |
185 | smp_rmb(); |
186 | next = entry + 1; | |
187 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
188 | break; | |
189 | } | |
190 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 191 | wmb(); |
1da177e4 | 192 | mcelog.entry[entry].finished = 1; |
7644143c | 193 | wmb(); |
1da177e4 | 194 | |
a0189c70 | 195 | mce->finished = 1; |
1020bcbc | 196 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
197 | } |
198 | ||
09371957 BP |
199 | static void drain_mcelog_buffer(void) |
200 | { | |
201 | unsigned int next, i, prev = 0; | |
202 | ||
b11e3d78 | 203 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
204 | |
205 | do { | |
206 | struct mce *m; | |
207 | ||
208 | /* drain what was logged during boot */ | |
209 | for (i = prev; i < next; i++) { | |
210 | unsigned long start = jiffies; | |
211 | unsigned retries = 1; | |
212 | ||
213 | m = &mcelog.entry[i]; | |
214 | ||
215 | while (!m->finished) { | |
216 | if (time_after_eq(jiffies, start + 2*retries)) | |
217 | retries++; | |
218 | ||
219 | cpu_relax(); | |
220 | ||
221 | if (!m->finished && retries >= 4) { | |
c767a54b | 222 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
223 | break; |
224 | } | |
225 | } | |
226 | smp_rmb(); | |
227 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
228 | } | |
229 | ||
230 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
231 | prev = next; | |
232 | next = cmpxchg(&mcelog.next, prev, 0); | |
233 | } while (next != prev); | |
234 | } | |
235 | ||
236 | ||
3653ada5 BP |
237 | void mce_register_decode_chain(struct notifier_block *nb) |
238 | { | |
239 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 240 | drain_mcelog_buffer(); |
3653ada5 BP |
241 | } |
242 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
243 | ||
244 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
245 | { | |
246 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
247 | } | |
248 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
249 | ||
77e26cca | 250 | static void print_mce(struct mce *m) |
1da177e4 | 251 | { |
dffa4b2f BP |
252 | int ret = 0; |
253 | ||
a2d7b0d4 | 254 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 255 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 256 | |
65ea5b03 | 257 | if (m->ip) { |
a2d7b0d4 | 258 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
259 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
260 | m->cs, m->ip); | |
261 | ||
1da177e4 | 262 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 263 | print_symbol("{%s}", m->ip); |
f436f8bb | 264 | pr_cont("\n"); |
1da177e4 | 265 | } |
f436f8bb | 266 | |
a2d7b0d4 | 267 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 268 | if (m->addr) |
f436f8bb | 269 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 270 | if (m->misc) |
f436f8bb | 271 | pr_cont("MISC %llx ", m->misc); |
549d042d | 272 | |
f436f8bb | 273 | pr_cont("\n"); |
506ed6b5 AK |
274 | /* |
275 | * Note this output is parsed by external tools and old fields | |
276 | * should not be changed. | |
277 | */ | |
881e23e5 | 278 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
279 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
280 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
281 | |
282 | /* | |
283 | * Print out human-readable details about the MCE error, | |
fb253195 | 284 | * (if the CPU has an implementation for that) |
f436f8bb | 285 | */ |
dffa4b2f BP |
286 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
287 | if (ret == NOTIFY_STOP) | |
288 | return; | |
289 | ||
290 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
291 | } |
292 | ||
f94b61c2 AK |
293 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
294 | ||
295 | static atomic_t mce_paniced; | |
296 | ||
bf783f9f HY |
297 | static int fake_panic; |
298 | static atomic_t mce_fake_paniced; | |
299 | ||
f94b61c2 AK |
300 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
301 | static void wait_for_panic(void) | |
302 | { | |
303 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 304 | |
f94b61c2 AK |
305 | preempt_disable(); |
306 | local_irq_enable(); | |
307 | while (timeout-- > 0) | |
308 | udelay(1); | |
29b0f591 | 309 | if (panic_timeout == 0) |
7af19e4a | 310 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
311 | panic("Panicing machine check CPU died"); |
312 | } | |
313 | ||
bd19a5e6 | 314 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 315 | { |
482908b4 | 316 | int i, apei_err = 0; |
e02e68d3 | 317 | |
bf783f9f HY |
318 | if (!fake_panic) { |
319 | /* | |
320 | * Make sure only one CPU runs in machine check panic | |
321 | */ | |
322 | if (atomic_inc_return(&mce_paniced) > 1) | |
323 | wait_for_panic(); | |
324 | barrier(); | |
f94b61c2 | 325 | |
bf783f9f HY |
326 | bust_spinlocks(1); |
327 | console_verbose(); | |
328 | } else { | |
329 | /* Don't log too much for fake panic */ | |
330 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
331 | return; | |
332 | } | |
a0189c70 | 333 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 334 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 335 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
336 | if (!(m->status & MCI_STATUS_VAL)) |
337 | continue; | |
482908b4 | 338 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 339 | print_mce(m); |
482908b4 HY |
340 | if (!apei_err) |
341 | apei_err = apei_write_mce(m); | |
342 | } | |
a0189c70 AK |
343 | } |
344 | /* Now print uncorrected but with the final one last */ | |
345 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
346 | struct mce *m = &mcelog.entry[i]; | |
347 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 348 | continue; |
77e26cca HS |
349 | if (!(m->status & MCI_STATUS_UC)) |
350 | continue; | |
482908b4 | 351 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 352 | print_mce(m); |
482908b4 HY |
353 | if (!apei_err) |
354 | apei_err = apei_write_mce(m); | |
355 | } | |
1da177e4 | 356 | } |
482908b4 | 357 | if (final) { |
77e26cca | 358 | print_mce(final); |
482908b4 HY |
359 | if (!apei_err) |
360 | apei_err = apei_write_mce(final); | |
361 | } | |
3c079792 | 362 | if (cpu_missing) |
a2d7b0d4 | 363 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 364 | if (exp) |
a2d7b0d4 | 365 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
366 | if (!fake_panic) { |
367 | if (panic_timeout == 0) | |
7af19e4a | 368 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
369 | panic(msg); |
370 | } else | |
a2d7b0d4 | 371 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 372 | } |
1da177e4 | 373 | |
ea149b36 AK |
374 | /* Support code for software error injection */ |
375 | ||
376 | static int msr_to_offset(u32 msr) | |
377 | { | |
0a3aee0d | 378 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 379 | |
84c2559d | 380 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 381 | return offsetof(struct mce, ip); |
a2d32bcb | 382 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 383 | return offsetof(struct mce, status); |
a2d32bcb | 384 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 385 | return offsetof(struct mce, addr); |
a2d32bcb | 386 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
387 | return offsetof(struct mce, misc); |
388 | if (msr == MSR_IA32_MCG_STATUS) | |
389 | return offsetof(struct mce, mcgstatus); | |
390 | return -1; | |
391 | } | |
392 | ||
5f8c1a54 AK |
393 | /* MSR access wrappers used for error injection */ |
394 | static u64 mce_rdmsrl(u32 msr) | |
395 | { | |
396 | u64 v; | |
11868a2d | 397 | |
0a3aee0d | 398 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 399 | int offset = msr_to_offset(msr); |
11868a2d | 400 | |
ea149b36 AK |
401 | if (offset < 0) |
402 | return 0; | |
89cbc767 | 403 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 404 | } |
11868a2d IM |
405 | |
406 | if (rdmsrl_safe(msr, &v)) { | |
407 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
408 | /* | |
409 | * Return zero in case the access faulted. This should | |
410 | * not happen normally but can happen if the CPU does | |
411 | * something weird, or if the code is buggy. | |
412 | */ | |
413 | v = 0; | |
414 | } | |
415 | ||
5f8c1a54 AK |
416 | return v; |
417 | } | |
418 | ||
419 | static void mce_wrmsrl(u32 msr, u64 v) | |
420 | { | |
0a3aee0d | 421 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 422 | int offset = msr_to_offset(msr); |
11868a2d | 423 | |
ea149b36 | 424 | if (offset >= 0) |
89cbc767 | 425 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
426 | return; |
427 | } | |
5f8c1a54 AK |
428 | wrmsrl(msr, v); |
429 | } | |
430 | ||
b8325c5b HS |
431 | /* |
432 | * Collect all global (w.r.t. this processor) status about this machine | |
433 | * check into our "mce" struct so that we can use it later to assess | |
434 | * the severity of the problem as we read per-bank specific details. | |
435 | */ | |
436 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
437 | { | |
438 | mce_setup(m); | |
439 | ||
440 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
441 | if (regs) { | |
442 | /* | |
443 | * Get the address of the instruction at the time of | |
444 | * the machine check error. | |
445 | */ | |
446 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
447 | m->ip = regs->ip; | |
448 | m->cs = regs->cs; | |
a129a7c8 AK |
449 | |
450 | /* | |
451 | * When in VM86 mode make the cs look like ring 3 | |
452 | * always. This is a lie, but it's better than passing | |
453 | * the additional vm86 bit around everywhere. | |
454 | */ | |
455 | if (v8086_mode(regs)) | |
456 | m->cs |= 3; | |
b8325c5b HS |
457 | } |
458 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
459 | if (mca_cfg.rip_msr) |
460 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
461 | } |
462 | } | |
463 | ||
9b1beaf2 AK |
464 | /* |
465 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
466 | * process context work function. This is vastly simplified because there's | |
467 | * only a single reader and a single writer. | |
468 | */ | |
469 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
470 | ||
471 | struct mce_ring { | |
472 | unsigned short start; | |
473 | unsigned short end; | |
474 | unsigned long ring[MCE_RING_SIZE]; | |
475 | }; | |
476 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
477 | ||
478 | /* Runs with CPU affinity in workqueue */ | |
479 | static int mce_ring_empty(void) | |
480 | { | |
89cbc767 | 481 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
482 | |
483 | return r->start == r->end; | |
484 | } | |
485 | ||
486 | static int mce_ring_get(unsigned long *pfn) | |
487 | { | |
488 | struct mce_ring *r; | |
489 | int ret = 0; | |
490 | ||
491 | *pfn = 0; | |
492 | get_cpu(); | |
89cbc767 | 493 | r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
494 | if (r->start == r->end) |
495 | goto out; | |
496 | *pfn = r->ring[r->start]; | |
497 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
498 | ret = 1; | |
499 | out: | |
500 | put_cpu(); | |
501 | return ret; | |
502 | } | |
503 | ||
504 | /* Always runs in MCE context with preempt off */ | |
505 | static int mce_ring_add(unsigned long pfn) | |
506 | { | |
89cbc767 | 507 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
508 | unsigned next; |
509 | ||
510 | next = (r->end + 1) % MCE_RING_SIZE; | |
511 | if (next == r->start) | |
512 | return -1; | |
513 | r->ring[r->end] = pfn; | |
514 | wmb(); | |
515 | r->end = next; | |
516 | return 0; | |
517 | } | |
518 | ||
88ccbedd | 519 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 520 | { |
1462594b | 521 | if (mca_cfg.disabled) |
5b4408fd | 522 | return 0; |
3d1712c9 | 523 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
524 | } |
525 | ||
9b1beaf2 AK |
526 | static void mce_schedule_work(void) |
527 | { | |
4d899be5 | 528 | if (!mce_ring_empty()) |
89cbc767 | 529 | schedule_work(this_cpu_ptr(&mce_work)); |
9b1beaf2 AK |
530 | } |
531 | ||
b77e70bf HS |
532 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
533 | ||
534 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 535 | { |
9ff36ee9 | 536 | mce_notify_irq(); |
9b1beaf2 | 537 | mce_schedule_work(); |
ccc3c319 | 538 | } |
ccc3c319 AK |
539 | |
540 | static void mce_report_event(struct pt_regs *regs) | |
541 | { | |
542 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 543 | mce_notify_irq(); |
9b1beaf2 AK |
544 | /* |
545 | * Triggering the work queue here is just an insurance | |
546 | * policy in case the syscall exit notify handler | |
547 | * doesn't run soon enough or ends up running on the | |
548 | * wrong CPU (can happen when audit sleeps) | |
549 | */ | |
550 | mce_schedule_work(); | |
ccc3c319 AK |
551 | return; |
552 | } | |
553 | ||
89cbc767 | 554 | irq_work_queue(this_cpu_ptr(&mce_irq_work)); |
ccc3c319 AK |
555 | } |
556 | ||
85f92694 TL |
557 | /* |
558 | * Read ADDR and MISC registers. | |
559 | */ | |
560 | static void mce_read_aux(struct mce *m, int i) | |
561 | { | |
562 | if (m->status & MCI_STATUS_MISCV) | |
563 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
564 | if (m->status & MCI_STATUS_ADDRV) { | |
565 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
566 | ||
567 | /* | |
568 | * Mask the reported address by the reported granularity. | |
569 | */ | |
1462594b | 570 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
571 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
572 | m->addr >>= shift; | |
573 | m->addr <<= shift; | |
574 | } | |
575 | } | |
576 | } | |
577 | ||
fa92c586 CY |
578 | static bool memory_error(struct mce *m) |
579 | { | |
580 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
581 | ||
582 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
583 | /* | |
584 | * coming soon | |
585 | */ | |
586 | return false; | |
587 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { | |
588 | /* | |
589 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
590 | * | |
591 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
592 | * indicating a memory error. Bit 8 is used for indicating a | |
593 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
594 | * is used for indicating a `generic' cache hierarchy error | |
595 | * But we can't just blindly check the above bits, because if | |
596 | * bit 11 is set, then it is a bus/interconnect error - and | |
597 | * either way the above bits just gives more detail on what | |
598 | * bus/interconnect error happened. Note that bit 12 can be | |
599 | * ignored, as it's the "filter" bit. | |
600 | */ | |
601 | return (m->status & 0xef80) == BIT(7) || | |
602 | (m->status & 0xef00) == BIT(8) || | |
603 | (m->status & 0xeffc) == 0xc; | |
604 | } | |
605 | ||
606 | return false; | |
607 | } | |
608 | ||
ca84f696 AK |
609 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
610 | ||
d88203d1 | 611 | /* |
b79109c3 AK |
612 | * Poll for corrected events or events that happened before reset. |
613 | * Those are just logged through /dev/mcelog. | |
614 | * | |
615 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
616 | * |
617 | * Note: spec recommends to panic for fatal unsignalled | |
618 | * errors here. However this would be quite problematic -- | |
619 | * we would need to reimplement the Monarch handling and | |
620 | * it would mess up the exclusion between exception handler | |
621 | * and poll hander -- * so we skip this for now. | |
622 | * These cases should not happen anyways, or only when the CPU | |
623 | * is already totally * confused. In this case it's likely it will | |
624 | * not fully execute the machine check handler either. | |
b79109c3 | 625 | */ |
ee031c31 | 626 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
627 | { |
628 | struct mce m; | |
fa92c586 | 629 | int severity; |
b79109c3 AK |
630 | int i; |
631 | ||
c6ae41e7 | 632 | this_cpu_inc(mce_poll_count); |
ca84f696 | 633 | |
b8325c5b | 634 | mce_gather_info(&m, NULL); |
b79109c3 | 635 | |
d203f0b8 | 636 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 637 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
638 | continue; |
639 | ||
640 | m.misc = 0; | |
641 | m.addr = 0; | |
642 | m.bank = i; | |
643 | m.tsc = 0; | |
644 | ||
645 | barrier(); | |
a2d32bcb | 646 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
647 | if (!(m.status & MCI_STATUS_VAL)) |
648 | continue; | |
649 | ||
ea431643 | 650 | this_cpu_write(mce_polled_error, 1); |
b79109c3 | 651 | /* |
ed7290d0 AK |
652 | * Uncorrected or signalled events are handled by the exception |
653 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
654 | * |
655 | * TBD do the same check for MCI_STATUS_EN here? | |
656 | */ | |
ed7290d0 | 657 | if (!(flags & MCP_UC) && |
1462594b | 658 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
659 | continue; |
660 | ||
85f92694 | 661 | mce_read_aux(&m, i); |
b79109c3 AK |
662 | |
663 | if (!(flags & MCP_TIMESTAMP)) | |
664 | m.tsc = 0; | |
fa92c586 CY |
665 | |
666 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
667 | ||
668 | /* | |
669 | * In the cases where we don't have a valid address after all, | |
670 | * do not add it into the ring buffer. | |
671 | */ | |
672 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) { | |
673 | if (m.status & MCI_STATUS_ADDRV) { | |
674 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
675 | mce_schedule_work(); | |
676 | } | |
677 | } | |
678 | ||
b79109c3 AK |
679 | /* |
680 | * Don't get the IP here because it's unlikely to | |
681 | * have anything to do with the actual error location. | |
682 | */ | |
d203f0b8 | 683 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 684 | mce_log(&m); |
b79109c3 AK |
685 | |
686 | /* | |
687 | * Clear state for this bank. | |
688 | */ | |
a2d32bcb | 689 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
690 | } |
691 | ||
692 | /* | |
693 | * Don't clear MCG_STATUS here because it's only defined for | |
694 | * exceptions. | |
695 | */ | |
88921be3 AK |
696 | |
697 | sync_core(); | |
b79109c3 | 698 | } |
ea149b36 | 699 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 700 | |
bd19a5e6 AK |
701 | /* |
702 | * Do a quick check if any of the events requires a panic. | |
703 | * This decides if we keep the events around or clear them. | |
704 | */ | |
61b0fccd TL |
705 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
706 | struct pt_regs *regs) | |
bd19a5e6 | 707 | { |
95022b8c | 708 | int i, ret = 0; |
bd19a5e6 | 709 | |
d203f0b8 | 710 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 711 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 712 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 713 | __set_bit(i, validp); |
61b0fccd TL |
714 | if (quirk_no_way_out) |
715 | quirk_no_way_out(i, m, regs); | |
716 | } | |
e3480271 CY |
717 | if (mce_severity(m, mca_cfg.tolerant, msg, true) >= |
718 | MCE_PANIC_SEVERITY) | |
95022b8c | 719 | ret = 1; |
bd19a5e6 | 720 | } |
95022b8c | 721 | return ret; |
bd19a5e6 AK |
722 | } |
723 | ||
3c079792 AK |
724 | /* |
725 | * Variable to establish order between CPUs while scanning. | |
726 | * Each CPU spins initially until executing is equal its number. | |
727 | */ | |
728 | static atomic_t mce_executing; | |
729 | ||
730 | /* | |
731 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
732 | */ | |
733 | static atomic_t mce_callin; | |
734 | ||
735 | /* | |
736 | * Check if a timeout waiting for other CPUs happened. | |
737 | */ | |
738 | static int mce_timed_out(u64 *t) | |
739 | { | |
740 | /* | |
741 | * The others already did panic for some reason. | |
742 | * Bail out like in a timeout. | |
743 | * rmb() to tell the compiler that system_state | |
744 | * might have been modified by someone else. | |
745 | */ | |
746 | rmb(); | |
747 | if (atomic_read(&mce_paniced)) | |
748 | wait_for_panic(); | |
84c2559d | 749 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
750 | goto out; |
751 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 752 | if (mca_cfg.tolerant <= 1) |
3c079792 AK |
753 | mce_panic("Timeout synchronizing machine check over CPUs", |
754 | NULL, NULL); | |
755 | cpu_missing = 1; | |
756 | return 1; | |
757 | } | |
758 | *t -= SPINUNIT; | |
759 | out: | |
760 | touch_nmi_watchdog(); | |
761 | return 0; | |
762 | } | |
763 | ||
764 | /* | |
765 | * The Monarch's reign. The Monarch is the CPU who entered | |
766 | * the machine check handler first. It waits for the others to | |
767 | * raise the exception too and then grades them. When any | |
768 | * error is fatal panic. Only then let the others continue. | |
769 | * | |
770 | * The other CPUs entering the MCE handler will be controlled by the | |
771 | * Monarch. They are called Subjects. | |
772 | * | |
773 | * This way we prevent any potential data corruption in a unrecoverable case | |
774 | * and also makes sure always all CPU's errors are examined. | |
775 | * | |
680b6cfd | 776 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
777 | * space (not detected by any CPUs) In this case some external agent wants |
778 | * us to shut down, so panic too. | |
779 | * | |
780 | * The other CPUs might still decide to panic if the handler happens | |
781 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
782 | * state and won't corrupt anything by itself. It's ok to let the others | |
783 | * continue for a bit first. | |
784 | * | |
785 | * All the spin loops have timeouts; when a timeout happens a CPU | |
786 | * typically elects itself to be Monarch. | |
787 | */ | |
788 | static void mce_reign(void) | |
789 | { | |
790 | int cpu; | |
791 | struct mce *m = NULL; | |
792 | int global_worst = 0; | |
793 | char *msg = NULL; | |
794 | char *nmsg = NULL; | |
795 | ||
796 | /* | |
797 | * This CPU is the Monarch and the other CPUs have run | |
798 | * through their handlers. | |
799 | * Grade the severity of the errors of all the CPUs. | |
800 | */ | |
801 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
802 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
803 | mca_cfg.tolerant, | |
e3480271 | 804 | &nmsg, true); |
3c079792 AK |
805 | if (severity > global_worst) { |
806 | msg = nmsg; | |
807 | global_worst = severity; | |
808 | m = &per_cpu(mces_seen, cpu); | |
809 | } | |
810 | } | |
811 | ||
812 | /* | |
813 | * Cannot recover? Panic here then. | |
814 | * This dumps all the mces in the log buffer and stops the | |
815 | * other CPUs. | |
816 | */ | |
d203f0b8 | 817 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
ac960375 | 818 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
819 | |
820 | /* | |
821 | * For UC somewhere we let the CPU who detects it handle it. | |
822 | * Also must let continue the others, otherwise the handling | |
823 | * CPU could deadlock on a lock. | |
824 | */ | |
825 | ||
826 | /* | |
827 | * No machine check event found. Must be some external | |
828 | * source or one CPU is hung. Panic. | |
829 | */ | |
d203f0b8 | 830 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
3c079792 AK |
831 | mce_panic("Machine check from unknown source", NULL, NULL); |
832 | ||
833 | /* | |
834 | * Now clear all the mces_seen so that they don't reappear on | |
835 | * the next mce. | |
836 | */ | |
837 | for_each_possible_cpu(cpu) | |
838 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
839 | } | |
840 | ||
841 | static atomic_t global_nwo; | |
842 | ||
843 | /* | |
844 | * Start of Monarch synchronization. This waits until all CPUs have | |
845 | * entered the exception handler and then determines if any of them | |
846 | * saw a fatal event that requires panic. Then it executes them | |
847 | * in the entry order. | |
848 | * TBD double check parallel CPU hotunplug | |
849 | */ | |
7fb06fc9 | 850 | static int mce_start(int *no_way_out) |
3c079792 | 851 | { |
7fb06fc9 | 852 | int order; |
3c079792 | 853 | int cpus = num_online_cpus(); |
84c2559d | 854 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 855 | |
7fb06fc9 HS |
856 | if (!timeout) |
857 | return -1; | |
3c079792 | 858 | |
7fb06fc9 | 859 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
860 | /* |
861 | * global_nwo should be updated before mce_callin | |
862 | */ | |
863 | smp_wmb(); | |
a95436e4 | 864 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
865 | |
866 | /* | |
867 | * Wait for everyone. | |
868 | */ | |
869 | while (atomic_read(&mce_callin) != cpus) { | |
870 | if (mce_timed_out(&timeout)) { | |
871 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 872 | return -1; |
3c079792 AK |
873 | } |
874 | ndelay(SPINUNIT); | |
875 | } | |
876 | ||
184e1fdf HY |
877 | /* |
878 | * mce_callin should be read before global_nwo | |
879 | */ | |
880 | smp_rmb(); | |
3c079792 | 881 | |
7fb06fc9 HS |
882 | if (order == 1) { |
883 | /* | |
884 | * Monarch: Starts executing now, the others wait. | |
885 | */ | |
3c079792 | 886 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
887 | } else { |
888 | /* | |
889 | * Subject: Now start the scanning loop one by one in | |
890 | * the original callin order. | |
891 | * This way when there are any shared banks it will be | |
892 | * only seen by one CPU before cleared, avoiding duplicates. | |
893 | */ | |
894 | while (atomic_read(&mce_executing) < order) { | |
895 | if (mce_timed_out(&timeout)) { | |
896 | atomic_set(&global_nwo, 0); | |
897 | return -1; | |
898 | } | |
899 | ndelay(SPINUNIT); | |
900 | } | |
3c079792 AK |
901 | } |
902 | ||
903 | /* | |
7fb06fc9 | 904 | * Cache the global no_way_out state. |
3c079792 | 905 | */ |
7fb06fc9 HS |
906 | *no_way_out = atomic_read(&global_nwo); |
907 | ||
908 | return order; | |
3c079792 AK |
909 | } |
910 | ||
911 | /* | |
912 | * Synchronize between CPUs after main scanning loop. | |
913 | * This invokes the bulk of the Monarch processing. | |
914 | */ | |
915 | static int mce_end(int order) | |
916 | { | |
917 | int ret = -1; | |
84c2559d | 918 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
919 | |
920 | if (!timeout) | |
921 | goto reset; | |
922 | if (order < 0) | |
923 | goto reset; | |
924 | ||
925 | /* | |
926 | * Allow others to run. | |
927 | */ | |
928 | atomic_inc(&mce_executing); | |
929 | ||
930 | if (order == 1) { | |
931 | /* CHECKME: Can this race with a parallel hotplug? */ | |
932 | int cpus = num_online_cpus(); | |
933 | ||
934 | /* | |
935 | * Monarch: Wait for everyone to go through their scanning | |
936 | * loops. | |
937 | */ | |
938 | while (atomic_read(&mce_executing) <= cpus) { | |
939 | if (mce_timed_out(&timeout)) | |
940 | goto reset; | |
941 | ndelay(SPINUNIT); | |
942 | } | |
943 | ||
944 | mce_reign(); | |
945 | barrier(); | |
946 | ret = 0; | |
947 | } else { | |
948 | /* | |
949 | * Subject: Wait for Monarch to finish. | |
950 | */ | |
951 | while (atomic_read(&mce_executing) != 0) { | |
952 | if (mce_timed_out(&timeout)) | |
953 | goto reset; | |
954 | ndelay(SPINUNIT); | |
955 | } | |
956 | ||
957 | /* | |
958 | * Don't reset anything. That's done by the Monarch. | |
959 | */ | |
960 | return 0; | |
961 | } | |
962 | ||
963 | /* | |
964 | * Reset all global state. | |
965 | */ | |
966 | reset: | |
967 | atomic_set(&global_nwo, 0); | |
968 | atomic_set(&mce_callin, 0); | |
969 | barrier(); | |
970 | ||
971 | /* | |
972 | * Let others run again. | |
973 | */ | |
974 | atomic_set(&mce_executing, 0); | |
975 | return ret; | |
976 | } | |
977 | ||
9b1beaf2 AK |
978 | /* |
979 | * Check if the address reported by the CPU is in a format we can parse. | |
980 | * It would be possible to add code for most other cases, but all would | |
981 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 982 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
983 | */ |
984 | static int mce_usable_address(struct mce *m) | |
985 | { | |
986 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
987 | return 0; | |
2b90e77e | 988 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 989 | return 0; |
2b90e77e | 990 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
991 | return 0; |
992 | return 1; | |
993 | } | |
994 | ||
3c079792 AK |
995 | static void mce_clear_state(unsigned long *toclear) |
996 | { | |
997 | int i; | |
998 | ||
d203f0b8 | 999 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1000 | if (test_bit(i, toclear)) |
a2d32bcb | 1001 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
1002 | } |
1003 | } | |
1004 | ||
af104e39 TL |
1005 | /* |
1006 | * Need to save faulting physical address associated with a process | |
1007 | * in the machine check handler some place where we can grab it back | |
1008 | * later in mce_notify_process() | |
1009 | */ | |
1010 | #define MCE_INFO_MAX 16 | |
1011 | ||
1012 | struct mce_info { | |
1013 | atomic_t inuse; | |
1014 | struct task_struct *t; | |
1015 | __u64 paddr; | |
dad1743e | 1016 | int restartable; |
af104e39 TL |
1017 | } mce_info[MCE_INFO_MAX]; |
1018 | ||
dad1743e | 1019 | static void mce_save_info(__u64 addr, int c) |
af104e39 TL |
1020 | { |
1021 | struct mce_info *mi; | |
1022 | ||
1023 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { | |
1024 | if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { | |
1025 | mi->t = current; | |
1026 | mi->paddr = addr; | |
dad1743e | 1027 | mi->restartable = c; |
af104e39 TL |
1028 | return; |
1029 | } | |
1030 | } | |
1031 | ||
1032 | mce_panic("Too many concurrent recoverable errors", NULL, NULL); | |
1033 | } | |
1034 | ||
1035 | static struct mce_info *mce_find_info(void) | |
1036 | { | |
1037 | struct mce_info *mi; | |
1038 | ||
1039 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) | |
1040 | if (atomic_read(&mi->inuse) && mi->t == current) | |
1041 | return mi; | |
1042 | return NULL; | |
1043 | } | |
1044 | ||
1045 | static void mce_clear_info(struct mce_info *mi) | |
1046 | { | |
1047 | atomic_set(&mi->inuse, 0); | |
1048 | } | |
1049 | ||
b79109c3 AK |
1050 | /* |
1051 | * The actual machine check handler. This only handles real | |
1052 | * exceptions when something got corrupted coming in through int 18. | |
1053 | * | |
1054 | * This is executed in NMI context not subject to normal locking rules. This | |
1055 | * implies that most kernel services cannot be safely used. Don't even | |
1056 | * think about putting a printk in there! | |
3c079792 AK |
1057 | * |
1058 | * On Intel systems this is entered on all CPUs in parallel through | |
1059 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1060 | * so be always careful when synchronizing with others. | |
1da177e4 | 1061 | */ |
e9eee03e | 1062 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1063 | { |
1462594b | 1064 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1065 | struct mce m, *final; |
1da177e4 | 1066 | int i; |
3c079792 AK |
1067 | int worst = 0; |
1068 | int severity; | |
1069 | /* | |
1070 | * Establish sequential order between the CPUs entering the machine | |
1071 | * check handler. | |
1072 | */ | |
7fb06fc9 | 1073 | int order; |
bd78432c TH |
1074 | /* |
1075 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1076 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1077 | */ |
1078 | int no_way_out = 0; | |
1079 | /* | |
1080 | * If kill_it gets set, there might be a way to recover from this | |
1081 | * error. | |
1082 | */ | |
1083 | int kill_it = 0; | |
b79109c3 | 1084 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1085 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1086 | char *msg = "Unknown"; |
1da177e4 | 1087 | |
c6ae41e7 | 1088 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1089 | |
1462594b | 1090 | if (!cfg->banks) |
32561696 | 1091 | goto out; |
1da177e4 | 1092 | |
b8325c5b | 1093 | mce_gather_info(&m, regs); |
b5f2fa4e | 1094 | |
89cbc767 | 1095 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1096 | *final = m; |
1097 | ||
95022b8c | 1098 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1099 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1100 | |
1da177e4 LT |
1101 | barrier(); |
1102 | ||
ed7290d0 | 1103 | /* |
a8c321fb TL |
1104 | * When no restart IP might need to kill or panic. |
1105 | * Assume the worst for now, but if we find the | |
1106 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1107 | */ |
1108 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1109 | kill_it = 1; | |
1110 | ||
3c079792 AK |
1111 | /* |
1112 | * Go through all the banks in exclusion of the other CPUs. | |
1113 | * This way we don't report duplicated events on shared banks | |
1114 | * because the first one to see it will clear it. | |
1115 | */ | |
7fb06fc9 | 1116 | order = mce_start(&no_way_out); |
1462594b | 1117 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1118 | __clear_bit(i, toclear); |
95022b8c TL |
1119 | if (!test_bit(i, valid_banks)) |
1120 | continue; | |
cebe1820 | 1121 | if (!mce_banks[i].ctl) |
1da177e4 | 1122 | continue; |
d88203d1 TG |
1123 | |
1124 | m.misc = 0; | |
1da177e4 LT |
1125 | m.addr = 0; |
1126 | m.bank = i; | |
1da177e4 | 1127 | |
a2d32bcb | 1128 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1129 | if ((m.status & MCI_STATUS_VAL) == 0) |
1130 | continue; | |
1131 | ||
b79109c3 | 1132 | /* |
ed7290d0 AK |
1133 | * Non uncorrected or non signaled errors are handled by |
1134 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1135 | */ |
1462594b | 1136 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1137 | !no_way_out) |
b79109c3 AK |
1138 | continue; |
1139 | ||
1140 | /* | |
1141 | * Set taint even when machine check was not enabled. | |
1142 | */ | |
373d4d09 | 1143 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1144 | |
e3480271 | 1145 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1146 | |
ed7290d0 | 1147 | /* |
e3480271 CY |
1148 | * When machine check was for corrected/deferred handler don't |
1149 | * touch, unless we're panicing. | |
ed7290d0 | 1150 | */ |
e3480271 CY |
1151 | if ((severity == MCE_KEEP_SEVERITY || |
1152 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1153 | continue; |
1154 | __set_bit(i, toclear); | |
1155 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1156 | /* |
1157 | * Machine check event was not enabled. Clear, but | |
1158 | * ignore. | |
1159 | */ | |
1160 | continue; | |
1da177e4 LT |
1161 | } |
1162 | ||
85f92694 | 1163 | mce_read_aux(&m, i); |
1da177e4 | 1164 | |
9b1beaf2 AK |
1165 | /* |
1166 | * Action optional error. Queue address for later processing. | |
1167 | * When the ring overflows we just ignore the AO error. | |
1168 | * RED-PEN add some logging mechanism when | |
1169 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1170 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1171 | */ |
1172 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1173 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1174 | ||
b79109c3 | 1175 | mce_log(&m); |
1da177e4 | 1176 | |
3c079792 AK |
1177 | if (severity > worst) { |
1178 | *final = m; | |
1179 | worst = severity; | |
1da177e4 | 1180 | } |
1da177e4 LT |
1181 | } |
1182 | ||
a8c321fb TL |
1183 | /* mce_clear_state will clear *final, save locally for use later */ |
1184 | m = *final; | |
1185 | ||
3c079792 AK |
1186 | if (!no_way_out) |
1187 | mce_clear_state(toclear); | |
1188 | ||
e9eee03e | 1189 | /* |
3c079792 AK |
1190 | * Do most of the synchronization with other CPUs. |
1191 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1192 | */ |
3c079792 AK |
1193 | if (mce_end(order) < 0) |
1194 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1195 | |
1196 | /* | |
a8c321fb TL |
1197 | * At insane "tolerant" levels we take no action. Otherwise |
1198 | * we only die if we have no other choice. For less serious | |
1199 | * issues we try to recover, or limit damage to the current | |
1200 | * process. | |
bd78432c | 1201 | */ |
1462594b | 1202 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1203 | if (no_way_out) |
1204 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1205 | if (worst == MCE_AR_SEVERITY) { | |
1206 | /* schedule action before return to userland */ | |
dad1743e | 1207 | mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); |
a8c321fb TL |
1208 | set_thread_flag(TIF_MCE_NOTIFY); |
1209 | } else if (kill_it) { | |
1210 | force_sig(SIGBUS, current); | |
1211 | } | |
1212 | } | |
e02e68d3 | 1213 | |
3c079792 AK |
1214 | if (worst > 0) |
1215 | mce_report_event(regs); | |
5f8c1a54 | 1216 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1217 | out: |
88921be3 | 1218 | sync_core(); |
1da177e4 | 1219 | } |
ea149b36 | 1220 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1221 | |
cd42f4a3 TL |
1222 | #ifndef CONFIG_MEMORY_FAILURE |
1223 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1224 | { |
a8c321fb TL |
1225 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1226 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1227 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1228 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1229 | pfn); | |
cd42f4a3 TL |
1230 | |
1231 | return 0; | |
9b1beaf2 | 1232 | } |
cd42f4a3 | 1233 | #endif |
9b1beaf2 AK |
1234 | |
1235 | /* | |
a8c321fb TL |
1236 | * Called in process context that interrupted by MCE and marked with |
1237 | * TIF_MCE_NOTIFY, just before returning to erroneous userland. | |
1238 | * This code is allowed to sleep. | |
1239 | * Attempt possible recovery such as calling the high level VM handler to | |
1240 | * process any corrupted pages, and kill/signal current process if required. | |
1241 | * Action required errors are handled here. | |
9b1beaf2 AK |
1242 | */ |
1243 | void mce_notify_process(void) | |
1244 | { | |
1245 | unsigned long pfn; | |
a8c321fb | 1246 | struct mce_info *mi = mce_find_info(); |
6751ed65 | 1247 | int flags = MF_ACTION_REQUIRED; |
a8c321fb TL |
1248 | |
1249 | if (!mi) | |
1250 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | |
1251 | pfn = mi->paddr >> PAGE_SHIFT; | |
1252 | ||
1253 | clear_thread_flag(TIF_MCE_NOTIFY); | |
1254 | ||
1255 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1256 | mi->paddr); | |
dad1743e TL |
1257 | /* |
1258 | * We must call memory_failure() here even if the current process is | |
1259 | * doomed. We still need to mark the page as poisoned and alert any | |
1260 | * other users of the page. | |
1261 | */ | |
6751ed65 TL |
1262 | if (!mi->restartable) |
1263 | flags |= MF_MUST_KILL; | |
1264 | if (memory_failure(pfn, MCE_VECTOR, flags) < 0) { | |
a8c321fb TL |
1265 | pr_err("Memory error not recovered"); |
1266 | force_sig(SIGBUS, current); | |
1267 | } | |
1268 | mce_clear_info(mi); | |
9b1beaf2 AK |
1269 | } |
1270 | ||
a8c321fb TL |
1271 | /* |
1272 | * Action optional processing happens here (picking up | |
1273 | * from the list of faulting pages that do_machine_check() | |
1274 | * placed into the "ring"). | |
1275 | */ | |
9b1beaf2 AK |
1276 | static void mce_process_work(struct work_struct *dummy) |
1277 | { | |
a8c321fb TL |
1278 | unsigned long pfn; |
1279 | ||
1280 | while (mce_ring_get(&pfn)) | |
1281 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1282 | } |
1283 | ||
15d5f839 DZ |
1284 | #ifdef CONFIG_X86_MCE_INTEL |
1285 | /*** | |
1286 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1287 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1288 | * @status: Event status information |
1289 | * | |
1290 | * This function should be called by the thermal interrupt after the | |
1291 | * event has been processed and the decision was made to log the event | |
1292 | * further. | |
1293 | * | |
1294 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1295 | * and historically has been the register value of the | |
1296 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1297 | */ | |
b5f2fa4e | 1298 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1299 | { |
1300 | struct mce m; | |
1301 | ||
b5f2fa4e | 1302 | mce_setup(&m); |
15d5f839 DZ |
1303 | m.bank = MCE_THERMAL_BANK; |
1304 | m.status = status; | |
15d5f839 DZ |
1305 | mce_log(&m); |
1306 | } | |
1307 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1308 | ||
1da177e4 | 1309 | /* |
8a336b0a TH |
1310 | * Periodic polling timer for "silent" machine check errors. If the |
1311 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1312 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1313 | */ |
82f7af09 | 1314 | static unsigned long check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1315 | |
82f7af09 | 1316 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1317 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1318 | |
55babd8f CG |
1319 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1320 | { | |
1321 | return interval; | |
1322 | } | |
1323 | ||
1324 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = | |
1325 | mce_adjust_timer_default; | |
1326 | ||
27f6c573 CG |
1327 | static int cmc_error_seen(void) |
1328 | { | |
89cbc767 | 1329 | unsigned long *v = this_cpu_ptr(&mce_polled_error); |
27f6c573 CG |
1330 | |
1331 | return test_and_clear_bit(0, v); | |
1332 | } | |
1333 | ||
82f7af09 | 1334 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1335 | { |
89cbc767 | 1336 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
82f7af09 | 1337 | unsigned long iv; |
27f6c573 | 1338 | int notify; |
52d168e2 AK |
1339 | |
1340 | WARN_ON(smp_processor_id() != data); | |
1341 | ||
89cbc767 | 1342 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
ee031c31 | 1343 | machine_check_poll(MCP_TIMESTAMP, |
89cbc767 | 1344 | this_cpu_ptr(&mce_poll_banks)); |
55babd8f | 1345 | mce_intel_cmci_poll(); |
e9eee03e | 1346 | } |
1da177e4 LT |
1347 | |
1348 | /* | |
e02e68d3 TH |
1349 | * Alert userspace if needed. If we logged an MCE, reduce the |
1350 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1351 | */ |
82f7af09 | 1352 | iv = __this_cpu_read(mce_next_interval); |
27f6c573 CG |
1353 | notify = mce_notify_irq(); |
1354 | notify |= cmc_error_seen(); | |
1355 | if (notify) { | |
958fb3c5 | 1356 | iv = max(iv / 2, (unsigned long) HZ/100); |
55babd8f | 1357 | } else { |
82f7af09 | 1358 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
55babd8f CG |
1359 | iv = mce_adjust_timer(iv); |
1360 | } | |
82f7af09 | 1361 | __this_cpu_write(mce_next_interval, iv); |
55babd8f CG |
1362 | /* Might have become 0 after CMCI storm subsided */ |
1363 | if (iv) { | |
1364 | t->expires = jiffies + iv; | |
1365 | add_timer_on(t, smp_processor_id()); | |
1366 | } | |
1367 | } | |
e02e68d3 | 1368 | |
55babd8f CG |
1369 | /* |
1370 | * Ensure that the timer is firing in @interval from now. | |
1371 | */ | |
1372 | void mce_timer_kick(unsigned long interval) | |
1373 | { | |
89cbc767 | 1374 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1375 | unsigned long when = jiffies + interval; |
1376 | unsigned long iv = __this_cpu_read(mce_next_interval); | |
1377 | ||
1378 | if (timer_pending(t)) { | |
1379 | if (time_before(when, t->expires)) | |
1380 | mod_timer_pinned(t, when); | |
1381 | } else { | |
1382 | t->expires = round_jiffies(when); | |
1383 | add_timer_on(t, smp_processor_id()); | |
1384 | } | |
1385 | if (interval < iv) | |
1386 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1387 | } |
1388 | ||
9aaef96f HS |
1389 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1390 | static void mce_timer_delete_all(void) | |
1391 | { | |
1392 | int cpu; | |
1393 | ||
1394 | for_each_online_cpu(cpu) | |
1395 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1396 | } | |
1397 | ||
9bd98405 AK |
1398 | static void mce_do_trigger(struct work_struct *work) |
1399 | { | |
1020bcbc | 1400 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1401 | } |
1402 | ||
1403 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1404 | ||
e02e68d3 | 1405 | /* |
9bd98405 AK |
1406 | * Notify the user(s) about new machine check events. |
1407 | * Can be called from interrupt context, but not from machine check/NMI | |
1408 | * context. | |
e02e68d3 | 1409 | */ |
9ff36ee9 | 1410 | int mce_notify_irq(void) |
e02e68d3 | 1411 | { |
8457c84d AK |
1412 | /* Not more than two messages every minute */ |
1413 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1414 | ||
1020bcbc | 1415 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1416 | /* wake processes polling /dev/mcelog */ |
1417 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1418 | |
4d899be5 | 1419 | if (mce_helper[0]) |
9bd98405 | 1420 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1421 | |
8457c84d | 1422 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1423 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1424 | |
1425 | return 1; | |
1da177e4 | 1426 | } |
e02e68d3 TH |
1427 | return 0; |
1428 | } | |
9ff36ee9 | 1429 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1430 | |
148f9bb8 | 1431 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1432 | { |
1433 | int i; | |
d203f0b8 | 1434 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1435 | |
d203f0b8 | 1436 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1437 | if (!mce_banks) |
1438 | return -ENOMEM; | |
d203f0b8 BP |
1439 | |
1440 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1441 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1442 | |
cebe1820 AK |
1443 | b->ctl = -1ULL; |
1444 | b->init = 1; | |
1445 | } | |
1446 | return 0; | |
1447 | } | |
1448 | ||
d88203d1 | 1449 | /* |
1da177e4 LT |
1450 | * Initialize Machine Checks for a CPU. |
1451 | */ | |
148f9bb8 | 1452 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1453 | { |
0d7482e3 | 1454 | unsigned b; |
e9eee03e | 1455 | u64 cap; |
1da177e4 LT |
1456 | |
1457 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1458 | |
1459 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1460 | if (!mca_cfg.banks) |
c767a54b | 1461 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1462 | |
0d7482e3 | 1463 | if (b > MAX_NR_BANKS) { |
c767a54b | 1464 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1465 | MAX_NR_BANKS, b); |
1466 | b = MAX_NR_BANKS; | |
1467 | } | |
1468 | ||
1469 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1470 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1471 | mca_cfg.banks = b; | |
1472 | ||
cebe1820 | 1473 | if (!mce_banks) { |
cffd377e | 1474 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1475 | |
cebe1820 AK |
1476 | if (err) |
1477 | return err; | |
1da177e4 | 1478 | } |
0d7482e3 | 1479 | |
94ad8474 | 1480 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1481 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1482 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1483 | |
ed7290d0 | 1484 | if (cap & MCG_SER_P) |
1462594b | 1485 | mca_cfg.ser = true; |
ed7290d0 | 1486 | |
0d7482e3 AK |
1487 | return 0; |
1488 | } | |
1489 | ||
5e09954a | 1490 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1491 | { |
84c2559d | 1492 | enum mcp_flags m_fl = 0; |
e9eee03e | 1493 | mce_banks_t all_banks; |
0d7482e3 AK |
1494 | u64 cap; |
1495 | int i; | |
1496 | ||
84c2559d BP |
1497 | if (!mca_cfg.bootlog) |
1498 | m_fl = MCP_DONTLOG; | |
1499 | ||
b79109c3 AK |
1500 | /* |
1501 | * Log the machine checks left over from the previous reset. | |
1502 | */ | |
ee031c31 | 1503 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1504 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 LT |
1505 | |
1506 | set_in_cr4(X86_CR4_MCE); | |
1507 | ||
0d7482e3 | 1508 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1509 | if (cap & MCG_CTL_P) |
1510 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1511 | ||
d203f0b8 | 1512 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1513 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1514 | |
cebe1820 | 1515 | if (!b->init) |
06b7a7a5 | 1516 | continue; |
a2d32bcb AK |
1517 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1518 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1519 | } |
1da177e4 LT |
1520 | } |
1521 | ||
61b0fccd TL |
1522 | /* |
1523 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1524 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1525 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1526 | * whether the machine check occurred in kernel or user mode, and also | |
1527 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1528 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1529 | */ | |
1530 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1531 | { | |
1532 | if (bank != 0) | |
1533 | return; | |
1534 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1535 | return; | |
1536 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1537 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1538 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1539 | MCACOD)) != | |
1540 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1541 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1542 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1543 | return; | |
1544 | ||
1545 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1546 | m->ip = regs->ip; | |
1547 | m->cs = regs->cs; | |
1548 | } | |
1549 | ||
1da177e4 | 1550 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1551 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1552 | { |
d203f0b8 BP |
1553 | struct mca_config *cfg = &mca_cfg; |
1554 | ||
e412cd25 | 1555 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1556 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1557 | return -EOPNOTSUPP; |
1558 | } | |
1559 | ||
1da177e4 | 1560 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1561 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1562 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1563 | /* |
1564 | * disable GART TBL walk error reporting, which | |
1565 | * trips off incorrectly with the IOMMU & 3ware | |
1566 | * & Cerberus: | |
1567 | */ | |
cebe1820 | 1568 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1569 | } |
84c2559d | 1570 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1571 | /* |
1572 | * Lots of broken BIOS around that don't clear them | |
1573 | * by default and leave crap in there. Don't log: | |
1574 | */ | |
84c2559d | 1575 | cfg->bootlog = 0; |
e9eee03e | 1576 | } |
2e6f694f AK |
1577 | /* |
1578 | * Various K7s with broken bank 0 around. Always disable | |
1579 | * by default. | |
1580 | */ | |
d203f0b8 | 1581 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1582 | mce_banks[0].ctl = 0; |
575203b4 BP |
1583 | |
1584 | /* | |
1585 | * Turn off MC4_MISC thresholding banks on those models since | |
1586 | * they're not supported there. | |
1587 | */ | |
1588 | if (c->x86 == 0x15 && | |
1589 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1590 | int i; | |
1591 | u64 val, hwcr; | |
1592 | bool need_toggle; | |
1593 | u32 msrs[] = { | |
1594 | 0x00000413, /* MC4_MISC0 */ | |
1595 | 0xc0000408, /* MC4_MISC1 */ | |
1596 | }; | |
1597 | ||
1598 | rdmsrl(MSR_K7_HWCR, hwcr); | |
1599 | ||
1600 | /* McStatusWrEn has to be set */ | |
1601 | need_toggle = !(hwcr & BIT(18)); | |
1602 | ||
1603 | if (need_toggle) | |
1604 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
1605 | ||
1606 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | |
1607 | rdmsrl(msrs[i], val); | |
1608 | ||
1609 | /* CntP bit set? */ | |
80f03361 BP |
1610 | if (val & BIT_64(62)) { |
1611 | val &= ~BIT_64(62); | |
1612 | wrmsrl(msrs[i], val); | |
575203b4 BP |
1613 | } |
1614 | } | |
1615 | ||
1616 | /* restore old settings */ | |
1617 | if (need_toggle) | |
1618 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1619 | } | |
1da177e4 | 1620 | } |
e583538f | 1621 | |
06b7a7a5 AK |
1622 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1623 | /* | |
1624 | * SDM documents that on family 6 bank 0 should not be written | |
1625 | * because it aliases to another special BIOS controlled | |
1626 | * register. | |
1627 | * But it's not aliased anymore on model 0x1a+ | |
1628 | * Don't ignore bank 0 completely because there could be a | |
1629 | * valid event later, merely don't write CTL0. | |
1630 | */ | |
1631 | ||
d203f0b8 | 1632 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1633 | mce_banks[0].init = 0; |
3c079792 AK |
1634 | |
1635 | /* | |
1636 | * All newer Intel systems support MCE broadcasting. Enable | |
1637 | * synchronization with a one second timeout. | |
1638 | */ | |
1639 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1640 | cfg->monarch_timeout < 0) |
1641 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1642 | |
e412cd25 IM |
1643 | /* |
1644 | * There are also broken BIOSes on some Pentium M and | |
1645 | * earlier systems: | |
1646 | */ | |
84c2559d BP |
1647 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1648 | cfg->bootlog = 0; | |
61b0fccd TL |
1649 | |
1650 | if (c->x86 == 6 && c->x86_model == 45) | |
1651 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1652 | } |
84c2559d BP |
1653 | if (cfg->monarch_timeout < 0) |
1654 | cfg->monarch_timeout = 0; | |
1655 | if (cfg->bootlog != 0) | |
7af19e4a | 1656 | cfg->panic_timeout = 30; |
e412cd25 IM |
1657 | |
1658 | return 0; | |
d88203d1 | 1659 | } |
1da177e4 | 1660 | |
148f9bb8 | 1661 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1662 | { |
1663 | if (c->x86 != 5) | |
3a97fc34 HS |
1664 | return 0; |
1665 | ||
4efc0670 AK |
1666 | switch (c->x86_vendor) { |
1667 | case X86_VENDOR_INTEL: | |
c6978369 | 1668 | intel_p5_mcheck_init(c); |
3a97fc34 | 1669 | return 1; |
4efc0670 AK |
1670 | break; |
1671 | case X86_VENDOR_CENTAUR: | |
1672 | winchip_mcheck_init(c); | |
3a97fc34 | 1673 | return 1; |
4efc0670 AK |
1674 | break; |
1675 | } | |
3a97fc34 HS |
1676 | |
1677 | return 0; | |
4efc0670 AK |
1678 | } |
1679 | ||
5e09954a | 1680 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1681 | { |
1682 | switch (c->x86_vendor) { | |
1683 | case X86_VENDOR_INTEL: | |
1684 | mce_intel_feature_init(c); | |
55babd8f | 1685 | mce_adjust_timer = mce_intel_adjust_timer; |
1da177e4 | 1686 | break; |
89b831ef JS |
1687 | case X86_VENDOR_AMD: |
1688 | mce_amd_feature_init(c); | |
1689 | break; | |
1da177e4 LT |
1690 | default: |
1691 | break; | |
1692 | } | |
1693 | } | |
1694 | ||
26c3c283 | 1695 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1696 | { |
4f75d841 | 1697 | unsigned long iv = check_interval * HZ; |
bc09effa | 1698 | |
7af19e4a | 1699 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1700 | return; |
1701 | ||
4f75d841 BP |
1702 | per_cpu(mce_next_interval, cpu) = iv; |
1703 | ||
82f7af09 | 1704 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1705 | add_timer_on(t, cpu); |
52d168e2 AK |
1706 | } |
1707 | ||
26c3c283 TG |
1708 | static void __mcheck_cpu_init_timer(void) |
1709 | { | |
89cbc767 | 1710 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1711 | unsigned int cpu = smp_processor_id(); |
1712 | ||
1713 | setup_timer(t, mce_timer_fn, cpu); | |
1714 | mce_start_timer(cpu, t); | |
1715 | } | |
1716 | ||
9eda8cb3 AK |
1717 | /* Handle unconfigured int18 (should never happen) */ |
1718 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1719 | { | |
c767a54b | 1720 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1721 | smp_processor_id()); |
1722 | } | |
1723 | ||
1724 | /* Call the installed machine check handler for this CPU setup. */ | |
1725 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1726 | unexpected_machine_check; | |
1727 | ||
d88203d1 | 1728 | /* |
1da177e4 | 1729 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1730 | * Must be called with preempt off: |
1da177e4 | 1731 | */ |
148f9bb8 | 1732 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1733 | { |
1462594b | 1734 | if (mca_cfg.disabled) |
4efc0670 AK |
1735 | return; |
1736 | ||
3a97fc34 HS |
1737 | if (__mcheck_cpu_ancient_init(c)) |
1738 | return; | |
4efc0670 | 1739 | |
5b4408fd | 1740 | if (!mce_available(c)) |
1da177e4 LT |
1741 | return; |
1742 | ||
5e09954a | 1743 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1744 | mca_cfg.disabled = true; |
0d7482e3 AK |
1745 | return; |
1746 | } | |
0d7482e3 | 1747 | |
5d727926 AK |
1748 | machine_check_vector = do_machine_check; |
1749 | ||
5e09954a BP |
1750 | __mcheck_cpu_init_generic(); |
1751 | __mcheck_cpu_init_vendor(c); | |
1752 | __mcheck_cpu_init_timer(); | |
89cbc767 CL |
1753 | INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work); |
1754 | init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb); | |
1da177e4 LT |
1755 | } |
1756 | ||
1757 | /* | |
93b62c3c | 1758 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1759 | */ |
1760 | ||
93b62c3c HS |
1761 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1762 | static int mce_chrdev_open_count; /* #times opened */ | |
1763 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1764 | |
93b62c3c | 1765 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1766 | { |
93b62c3c | 1767 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1768 | |
93b62c3c HS |
1769 | if (mce_chrdev_open_exclu || |
1770 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1771 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1772 | |
f528e7ba TH |
1773 | return -EBUSY; |
1774 | } | |
1775 | ||
1776 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1777 | mce_chrdev_open_exclu = 1; |
1778 | mce_chrdev_open_count++; | |
f528e7ba | 1779 | |
93b62c3c | 1780 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1781 | |
bd78432c | 1782 | return nonseekable_open(inode, file); |
f528e7ba TH |
1783 | } |
1784 | ||
93b62c3c | 1785 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1786 | { |
93b62c3c | 1787 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1788 | |
93b62c3c HS |
1789 | mce_chrdev_open_count--; |
1790 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1791 | |
93b62c3c | 1792 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1793 | |
1794 | return 0; | |
1795 | } | |
1796 | ||
d88203d1 TG |
1797 | static void collect_tscs(void *data) |
1798 | { | |
1da177e4 | 1799 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1800 | |
1da177e4 | 1801 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1802 | } |
1da177e4 | 1803 | |
482908b4 HY |
1804 | static int mce_apei_read_done; |
1805 | ||
1806 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1807 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1808 | { | |
1809 | int rc; | |
1810 | u64 record_id; | |
1811 | struct mce m; | |
1812 | ||
1813 | if (usize < sizeof(struct mce)) | |
1814 | return -EINVAL; | |
1815 | ||
1816 | rc = apei_read_mce(&m, &record_id); | |
1817 | /* Error or no more MCE record */ | |
1818 | if (rc <= 0) { | |
1819 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1820 | /* |
1821 | * When ERST is disabled, mce_chrdev_read() should return | |
1822 | * "no record" instead of "no device." | |
1823 | */ | |
1824 | if (rc == -ENODEV) | |
1825 | return 0; | |
482908b4 HY |
1826 | return rc; |
1827 | } | |
1828 | rc = -EFAULT; | |
1829 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1830 | return rc; | |
1831 | /* | |
1832 | * In fact, we should have cleared the record after that has | |
1833 | * been flushed to the disk or sent to network in | |
1834 | * /sbin/mcelog, but we have no interface to support that now, | |
1835 | * so just clear it to avoid duplication. | |
1836 | */ | |
1837 | rc = apei_clear_mce(record_id); | |
1838 | if (rc) { | |
1839 | mce_apei_read_done = 1; | |
1840 | return rc; | |
1841 | } | |
1842 | *ubuf += sizeof(struct mce); | |
1843 | ||
1844 | return 0; | |
1845 | } | |
1846 | ||
93b62c3c HS |
1847 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1848 | size_t usize, loff_t *off) | |
1da177e4 | 1849 | { |
e9eee03e | 1850 | char __user *buf = ubuf; |
f0de53bb | 1851 | unsigned long *cpu_tsc; |
ef41df43 | 1852 | unsigned prev, next; |
1da177e4 LT |
1853 | int i, err; |
1854 | ||
6bca67f9 | 1855 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1856 | if (!cpu_tsc) |
1857 | return -ENOMEM; | |
1858 | ||
93b62c3c | 1859 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1860 | |
1861 | if (!mce_apei_read_done) { | |
1862 | err = __mce_read_apei(&buf, usize); | |
1863 | if (err || buf != ubuf) | |
1864 | goto out; | |
1865 | } | |
1866 | ||
f56e8a07 | 1867 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1868 | |
1869 | /* Only supports full reads right now */ | |
482908b4 HY |
1870 | err = -EINVAL; |
1871 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1872 | goto out; | |
1da177e4 LT |
1873 | |
1874 | err = 0; | |
ef41df43 HY |
1875 | prev = 0; |
1876 | do { | |
1877 | for (i = prev; i < next; i++) { | |
1878 | unsigned long start = jiffies; | |
559faa6b | 1879 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1880 | |
559faa6b | 1881 | while (!m->finished) { |
ef41df43 | 1882 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1883 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1884 | goto timeout; |
1885 | } | |
1886 | cpu_relax(); | |
673242c1 | 1887 | } |
ef41df43 | 1888 | smp_rmb(); |
559faa6b HS |
1889 | err |= copy_to_user(buf, m, sizeof(*m)); |
1890 | buf += sizeof(*m); | |
ef41df43 HY |
1891 | timeout: |
1892 | ; | |
673242c1 | 1893 | } |
1da177e4 | 1894 | |
ef41df43 HY |
1895 | memset(mcelog.entry + prev, 0, |
1896 | (next - prev) * sizeof(struct mce)); | |
1897 | prev = next; | |
1898 | next = cmpxchg(&mcelog.next, prev, 0); | |
1899 | } while (next != prev); | |
1da177e4 | 1900 | |
b2b18660 | 1901 | synchronize_sched(); |
1da177e4 | 1902 | |
d88203d1 TG |
1903 | /* |
1904 | * Collect entries that were still getting written before the | |
1905 | * synchronize. | |
1906 | */ | |
15c8b6c1 | 1907 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1908 | |
d88203d1 | 1909 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1910 | struct mce *m = &mcelog.entry[i]; |
1911 | ||
1912 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1913 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1914 | smp_rmb(); |
559faa6b HS |
1915 | buf += sizeof(*m); |
1916 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1917 | } |
d88203d1 | 1918 | } |
482908b4 HY |
1919 | |
1920 | if (err) | |
1921 | err = -EFAULT; | |
1922 | ||
1923 | out: | |
93b62c3c | 1924 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1925 | kfree(cpu_tsc); |
e9eee03e | 1926 | |
482908b4 | 1927 | return err ? err : buf - ubuf; |
1da177e4 LT |
1928 | } |
1929 | ||
93b62c3c | 1930 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1931 | { |
93b62c3c | 1932 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1933 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1934 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1935 | if (!mce_apei_read_done && apei_check_mce()) |
1936 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1937 | return 0; |
1938 | } | |
1939 | ||
93b62c3c HS |
1940 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1941 | unsigned long arg) | |
1da177e4 LT |
1942 | { |
1943 | int __user *p = (int __user *)arg; | |
d88203d1 | 1944 | |
1da177e4 | 1945 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1946 | return -EPERM; |
e9eee03e | 1947 | |
1da177e4 | 1948 | switch (cmd) { |
d88203d1 | 1949 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1950 | return put_user(sizeof(struct mce), p); |
1951 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1952 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1953 | case MCE_GETCLEAR_FLAGS: { |
1954 | unsigned flags; | |
d88203d1 TG |
1955 | |
1956 | do { | |
1da177e4 | 1957 | flags = mcelog.flags; |
d88203d1 | 1958 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1959 | |
d88203d1 | 1960 | return put_user(flags, p); |
1da177e4 LT |
1961 | } |
1962 | default: | |
d88203d1 TG |
1963 | return -ENOTTY; |
1964 | } | |
1da177e4 LT |
1965 | } |
1966 | ||
66f5ddf3 LT |
1967 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1968 | size_t usize, loff_t *off); | |
1969 | ||
1970 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1971 | const char __user *ubuf, | |
1972 | size_t usize, loff_t *off)) | |
1973 | { | |
1974 | mce_write = fn; | |
1975 | } | |
1976 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1977 | ||
1978 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1979 | size_t usize, loff_t *off) | |
1980 | { | |
1981 | if (mce_write) | |
1982 | return mce_write(filp, ubuf, usize, off); | |
1983 | else | |
1984 | return -EINVAL; | |
1985 | } | |
1986 | ||
1987 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1988 | .open = mce_chrdev_open, |
1989 | .release = mce_chrdev_release, | |
1990 | .read = mce_chrdev_read, | |
66f5ddf3 | 1991 | .write = mce_chrdev_write, |
93b62c3c HS |
1992 | .poll = mce_chrdev_poll, |
1993 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1994 | .llseek = no_llseek, | |
1da177e4 LT |
1995 | }; |
1996 | ||
93b62c3c | 1997 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1998 | MISC_MCELOG_MINOR, |
1999 | "mcelog", | |
2000 | &mce_chrdev_ops, | |
2001 | }; | |
2002 | ||
c3d1fb56 NR |
2003 | static void __mce_disable_bank(void *arg) |
2004 | { | |
2005 | int bank = *((int *)arg); | |
89cbc767 | 2006 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
2007 | cmci_disable_bank(bank); |
2008 | } | |
2009 | ||
2010 | void mce_disable_bank(int bank) | |
2011 | { | |
2012 | if (bank >= mca_cfg.banks) { | |
2013 | pr_warn(FW_BUG | |
2014 | "Ignoring request to disable invalid MCA bank %d.\n", | |
2015 | bank); | |
2016 | return; | |
2017 | } | |
2018 | set_bit(bank, mce_banks_ce_disabled); | |
2019 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
2020 | } | |
2021 | ||
13503fa9 | 2022 | /* |
62fdac59 HS |
2023 | * mce=off Disables machine check |
2024 | * mce=no_cmci Disables CMCI | |
2025 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
2026 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
2027 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
2028 | * monarchtimeout is how long to wait for other CPUs on machine | |
2029 | * check, or 0 to not wait | |
13503fa9 HS |
2030 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
2031 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 2032 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 2033 | */ |
1da177e4 LT |
2034 | static int __init mcheck_enable(char *str) |
2035 | { | |
d203f0b8 BP |
2036 | struct mca_config *cfg = &mca_cfg; |
2037 | ||
e3346fc4 | 2038 | if (*str == 0) { |
4efc0670 | 2039 | enable_p5_mce(); |
e3346fc4 BZ |
2040 | return 1; |
2041 | } | |
4efc0670 AK |
2042 | if (*str == '=') |
2043 | str++; | |
1da177e4 | 2044 | if (!strcmp(str, "off")) |
1462594b | 2045 | cfg->disabled = true; |
62fdac59 | 2046 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2047 | cfg->cmci_disabled = true; |
62fdac59 | 2048 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2049 | cfg->dont_log_ce = true; |
62fdac59 | 2050 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2051 | cfg->ignore_ce = true; |
13503fa9 | 2052 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2053 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2054 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2055 | cfg->bios_cmci_threshold = true; |
3c079792 | 2056 | else if (isdigit(str[0])) { |
d203f0b8 | 2057 | get_option(&str, &(cfg->tolerant)); |
3c079792 AK |
2058 | if (*str == ',') { |
2059 | ++str; | |
84c2559d | 2060 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 AK |
2061 | } |
2062 | } else { | |
c767a54b | 2063 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2064 | return 0; |
2065 | } | |
9b41046c | 2066 | return 1; |
1da177e4 | 2067 | } |
4efc0670 | 2068 | __setup("mce", mcheck_enable); |
1da177e4 | 2069 | |
a2202aa2 | 2070 | int __init mcheck_init(void) |
b33a6363 | 2071 | { |
a2202aa2 YW |
2072 | mcheck_intel_therm_init(); |
2073 | ||
b33a6363 BP |
2074 | return 0; |
2075 | } | |
b33a6363 | 2076 | |
d88203d1 | 2077 | /* |
c7cece89 | 2078 | * mce_syscore: PM support |
d88203d1 | 2079 | */ |
1da177e4 | 2080 | |
973a2dd1 AK |
2081 | /* |
2082 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2083 | * them later. | |
2084 | */ | |
5e09954a | 2085 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2086 | { |
2087 | int i; | |
2088 | ||
d203f0b8 | 2089 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2090 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2091 | |
cebe1820 | 2092 | if (b->init) |
a2d32bcb | 2093 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2094 | } |
973a2dd1 AK |
2095 | return 0; |
2096 | } | |
2097 | ||
c7cece89 | 2098 | static int mce_syscore_suspend(void) |
973a2dd1 | 2099 | { |
5e09954a | 2100 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2101 | } |
2102 | ||
c7cece89 | 2103 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2104 | { |
f3c6ea1b | 2105 | mce_disable_error_reporting(); |
973a2dd1 AK |
2106 | } |
2107 | ||
e9eee03e IM |
2108 | /* |
2109 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2110 | * Only one CPU is active at this time, the others get re-added later using | |
2111 | * CPU hotplug: | |
2112 | */ | |
c7cece89 | 2113 | static void mce_syscore_resume(void) |
1da177e4 | 2114 | { |
5e09954a | 2115 | __mcheck_cpu_init_generic(); |
89cbc767 | 2116 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2117 | } |
2118 | ||
f3c6ea1b | 2119 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2120 | .suspend = mce_syscore_suspend, |
2121 | .shutdown = mce_syscore_shutdown, | |
2122 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2123 | }; |
2124 | ||
c7cece89 | 2125 | /* |
8a25a2fd | 2126 | * mce_device: Sysfs support |
c7cece89 HS |
2127 | */ |
2128 | ||
52d168e2 AK |
2129 | static void mce_cpu_restart(void *data) |
2130 | { | |
89cbc767 | 2131 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2132 | return; |
5e09954a BP |
2133 | __mcheck_cpu_init_generic(); |
2134 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2135 | } |
2136 | ||
1da177e4 | 2137 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2138 | static void mce_restart(void) |
2139 | { | |
9aaef96f | 2140 | mce_timer_delete_all(); |
52d168e2 | 2141 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2142 | } |
2143 | ||
9af43b54 | 2144 | /* Toggle features for corrected errors */ |
9aaef96f | 2145 | static void mce_disable_cmci(void *data) |
9af43b54 | 2146 | { |
89cbc767 | 2147 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2148 | return; |
9af43b54 HS |
2149 | cmci_clear(); |
2150 | } | |
2151 | ||
2152 | static void mce_enable_ce(void *all) | |
2153 | { | |
89cbc767 | 2154 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2155 | return; |
2156 | cmci_reenable(); | |
2157 | cmci_recheck(); | |
2158 | if (all) | |
5e09954a | 2159 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2160 | } |
2161 | ||
8a25a2fd | 2162 | static struct bus_type mce_subsys = { |
e9eee03e | 2163 | .name = "machinecheck", |
8a25a2fd | 2164 | .dev_name = "machinecheck", |
1da177e4 LT |
2165 | }; |
2166 | ||
d6126ef5 | 2167 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2168 | |
e9eee03e | 2169 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2170 | |
8a25a2fd | 2171 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2172 | { |
2173 | return container_of(attr, struct mce_bank, attr); | |
2174 | } | |
0d7482e3 | 2175 | |
8a25a2fd | 2176 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2177 | char *buf) |
2178 | { | |
cebe1820 | 2179 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2180 | } |
2181 | ||
8a25a2fd | 2182 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2183 | const char *buf, size_t size) |
0d7482e3 | 2184 | { |
9319cec8 | 2185 | u64 new; |
e9eee03e | 2186 | |
164109e3 | 2187 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2188 | return -EINVAL; |
e9eee03e | 2189 | |
cebe1820 | 2190 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2191 | mce_restart(); |
e9eee03e | 2192 | |
9319cec8 | 2193 | return size; |
0d7482e3 | 2194 | } |
a98f0dd3 | 2195 | |
e9eee03e | 2196 | static ssize_t |
8a25a2fd | 2197 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2198 | { |
1020bcbc | 2199 | strcpy(buf, mce_helper); |
a98f0dd3 | 2200 | strcat(buf, "\n"); |
1020bcbc | 2201 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2202 | } |
2203 | ||
8a25a2fd | 2204 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2205 | const char *buf, size_t siz) |
a98f0dd3 AK |
2206 | { |
2207 | char *p; | |
e9eee03e | 2208 | |
1020bcbc HS |
2209 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2210 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2211 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2212 | |
e9084ec9 | 2213 | if (p) |
e9eee03e IM |
2214 | *p = 0; |
2215 | ||
e9084ec9 | 2216 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2217 | } |
2218 | ||
8a25a2fd KS |
2219 | static ssize_t set_ignore_ce(struct device *s, |
2220 | struct device_attribute *attr, | |
9af43b54 HS |
2221 | const char *buf, size_t size) |
2222 | { | |
2223 | u64 new; | |
2224 | ||
164109e3 | 2225 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2226 | return -EINVAL; |
2227 | ||
7af19e4a | 2228 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2229 | if (new) { |
2230 | /* disable ce features */ | |
9aaef96f HS |
2231 | mce_timer_delete_all(); |
2232 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2233 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2234 | } else { |
2235 | /* enable ce features */ | |
7af19e4a | 2236 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2237 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2238 | } | |
2239 | } | |
2240 | return size; | |
2241 | } | |
2242 | ||
8a25a2fd KS |
2243 | static ssize_t set_cmci_disabled(struct device *s, |
2244 | struct device_attribute *attr, | |
9af43b54 HS |
2245 | const char *buf, size_t size) |
2246 | { | |
2247 | u64 new; | |
2248 | ||
164109e3 | 2249 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2250 | return -EINVAL; |
2251 | ||
7af19e4a | 2252 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2253 | if (new) { |
2254 | /* disable cmci */ | |
9aaef96f | 2255 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2256 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2257 | } else { |
2258 | /* enable cmci */ | |
7af19e4a | 2259 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2260 | on_each_cpu(mce_enable_ce, NULL, 1); |
2261 | } | |
2262 | } | |
2263 | return size; | |
2264 | } | |
2265 | ||
8a25a2fd KS |
2266 | static ssize_t store_int_with_restart(struct device *s, |
2267 | struct device_attribute *attr, | |
b56f642d AK |
2268 | const char *buf, size_t size) |
2269 | { | |
8a25a2fd | 2270 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2271 | mce_restart(); |
2272 | return ret; | |
2273 | } | |
2274 | ||
8a25a2fd | 2275 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2276 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2277 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2278 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2279 | |
8a25a2fd KS |
2280 | static struct dev_ext_attribute dev_attr_check_interval = { |
2281 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2282 | &check_interval |
2283 | }; | |
e9eee03e | 2284 | |
8a25a2fd | 2285 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2286 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2287 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2288 | }; |
2289 | ||
8a25a2fd | 2290 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2291 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2292 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2293 | }; |
2294 | ||
8a25a2fd KS |
2295 | static struct device_attribute *mce_device_attrs[] = { |
2296 | &dev_attr_tolerant.attr, | |
2297 | &dev_attr_check_interval.attr, | |
2298 | &dev_attr_trigger, | |
2299 | &dev_attr_monarch_timeout.attr, | |
2300 | &dev_attr_dont_log_ce.attr, | |
2301 | &dev_attr_ignore_ce.attr, | |
2302 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2303 | NULL |
2304 | }; | |
1da177e4 | 2305 | |
8a25a2fd | 2306 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2307 | |
e032d807 GKH |
2308 | static void mce_device_release(struct device *dev) |
2309 | { | |
2310 | kfree(dev); | |
2311 | } | |
2312 | ||
8a25a2fd | 2313 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2314 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2315 | { |
e032d807 | 2316 | struct device *dev; |
1da177e4 | 2317 | int err; |
b1f49f95 | 2318 | int i, j; |
92cb7612 | 2319 | |
90367556 | 2320 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2321 | return -EIO; |
2322 | ||
e032d807 GKH |
2323 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2324 | if (!dev) | |
2325 | return -ENOMEM; | |
8a25a2fd KS |
2326 | dev->id = cpu; |
2327 | dev->bus = &mce_subsys; | |
e032d807 | 2328 | dev->release = &mce_device_release; |
91c6d400 | 2329 | |
8a25a2fd | 2330 | err = device_register(dev); |
853d9b18 LK |
2331 | if (err) { |
2332 | put_device(dev); | |
d435d862 | 2333 | return err; |
853d9b18 | 2334 | } |
d435d862 | 2335 | |
8a25a2fd KS |
2336 | for (i = 0; mce_device_attrs[i]; i++) { |
2337 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2338 | if (err) |
2339 | goto error; | |
2340 | } | |
d203f0b8 | 2341 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2342 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2343 | if (err) |
2344 | goto error2; | |
2345 | } | |
8a25a2fd | 2346 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2347 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2348 | |
d435d862 | 2349 | return 0; |
0d7482e3 | 2350 | error2: |
b1f49f95 | 2351 | while (--j >= 0) |
8a25a2fd | 2352 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2353 | error: |
cb491fca | 2354 | while (--i >= 0) |
8a25a2fd | 2355 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2356 | |
8a25a2fd | 2357 | device_unregister(dev); |
d435d862 | 2358 | |
91c6d400 AK |
2359 | return err; |
2360 | } | |
2361 | ||
148f9bb8 | 2362 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2363 | { |
d6126ef5 | 2364 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2365 | int i; |
2366 | ||
8a25a2fd | 2367 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2368 | return; |
2369 | ||
8a25a2fd KS |
2370 | for (i = 0; mce_device_attrs[i]; i++) |
2371 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2372 | |
d203f0b8 | 2373 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2374 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2375 | |
8a25a2fd KS |
2376 | device_unregister(dev); |
2377 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2378 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2379 | } |
91c6d400 | 2380 | |
d6b75584 | 2381 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2382 | static void mce_disable_cpu(void *h) |
d6b75584 | 2383 | { |
88ccbedd | 2384 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2385 | int i; |
d6b75584 | 2386 | |
89cbc767 | 2387 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2388 | return; |
767df1bd | 2389 | |
88ccbedd AK |
2390 | if (!(action & CPU_TASKS_FROZEN)) |
2391 | cmci_clear(); | |
d203f0b8 | 2392 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2393 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2394 | |
cebe1820 | 2395 | if (b->init) |
a2d32bcb | 2396 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2397 | } |
d6b75584 AK |
2398 | } |
2399 | ||
148f9bb8 | 2400 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2401 | { |
88ccbedd | 2402 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2403 | int i; |
d6b75584 | 2404 | |
89cbc767 | 2405 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2406 | return; |
e9eee03e | 2407 | |
88ccbedd AK |
2408 | if (!(action & CPU_TASKS_FROZEN)) |
2409 | cmci_reenable(); | |
d203f0b8 | 2410 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2411 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2412 | |
cebe1820 | 2413 | if (b->init) |
a2d32bcb | 2414 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2415 | } |
d6b75584 AK |
2416 | } |
2417 | ||
91c6d400 | 2418 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2419 | static int |
e9eee03e | 2420 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2421 | { |
2422 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2423 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2424 | |
1a65f970 | 2425 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2426 | case CPU_ONLINE: |
8a25a2fd | 2427 | mce_device_create(cpu); |
8735728e RW |
2428 | if (threshold_cpu_callback) |
2429 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2430 | break; |
91c6d400 | 2431 | case CPU_DEAD: |
8735728e RW |
2432 | if (threshold_cpu_callback) |
2433 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2434 | mce_device_remove(cpu); |
55babd8f | 2435 | mce_intel_hcpu_update(cpu); |
38356c1f BP |
2436 | |
2437 | /* intentionally ignoring frozen here */ | |
2438 | if (!(action & CPU_TASKS_FROZEN)) | |
2439 | cmci_rediscover(); | |
91c6d400 | 2440 | break; |
52d168e2 | 2441 | case CPU_DOWN_PREPARE: |
88ccbedd | 2442 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2443 | del_timer_sync(t); |
52d168e2 AK |
2444 | break; |
2445 | case CPU_DOWN_FAILED: | |
88ccbedd | 2446 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2447 | mce_start_timer(cpu, t); |
88ccbedd | 2448 | break; |
1a65f970 TG |
2449 | } |
2450 | ||
bae19fe0 | 2451 | return NOTIFY_OK; |
91c6d400 AK |
2452 | } |
2453 | ||
148f9bb8 | 2454 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2455 | .notifier_call = mce_cpu_callback, |
2456 | }; | |
2457 | ||
cebe1820 | 2458 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2459 | { |
2460 | int i; | |
2461 | ||
d203f0b8 | 2462 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2463 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2464 | struct device_attribute *a = &b->attr; |
e9eee03e | 2465 | |
a07e4156 | 2466 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2467 | a->attr.name = b->attrname; |
2468 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2469 | |
2470 | a->attr.mode = 0644; | |
2471 | a->show = show_bank; | |
2472 | a->store = set_bank; | |
0d7482e3 | 2473 | } |
0d7482e3 AK |
2474 | } |
2475 | ||
5e09954a | 2476 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2477 | { |
2478 | int err; | |
2479 | int i = 0; | |
2480 | ||
9c15a24b MS |
2481 | if (!mce_available(&boot_cpu_data)) { |
2482 | err = -EIO; | |
2483 | goto err_out; | |
2484 | } | |
0d7482e3 | 2485 | |
9c15a24b MS |
2486 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2487 | err = -ENOMEM; | |
2488 | goto err_out; | |
2489 | } | |
996867d0 | 2490 | |
cebe1820 | 2491 | mce_init_banks(); |
0d7482e3 | 2492 | |
8a25a2fd | 2493 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2494 | if (err) |
9c15a24b | 2495 | goto err_out_mem; |
91c6d400 | 2496 | |
82a8f131 | 2497 | cpu_notifier_register_begin(); |
91c6d400 | 2498 | for_each_online_cpu(i) { |
8a25a2fd | 2499 | err = mce_device_create(i); |
82a8f131 | 2500 | if (err) { |
27c93415 BP |
2501 | /* |
2502 | * Register notifier anyway (and do not unreg it) so | |
2503 | * that we don't leave undeleted timers, see notifier | |
2504 | * callback above. | |
2505 | */ | |
2506 | __register_hotcpu_notifier(&mce_cpu_notifier); | |
82a8f131 | 2507 | cpu_notifier_register_done(); |
9c15a24b | 2508 | goto err_device_create; |
82a8f131 | 2509 | } |
91c6d400 AK |
2510 | } |
2511 | ||
82a8f131 SB |
2512 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2513 | cpu_notifier_register_done(); | |
93b62c3c | 2514 | |
9c15a24b MS |
2515 | register_syscore_ops(&mce_syscore_ops); |
2516 | ||
93b62c3c | 2517 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2518 | err = misc_register(&mce_chrdev_device); |
2519 | if (err) | |
2520 | goto err_register; | |
2521 | ||
2522 | return 0; | |
2523 | ||
2524 | err_register: | |
2525 | unregister_syscore_ops(&mce_syscore_ops); | |
2526 | ||
9c15a24b MS |
2527 | err_device_create: |
2528 | /* | |
2529 | * We didn't keep track of which devices were created above, but | |
2530 | * even if we had, the set of online cpus might have changed. | |
2531 | * Play safe and remove for every possible cpu, since | |
2532 | * mce_device_remove() will do the right thing. | |
2533 | */ | |
2534 | for_each_possible_cpu(i) | |
2535 | mce_device_remove(i); | |
2536 | ||
2537 | err_out_mem: | |
2538 | free_cpumask_var(mce_device_initialized); | |
2539 | ||
2540 | err_out: | |
2541 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2542 | |
1da177e4 | 2543 | return err; |
1da177e4 | 2544 | } |
cef12ee5 | 2545 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2546 | |
d7c3c9a6 AK |
2547 | /* |
2548 | * Old style boot options parsing. Only for compatibility. | |
2549 | */ | |
2550 | static int __init mcheck_disable(char *str) | |
2551 | { | |
1462594b | 2552 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2553 | return 1; |
2554 | } | |
2555 | __setup("nomce", mcheck_disable); | |
a988d334 | 2556 | |
5be9ed25 HY |
2557 | #ifdef CONFIG_DEBUG_FS |
2558 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2559 | { |
5be9ed25 | 2560 | static struct dentry *dmce; |
a988d334 | 2561 | |
5be9ed25 HY |
2562 | if (!dmce) |
2563 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2564 | |
5be9ed25 HY |
2565 | return dmce; |
2566 | } | |
a988d334 | 2567 | |
bf783f9f HY |
2568 | static void mce_reset(void) |
2569 | { | |
2570 | cpu_missing = 0; | |
2571 | atomic_set(&mce_fake_paniced, 0); | |
2572 | atomic_set(&mce_executing, 0); | |
2573 | atomic_set(&mce_callin, 0); | |
2574 | atomic_set(&global_nwo, 0); | |
2575 | } | |
a988d334 | 2576 | |
bf783f9f HY |
2577 | static int fake_panic_get(void *data, u64 *val) |
2578 | { | |
2579 | *val = fake_panic; | |
2580 | return 0; | |
a988d334 IM |
2581 | } |
2582 | ||
bf783f9f | 2583 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2584 | { |
bf783f9f HY |
2585 | mce_reset(); |
2586 | fake_panic = val; | |
2587 | return 0; | |
a988d334 | 2588 | } |
a988d334 | 2589 | |
bf783f9f HY |
2590 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2591 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2592 | |
5e09954a | 2593 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2594 | { |
bf783f9f HY |
2595 | struct dentry *dmce, *ffake_panic; |
2596 | ||
2597 | dmce = mce_get_debugfs_dir(); | |
2598 | if (!dmce) | |
2599 | return -ENOMEM; | |
2600 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2601 | &fake_panic_fops); | |
2602 | if (!ffake_panic) | |
2603 | return -ENOMEM; | |
2604 | ||
2605 | return 0; | |
d7c3c9a6 | 2606 | } |
5e09954a | 2607 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2608 | #endif |