Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
11122570 | 2 | * (c) 2005-2012 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
8 | * | |
e6d41e8c | 9 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 10 | * |
95268664 JS |
11 | * April 2006 |
12 | * - added support for AMD Family 0x10 processors | |
11122570 BP |
13 | * May 2012 |
14 | * - major scrubbing | |
89b831ef | 15 | * |
95268664 | 16 | * All MC4_MISCi registers are shared between multi-cores |
89b831ef | 17 | */ |
89b831ef | 18 | #include <linux/interrupt.h> |
89b831ef | 19 | #include <linux/notifier.h> |
1cb2a8e1 | 20 | #include <linux/kobject.h> |
34fa1967 | 21 | #include <linux/percpu.h> |
1cb2a8e1 IM |
22 | #include <linux/errno.h> |
23 | #include <linux/sched.h> | |
89b831ef | 24 | #include <linux/sysfs.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
1cb2a8e1 IM |
26 | #include <linux/init.h> |
27 | #include <linux/cpu.h> | |
28 | #include <linux/smp.h> | |
29 | ||
019f34fc | 30 | #include <asm/amd_nb.h> |
89b831ef | 31 | #include <asm/apic.h> |
1cb2a8e1 | 32 | #include <asm/idle.h> |
89b831ef JS |
33 | #include <asm/mce.h> |
34 | #include <asm/msr.h> | |
89b831ef | 35 | |
2903ee85 JS |
36 | #define NR_BLOCKS 9 |
37 | #define THRESHOLD_MAX 0xFFF | |
38 | #define INT_TYPE_APIC 0x00020000 | |
39 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
40 | #define MASK_CNTP_HI 0x40000000 |
41 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
42 | #define MASK_LVTOFF_HI 0x00F00000 |
43 | #define MASK_COUNT_EN_HI 0x00080000 | |
44 | #define MASK_INT_TYPE_HI 0x00060000 | |
45 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 46 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
47 | #define MASK_BLKPTR_LO 0xFF000000 |
48 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 49 | |
336d335a BP |
50 | static const char * const th_names[] = { |
51 | "load_store", | |
52 | "insn_fetch", | |
53 | "combined_unit", | |
54 | "", | |
55 | "northbridge", | |
56 | "execution_unit", | |
57 | }; | |
58 | ||
bafcdd3b | 59 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
89b831ef JS |
60 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
61 | ||
b2762686 AK |
62 | static void amd_threshold_interrupt(void); |
63 | ||
89b831ef JS |
64 | /* |
65 | * CPU Initialization | |
66 | */ | |
67 | ||
4cd4601d | 68 | struct thresh_restart { |
1cb2a8e1 IM |
69 | struct threshold_block *b; |
70 | int reset; | |
9c37c9d8 RR |
71 | int set_lvt_off; |
72 | int lvt_off; | |
1cb2a8e1 | 73 | u16 old_limit; |
4cd4601d MT |
74 | }; |
75 | ||
c76e8164 BO |
76 | static inline bool is_shared_bank(int bank) |
77 | { | |
78 | /* Bank 4 is for northbridge reporting and is thus shared */ | |
79 | return (bank == 4); | |
80 | } | |
81 | ||
2cd4c303 | 82 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
83 | { |
84 | switch (b->address) { | |
85 | /* MSR4_MISC0 */ | |
86 | case 0x00000413: | |
87 | return "dram"; | |
88 | ||
89 | case 0xc0000408: | |
90 | return "ht_links"; | |
91 | ||
92 | case 0xc0000409: | |
93 | return "l3_cache"; | |
94 | ||
95 | default: | |
96 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
97 | return ""; | |
98 | } | |
99 | }; | |
100 | ||
101 | ||
f227d430 BP |
102 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
103 | { | |
104 | /* | |
105 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
106 | */ | |
107 | if (bank == 4) | |
108 | return true; | |
109 | ||
110 | /* | |
111 | * IntP: interrupt present; if this bit is set, the thresholding | |
112 | * bank can generate APIC LVT interrupts | |
113 | */ | |
114 | return msr_high_bits & BIT(28); | |
115 | } | |
116 | ||
bbaff08d RR |
117 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
118 | { | |
119 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
120 | ||
121 | if (apic < 0) { | |
122 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
123 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
124 | b->bank, b->block, b->address, hi, lo); | |
125 | return 0; | |
126 | } | |
127 | ||
128 | if (apic != msr) { | |
129 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " | |
130 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
131 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
132 | return 0; | |
133 | } | |
134 | ||
135 | return 1; | |
136 | }; | |
137 | ||
f227d430 BP |
138 | /* |
139 | * Called via smp_call_function_single(), must be called with correct | |
140 | * cpu affinity. | |
141 | */ | |
a6b6a14e | 142 | static void threshold_restart_bank(void *_tr) |
89b831ef | 143 | { |
4cd4601d | 144 | struct thresh_restart *tr = _tr; |
7203a049 | 145 | u32 hi, lo; |
89b831ef | 146 | |
7203a049 | 147 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 148 | |
7203a049 | 149 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 150 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 151 | |
4cd4601d | 152 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
153 | hi = |
154 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
155 | (THRESHOLD_MAX - tr->b->threshold_limit); |
156 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 157 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 158 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 159 | |
7203a049 | 160 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
161 | (new_count & THRESHOLD_MAX); |
162 | } | |
163 | ||
f227d430 BP |
164 | /* clear IntType */ |
165 | hi &= ~MASK_INT_TYPE_HI; | |
166 | ||
167 | if (!tr->b->interrupt_capable) | |
168 | goto done; | |
169 | ||
9c37c9d8 | 170 | if (tr->set_lvt_off) { |
bbaff08d RR |
171 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
172 | /* set new lvt offset */ | |
173 | hi &= ~MASK_LVTOFF_HI; | |
174 | hi |= tr->lvt_off << 20; | |
175 | } | |
9c37c9d8 RR |
176 | } |
177 | ||
f227d430 BP |
178 | if (tr->b->interrupt_enable) |
179 | hi |= INT_TYPE_APIC; | |
180 | ||
181 | done: | |
89b831ef | 182 | |
7203a049 RR |
183 | hi |= MASK_COUNT_EN_HI; |
184 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
185 | } |
186 | ||
9c37c9d8 RR |
187 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
188 | { | |
189 | struct thresh_restart tr = { | |
190 | .b = b, | |
191 | .set_lvt_off = 1, | |
192 | .lvt_off = offset, | |
193 | }; | |
194 | ||
195 | b->threshold_limit = THRESHOLD_MAX; | |
196 | threshold_restart_bank(&tr); | |
197 | }; | |
198 | ||
bbaff08d RR |
199 | static int setup_APIC_mce(int reserved, int new) |
200 | { | |
201 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
202 | APIC_EILVT_MSG_FIX, 0)) | |
203 | return new; | |
204 | ||
205 | return reserved; | |
206 | } | |
207 | ||
95268664 | 208 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 209 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 210 | { |
9c37c9d8 | 211 | struct threshold_block b; |
89b831ef | 212 | unsigned int cpu = smp_processor_id(); |
95268664 | 213 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 214 | unsigned int bank, block; |
8dcf32ea | 215 | int offset = -1, new; |
89b831ef | 216 | |
bafcdd3b | 217 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
95268664 JS |
218 | for (block = 0; block < NR_BLOCKS; ++block) { |
219 | if (block == 0) | |
4b737d78 | 220 | address = MSR_IA32_MCx_MISC(bank); |
24ce0e96 JB |
221 | else if (block == 1) { |
222 | address = (low & MASK_BLKPTR_LO) >> 21; | |
223 | if (!address) | |
224 | break; | |
6dcbfe4f | 225 | |
24ce0e96 | 226 | address += MCG_XBLK_ADDR; |
1cb2a8e1 | 227 | } else |
95268664 JS |
228 | ++address; |
229 | ||
230 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 231 | break; |
95268664 | 232 | |
6dcbfe4f BP |
233 | if (!(high & MASK_VALID_HI)) |
234 | continue; | |
95268664 | 235 | |
24ce0e96 JB |
236 | if (!(high & MASK_CNTP_HI) || |
237 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
238 | continue; |
239 | ||
240 | if (!block) | |
241 | per_cpu(bank_map, cpu) |= (1 << bank); | |
141168c3 | 242 | |
9c37c9d8 | 243 | memset(&b, 0, sizeof(b)); |
f227d430 BP |
244 | b.cpu = cpu; |
245 | b.bank = bank; | |
246 | b.block = block; | |
247 | b.address = address; | |
248 | b.interrupt_capable = lvt_interrupt_supported(bank, high); | |
249 | ||
8dcf32ea CY |
250 | if (!b.interrupt_capable) |
251 | goto init; | |
b2762686 | 252 | |
d79f931f | 253 | b.interrupt_enable = 1; |
8dcf32ea CY |
254 | new = (high & MASK_LVTOFF_HI) >> 20; |
255 | offset = setup_APIC_mce(offset, new); | |
69b95758 | 256 | |
8dcf32ea CY |
257 | if ((offset == new) && |
258 | (mce_threshold_vector != amd_threshold_interrupt)) | |
69b95758 | 259 | mce_threshold_vector = amd_threshold_interrupt; |
8dcf32ea CY |
260 | |
261 | init: | |
262 | mce_threshold_block_init(&b, offset); | |
95268664 | 263 | } |
89b831ef JS |
264 | } |
265 | } | |
266 | ||
afdf344e AG |
267 | static void __log_error(unsigned int bank, bool threshold_err, u64 misc) |
268 | { | |
269 | struct mce m; | |
270 | u64 status; | |
271 | ||
272 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
273 | if (!(status & MCI_STATUS_VAL)) | |
274 | return; | |
275 | ||
276 | mce_setup(&m); | |
277 | ||
278 | m.status = status; | |
279 | m.bank = bank; | |
6e6e746e | 280 | |
afdf344e AG |
281 | if (threshold_err) |
282 | m.misc = misc; | |
283 | ||
6e6e746e AG |
284 | if (m.status & MCI_STATUS_ADDRV) |
285 | rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr); | |
afdf344e | 286 | |
6e6e746e | 287 | mce_log(&m); |
afdf344e AG |
288 | wrmsrl(MSR_IA32_MCx_STATUS(bank), 0); |
289 | } | |
290 | ||
89b831ef JS |
291 | /* |
292 | * APIC Interrupt Handler | |
293 | */ | |
294 | ||
295 | /* | |
296 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
297 | * the interrupt goes off when error_count reaches threshold_limit. | |
298 | * the handler will simply log mcelog w/ software defined bank number. | |
299 | */ | |
afdf344e | 300 | |
b2762686 | 301 | static void amd_threshold_interrupt(void) |
89b831ef | 302 | { |
1cb2a8e1 | 303 | u32 low = 0, high = 0, address = 0; |
44612a3a | 304 | int cpu = smp_processor_id(); |
95268664 | 305 | unsigned int bank, block; |
89b831ef | 306 | |
89b831ef | 307 | /* assume first bank caused it */ |
bafcdd3b | 308 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 309 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 310 | continue; |
95268664 | 311 | for (block = 0; block < NR_BLOCKS; ++block) { |
1cb2a8e1 | 312 | if (block == 0) { |
4b737d78 | 313 | address = MSR_IA32_MCx_MISC(bank); |
1cb2a8e1 | 314 | } else if (block == 1) { |
24ce0e96 JB |
315 | address = (low & MASK_BLKPTR_LO) >> 21; |
316 | if (!address) | |
317 | break; | |
318 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 319 | } else { |
95268664 | 320 | ++address; |
1cb2a8e1 | 321 | } |
95268664 JS |
322 | |
323 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 324 | break; |
95268664 JS |
325 | |
326 | if (!(high & MASK_VALID_HI)) { | |
327 | if (block) | |
328 | continue; | |
329 | else | |
330 | break; | |
331 | } | |
332 | ||
24ce0e96 JB |
333 | if (!(high & MASK_CNTP_HI) || |
334 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
335 | continue; |
336 | ||
1cb2a8e1 IM |
337 | /* |
338 | * Log the machine check that caused the threshold | |
339 | * event. | |
340 | */ | |
44612a3a CY |
341 | if (high & MASK_OVERFLOW_HI) |
342 | goto log; | |
89b831ef JS |
343 | } |
344 | } | |
44612a3a CY |
345 | return; |
346 | ||
347 | log: | |
afdf344e | 348 | __log_error(bank, true, ((u64)high << 32) | low); |
89b831ef JS |
349 | } |
350 | ||
351 | /* | |
352 | * Sysfs Interface | |
353 | */ | |
354 | ||
89b831ef | 355 | struct threshold_attr { |
2903ee85 | 356 | struct attribute attr; |
1cb2a8e1 IM |
357 | ssize_t (*show) (struct threshold_block *, char *); |
358 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
359 | }; |
360 | ||
1cb2a8e1 IM |
361 | #define SHOW_FIELDS(name) \ |
362 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
363 | { \ | |
18c20f37 | 364 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 365 | } |
89b831ef JS |
366 | SHOW_FIELDS(interrupt_enable) |
367 | SHOW_FIELDS(threshold_limit) | |
368 | ||
1cb2a8e1 | 369 | static ssize_t |
9319cec8 | 370 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 371 | { |
4cd4601d | 372 | struct thresh_restart tr; |
1cb2a8e1 | 373 | unsigned long new; |
1cb2a8e1 | 374 | |
f227d430 BP |
375 | if (!b->interrupt_capable) |
376 | return -EINVAL; | |
377 | ||
164109e3 | 378 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 379 | return -EINVAL; |
1cb2a8e1 | 380 | |
89b831ef JS |
381 | b->interrupt_enable = !!new; |
382 | ||
9c37c9d8 | 383 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 384 | tr.b = b; |
1cb2a8e1 | 385 | |
a6b6a14e | 386 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 387 | |
9319cec8 | 388 | return size; |
89b831ef JS |
389 | } |
390 | ||
1cb2a8e1 | 391 | static ssize_t |
9319cec8 | 392 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 393 | { |
4cd4601d | 394 | struct thresh_restart tr; |
1cb2a8e1 | 395 | unsigned long new; |
1cb2a8e1 | 396 | |
164109e3 | 397 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 398 | return -EINVAL; |
1cb2a8e1 | 399 | |
89b831ef JS |
400 | if (new > THRESHOLD_MAX) |
401 | new = THRESHOLD_MAX; | |
402 | if (new < 1) | |
403 | new = 1; | |
1cb2a8e1 | 404 | |
9c37c9d8 | 405 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 406 | tr.old_limit = b->threshold_limit; |
89b831ef | 407 | b->threshold_limit = new; |
4cd4601d | 408 | tr.b = b; |
89b831ef | 409 | |
a6b6a14e | 410 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 411 | |
9319cec8 | 412 | return size; |
89b831ef JS |
413 | } |
414 | ||
4cd4601d MT |
415 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
416 | { | |
2c9c42fa BP |
417 | u32 lo, hi; |
418 | ||
419 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 420 | |
2c9c42fa BP |
421 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
422 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
423 | } |
424 | ||
6e927361 BP |
425 | static struct threshold_attr error_count = { |
426 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
427 | .show = show_error_count, | |
428 | }; | |
89b831ef | 429 | |
34fa1967 HS |
430 | #define RW_ATTR(val) \ |
431 | static struct threshold_attr val = { \ | |
432 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
433 | .show = show_## val, \ | |
434 | .store = store_## val, \ | |
89b831ef JS |
435 | }; |
436 | ||
2903ee85 JS |
437 | RW_ATTR(interrupt_enable); |
438 | RW_ATTR(threshold_limit); | |
89b831ef JS |
439 | |
440 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
441 | &threshold_limit.attr, |
442 | &error_count.attr, | |
d26ecc48 BP |
443 | NULL, /* possibly interrupt_enable if supported, see below */ |
444 | NULL, | |
89b831ef JS |
445 | }; |
446 | ||
1cb2a8e1 IM |
447 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
448 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
449 | |
450 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
451 | { | |
95268664 | 452 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
453 | struct threshold_attr *a = to_attr(attr); |
454 | ssize_t ret; | |
1cb2a8e1 | 455 | |
89b831ef | 456 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 457 | |
89b831ef JS |
458 | return ret; |
459 | } | |
460 | ||
461 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
462 | const char *buf, size_t count) | |
463 | { | |
95268664 | 464 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
465 | struct threshold_attr *a = to_attr(attr); |
466 | ssize_t ret; | |
1cb2a8e1 | 467 | |
89b831ef | 468 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 469 | |
89b831ef JS |
470 | return ret; |
471 | } | |
472 | ||
52cf25d0 | 473 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
474 | .show = show, |
475 | .store = store, | |
89b831ef JS |
476 | }; |
477 | ||
478 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
479 | .sysfs_ops = &threshold_ops, |
480 | .default_attrs = default_attrs, | |
89b831ef JS |
481 | }; |
482 | ||
148f9bb8 PG |
483 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
484 | unsigned int block, u32 address) | |
95268664 | 485 | { |
95268664 | 486 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
487 | u32 low, high; |
488 | int err; | |
95268664 | 489 | |
bafcdd3b | 490 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
491 | return 0; |
492 | ||
a6b6a14e | 493 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 494 | return 0; |
95268664 JS |
495 | |
496 | if (!(high & MASK_VALID_HI)) { | |
497 | if (block) | |
498 | goto recurse; | |
499 | else | |
500 | return 0; | |
501 | } | |
502 | ||
24ce0e96 JB |
503 | if (!(high & MASK_CNTP_HI) || |
504 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
505 | goto recurse; |
506 | ||
507 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
508 | if (!b) | |
509 | return -ENOMEM; | |
95268664 | 510 | |
1cb2a8e1 IM |
511 | b->block = block; |
512 | b->bank = bank; | |
513 | b->cpu = cpu; | |
514 | b->address = address; | |
515 | b->interrupt_enable = 0; | |
f227d430 | 516 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 517 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 518 | |
d79f931f | 519 | if (b->interrupt_capable) { |
d26ecc48 | 520 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
521 | b->interrupt_enable = 1; |
522 | } else { | |
d26ecc48 | 523 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 524 | } |
d26ecc48 | 525 | |
95268664 JS |
526 | INIT_LIST_HEAD(&b->miscj); |
527 | ||
1cb2a8e1 | 528 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
529 | list_add(&b->miscj, |
530 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 531 | } else { |
95268664 | 532 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 533 | } |
95268664 | 534 | |
542eb75a GKH |
535 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
536 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 537 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
538 | if (err) |
539 | goto out_free; | |
540 | recurse: | |
541 | if (!block) { | |
542 | address = (low & MASK_BLKPTR_LO) >> 21; | |
543 | if (!address) | |
544 | return 0; | |
545 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 546 | } else { |
95268664 | 547 | ++address; |
1cb2a8e1 | 548 | } |
95268664 JS |
549 | |
550 | err = allocate_threshold_blocks(cpu, bank, ++block, address); | |
551 | if (err) | |
552 | goto out_free; | |
553 | ||
213eca7f GK |
554 | if (b) |
555 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 556 | |
95268664 JS |
557 | return err; |
558 | ||
559 | out_free: | |
560 | if (b) { | |
38a382ae | 561 | kobject_put(&b->kobj); |
d9a5ac9e | 562 | list_del(&b->miscj); |
95268664 JS |
563 | kfree(b); |
564 | } | |
565 | return err; | |
566 | } | |
567 | ||
148f9bb8 | 568 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
569 | { |
570 | struct list_head *head = &b->blocks->miscj; | |
571 | struct threshold_block *pos = NULL; | |
572 | struct threshold_block *tmp = NULL; | |
573 | int err = 0; | |
574 | ||
575 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
576 | if (err) | |
577 | return err; | |
578 | ||
579 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
580 | ||
581 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
582 | if (err) { | |
583 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
584 | kobject_del(&pos->kobj); | |
585 | ||
586 | return err; | |
587 | } | |
588 | } | |
589 | return err; | |
590 | } | |
591 | ||
148f9bb8 | 592 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 593 | { |
d6126ef5 | 594 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 595 | struct amd_northbridge *nb = NULL; |
92e26e2a | 596 | struct threshold_bank *b = NULL; |
336d335a | 597 | const char *name = th_names[bank]; |
92e26e2a | 598 | int err = 0; |
95268664 | 599 | |
c76e8164 | 600 | if (is_shared_bank(bank)) { |
019f34fc | 601 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
602 | |
603 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 604 | if (nb && nb->bank4) { |
019f34fc BP |
605 | /* yes, use it */ |
606 | b = nb->bank4; | |
607 | err = kobject_add(b->kobj, &dev->kobj, name); | |
608 | if (err) | |
609 | goto out; | |
610 | ||
611 | per_cpu(threshold_banks, cpu)[bank] = b; | |
612 | atomic_inc(&b->cpus); | |
613 | ||
614 | err = __threshold_add_blocks(b); | |
615 | ||
616 | goto out; | |
617 | } | |
618 | } | |
619 | ||
95268664 | 620 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
621 | if (!b) { |
622 | err = -ENOMEM; | |
623 | goto out; | |
624 | } | |
89b831ef | 625 | |
e032d807 | 626 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
627 | if (!b->kobj) { |
628 | err = -EINVAL; | |
a521cf20 | 629 | goto out_free; |
92e26e2a | 630 | } |
95268664 | 631 | |
89b831ef | 632 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 633 | |
c76e8164 | 634 | if (is_shared_bank(bank)) { |
019f34fc BP |
635 | atomic_set(&b->cpus, 1); |
636 | ||
637 | /* nb is already initialized, see above */ | |
21c5e50e DB |
638 | if (nb) { |
639 | WARN_ON(nb->bank4); | |
640 | nb->bank4 = b; | |
641 | } | |
019f34fc BP |
642 | } |
643 | ||
4b737d78 | 644 | err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); |
92e26e2a BP |
645 | if (!err) |
646 | goto out; | |
95268664 | 647 | |
019f34fc | 648 | out_free: |
95268664 | 649 | kfree(b); |
019f34fc BP |
650 | |
651 | out: | |
89b831ef JS |
652 | return err; |
653 | } | |
654 | ||
655 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 656 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 657 | { |
2903ee85 | 658 | unsigned int bank; |
bafcdd3b | 659 | struct threshold_bank **bp; |
89b831ef JS |
660 | int err = 0; |
661 | ||
bafcdd3b BO |
662 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
663 | GFP_KERNEL); | |
664 | if (!bp) | |
665 | return -ENOMEM; | |
666 | ||
667 | per_cpu(threshold_banks, cpu) = bp; | |
668 | ||
669 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 670 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
671 | continue; |
672 | err = threshold_create_bank(cpu, bank); | |
673 | if (err) | |
0a17941e | 674 | return err; |
89b831ef | 675 | } |
0a17941e | 676 | |
89b831ef JS |
677 | return err; |
678 | } | |
679 | ||
be6b5a35 | 680 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
681 | unsigned int bank) |
682 | { | |
683 | struct threshold_block *pos = NULL; | |
684 | struct threshold_block *tmp = NULL; | |
685 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
686 | ||
687 | if (!head) | |
688 | return; | |
689 | ||
690 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 691 | kobject_put(&pos->kobj); |
95268664 JS |
692 | list_del(&pos->miscj); |
693 | kfree(pos); | |
694 | } | |
695 | ||
696 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
697 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
698 | } | |
699 | ||
019f34fc BP |
700 | static void __threshold_remove_blocks(struct threshold_bank *b) |
701 | { | |
702 | struct threshold_block *pos = NULL; | |
703 | struct threshold_block *tmp = NULL; | |
704 | ||
705 | kobject_del(b->kobj); | |
706 | ||
707 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
708 | kobject_del(&pos->kobj); | |
709 | } | |
710 | ||
be6b5a35 | 711 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 712 | { |
019f34fc | 713 | struct amd_northbridge *nb; |
89b831ef | 714 | struct threshold_bank *b; |
89b831ef JS |
715 | |
716 | b = per_cpu(threshold_banks, cpu)[bank]; | |
717 | if (!b) | |
718 | return; | |
019f34fc | 719 | |
95268664 JS |
720 | if (!b->blocks) |
721 | goto free_out; | |
722 | ||
c76e8164 | 723 | if (is_shared_bank(bank)) { |
019f34fc BP |
724 | if (!atomic_dec_and_test(&b->cpus)) { |
725 | __threshold_remove_blocks(b); | |
726 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
727 | return; | |
728 | } else { | |
729 | /* | |
730 | * the last CPU on this node using the shared bank is | |
731 | * going away, remove that bank now. | |
732 | */ | |
733 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
734 | nb->bank4 = NULL; | |
735 | } | |
736 | } | |
737 | ||
95268664 JS |
738 | deallocate_threshold_block(cpu, bank); |
739 | ||
740 | free_out: | |
8735728e | 741 | kobject_del(b->kobj); |
38a382ae | 742 | kobject_put(b->kobj); |
95268664 JS |
743 | kfree(b); |
744 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
745 | } |
746 | ||
be6b5a35 | 747 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 748 | { |
2903ee85 | 749 | unsigned int bank; |
89b831ef | 750 | |
bafcdd3b | 751 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 752 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
753 | continue; |
754 | threshold_remove_bank(cpu, bank); | |
755 | } | |
bafcdd3b | 756 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
757 | } |
758 | ||
89b831ef | 759 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 760 | static void |
1cb2a8e1 | 761 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 762 | { |
89b831ef JS |
763 | switch (action) { |
764 | case CPU_ONLINE: | |
8bb78442 | 765 | case CPU_ONLINE_FROZEN: |
89b831ef | 766 | threshold_create_device(cpu); |
89b831ef JS |
767 | break; |
768 | case CPU_DEAD: | |
8bb78442 | 769 | case CPU_DEAD_FROZEN: |
89b831ef JS |
770 | threshold_remove_device(cpu); |
771 | break; | |
772 | default: | |
773 | break; | |
774 | } | |
89b831ef JS |
775 | } |
776 | ||
89b831ef JS |
777 | static __init int threshold_init_device(void) |
778 | { | |
2903ee85 | 779 | unsigned lcpu = 0; |
89b831ef | 780 | |
89b831ef JS |
781 | /* to hit CPUs online before the notifier is up */ |
782 | for_each_online_cpu(lcpu) { | |
fff2e89f | 783 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 784 | |
89b831ef | 785 | if (err) |
fff2e89f | 786 | return err; |
89b831ef | 787 | } |
8735728e | 788 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 789 | |
fff2e89f | 790 | return 0; |
89b831ef | 791 | } |
a8fccdb0 LJ |
792 | /* |
793 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
794 | * 1. xen_late_init_mcelog | |
795 | * 2. mcheck_init_device | |
796 | * 3. threshold_init_device | |
797 | * | |
798 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
799 | * native mce_chrdev_device registration if running under xen platform; | |
800 | * | |
801 | * mcheck_init_device should be inited before threshold_init_device to | |
802 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
803 | * | |
804 | * so we use following _initcalls | |
805 | * 1. device_initcall(xen_late_init_mcelog); | |
806 | * 2. device_initcall_sync(mcheck_init_device); | |
807 | * 3. late_initcall(threshold_init_device); | |
808 | * | |
809 | * when running under xen, the initcall order is 1,2,3; | |
810 | * on baremetal, we skip 1 and we do only 2 and 3. | |
811 | */ | |
812 | late_initcall(threshold_init_device); |