Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
3490c0e4 | 2 | * (c) 2005-2015 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | ||
019f34fc | 24 | #include <asm/amd_nb.h> |
89b831ef | 25 | #include <asm/apic.h> |
1cb2a8e1 | 26 | #include <asm/idle.h> |
89b831ef JS |
27 | #include <asm/mce.h> |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
60f116fc | 31 | #define NR_BLOCKS 5 |
2903ee85 JS |
32 | #define THRESHOLD_MAX 0xFFF |
33 | #define INT_TYPE_APIC 0x00020000 | |
34 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
35 | #define MASK_CNTP_HI 0x40000000 |
36 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
37 | #define MASK_LVTOFF_HI 0x00F00000 |
38 | #define MASK_COUNT_EN_HI 0x00080000 | |
39 | #define MASK_INT_TYPE_HI 0x00060000 | |
40 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 41 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
42 | #define MASK_BLKPTR_LO 0xFF000000 |
43 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 44 | |
24fd78a8 AG |
45 | /* Deferred error settings */ |
46 | #define MSR_CU_DEF_ERR 0xC0000410 | |
47 | #define MASK_DEF_LVTOFF 0x000000F0 | |
48 | #define MASK_DEF_INT_TYPE 0x00000006 | |
49 | #define DEF_LVT_OFF 0x2 | |
50 | #define DEF_INT_TYPE_APIC 0x2 | |
51 | ||
f57a1f3c AG |
52 | /* Scalable MCA: */ |
53 | ||
54 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
55 | #define SMCA_THR_LVT_OFF 0xF000 | |
56 | ||
336d335a BP |
57 | static const char * const th_names[] = { |
58 | "load_store", | |
59 | "insn_fetch", | |
60 | "combined_unit", | |
61 | "", | |
62 | "northbridge", | |
63 | "execution_unit", | |
64 | }; | |
65 | ||
bafcdd3b | 66 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
89b831ef JS |
67 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
68 | ||
b2762686 | 69 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
70 | static void amd_deferred_error_interrupt(void); |
71 | ||
72 | static void default_deferred_error_interrupt(void) | |
73 | { | |
74 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
75 | } | |
76 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 77 | |
89b831ef JS |
78 | /* |
79 | * CPU Initialization | |
80 | */ | |
81 | ||
4cd4601d | 82 | struct thresh_restart { |
1cb2a8e1 IM |
83 | struct threshold_block *b; |
84 | int reset; | |
9c37c9d8 RR |
85 | int set_lvt_off; |
86 | int lvt_off; | |
1cb2a8e1 | 87 | u16 old_limit; |
4cd4601d MT |
88 | }; |
89 | ||
c76e8164 BO |
90 | static inline bool is_shared_bank(int bank) |
91 | { | |
284b965c AG |
92 | /* |
93 | * Scalable MCA provides for only one core to have access to the MSRs of | |
94 | * a shared bank. | |
95 | */ | |
96 | if (mce_flags.smca) | |
97 | return false; | |
98 | ||
c76e8164 BO |
99 | /* Bank 4 is for northbridge reporting and is thus shared */ |
100 | return (bank == 4); | |
101 | } | |
102 | ||
2cd4c303 | 103 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
104 | { |
105 | switch (b->address) { | |
106 | /* MSR4_MISC0 */ | |
107 | case 0x00000413: | |
108 | return "dram"; | |
109 | ||
110 | case 0xc0000408: | |
111 | return "ht_links"; | |
112 | ||
113 | case 0xc0000409: | |
114 | return "l3_cache"; | |
115 | ||
116 | default: | |
117 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
118 | return ""; | |
119 | } | |
120 | }; | |
121 | ||
122 | ||
f227d430 BP |
123 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
124 | { | |
125 | /* | |
126 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
127 | */ | |
128 | if (bank == 4) | |
129 | return true; | |
130 | ||
131 | /* | |
132 | * IntP: interrupt present; if this bit is set, the thresholding | |
133 | * bank can generate APIC LVT interrupts | |
134 | */ | |
135 | return msr_high_bits & BIT(28); | |
136 | } | |
137 | ||
bbaff08d RR |
138 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
139 | { | |
140 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
141 | ||
142 | if (apic < 0) { | |
143 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
144 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
145 | b->bank, b->block, b->address, hi, lo); | |
146 | return 0; | |
147 | } | |
148 | ||
149 | if (apic != msr) { | |
f57a1f3c AG |
150 | /* |
151 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
152 | * the BIOS provides the value. The original field where LVT offset | |
153 | * was set is reserved. Return early here: | |
154 | */ | |
155 | if (mce_flags.smca) | |
156 | return 0; | |
157 | ||
bbaff08d RR |
158 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
159 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
160 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
161 | return 0; | |
162 | } | |
163 | ||
164 | return 1; | |
165 | }; | |
166 | ||
f227d430 BP |
167 | /* |
168 | * Called via smp_call_function_single(), must be called with correct | |
169 | * cpu affinity. | |
170 | */ | |
a6b6a14e | 171 | static void threshold_restart_bank(void *_tr) |
89b831ef | 172 | { |
4cd4601d | 173 | struct thresh_restart *tr = _tr; |
7203a049 | 174 | u32 hi, lo; |
89b831ef | 175 | |
7203a049 | 176 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 177 | |
7203a049 | 178 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 179 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 180 | |
4cd4601d | 181 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
182 | hi = |
183 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
184 | (THRESHOLD_MAX - tr->b->threshold_limit); |
185 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 186 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 187 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 188 | |
7203a049 | 189 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
190 | (new_count & THRESHOLD_MAX); |
191 | } | |
192 | ||
f227d430 BP |
193 | /* clear IntType */ |
194 | hi &= ~MASK_INT_TYPE_HI; | |
195 | ||
196 | if (!tr->b->interrupt_capable) | |
197 | goto done; | |
198 | ||
9c37c9d8 | 199 | if (tr->set_lvt_off) { |
bbaff08d RR |
200 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
201 | /* set new lvt offset */ | |
202 | hi &= ~MASK_LVTOFF_HI; | |
203 | hi |= tr->lvt_off << 20; | |
204 | } | |
9c37c9d8 RR |
205 | } |
206 | ||
f227d430 BP |
207 | if (tr->b->interrupt_enable) |
208 | hi |= INT_TYPE_APIC; | |
209 | ||
210 | done: | |
89b831ef | 211 | |
7203a049 RR |
212 | hi |= MASK_COUNT_EN_HI; |
213 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
214 | } |
215 | ||
9c37c9d8 RR |
216 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
217 | { | |
218 | struct thresh_restart tr = { | |
219 | .b = b, | |
220 | .set_lvt_off = 1, | |
221 | .lvt_off = offset, | |
222 | }; | |
223 | ||
224 | b->threshold_limit = THRESHOLD_MAX; | |
225 | threshold_restart_bank(&tr); | |
226 | }; | |
227 | ||
868c00bb | 228 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
229 | { |
230 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
231 | APIC_EILVT_MSG_FIX, 0)) | |
232 | return new; | |
233 | ||
234 | return reserved; | |
235 | } | |
236 | ||
24fd78a8 AG |
237 | static int setup_APIC_deferred_error(int reserved, int new) |
238 | { | |
239 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
240 | APIC_EILVT_MSG_FIX, 0)) | |
241 | return new; | |
242 | ||
243 | return reserved; | |
244 | } | |
245 | ||
246 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
247 | { | |
248 | u32 low = 0, high = 0; | |
249 | int def_offset = -1, def_new; | |
250 | ||
251 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
252 | return; | |
253 | ||
254 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
255 | if (!(low & MASK_DEF_LVTOFF)) { | |
256 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
257 | def_new = DEF_LVT_OFF; | |
258 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
259 | } | |
260 | ||
261 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
262 | if ((def_offset == def_new) && | |
263 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
264 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
265 | ||
266 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
267 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
268 | } | |
269 | ||
95268664 | 270 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 271 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 272 | { |
9c37c9d8 | 273 | struct threshold_block b; |
89b831ef | 274 | unsigned int cpu = smp_processor_id(); |
95268664 | 275 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 276 | unsigned int bank, block; |
8dcf32ea | 277 | int offset = -1, new; |
89b831ef | 278 | |
bafcdd3b | 279 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
95268664 JS |
280 | for (block = 0; block < NR_BLOCKS; ++block) { |
281 | if (block == 0) | |
4b737d78 | 282 | address = MSR_IA32_MCx_MISC(bank); |
24ce0e96 JB |
283 | else if (block == 1) { |
284 | address = (low & MASK_BLKPTR_LO) >> 21; | |
285 | if (!address) | |
286 | break; | |
6dcbfe4f | 287 | |
24ce0e96 | 288 | address += MCG_XBLK_ADDR; |
1cb2a8e1 | 289 | } else |
95268664 JS |
290 | ++address; |
291 | ||
292 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 293 | break; |
95268664 | 294 | |
6dcbfe4f BP |
295 | if (!(high & MASK_VALID_HI)) |
296 | continue; | |
95268664 | 297 | |
24ce0e96 JB |
298 | if (!(high & MASK_CNTP_HI) || |
299 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
300 | continue; |
301 | ||
302 | if (!block) | |
303 | per_cpu(bank_map, cpu) |= (1 << bank); | |
141168c3 | 304 | |
9c37c9d8 | 305 | memset(&b, 0, sizeof(b)); |
f227d430 BP |
306 | b.cpu = cpu; |
307 | b.bank = bank; | |
308 | b.block = block; | |
309 | b.address = address; | |
310 | b.interrupt_capable = lvt_interrupt_supported(bank, high); | |
311 | ||
8dcf32ea CY |
312 | if (!b.interrupt_capable) |
313 | goto init; | |
b2762686 | 314 | |
d79f931f | 315 | b.interrupt_enable = 1; |
f57a1f3c AG |
316 | |
317 | if (mce_flags.smca) { | |
318 | u32 smca_low, smca_high; | |
319 | ||
320 | /* Gather LVT offset for thresholding: */ | |
321 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
322 | break; | |
323 | ||
324 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
325 | } else { | |
326 | new = (high & MASK_LVTOFF_HI) >> 20; | |
327 | } | |
328 | ||
868c00bb | 329 | offset = setup_APIC_mce_threshold(offset, new); |
69b95758 | 330 | |
8dcf32ea CY |
331 | if ((offset == new) && |
332 | (mce_threshold_vector != amd_threshold_interrupt)) | |
69b95758 | 333 | mce_threshold_vector = amd_threshold_interrupt; |
8dcf32ea CY |
334 | |
335 | init: | |
336 | mce_threshold_block_init(&b, offset); | |
95268664 | 337 | } |
89b831ef | 338 | } |
24fd78a8 AG |
339 | |
340 | if (mce_flags.succor) | |
341 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
342 | } |
343 | ||
afdf344e AG |
344 | static void __log_error(unsigned int bank, bool threshold_err, u64 misc) |
345 | { | |
346 | struct mce m; | |
347 | u64 status; | |
348 | ||
349 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
350 | if (!(status & MCI_STATUS_VAL)) | |
351 | return; | |
352 | ||
353 | mce_setup(&m); | |
354 | ||
355 | m.status = status; | |
356 | m.bank = bank; | |
6e6e746e | 357 | |
afdf344e AG |
358 | if (threshold_err) |
359 | m.misc = misc; | |
360 | ||
6e6e746e AG |
361 | if (m.status & MCI_STATUS_ADDRV) |
362 | rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr); | |
afdf344e | 363 | |
6e6e746e | 364 | mce_log(&m); |
afdf344e AG |
365 | wrmsrl(MSR_IA32_MCx_STATUS(bank), 0); |
366 | } | |
367 | ||
24fd78a8 AG |
368 | static inline void __smp_deferred_error_interrupt(void) |
369 | { | |
370 | inc_irq_stat(irq_deferred_error_count); | |
371 | deferred_error_int_vector(); | |
372 | } | |
373 | ||
374 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
375 | { | |
376 | entering_irq(); | |
377 | __smp_deferred_error_interrupt(); | |
378 | exiting_ack_irq(); | |
379 | } | |
380 | ||
381 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
382 | { | |
383 | entering_irq(); | |
384 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
385 | __smp_deferred_error_interrupt(); | |
386 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
387 | exiting_ack_irq(); | |
388 | } | |
389 | ||
390 | /* APIC interrupt handler for deferred errors */ | |
391 | static void amd_deferred_error_interrupt(void) | |
392 | { | |
393 | u64 status; | |
394 | unsigned int bank; | |
395 | ||
396 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
397 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
398 | ||
399 | if (!(status & MCI_STATUS_VAL) || | |
400 | !(status & MCI_STATUS_DEFERRED)) | |
401 | continue; | |
402 | ||
403 | __log_error(bank, false, 0); | |
404 | break; | |
405 | } | |
406 | } | |
407 | ||
89b831ef JS |
408 | /* |
409 | * APIC Interrupt Handler | |
410 | */ | |
411 | ||
412 | /* | |
413 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
414 | * the interrupt goes off when error_count reaches threshold_limit. | |
415 | * the handler will simply log mcelog w/ software defined bank number. | |
416 | */ | |
afdf344e | 417 | |
b2762686 | 418 | static void amd_threshold_interrupt(void) |
89b831ef | 419 | { |
1cb2a8e1 | 420 | u32 low = 0, high = 0, address = 0; |
44612a3a | 421 | int cpu = smp_processor_id(); |
95268664 | 422 | unsigned int bank, block; |
89b831ef | 423 | |
89b831ef | 424 | /* assume first bank caused it */ |
bafcdd3b | 425 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 426 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 427 | continue; |
95268664 | 428 | for (block = 0; block < NR_BLOCKS; ++block) { |
1cb2a8e1 | 429 | if (block == 0) { |
4b737d78 | 430 | address = MSR_IA32_MCx_MISC(bank); |
1cb2a8e1 | 431 | } else if (block == 1) { |
24ce0e96 JB |
432 | address = (low & MASK_BLKPTR_LO) >> 21; |
433 | if (!address) | |
434 | break; | |
435 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 436 | } else { |
95268664 | 437 | ++address; |
1cb2a8e1 | 438 | } |
95268664 JS |
439 | |
440 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 441 | break; |
95268664 JS |
442 | |
443 | if (!(high & MASK_VALID_HI)) { | |
444 | if (block) | |
445 | continue; | |
446 | else | |
447 | break; | |
448 | } | |
449 | ||
24ce0e96 JB |
450 | if (!(high & MASK_CNTP_HI) || |
451 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
452 | continue; |
453 | ||
1cb2a8e1 IM |
454 | /* |
455 | * Log the machine check that caused the threshold | |
456 | * event. | |
457 | */ | |
44612a3a CY |
458 | if (high & MASK_OVERFLOW_HI) |
459 | goto log; | |
89b831ef JS |
460 | } |
461 | } | |
44612a3a CY |
462 | return; |
463 | ||
464 | log: | |
afdf344e | 465 | __log_error(bank, true, ((u64)high << 32) | low); |
89b831ef JS |
466 | } |
467 | ||
468 | /* | |
469 | * Sysfs Interface | |
470 | */ | |
471 | ||
89b831ef | 472 | struct threshold_attr { |
2903ee85 | 473 | struct attribute attr; |
1cb2a8e1 IM |
474 | ssize_t (*show) (struct threshold_block *, char *); |
475 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
476 | }; |
477 | ||
1cb2a8e1 IM |
478 | #define SHOW_FIELDS(name) \ |
479 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
480 | { \ | |
18c20f37 | 481 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 482 | } |
89b831ef JS |
483 | SHOW_FIELDS(interrupt_enable) |
484 | SHOW_FIELDS(threshold_limit) | |
485 | ||
1cb2a8e1 | 486 | static ssize_t |
9319cec8 | 487 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 488 | { |
4cd4601d | 489 | struct thresh_restart tr; |
1cb2a8e1 | 490 | unsigned long new; |
1cb2a8e1 | 491 | |
f227d430 BP |
492 | if (!b->interrupt_capable) |
493 | return -EINVAL; | |
494 | ||
164109e3 | 495 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 496 | return -EINVAL; |
1cb2a8e1 | 497 | |
89b831ef JS |
498 | b->interrupt_enable = !!new; |
499 | ||
9c37c9d8 | 500 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 501 | tr.b = b; |
1cb2a8e1 | 502 | |
a6b6a14e | 503 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 504 | |
9319cec8 | 505 | return size; |
89b831ef JS |
506 | } |
507 | ||
1cb2a8e1 | 508 | static ssize_t |
9319cec8 | 509 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 510 | { |
4cd4601d | 511 | struct thresh_restart tr; |
1cb2a8e1 | 512 | unsigned long new; |
1cb2a8e1 | 513 | |
164109e3 | 514 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 515 | return -EINVAL; |
1cb2a8e1 | 516 | |
89b831ef JS |
517 | if (new > THRESHOLD_MAX) |
518 | new = THRESHOLD_MAX; | |
519 | if (new < 1) | |
520 | new = 1; | |
1cb2a8e1 | 521 | |
9c37c9d8 | 522 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 523 | tr.old_limit = b->threshold_limit; |
89b831ef | 524 | b->threshold_limit = new; |
4cd4601d | 525 | tr.b = b; |
89b831ef | 526 | |
a6b6a14e | 527 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 528 | |
9319cec8 | 529 | return size; |
89b831ef JS |
530 | } |
531 | ||
4cd4601d MT |
532 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
533 | { | |
2c9c42fa BP |
534 | u32 lo, hi; |
535 | ||
536 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 537 | |
2c9c42fa BP |
538 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
539 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
540 | } |
541 | ||
6e927361 BP |
542 | static struct threshold_attr error_count = { |
543 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
544 | .show = show_error_count, | |
545 | }; | |
89b831ef | 546 | |
34fa1967 HS |
547 | #define RW_ATTR(val) \ |
548 | static struct threshold_attr val = { \ | |
549 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
550 | .show = show_## val, \ | |
551 | .store = store_## val, \ | |
89b831ef JS |
552 | }; |
553 | ||
2903ee85 JS |
554 | RW_ATTR(interrupt_enable); |
555 | RW_ATTR(threshold_limit); | |
89b831ef JS |
556 | |
557 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
558 | &threshold_limit.attr, |
559 | &error_count.attr, | |
d26ecc48 BP |
560 | NULL, /* possibly interrupt_enable if supported, see below */ |
561 | NULL, | |
89b831ef JS |
562 | }; |
563 | ||
1cb2a8e1 IM |
564 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
565 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
566 | |
567 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
568 | { | |
95268664 | 569 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
570 | struct threshold_attr *a = to_attr(attr); |
571 | ssize_t ret; | |
1cb2a8e1 | 572 | |
89b831ef | 573 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 574 | |
89b831ef JS |
575 | return ret; |
576 | } | |
577 | ||
578 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
579 | const char *buf, size_t count) | |
580 | { | |
95268664 | 581 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
582 | struct threshold_attr *a = to_attr(attr); |
583 | ssize_t ret; | |
1cb2a8e1 | 584 | |
89b831ef | 585 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 586 | |
89b831ef JS |
587 | return ret; |
588 | } | |
589 | ||
52cf25d0 | 590 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
591 | .show = show, |
592 | .store = store, | |
89b831ef JS |
593 | }; |
594 | ||
595 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
596 | .sysfs_ops = &threshold_ops, |
597 | .default_attrs = default_attrs, | |
89b831ef JS |
598 | }; |
599 | ||
148f9bb8 PG |
600 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
601 | unsigned int block, u32 address) | |
95268664 | 602 | { |
95268664 | 603 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
604 | u32 low, high; |
605 | int err; | |
95268664 | 606 | |
bafcdd3b | 607 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
608 | return 0; |
609 | ||
a6b6a14e | 610 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 611 | return 0; |
95268664 JS |
612 | |
613 | if (!(high & MASK_VALID_HI)) { | |
614 | if (block) | |
615 | goto recurse; | |
616 | else | |
617 | return 0; | |
618 | } | |
619 | ||
24ce0e96 JB |
620 | if (!(high & MASK_CNTP_HI) || |
621 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
622 | goto recurse; |
623 | ||
624 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
625 | if (!b) | |
626 | return -ENOMEM; | |
95268664 | 627 | |
1cb2a8e1 IM |
628 | b->block = block; |
629 | b->bank = bank; | |
630 | b->cpu = cpu; | |
631 | b->address = address; | |
632 | b->interrupt_enable = 0; | |
f227d430 | 633 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 634 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 635 | |
d79f931f | 636 | if (b->interrupt_capable) { |
d26ecc48 | 637 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
638 | b->interrupt_enable = 1; |
639 | } else { | |
d26ecc48 | 640 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 641 | } |
d26ecc48 | 642 | |
95268664 JS |
643 | INIT_LIST_HEAD(&b->miscj); |
644 | ||
1cb2a8e1 | 645 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
646 | list_add(&b->miscj, |
647 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 648 | } else { |
95268664 | 649 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 650 | } |
95268664 | 651 | |
542eb75a GKH |
652 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
653 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 654 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
655 | if (err) |
656 | goto out_free; | |
657 | recurse: | |
658 | if (!block) { | |
659 | address = (low & MASK_BLKPTR_LO) >> 21; | |
660 | if (!address) | |
661 | return 0; | |
662 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 663 | } else { |
95268664 | 664 | ++address; |
1cb2a8e1 | 665 | } |
95268664 JS |
666 | |
667 | err = allocate_threshold_blocks(cpu, bank, ++block, address); | |
668 | if (err) | |
669 | goto out_free; | |
670 | ||
213eca7f GK |
671 | if (b) |
672 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 673 | |
95268664 JS |
674 | return err; |
675 | ||
676 | out_free: | |
677 | if (b) { | |
38a382ae | 678 | kobject_put(&b->kobj); |
d9a5ac9e | 679 | list_del(&b->miscj); |
95268664 JS |
680 | kfree(b); |
681 | } | |
682 | return err; | |
683 | } | |
684 | ||
148f9bb8 | 685 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
686 | { |
687 | struct list_head *head = &b->blocks->miscj; | |
688 | struct threshold_block *pos = NULL; | |
689 | struct threshold_block *tmp = NULL; | |
690 | int err = 0; | |
691 | ||
692 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
693 | if (err) | |
694 | return err; | |
695 | ||
696 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
697 | ||
698 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
699 | if (err) { | |
700 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
701 | kobject_del(&pos->kobj); | |
702 | ||
703 | return err; | |
704 | } | |
705 | } | |
706 | return err; | |
707 | } | |
708 | ||
148f9bb8 | 709 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 710 | { |
d6126ef5 | 711 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 712 | struct amd_northbridge *nb = NULL; |
92e26e2a | 713 | struct threshold_bank *b = NULL; |
336d335a | 714 | const char *name = th_names[bank]; |
92e26e2a | 715 | int err = 0; |
95268664 | 716 | |
c76e8164 | 717 | if (is_shared_bank(bank)) { |
019f34fc | 718 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
719 | |
720 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 721 | if (nb && nb->bank4) { |
019f34fc BP |
722 | /* yes, use it */ |
723 | b = nb->bank4; | |
724 | err = kobject_add(b->kobj, &dev->kobj, name); | |
725 | if (err) | |
726 | goto out; | |
727 | ||
728 | per_cpu(threshold_banks, cpu)[bank] = b; | |
729 | atomic_inc(&b->cpus); | |
730 | ||
731 | err = __threshold_add_blocks(b); | |
732 | ||
733 | goto out; | |
734 | } | |
735 | } | |
736 | ||
95268664 | 737 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
738 | if (!b) { |
739 | err = -ENOMEM; | |
740 | goto out; | |
741 | } | |
89b831ef | 742 | |
e032d807 | 743 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
744 | if (!b->kobj) { |
745 | err = -EINVAL; | |
a521cf20 | 746 | goto out_free; |
92e26e2a | 747 | } |
95268664 | 748 | |
89b831ef | 749 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 750 | |
c76e8164 | 751 | if (is_shared_bank(bank)) { |
019f34fc BP |
752 | atomic_set(&b->cpus, 1); |
753 | ||
754 | /* nb is already initialized, see above */ | |
21c5e50e DB |
755 | if (nb) { |
756 | WARN_ON(nb->bank4); | |
757 | nb->bank4 = b; | |
758 | } | |
019f34fc BP |
759 | } |
760 | ||
4b737d78 | 761 | err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); |
92e26e2a BP |
762 | if (!err) |
763 | goto out; | |
95268664 | 764 | |
019f34fc | 765 | out_free: |
95268664 | 766 | kfree(b); |
019f34fc BP |
767 | |
768 | out: | |
89b831ef JS |
769 | return err; |
770 | } | |
771 | ||
772 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 773 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 774 | { |
2903ee85 | 775 | unsigned int bank; |
bafcdd3b | 776 | struct threshold_bank **bp; |
89b831ef JS |
777 | int err = 0; |
778 | ||
bafcdd3b BO |
779 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
780 | GFP_KERNEL); | |
781 | if (!bp) | |
782 | return -ENOMEM; | |
783 | ||
784 | per_cpu(threshold_banks, cpu) = bp; | |
785 | ||
786 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 787 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
788 | continue; |
789 | err = threshold_create_bank(cpu, bank); | |
790 | if (err) | |
0a17941e | 791 | return err; |
89b831ef | 792 | } |
0a17941e | 793 | |
89b831ef JS |
794 | return err; |
795 | } | |
796 | ||
be6b5a35 | 797 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
798 | unsigned int bank) |
799 | { | |
800 | struct threshold_block *pos = NULL; | |
801 | struct threshold_block *tmp = NULL; | |
802 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
803 | ||
804 | if (!head) | |
805 | return; | |
806 | ||
807 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 808 | kobject_put(&pos->kobj); |
95268664 JS |
809 | list_del(&pos->miscj); |
810 | kfree(pos); | |
811 | } | |
812 | ||
813 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
814 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
815 | } | |
816 | ||
019f34fc BP |
817 | static void __threshold_remove_blocks(struct threshold_bank *b) |
818 | { | |
819 | struct threshold_block *pos = NULL; | |
820 | struct threshold_block *tmp = NULL; | |
821 | ||
822 | kobject_del(b->kobj); | |
823 | ||
824 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
825 | kobject_del(&pos->kobj); | |
826 | } | |
827 | ||
be6b5a35 | 828 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 829 | { |
019f34fc | 830 | struct amd_northbridge *nb; |
89b831ef | 831 | struct threshold_bank *b; |
89b831ef JS |
832 | |
833 | b = per_cpu(threshold_banks, cpu)[bank]; | |
834 | if (!b) | |
835 | return; | |
019f34fc | 836 | |
95268664 JS |
837 | if (!b->blocks) |
838 | goto free_out; | |
839 | ||
c76e8164 | 840 | if (is_shared_bank(bank)) { |
019f34fc BP |
841 | if (!atomic_dec_and_test(&b->cpus)) { |
842 | __threshold_remove_blocks(b); | |
843 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
844 | return; | |
845 | } else { | |
846 | /* | |
847 | * the last CPU on this node using the shared bank is | |
848 | * going away, remove that bank now. | |
849 | */ | |
850 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
851 | nb->bank4 = NULL; | |
852 | } | |
853 | } | |
854 | ||
95268664 JS |
855 | deallocate_threshold_block(cpu, bank); |
856 | ||
857 | free_out: | |
8735728e | 858 | kobject_del(b->kobj); |
38a382ae | 859 | kobject_put(b->kobj); |
95268664 JS |
860 | kfree(b); |
861 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
862 | } |
863 | ||
be6b5a35 | 864 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 865 | { |
2903ee85 | 866 | unsigned int bank; |
89b831ef | 867 | |
bafcdd3b | 868 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 869 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
870 | continue; |
871 | threshold_remove_bank(cpu, bank); | |
872 | } | |
bafcdd3b | 873 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
874 | } |
875 | ||
89b831ef | 876 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 877 | static void |
1cb2a8e1 | 878 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 879 | { |
89b831ef JS |
880 | switch (action) { |
881 | case CPU_ONLINE: | |
8bb78442 | 882 | case CPU_ONLINE_FROZEN: |
89b831ef | 883 | threshold_create_device(cpu); |
89b831ef JS |
884 | break; |
885 | case CPU_DEAD: | |
8bb78442 | 886 | case CPU_DEAD_FROZEN: |
89b831ef JS |
887 | threshold_remove_device(cpu); |
888 | break; | |
889 | default: | |
890 | break; | |
891 | } | |
89b831ef JS |
892 | } |
893 | ||
89b831ef JS |
894 | static __init int threshold_init_device(void) |
895 | { | |
2903ee85 | 896 | unsigned lcpu = 0; |
89b831ef | 897 | |
89b831ef JS |
898 | /* to hit CPUs online before the notifier is up */ |
899 | for_each_online_cpu(lcpu) { | |
fff2e89f | 900 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 901 | |
89b831ef | 902 | if (err) |
fff2e89f | 903 | return err; |
89b831ef | 904 | } |
8735728e | 905 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 906 | |
fff2e89f | 907 | return 0; |
89b831ef | 908 | } |
a8fccdb0 LJ |
909 | /* |
910 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
911 | * 1. xen_late_init_mcelog | |
912 | * 2. mcheck_init_device | |
913 | * 3. threshold_init_device | |
914 | * | |
915 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
916 | * native mce_chrdev_device registration if running under xen platform; | |
917 | * | |
918 | * mcheck_init_device should be inited before threshold_init_device to | |
919 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
920 | * | |
921 | * so we use following _initcalls | |
922 | * 1. device_initcall(xen_late_init_mcelog); | |
923 | * 2. device_initcall_sync(mcheck_init_device); | |
924 | * 3. late_initcall(threshold_init_device); | |
925 | * | |
926 | * when running under xen, the initcall order is 1,2,3; | |
927 | * on baremetal, we skip 1 and we do only 2 and 3. | |
928 | */ | |
929 | late_initcall(threshold_init_device); |