Commit | Line | Data |
---|---|---|
15d5f839 | 1 | /* |
3222b36f DZ |
2 | * Thermal throttle event support code (such as syslog messaging and rate |
3 | * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). | |
cb6f3c15 | 4 | * |
3222b36f DZ |
5 | * This allows consistent reporting of CPU thermal throttle events. |
6 | * | |
7 | * Maintains a counter in /sys that keeps track of the number of thermal | |
8 | * events, such that the user knows how bad the thermal problem might be | |
9 | * (since the logging to syslog and mcelog is rate limited). | |
15d5f839 DZ |
10 | * |
11 | * Author: Dmitriy Zavin (dmitriyz@google.com) | |
12 | * | |
13 | * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. | |
3222b36f | 14 | * Inspired by Ross Biro's and Al Borchers' counter code. |
15d5f839 | 15 | */ |
a65c88dd | 16 | #include <linux/interrupt.h> |
cb6f3c15 IM |
17 | #include <linux/notifier.h> |
18 | #include <linux/jiffies.h> | |
895287c0 | 19 | #include <linux/kernel.h> |
15d5f839 | 20 | #include <linux/percpu.h> |
69c60c88 | 21 | #include <linux/export.h> |
895287c0 HS |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/smp.h> | |
15d5f839 | 25 | #include <linux/cpu.h> |
cb6f3c15 | 26 | |
895287c0 | 27 | #include <asm/processor.h> |
895287c0 | 28 | #include <asm/apic.h> |
a65c88dd HS |
29 | #include <asm/idle.h> |
30 | #include <asm/mce.h> | |
895287c0 | 31 | #include <asm/msr.h> |
cf910e83 | 32 | #include <asm/trace/irq_vectors.h> |
15d5f839 DZ |
33 | |
34 | /* How long to wait between reporting thermal events */ | |
cb6f3c15 | 35 | #define CHECK_INTERVAL (300 * HZ) |
15d5f839 | 36 | |
0199114c FY |
37 | #define THERMAL_THROTTLING_EVENT 0 |
38 | #define POWER_LIMIT_EVENT 1 | |
39 | ||
39676840 | 40 | /* |
0199114c | 41 | * Current thermal event state: |
39676840 | 42 | */ |
55d435a2 | 43 | struct _thermal_state { |
0199114c FY |
44 | bool new_event; |
45 | int event; | |
39676840 | 46 | u64 next_check; |
0199114c FY |
47 | unsigned long count; |
48 | unsigned long last_count; | |
39676840 | 49 | }; |
cb6f3c15 | 50 | |
55d435a2 | 51 | struct thermal_state { |
0199114c FY |
52 | struct _thermal_state core_throttle; |
53 | struct _thermal_state core_power_limit; | |
54 | struct _thermal_state package_throttle; | |
55 | struct _thermal_state package_power_limit; | |
9e76a97e D |
56 | struct _thermal_state core_thresh0; |
57 | struct _thermal_state core_thresh1; | |
25cdce17 SP |
58 | struct _thermal_state pkg_thresh0; |
59 | struct _thermal_state pkg_thresh1; | |
55d435a2 FY |
60 | }; |
61 | ||
9e76a97e D |
62 | /* Callback to handle core threshold interrupts */ |
63 | int (*platform_thermal_notify)(__u64 msr_val); | |
f21bbec9 | 64 | EXPORT_SYMBOL(platform_thermal_notify); |
9e76a97e | 65 | |
25cdce17 SP |
66 | /* Callback to handle core package threshold_interrupts */ |
67 | int (*platform_thermal_package_notify)(__u64 msr_val); | |
68 | EXPORT_SYMBOL_GPL(platform_thermal_package_notify); | |
69 | ||
70 | /* Callback support of rate control, return true, if | |
71 | * callback has rate control */ | |
72 | bool (*platform_thermal_package_rate_control)(void); | |
73 | EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control); | |
74 | ||
75 | ||
39676840 IM |
76 | static DEFINE_PER_CPU(struct thermal_state, thermal_state); |
77 | ||
78 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | |
3222b36f | 79 | |
a2202aa2 YW |
80 | static u32 lvtthmr_init __read_mostly; |
81 | ||
3222b36f | 82 | #ifdef CONFIG_SYSFS |
8a25a2fd KS |
83 | #define define_therm_throt_device_one_ro(_name) \ |
84 | static DEVICE_ATTR(_name, 0444, \ | |
85 | therm_throt_device_show_##_name, \ | |
55d435a2 | 86 | NULL) \ |
cb6f3c15 | 87 | |
8a25a2fd | 88 | #define define_therm_throt_device_show_func(event, name) \ |
39676840 | 89 | \ |
8a25a2fd KS |
90 | static ssize_t therm_throt_device_show_##event##_##name( \ |
91 | struct device *dev, \ | |
92 | struct device_attribute *attr, \ | |
39676840 | 93 | char *buf) \ |
cb6f3c15 IM |
94 | { \ |
95 | unsigned int cpu = dev->id; \ | |
96 | ssize_t ret; \ | |
97 | \ | |
98 | preempt_disable(); /* CPU hotplug */ \ | |
55d435a2 | 99 | if (cpu_online(cpu)) { \ |
cb6f3c15 | 100 | ret = sprintf(buf, "%lu\n", \ |
0199114c | 101 | per_cpu(thermal_state, cpu).event.name); \ |
55d435a2 | 102 | } else \ |
cb6f3c15 IM |
103 | ret = 0; \ |
104 | preempt_enable(); \ | |
105 | \ | |
106 | return ret; \ | |
3222b36f DZ |
107 | } |
108 | ||
8a25a2fd KS |
109 | define_therm_throt_device_show_func(core_throttle, count); |
110 | define_therm_throt_device_one_ro(core_throttle_count); | |
55d435a2 | 111 | |
8a25a2fd KS |
112 | define_therm_throt_device_show_func(core_power_limit, count); |
113 | define_therm_throt_device_one_ro(core_power_limit_count); | |
0199114c | 114 | |
8a25a2fd KS |
115 | define_therm_throt_device_show_func(package_throttle, count); |
116 | define_therm_throt_device_one_ro(package_throttle_count); | |
3222b36f | 117 | |
8a25a2fd KS |
118 | define_therm_throt_device_show_func(package_power_limit, count); |
119 | define_therm_throt_device_one_ro(package_power_limit_count); | |
0199114c | 120 | |
3222b36f | 121 | static struct attribute *thermal_throttle_attrs[] = { |
8a25a2fd | 122 | &dev_attr_core_throttle_count.attr, |
3222b36f DZ |
123 | NULL |
124 | }; | |
125 | ||
0199114c | 126 | static struct attribute_group thermal_attr_group = { |
cb6f3c15 IM |
127 | .attrs = thermal_throttle_attrs, |
128 | .name = "thermal_throttle" | |
3222b36f DZ |
129 | }; |
130 | #endif /* CONFIG_SYSFS */ | |
15d5f839 | 131 | |
0199114c FY |
132 | #define CORE_LEVEL 0 |
133 | #define PACKAGE_LEVEL 1 | |
134 | ||
15d5f839 | 135 | /*** |
3222b36f | 136 | * therm_throt_process - Process thermal throttling event from interrupt |
15d5f839 DZ |
137 | * @curr: Whether the condition is current or not (boolean), since the |
138 | * thermal interrupt normally gets called both when the thermal | |
139 | * event begins and once the event has ended. | |
140 | * | |
3222b36f | 141 | * This function is called by the thermal interrupt after the |
15d5f839 DZ |
142 | * IRQ has been acknowledged. |
143 | * | |
144 | * It will take care of rate limiting and printing messages to the syslog. | |
145 | * | |
146 | * Returns: 0 : Event should NOT be further logged, i.e. still in | |
147 | * "timeout" from previous log message. | |
148 | * 1 : Event should be logged further, and a message has been | |
149 | * printed to the syslog. | |
150 | */ | |
0199114c | 151 | static int therm_throt_process(bool new_event, int event, int level) |
15d5f839 | 152 | { |
55d435a2 | 153 | struct _thermal_state *state; |
0199114c FY |
154 | unsigned int this_cpu = smp_processor_id(); |
155 | bool old_event; | |
39676840 | 156 | u64 now; |
0199114c | 157 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); |
39676840 | 158 | |
39676840 | 159 | now = get_jiffies_64(); |
0199114c FY |
160 | if (level == CORE_LEVEL) { |
161 | if (event == THERMAL_THROTTLING_EVENT) | |
162 | state = &pstate->core_throttle; | |
163 | else if (event == POWER_LIMIT_EVENT) | |
164 | state = &pstate->core_power_limit; | |
165 | else | |
166 | return 0; | |
167 | } else if (level == PACKAGE_LEVEL) { | |
168 | if (event == THERMAL_THROTTLING_EVENT) | |
169 | state = &pstate->package_throttle; | |
170 | else if (event == POWER_LIMIT_EVENT) | |
171 | state = &pstate->package_power_limit; | |
172 | else | |
173 | return 0; | |
174 | } else | |
175 | return 0; | |
39676840 | 176 | |
0199114c FY |
177 | old_event = state->new_event; |
178 | state->new_event = new_event; | |
15d5f839 | 179 | |
0199114c FY |
180 | if (new_event) |
181 | state->count++; | |
3222b36f | 182 | |
b417c9fd | 183 | if (time_before64(now, state->next_check) && |
0199114c | 184 | state->count != state->last_count) |
15d5f839 DZ |
185 | return 0; |
186 | ||
39676840 | 187 | state->next_check = now + CHECK_INTERVAL; |
0199114c | 188 | state->last_count = state->count; |
15d5f839 DZ |
189 | |
190 | /* if we just entered the thermal event */ | |
0199114c FY |
191 | if (new_event) { |
192 | if (event == THERMAL_THROTTLING_EVENT) | |
193 | printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n", | |
194 | this_cpu, | |
195 | level == CORE_LEVEL ? "Core" : "Package", | |
196 | state->count); | |
4e5c25d4 HD |
197 | return 1; |
198 | } | |
0199114c FY |
199 | if (old_event) { |
200 | if (event == THERMAL_THROTTLING_EVENT) | |
201 | printk(KERN_INFO "CPU%d: %s temperature/speed normal\n", | |
202 | this_cpu, | |
203 | level == CORE_LEVEL ? "Core" : "Package"); | |
4e5c25d4 | 204 | return 1; |
15d5f839 DZ |
205 | } |
206 | ||
4e5c25d4 | 207 | return 0; |
15d5f839 | 208 | } |
3222b36f | 209 | |
25cdce17 | 210 | static int thresh_event_valid(int level, int event) |
9e76a97e D |
211 | { |
212 | struct _thermal_state *state; | |
213 | unsigned int this_cpu = smp_processor_id(); | |
214 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); | |
215 | u64 now = get_jiffies_64(); | |
216 | ||
25cdce17 SP |
217 | if (level == PACKAGE_LEVEL) |
218 | state = (event == 0) ? &pstate->pkg_thresh0 : | |
219 | &pstate->pkg_thresh1; | |
220 | else | |
221 | state = (event == 0) ? &pstate->core_thresh0 : | |
222 | &pstate->core_thresh1; | |
9e76a97e D |
223 | |
224 | if (time_before64(now, state->next_check)) | |
225 | return 0; | |
226 | ||
227 | state->next_check = now + CHECK_INTERVAL; | |
25cdce17 | 228 | |
9e76a97e D |
229 | return 1; |
230 | } | |
231 | ||
6bb2ff84 FY |
232 | static bool int_pln_enable; |
233 | static int __init int_pln_enable_setup(char *s) | |
234 | { | |
235 | int_pln_enable = true; | |
236 | ||
237 | return 1; | |
238 | } | |
239 | __setup("int_pln_enable", int_pln_enable_setup); | |
240 | ||
3222b36f | 241 | #ifdef CONFIG_SYSFS |
cb6f3c15 | 242 | /* Add/Remove thermal_throttle interface for CPU device: */ |
8a25a2fd | 243 | static __cpuinit int thermal_throttle_add_dev(struct device *dev, |
51e3c1b5 | 244 | unsigned int cpu) |
3222b36f | 245 | { |
55d435a2 | 246 | int err; |
51e3c1b5 | 247 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
55d435a2 | 248 | |
8a25a2fd | 249 | err = sysfs_create_group(&dev->kobj, &thermal_attr_group); |
55d435a2 FY |
250 | if (err) |
251 | return err; | |
252 | ||
6bb2ff84 | 253 | if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) |
8a25a2fd KS |
254 | err = sysfs_add_file_to_group(&dev->kobj, |
255 | &dev_attr_core_power_limit_count.attr, | |
0199114c | 256 | thermal_attr_group.name); |
b62be8ea | 257 | if (cpu_has(c, X86_FEATURE_PTS)) { |
8a25a2fd KS |
258 | err = sysfs_add_file_to_group(&dev->kobj, |
259 | &dev_attr_package_throttle_count.attr, | |
0199114c | 260 | thermal_attr_group.name); |
6bb2ff84 | 261 | if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) |
8a25a2fd KS |
262 | err = sysfs_add_file_to_group(&dev->kobj, |
263 | &dev_attr_package_power_limit_count.attr, | |
0199114c | 264 | thermal_attr_group.name); |
b62be8ea | 265 | } |
55d435a2 FY |
266 | |
267 | return err; | |
3222b36f DZ |
268 | } |
269 | ||
8a25a2fd | 270 | static __cpuinit void thermal_throttle_remove_dev(struct device *dev) |
3222b36f | 271 | { |
8a25a2fd | 272 | sysfs_remove_group(&dev->kobj, &thermal_attr_group); |
3222b36f DZ |
273 | } |
274 | ||
cb6f3c15 | 275 | /* Mutex protecting device creation against CPU hotplug: */ |
3222b36f DZ |
276 | static DEFINE_MUTEX(therm_cpu_lock); |
277 | ||
278 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ | |
cb6f3c15 IM |
279 | static __cpuinit int |
280 | thermal_throttle_cpu_callback(struct notifier_block *nfb, | |
281 | unsigned long action, | |
282 | void *hcpu) | |
3222b36f DZ |
283 | { |
284 | unsigned int cpu = (unsigned long)hcpu; | |
8a25a2fd | 285 | struct device *dev; |
c7e38a9c | 286 | int err = 0; |
3222b36f | 287 | |
8a25a2fd | 288 | dev = get_cpu_device(cpu); |
cb6f3c15 | 289 | |
3222b36f | 290 | switch (action) { |
c7e38a9c AM |
291 | case CPU_UP_PREPARE: |
292 | case CPU_UP_PREPARE_FROZEN: | |
38ef6d19 | 293 | mutex_lock(&therm_cpu_lock); |
8a25a2fd | 294 | err = thermal_throttle_add_dev(dev, cpu); |
38ef6d19 | 295 | mutex_unlock(&therm_cpu_lock); |
6569345a | 296 | WARN_ON(err); |
3222b36f | 297 | break; |
c7e38a9c AM |
298 | case CPU_UP_CANCELED: |
299 | case CPU_UP_CANCELED_FROZEN: | |
3222b36f | 300 | case CPU_DEAD: |
8bb78442 | 301 | case CPU_DEAD_FROZEN: |
38ef6d19 | 302 | mutex_lock(&therm_cpu_lock); |
8a25a2fd | 303 | thermal_throttle_remove_dev(dev); |
38ef6d19 | 304 | mutex_unlock(&therm_cpu_lock); |
3222b36f DZ |
305 | break; |
306 | } | |
a94247e7 | 307 | return notifier_from_errno(err); |
3222b36f DZ |
308 | } |
309 | ||
25d1b516 | 310 | static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata = |
3222b36f DZ |
311 | { |
312 | .notifier_call = thermal_throttle_cpu_callback, | |
313 | }; | |
3222b36f DZ |
314 | |
315 | static __init int thermal_throttle_init_device(void) | |
316 | { | |
317 | unsigned int cpu = 0; | |
6569345a | 318 | int err; |
3222b36f DZ |
319 | |
320 | if (!atomic_read(&therm_throt_en)) | |
321 | return 0; | |
322 | ||
323 | register_hotcpu_notifier(&thermal_throttle_cpu_notifier); | |
324 | ||
325 | #ifdef CONFIG_HOTPLUG_CPU | |
326 | mutex_lock(&therm_cpu_lock); | |
327 | #endif | |
328 | /* connect live CPUs to sysfs */ | |
6569345a | 329 | for_each_online_cpu(cpu) { |
8a25a2fd | 330 | err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu); |
6569345a SH |
331 | WARN_ON(err); |
332 | } | |
3222b36f DZ |
333 | #ifdef CONFIG_HOTPLUG_CPU |
334 | mutex_unlock(&therm_cpu_lock); | |
335 | #endif | |
336 | ||
337 | return 0; | |
338 | } | |
3222b36f | 339 | device_initcall(thermal_throttle_init_device); |
a65c88dd | 340 | |
3222b36f | 341 | #endif /* CONFIG_SYSFS */ |
a65c88dd | 342 | |
25cdce17 SP |
343 | static void notify_package_thresholds(__u64 msr_val) |
344 | { | |
345 | bool notify_thres_0 = false; | |
346 | bool notify_thres_1 = false; | |
347 | ||
348 | if (!platform_thermal_package_notify) | |
349 | return; | |
350 | ||
351 | /* lower threshold check */ | |
352 | if (msr_val & THERM_LOG_THRESHOLD0) | |
353 | notify_thres_0 = true; | |
354 | /* higher threshold check */ | |
355 | if (msr_val & THERM_LOG_THRESHOLD1) | |
356 | notify_thres_1 = true; | |
357 | ||
358 | if (!notify_thres_0 && !notify_thres_1) | |
359 | return; | |
360 | ||
361 | if (platform_thermal_package_rate_control && | |
362 | platform_thermal_package_rate_control()) { | |
363 | /* Rate control is implemented in callback */ | |
364 | platform_thermal_package_notify(msr_val); | |
365 | return; | |
366 | } | |
367 | ||
368 | /* lower threshold reached */ | |
369 | if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0)) | |
370 | platform_thermal_package_notify(msr_val); | |
371 | /* higher threshold reached */ | |
372 | if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1)) | |
373 | platform_thermal_package_notify(msr_val); | |
374 | } | |
375 | ||
9e76a97e D |
376 | static void notify_thresholds(__u64 msr_val) |
377 | { | |
378 | /* check whether the interrupt handler is defined; | |
379 | * otherwise simply return | |
380 | */ | |
381 | if (!platform_thermal_notify) | |
382 | return; | |
383 | ||
384 | /* lower threshold reached */ | |
25cdce17 SP |
385 | if ((msr_val & THERM_LOG_THRESHOLD0) && |
386 | thresh_event_valid(CORE_LEVEL, 0)) | |
9e76a97e D |
387 | platform_thermal_notify(msr_val); |
388 | /* higher threshold reached */ | |
25cdce17 SP |
389 | if ((msr_val & THERM_LOG_THRESHOLD1) && |
390 | thresh_event_valid(CORE_LEVEL, 1)) | |
9e76a97e D |
391 | platform_thermal_notify(msr_val); |
392 | } | |
393 | ||
a65c88dd | 394 | /* Thermal transition interrupt handler */ |
8363fc82 | 395 | static void intel_thermal_interrupt(void) |
a65c88dd HS |
396 | { |
397 | __u64 msr_val; | |
398 | ||
399 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | |
0199114c | 400 | |
9e76a97e D |
401 | /* Check for violation of core thermal thresholds*/ |
402 | notify_thresholds(msr_val); | |
403 | ||
55d435a2 | 404 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT, |
0199114c | 405 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 406 | CORE_LEVEL) != 0) |
29e9bf18 | 407 | mce_log_therm_throt_event(msr_val); |
0199114c | 408 | |
6bb2ff84 | 409 | if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) |
29e9bf18 | 410 | therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, |
0199114c | 411 | POWER_LIMIT_EVENT, |
29e9bf18 | 412 | CORE_LEVEL); |
55d435a2 | 413 | |
fe504213 | 414 | if (this_cpu_has(X86_FEATURE_PTS)) { |
55d435a2 | 415 | rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); |
25cdce17 SP |
416 | /* check violations of package thermal thresholds */ |
417 | notify_package_thresholds(msr_val); | |
29e9bf18 | 418 | therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, |
0199114c | 419 | THERMAL_THROTTLING_EVENT, |
29e9bf18 | 420 | PACKAGE_LEVEL); |
6bb2ff84 | 421 | if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) |
29e9bf18 | 422 | therm_throt_process(msr_val & |
0199114c FY |
423 | PACKAGE_THERM_STATUS_POWER_LIMIT, |
424 | POWER_LIMIT_EVENT, | |
29e9bf18 | 425 | PACKAGE_LEVEL); |
55d435a2 | 426 | } |
a65c88dd HS |
427 | } |
428 | ||
429 | static void unexpected_thermal_interrupt(void) | |
430 | { | |
592091c0 | 431 | printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n", |
a65c88dd | 432 | smp_processor_id()); |
a65c88dd HS |
433 | } |
434 | ||
435 | static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; | |
436 | ||
eddc0e92 | 437 | static inline void __smp_thermal_interrupt(void) |
a65c88dd | 438 | { |
a65c88dd HS |
439 | inc_irq_stat(irq_thermal_count); |
440 | smp_thermal_vector(); | |
eddc0e92 SA |
441 | } |
442 | ||
443 | asmlinkage void smp_thermal_interrupt(struct pt_regs *regs) | |
444 | { | |
445 | entering_irq(); | |
446 | __smp_thermal_interrupt(); | |
447 | exiting_ack_irq(); | |
a65c88dd HS |
448 | } |
449 | ||
cf910e83 SA |
450 | asmlinkage void smp_trace_thermal_interrupt(struct pt_regs *regs) |
451 | { | |
452 | entering_irq(); | |
453 | trace_thermal_apic_entry(THERMAL_APIC_VECTOR); | |
454 | __smp_thermal_interrupt(); | |
455 | trace_thermal_apic_exit(THERMAL_APIC_VECTOR); | |
456 | exiting_ack_irq(); | |
457 | } | |
458 | ||
70fe4407 HS |
459 | /* Thermal monitoring depends on APIC, ACPI and clock modulation */ |
460 | static int intel_thermal_supported(struct cpuinfo_x86 *c) | |
461 | { | |
462 | if (!cpu_has_apic) | |
463 | return 0; | |
464 | if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) | |
465 | return 0; | |
466 | return 1; | |
467 | } | |
468 | ||
ce6b5d76 | 469 | void __init mcheck_intel_therm_init(void) |
a2202aa2 YW |
470 | { |
471 | /* | |
472 | * This function is only called on boot CPU. Save the init thermal | |
473 | * LVT value on BSP and use that value to restore APs' thermal LVT | |
474 | * entry BIOS programmed later | |
475 | */ | |
70fe4407 | 476 | if (intel_thermal_supported(&boot_cpu_data)) |
a2202aa2 YW |
477 | lvtthmr_init = apic_read(APIC_LVTTHMR); |
478 | } | |
479 | ||
cffd377e | 480 | void intel_init_thermal(struct cpuinfo_x86 *c) |
895287c0 HS |
481 | { |
482 | unsigned int cpu = smp_processor_id(); | |
483 | int tm2 = 0; | |
484 | u32 l, h; | |
485 | ||
70fe4407 | 486 | if (!intel_thermal_supported(c)) |
895287c0 HS |
487 | return; |
488 | ||
489 | /* | |
490 | * First check if its enabled already, in which case there might | |
491 | * be some SMM goo which handles it, so we can't even put a handler | |
492 | * since it might be delivered via SMI already: | |
493 | */ | |
494 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
a2202aa2 | 495 | |
e503f9e4 | 496 | h = lvtthmr_init; |
a2202aa2 YW |
497 | /* |
498 | * The initial value of thermal LVT entries on all APs always reads | |
499 | * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI | |
500 | * sequence to them and LVT registers are reset to 0s except for | |
501 | * the mask bits which are set to 1s when APs receive INIT IPI. | |
e503f9e4 YS |
502 | * If BIOS takes over the thermal interrupt and sets its interrupt |
503 | * delivery mode to SMI (not fixed), it restores the value that the | |
504 | * BIOS has programmed on AP based on BSP's info we saved since BIOS | |
505 | * is always setting the same value for all threads/cores. | |
a2202aa2 | 506 | */ |
e503f9e4 YS |
507 | if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED) |
508 | apic_write(APIC_LVTTHMR, lvtthmr_init); | |
a2202aa2 | 509 | |
a2202aa2 | 510 | |
895287c0 HS |
511 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
512 | printk(KERN_DEBUG | |
513 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); | |
514 | return; | |
515 | } | |
516 | ||
895287c0 HS |
517 | /* Check whether a vector already exists */ |
518 | if (h & APIC_VECTOR_MASK) { | |
519 | printk(KERN_DEBUG | |
520 | "CPU%d: Thermal LVT vector (%#x) already installed\n", | |
521 | cpu, (h & APIC_VECTOR_MASK)); | |
522 | return; | |
523 | } | |
524 | ||
f3a0867b BZ |
525 | /* early Pentium M models use different method for enabling TM2 */ |
526 | if (cpu_has(c, X86_FEATURE_TM2)) { | |
527 | if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { | |
528 | rdmsr(MSR_THERM2_CTL, l, h); | |
529 | if (l & MSR_THERM2_CTL_TM_SELECT) | |
530 | tm2 = 1; | |
531 | } else if (l & MSR_IA32_MISC_ENABLE_TM2) | |
532 | tm2 = 1; | |
533 | } | |
534 | ||
895287c0 HS |
535 | /* We'll mask the thermal vector in the lapic till we're ready: */ |
536 | h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; | |
537 | apic_write(APIC_LVTTHMR, h); | |
538 | ||
539 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | |
6bb2ff84 | 540 | if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) |
0199114c | 541 | wrmsr(MSR_IA32_THERM_INTERRUPT, |
6bb2ff84 FY |
542 | (l | (THERM_INT_LOW_ENABLE |
543 | | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h); | |
544 | else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) | |
0199114c | 545 | wrmsr(MSR_IA32_THERM_INTERRUPT, |
6bb2ff84 | 546 | l | (THERM_INT_LOW_ENABLE |
0199114c FY |
547 | | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); |
548 | else | |
549 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
550 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | |
895287c0 | 551 | |
55d435a2 FY |
552 | if (cpu_has(c, X86_FEATURE_PTS)) { |
553 | rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
6bb2ff84 | 554 | if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) |
0199114c | 555 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, |
6bb2ff84 FY |
556 | (l | (PACKAGE_THERM_INT_LOW_ENABLE |
557 | | PACKAGE_THERM_INT_HIGH_ENABLE)) | |
558 | & ~PACKAGE_THERM_INT_PLN_ENABLE, h); | |
559 | else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) | |
560 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
561 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
0199114c FY |
562 | | PACKAGE_THERM_INT_HIGH_ENABLE |
563 | | PACKAGE_THERM_INT_PLN_ENABLE), h); | |
564 | else | |
565 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
566 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
567 | | PACKAGE_THERM_INT_HIGH_ENABLE), h); | |
55d435a2 FY |
568 | } |
569 | ||
8363fc82 | 570 | smp_thermal_vector = intel_thermal_interrupt; |
895287c0 HS |
571 | |
572 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
573 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); | |
574 | ||
575 | /* Unmask the thermal vector: */ | |
576 | l = apic_read(APIC_LVTTHMR); | |
577 | apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); | |
578 | ||
2eaad1fd MT |
579 | printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n", |
580 | tm2 ? "TM2" : "TM1"); | |
895287c0 HS |
581 | |
582 | /* enable thermal throttle processing */ | |
583 | atomic_set(&therm_throt_en, 1); | |
584 | } |