Commit | Line | Data |
---|---|---|
15d5f839 | 1 | /* |
3222b36f DZ |
2 | * Thermal throttle event support code (such as syslog messaging and rate |
3 | * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). | |
cb6f3c15 | 4 | * |
3222b36f DZ |
5 | * This allows consistent reporting of CPU thermal throttle events. |
6 | * | |
7 | * Maintains a counter in /sys that keeps track of the number of thermal | |
8 | * events, such that the user knows how bad the thermal problem might be | |
9 | * (since the logging to syslog and mcelog is rate limited). | |
15d5f839 DZ |
10 | * |
11 | * Author: Dmitriy Zavin (dmitriyz@google.com) | |
12 | * | |
13 | * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. | |
3222b36f | 14 | * Inspired by Ross Biro's and Al Borchers' counter code. |
15d5f839 | 15 | */ |
a65c88dd | 16 | #include <linux/interrupt.h> |
cb6f3c15 IM |
17 | #include <linux/notifier.h> |
18 | #include <linux/jiffies.h> | |
895287c0 | 19 | #include <linux/kernel.h> |
15d5f839 | 20 | #include <linux/percpu.h> |
3222b36f | 21 | #include <linux/sysdev.h> |
895287c0 HS |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/smp.h> | |
15d5f839 | 25 | #include <linux/cpu.h> |
cb6f3c15 | 26 | |
895287c0 HS |
27 | #include <asm/processor.h> |
28 | #include <asm/system.h> | |
29 | #include <asm/apic.h> | |
a65c88dd HS |
30 | #include <asm/idle.h> |
31 | #include <asm/mce.h> | |
895287c0 | 32 | #include <asm/msr.h> |
15d5f839 DZ |
33 | |
34 | /* How long to wait between reporting thermal events */ | |
cb6f3c15 | 35 | #define CHECK_INTERVAL (300 * HZ) |
15d5f839 | 36 | |
39676840 IM |
37 | /* |
38 | * Current thermal throttling state: | |
39 | */ | |
40 | struct thermal_state { | |
41 | bool is_throttled; | |
42 | ||
43 | u64 next_check; | |
44 | unsigned long throttle_count; | |
b417c9fd | 45 | unsigned long last_throttle_count; |
39676840 | 46 | }; |
cb6f3c15 | 47 | |
39676840 IM |
48 | static DEFINE_PER_CPU(struct thermal_state, thermal_state); |
49 | ||
50 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | |
3222b36f | 51 | |
a2202aa2 YW |
52 | static u32 lvtthmr_init __read_mostly; |
53 | ||
3222b36f | 54 | #ifdef CONFIG_SYSFS |
cb6f3c15 IM |
55 | #define define_therm_throt_sysdev_one_ro(_name) \ |
56 | static SYSDEV_ATTR(_name, 0444, therm_throt_sysdev_show_##_name, NULL) | |
57 | ||
58 | #define define_therm_throt_sysdev_show_func(name) \ | |
39676840 IM |
59 | \ |
60 | static ssize_t therm_throt_sysdev_show_##name( \ | |
61 | struct sys_device *dev, \ | |
62 | struct sysdev_attribute *attr, \ | |
63 | char *buf) \ | |
cb6f3c15 IM |
64 | { \ |
65 | unsigned int cpu = dev->id; \ | |
66 | ssize_t ret; \ | |
67 | \ | |
68 | preempt_disable(); /* CPU hotplug */ \ | |
69 | if (cpu_online(cpu)) \ | |
70 | ret = sprintf(buf, "%lu\n", \ | |
39676840 | 71 | per_cpu(thermal_state, cpu).name); \ |
cb6f3c15 IM |
72 | else \ |
73 | ret = 0; \ | |
74 | preempt_enable(); \ | |
75 | \ | |
76 | return ret; \ | |
3222b36f DZ |
77 | } |
78 | ||
39676840 IM |
79 | define_therm_throt_sysdev_show_func(throttle_count); |
80 | define_therm_throt_sysdev_one_ro(throttle_count); | |
3222b36f DZ |
81 | |
82 | static struct attribute *thermal_throttle_attrs[] = { | |
39676840 | 83 | &attr_throttle_count.attr, |
3222b36f DZ |
84 | NULL |
85 | }; | |
86 | ||
87 | static struct attribute_group thermal_throttle_attr_group = { | |
cb6f3c15 IM |
88 | .attrs = thermal_throttle_attrs, |
89 | .name = "thermal_throttle" | |
3222b36f DZ |
90 | }; |
91 | #endif /* CONFIG_SYSFS */ | |
15d5f839 DZ |
92 | |
93 | /*** | |
3222b36f | 94 | * therm_throt_process - Process thermal throttling event from interrupt |
15d5f839 DZ |
95 | * @curr: Whether the condition is current or not (boolean), since the |
96 | * thermal interrupt normally gets called both when the thermal | |
97 | * event begins and once the event has ended. | |
98 | * | |
3222b36f | 99 | * This function is called by the thermal interrupt after the |
15d5f839 DZ |
100 | * IRQ has been acknowledged. |
101 | * | |
102 | * It will take care of rate limiting and printing messages to the syslog. | |
103 | * | |
104 | * Returns: 0 : Event should NOT be further logged, i.e. still in | |
105 | * "timeout" from previous log message. | |
106 | * 1 : Event should be logged further, and a message has been | |
107 | * printed to the syslog. | |
108 | */ | |
39676840 | 109 | static int therm_throt_process(bool is_throttled) |
15d5f839 | 110 | { |
39676840 IM |
111 | struct thermal_state *state; |
112 | unsigned int this_cpu; | |
113 | bool was_throttled; | |
114 | u64 now; | |
115 | ||
116 | this_cpu = smp_processor_id(); | |
117 | now = get_jiffies_64(); | |
118 | state = &per_cpu(thermal_state, this_cpu); | |
119 | ||
120 | was_throttled = state->is_throttled; | |
121 | state->is_throttled = is_throttled; | |
15d5f839 | 122 | |
0d01f314 | 123 | if (is_throttled) |
39676840 | 124 | state->throttle_count++; |
3222b36f | 125 | |
b417c9fd IM |
126 | if (time_before64(now, state->next_check) && |
127 | state->throttle_count != state->last_throttle_count) | |
15d5f839 DZ |
128 | return 0; |
129 | ||
39676840 | 130 | state->next_check = now + CHECK_INTERVAL; |
b417c9fd | 131 | state->last_throttle_count = state->throttle_count; |
15d5f839 DZ |
132 | |
133 | /* if we just entered the thermal event */ | |
0d01f314 | 134 | if (is_throttled) { |
39676840 | 135 | printk(KERN_CRIT "CPU%d: Temperature above threshold, cpu clock throttled (total events = %lu)\n", this_cpu, state->throttle_count); |
3222b36f | 136 | |
15d5f839 | 137 | add_taint(TAINT_MACHINE_CHECK); |
4e5c25d4 HD |
138 | return 1; |
139 | } | |
140 | if (was_throttled) { | |
39676840 | 141 | printk(KERN_INFO "CPU%d: Temperature/speed normal\n", this_cpu); |
4e5c25d4 | 142 | return 1; |
15d5f839 DZ |
143 | } |
144 | ||
4e5c25d4 | 145 | return 0; |
15d5f839 | 146 | } |
3222b36f DZ |
147 | |
148 | #ifdef CONFIG_SYSFS | |
cb6f3c15 | 149 | /* Add/Remove thermal_throttle interface for CPU device: */ |
6569345a | 150 | static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev) |
3222b36f | 151 | { |
cb6f3c15 IM |
152 | return sysfs_create_group(&sys_dev->kobj, |
153 | &thermal_throttle_attr_group); | |
3222b36f DZ |
154 | } |
155 | ||
6569345a | 156 | static __cpuinit void thermal_throttle_remove_dev(struct sys_device *sys_dev) |
3222b36f | 157 | { |
7c36752a | 158 | sysfs_remove_group(&sys_dev->kobj, &thermal_throttle_attr_group); |
3222b36f DZ |
159 | } |
160 | ||
cb6f3c15 | 161 | /* Mutex protecting device creation against CPU hotplug: */ |
3222b36f DZ |
162 | static DEFINE_MUTEX(therm_cpu_lock); |
163 | ||
164 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ | |
cb6f3c15 IM |
165 | static __cpuinit int |
166 | thermal_throttle_cpu_callback(struct notifier_block *nfb, | |
167 | unsigned long action, | |
168 | void *hcpu) | |
3222b36f DZ |
169 | { |
170 | unsigned int cpu = (unsigned long)hcpu; | |
171 | struct sys_device *sys_dev; | |
c7e38a9c | 172 | int err = 0; |
3222b36f DZ |
173 | |
174 | sys_dev = get_cpu_sysdev(cpu); | |
cb6f3c15 | 175 | |
3222b36f | 176 | switch (action) { |
c7e38a9c AM |
177 | case CPU_UP_PREPARE: |
178 | case CPU_UP_PREPARE_FROZEN: | |
38ef6d19 | 179 | mutex_lock(&therm_cpu_lock); |
6569345a | 180 | err = thermal_throttle_add_dev(sys_dev); |
38ef6d19 | 181 | mutex_unlock(&therm_cpu_lock); |
6569345a | 182 | WARN_ON(err); |
3222b36f | 183 | break; |
c7e38a9c AM |
184 | case CPU_UP_CANCELED: |
185 | case CPU_UP_CANCELED_FROZEN: | |
3222b36f | 186 | case CPU_DEAD: |
8bb78442 | 187 | case CPU_DEAD_FROZEN: |
38ef6d19 | 188 | mutex_lock(&therm_cpu_lock); |
3222b36f | 189 | thermal_throttle_remove_dev(sys_dev); |
38ef6d19 | 190 | mutex_unlock(&therm_cpu_lock); |
3222b36f DZ |
191 | break; |
192 | } | |
a94247e7 | 193 | return notifier_from_errno(err); |
3222b36f DZ |
194 | } |
195 | ||
25d1b516 | 196 | static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata = |
3222b36f DZ |
197 | { |
198 | .notifier_call = thermal_throttle_cpu_callback, | |
199 | }; | |
3222b36f DZ |
200 | |
201 | static __init int thermal_throttle_init_device(void) | |
202 | { | |
203 | unsigned int cpu = 0; | |
6569345a | 204 | int err; |
3222b36f DZ |
205 | |
206 | if (!atomic_read(&therm_throt_en)) | |
207 | return 0; | |
208 | ||
209 | register_hotcpu_notifier(&thermal_throttle_cpu_notifier); | |
210 | ||
211 | #ifdef CONFIG_HOTPLUG_CPU | |
212 | mutex_lock(&therm_cpu_lock); | |
213 | #endif | |
214 | /* connect live CPUs to sysfs */ | |
6569345a SH |
215 | for_each_online_cpu(cpu) { |
216 | err = thermal_throttle_add_dev(get_cpu_sysdev(cpu)); | |
217 | WARN_ON(err); | |
218 | } | |
3222b36f DZ |
219 | #ifdef CONFIG_HOTPLUG_CPU |
220 | mutex_unlock(&therm_cpu_lock); | |
221 | #endif | |
222 | ||
223 | return 0; | |
224 | } | |
3222b36f | 225 | device_initcall(thermal_throttle_init_device); |
a65c88dd | 226 | |
3222b36f | 227 | #endif /* CONFIG_SYSFS */ |
a65c88dd HS |
228 | |
229 | /* Thermal transition interrupt handler */ | |
8363fc82 | 230 | static void intel_thermal_interrupt(void) |
a65c88dd HS |
231 | { |
232 | __u64 msr_val; | |
233 | ||
234 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | |
39676840 | 235 | if (therm_throt_process((msr_val & THERM_STATUS_PROCHOT) != 0)) |
a65c88dd HS |
236 | mce_log_therm_throt_event(msr_val); |
237 | } | |
238 | ||
239 | static void unexpected_thermal_interrupt(void) | |
240 | { | |
241 | printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n", | |
242 | smp_processor_id()); | |
243 | add_taint(TAINT_MACHINE_CHECK); | |
244 | } | |
245 | ||
246 | static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; | |
247 | ||
248 | asmlinkage void smp_thermal_interrupt(struct pt_regs *regs) | |
249 | { | |
250 | exit_idle(); | |
251 | irq_enter(); | |
252 | inc_irq_stat(irq_thermal_count); | |
253 | smp_thermal_vector(); | |
254 | irq_exit(); | |
255 | /* Ack only at the end to avoid potential reentry */ | |
256 | ack_APIC_irq(); | |
257 | } | |
258 | ||
70fe4407 HS |
259 | /* Thermal monitoring depends on APIC, ACPI and clock modulation */ |
260 | static int intel_thermal_supported(struct cpuinfo_x86 *c) | |
261 | { | |
262 | if (!cpu_has_apic) | |
263 | return 0; | |
264 | if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) | |
265 | return 0; | |
266 | return 1; | |
267 | } | |
268 | ||
ce6b5d76 | 269 | void __init mcheck_intel_therm_init(void) |
a2202aa2 YW |
270 | { |
271 | /* | |
272 | * This function is only called on boot CPU. Save the init thermal | |
273 | * LVT value on BSP and use that value to restore APs' thermal LVT | |
274 | * entry BIOS programmed later | |
275 | */ | |
70fe4407 | 276 | if (intel_thermal_supported(&boot_cpu_data)) |
a2202aa2 YW |
277 | lvtthmr_init = apic_read(APIC_LVTTHMR); |
278 | } | |
279 | ||
cffd377e | 280 | void intel_init_thermal(struct cpuinfo_x86 *c) |
895287c0 HS |
281 | { |
282 | unsigned int cpu = smp_processor_id(); | |
283 | int tm2 = 0; | |
284 | u32 l, h; | |
285 | ||
70fe4407 | 286 | if (!intel_thermal_supported(c)) |
895287c0 HS |
287 | return; |
288 | ||
289 | /* | |
290 | * First check if its enabled already, in which case there might | |
291 | * be some SMM goo which handles it, so we can't even put a handler | |
292 | * since it might be delivered via SMI already: | |
293 | */ | |
294 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
a2202aa2 YW |
295 | |
296 | /* | |
297 | * The initial value of thermal LVT entries on all APs always reads | |
298 | * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI | |
299 | * sequence to them and LVT registers are reset to 0s except for | |
300 | * the mask bits which are set to 1s when APs receive INIT IPI. | |
301 | * Always restore the value that BIOS has programmed on AP based on | |
302 | * BSP's info we saved since BIOS is always setting the same value | |
303 | * for all threads/cores | |
304 | */ | |
305 | apic_write(APIC_LVTTHMR, lvtthmr_init); | |
306 | ||
307 | h = lvtthmr_init; | |
308 | ||
895287c0 HS |
309 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
310 | printk(KERN_DEBUG | |
311 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); | |
312 | return; | |
313 | } | |
314 | ||
895287c0 HS |
315 | /* Check whether a vector already exists */ |
316 | if (h & APIC_VECTOR_MASK) { | |
317 | printk(KERN_DEBUG | |
318 | "CPU%d: Thermal LVT vector (%#x) already installed\n", | |
319 | cpu, (h & APIC_VECTOR_MASK)); | |
320 | return; | |
321 | } | |
322 | ||
f3a0867b BZ |
323 | /* early Pentium M models use different method for enabling TM2 */ |
324 | if (cpu_has(c, X86_FEATURE_TM2)) { | |
325 | if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { | |
326 | rdmsr(MSR_THERM2_CTL, l, h); | |
327 | if (l & MSR_THERM2_CTL_TM_SELECT) | |
328 | tm2 = 1; | |
329 | } else if (l & MSR_IA32_MISC_ENABLE_TM2) | |
330 | tm2 = 1; | |
331 | } | |
332 | ||
895287c0 HS |
333 | /* We'll mask the thermal vector in the lapic till we're ready: */ |
334 | h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; | |
335 | apic_write(APIC_LVTTHMR, h); | |
336 | ||
337 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | |
338 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
339 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | |
340 | ||
8363fc82 | 341 | smp_thermal_vector = intel_thermal_interrupt; |
895287c0 HS |
342 | |
343 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
344 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); | |
345 | ||
346 | /* Unmask the thermal vector: */ | |
347 | l = apic_read(APIC_LVTTHMR); | |
348 | apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); | |
349 | ||
2eaad1fd MT |
350 | printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n", |
351 | tm2 ? "TM2" : "TM1"); | |
895287c0 HS |
352 | |
353 | /* enable thermal throttle processing */ | |
354 | atomic_set(&therm_throt_en, 1); | |
355 | } |