Commit | Line | Data |
---|---|---|
3e135d88 | 1 | /* |
6b44e72a | 2 | * CPU Microcode Update Driver for Linux |
3e135d88 | 3 | * |
6b44e72a BP |
4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
5 | * 2006 Shaohua Li <shaohua.li@intel.com> | |
6 | * 2013-2015 Borislav Petkov <bp@alien8.de> | |
3e135d88 | 7 | * |
fe055896 BP |
8 | * X86 CPU microcode early update for Linux: |
9 | * | |
10 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
11 | * H Peter Anvin" <hpa@zytor.com> | |
12 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
13 | * | |
6b44e72a | 14 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 15 | * |
6b44e72a BP |
16 | * This program is free software; you can redistribute it and/or |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
3e135d88 | 20 | */ |
f58e1f53 | 21 | |
6b26e1bf | 22 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 23 | |
4bae1967 | 24 | #include <linux/platform_device.h> |
fe055896 | 25 | #include <linux/syscore_ops.h> |
4bae1967 | 26 | #include <linux/miscdevice.h> |
871b72dd | 27 | #include <linux/capability.h> |
fe055896 | 28 | #include <linux/firmware.h> |
4bae1967 | 29 | #include <linux/kernel.h> |
3e135d88 PO |
30 | #include <linux/mutex.h> |
31 | #include <linux/cpu.h> | |
4bae1967 IM |
32 | #include <linux/fs.h> |
33 | #include <linux/mm.h> | |
3e135d88 | 34 | |
fe055896 | 35 | #include <asm/microcode_intel.h> |
78ff123b | 36 | #include <asm/cpu_device_id.h> |
fe055896 | 37 | #include <asm/microcode_amd.h> |
c93dc84c | 38 | #include <asm/perf_event.h> |
fe055896 BP |
39 | #include <asm/microcode.h> |
40 | #include <asm/processor.h> | |
41 | #include <asm/cmdline.h> | |
3e135d88 | 42 | |
6b26e1bf | 43 | #define MICROCODE_VERSION "2.01" |
3e135d88 | 44 | |
4bae1967 | 45 | static struct microcode_ops *microcode_ops; |
6b26e1bf BP |
46 | static bool dis_ucode_ldr; |
47 | ||
871b72dd DA |
48 | /* |
49 | * Synchronization. | |
50 | * | |
51 | * All non cpu-hotplug-callback call sites use: | |
52 | * | |
53 | * - microcode_mutex to synchronize with each other; | |
54 | * - get/put_online_cpus() to synchronize with | |
55 | * the cpu-hotplug-callback call sites. | |
56 | * | |
57 | * We guarantee that only a single cpu is being | |
58 | * updated at any particular moment of time. | |
59 | */ | |
d45de409 | 60 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 61 | |
4bae1967 | 62 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
8d86f390 | 63 | EXPORT_SYMBOL_GPL(ucode_cpu_info); |
3e135d88 | 64 | |
871b72dd DA |
65 | /* |
66 | * Operations that are run on a target cpu: | |
67 | */ | |
68 | ||
69 | struct cpu_info_ctx { | |
70 | struct cpu_signature *cpu_sig; | |
71 | int err; | |
72 | }; | |
73 | ||
fe055896 BP |
74 | static bool __init check_loader_disabled_bsp(void) |
75 | { | |
e8c8165e BP |
76 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
77 | ||
fe055896 BP |
78 | #ifdef CONFIG_X86_32 |
79 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 80 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
81 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
82 | ||
83 | #else /* CONFIG_X86_64 */ | |
84 | const char *cmdline = boot_command_line; | |
e8c8165e | 85 | const char *option = __dis_opt_str; |
fe055896 BP |
86 | bool *res = &dis_ucode_ldr; |
87 | #endif | |
88 | ||
89 | if (cmdline_find_option_bool(cmdline, option)) | |
90 | *res = true; | |
91 | ||
92 | return *res; | |
93 | } | |
94 | ||
95 | extern struct builtin_fw __start_builtin_fw[]; | |
96 | extern struct builtin_fw __end_builtin_fw[]; | |
97 | ||
98 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
99 | { | |
100 | #ifdef CONFIG_FW_LOADER | |
101 | struct builtin_fw *b_fw; | |
102 | ||
103 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
104 | if (!strcmp(name, b_fw->name)) { | |
105 | cd->size = b_fw->size; | |
106 | cd->data = b_fw->data; | |
107 | return true; | |
108 | } | |
109 | } | |
110 | #endif | |
111 | return false; | |
112 | } | |
113 | ||
114 | void __init load_ucode_bsp(void) | |
115 | { | |
116 | int vendor; | |
117 | unsigned int family; | |
118 | ||
119 | if (check_loader_disabled_bsp()) | |
120 | return; | |
121 | ||
122 | if (!have_cpuid_p()) | |
123 | return; | |
124 | ||
99f925ce BP |
125 | vendor = x86_cpuid_vendor(); |
126 | family = x86_cpuid_family(); | |
fe055896 BP |
127 | |
128 | switch (vendor) { | |
129 | case X86_VENDOR_INTEL: | |
130 | if (family >= 6) | |
131 | load_ucode_intel_bsp(); | |
132 | break; | |
133 | case X86_VENDOR_AMD: | |
134 | if (family >= 0x10) | |
135 | load_ucode_amd_bsp(family); | |
136 | break; | |
137 | default: | |
138 | break; | |
139 | } | |
140 | } | |
141 | ||
142 | static bool check_loader_disabled_ap(void) | |
143 | { | |
144 | #ifdef CONFIG_X86_32 | |
145 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
146 | #else | |
147 | return dis_ucode_ldr; | |
148 | #endif | |
149 | } | |
150 | ||
151 | void load_ucode_ap(void) | |
152 | { | |
153 | int vendor, family; | |
154 | ||
155 | if (check_loader_disabled_ap()) | |
156 | return; | |
157 | ||
158 | if (!have_cpuid_p()) | |
159 | return; | |
160 | ||
99f925ce BP |
161 | vendor = x86_cpuid_vendor(); |
162 | family = x86_cpuid_family(); | |
fe055896 BP |
163 | |
164 | switch (vendor) { | |
165 | case X86_VENDOR_INTEL: | |
166 | if (family >= 6) | |
167 | load_ucode_intel_ap(); | |
168 | break; | |
169 | case X86_VENDOR_AMD: | |
170 | if (family >= 0x10) | |
171 | load_ucode_amd_ap(); | |
172 | break; | |
173 | default: | |
174 | break; | |
175 | } | |
176 | } | |
177 | ||
178 | int __init save_microcode_in_initrd(void) | |
179 | { | |
180 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
181 | ||
182 | switch (c->x86_vendor) { | |
183 | case X86_VENDOR_INTEL: | |
184 | if (c->x86 >= 6) | |
185 | save_microcode_in_initrd_intel(); | |
186 | break; | |
187 | case X86_VENDOR_AMD: | |
188 | if (c->x86 >= 0x10) | |
189 | save_microcode_in_initrd_amd(); | |
190 | break; | |
191 | default: | |
192 | break; | |
193 | } | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | void reload_early_microcode(void) | |
199 | { | |
200 | int vendor, family; | |
201 | ||
99f925ce BP |
202 | vendor = x86_cpuid_vendor(); |
203 | family = x86_cpuid_family(); | |
fe055896 BP |
204 | |
205 | switch (vendor) { | |
206 | case X86_VENDOR_INTEL: | |
207 | if (family >= 6) | |
208 | reload_ucode_intel(); | |
209 | break; | |
210 | case X86_VENDOR_AMD: | |
211 | if (family >= 0x10) | |
212 | reload_ucode_amd(); | |
213 | break; | |
214 | default: | |
215 | break; | |
216 | } | |
217 | } | |
218 | ||
871b72dd DA |
219 | static void collect_cpu_info_local(void *arg) |
220 | { | |
221 | struct cpu_info_ctx *ctx = arg; | |
222 | ||
223 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
224 | ctx->cpu_sig); | |
225 | } | |
226 | ||
227 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
228 | { | |
229 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
230 | int ret; | |
231 | ||
232 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
233 | if (!ret) | |
234 | ret = ctx.err; | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
239 | static int collect_cpu_info(int cpu) | |
240 | { | |
241 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
242 | int ret; | |
243 | ||
244 | memset(uci, 0, sizeof(*uci)); | |
245 | ||
246 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
247 | if (!ret) | |
248 | uci->valid = 1; | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
253 | struct apply_microcode_ctx { | |
254 | int err; | |
255 | }; | |
256 | ||
257 | static void apply_microcode_local(void *arg) | |
258 | { | |
259 | struct apply_microcode_ctx *ctx = arg; | |
260 | ||
261 | ctx->err = microcode_ops->apply_microcode(smp_processor_id()); | |
262 | } | |
263 | ||
264 | static int apply_microcode_on_target(int cpu) | |
265 | { | |
266 | struct apply_microcode_ctx ctx = { .err = 0 }; | |
267 | int ret; | |
268 | ||
269 | ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1); | |
270 | if (!ret) | |
271 | ret = ctx.err; | |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
3e135d88 | 276 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 277 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 278 | { |
3e135d88 | 279 | int error = 0; |
3e135d88 | 280 | int cpu; |
6f66cbc6 | 281 | |
a0a29b62 DA |
282 | for_each_online_cpu(cpu) { |
283 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 284 | enum ucode_state ustate; |
a0a29b62 DA |
285 | |
286 | if (!uci->valid) | |
287 | continue; | |
6f66cbc6 | 288 | |
871b72dd DA |
289 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
290 | if (ustate == UCODE_ERROR) { | |
291 | error = -1; | |
292 | break; | |
293 | } else if (ustate == UCODE_OK) | |
294 | apply_microcode_on_target(cpu); | |
3e135d88 | 295 | } |
871b72dd | 296 | |
3e135d88 PO |
297 | return error; |
298 | } | |
299 | ||
3f10940e | 300 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 301 | { |
3f10940e | 302 | return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM; |
3e135d88 PO |
303 | } |
304 | ||
d33dcb9e PO |
305 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
306 | size_t len, loff_t *ppos) | |
3e135d88 | 307 | { |
871b72dd | 308 | ssize_t ret = -EINVAL; |
3e135d88 | 309 | |
4481374c | 310 | if ((len >> PAGE_SHIFT) > totalram_pages) { |
f58e1f53 | 311 | pr_err("too much data (max %ld pages)\n", totalram_pages); |
871b72dd | 312 | return ret; |
3e135d88 PO |
313 | } |
314 | ||
315 | get_online_cpus(); | |
316 | mutex_lock(µcode_mutex); | |
317 | ||
871b72dd | 318 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
319 | ret = (ssize_t)len; |
320 | ||
e3e45c01 SE |
321 | if (ret > 0) |
322 | perf_check_microcode(); | |
323 | ||
3e135d88 PO |
324 | mutex_unlock(µcode_mutex); |
325 | put_online_cpus(); | |
326 | ||
327 | return ret; | |
328 | } | |
329 | ||
330 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
331 | .owner = THIS_MODULE, |
332 | .write = microcode_write, | |
333 | .open = microcode_open, | |
6038f373 | 334 | .llseek = no_llseek, |
3e135d88 PO |
335 | }; |
336 | ||
337 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
338 | .minor = MICROCODE_MINOR, |
339 | .name = "microcode", | |
e454cea2 | 340 | .nodename = "cpu/microcode", |
871b72dd | 341 | .fops = µcode_fops, |
3e135d88 PO |
342 | }; |
343 | ||
d33dcb9e | 344 | static int __init microcode_dev_init(void) |
3e135d88 PO |
345 | { |
346 | int error; | |
347 | ||
348 | error = misc_register(µcode_dev); | |
349 | if (error) { | |
f58e1f53 | 350 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
351 | return error; |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
bd399063 | 357 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
358 | { |
359 | misc_deregister(µcode_dev); | |
360 | } | |
3e135d88 | 361 | #else |
4bae1967 IM |
362 | #define microcode_dev_init() 0 |
363 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
364 | #endif |
365 | ||
366 | /* fake device for request_firmware */ | |
4bae1967 | 367 | static struct platform_device *microcode_pdev; |
3e135d88 | 368 | |
871b72dd | 369 | static int reload_for_cpu(int cpu) |
af5c820a | 370 | { |
871b72dd | 371 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
4dbf32c3 | 372 | enum ucode_state ustate; |
af5c820a RR |
373 | int err = 0; |
374 | ||
4dbf32c3 BP |
375 | if (!uci->valid) |
376 | return err; | |
871b72dd | 377 | |
48e30685 | 378 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, true); |
4dbf32c3 BP |
379 | if (ustate == UCODE_OK) |
380 | apply_microcode_on_target(cpu); | |
381 | else | |
382 | if (ustate == UCODE_ERROR) | |
383 | err = -EINVAL; | |
af5c820a RR |
384 | return err; |
385 | } | |
386 | ||
8a25a2fd KS |
387 | static ssize_t reload_store(struct device *dev, |
388 | struct device_attribute *attr, | |
871b72dd | 389 | const char *buf, size_t size) |
3e135d88 | 390 | { |
871b72dd | 391 | unsigned long val; |
c9fc3f77 BP |
392 | int cpu; |
393 | ssize_t ret = 0, tmp_ret; | |
394 | ||
e826abd5 SK |
395 | ret = kstrtoul(buf, 0, &val); |
396 | if (ret) | |
397 | return ret; | |
871b72dd | 398 | |
c9fc3f77 BP |
399 | if (val != 1) |
400 | return size; | |
401 | ||
402 | get_online_cpus(); | |
c93dc84c | 403 | mutex_lock(µcode_mutex); |
c9fc3f77 BP |
404 | for_each_online_cpu(cpu) { |
405 | tmp_ret = reload_for_cpu(cpu); | |
406 | if (tmp_ret != 0) | |
407 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
408 | ||
409 | /* save retval of the first encountered reload error */ | |
410 | if (!ret) | |
411 | ret = tmp_ret; | |
3e135d88 | 412 | } |
c93dc84c PZ |
413 | if (!ret) |
414 | perf_check_microcode(); | |
415 | mutex_unlock(µcode_mutex); | |
c9fc3f77 | 416 | put_online_cpus(); |
871b72dd DA |
417 | |
418 | if (!ret) | |
419 | ret = size; | |
420 | ||
421 | return ret; | |
3e135d88 PO |
422 | } |
423 | ||
8a25a2fd KS |
424 | static ssize_t version_show(struct device *dev, |
425 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
426 | { |
427 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
428 | ||
d45de409 | 429 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
430 | } |
431 | ||
8a25a2fd KS |
432 | static ssize_t pf_show(struct device *dev, |
433 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
434 | { |
435 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
436 | ||
d45de409 | 437 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
438 | } |
439 | ||
8a25a2fd KS |
440 | static DEVICE_ATTR(reload, 0200, NULL, reload_store); |
441 | static DEVICE_ATTR(version, 0400, version_show, NULL); | |
442 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | |
3e135d88 PO |
443 | |
444 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
445 | &dev_attr_version.attr, |
446 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
447 | NULL |
448 | }; | |
449 | ||
450 | static struct attribute_group mc_attr_group = { | |
871b72dd DA |
451 | .attrs = mc_default_attrs, |
452 | .name = "microcode", | |
3e135d88 PO |
453 | }; |
454 | ||
871b72dd | 455 | static void microcode_fini_cpu(int cpu) |
d45de409 | 456 | { |
d45de409 | 457 | microcode_ops->microcode_fini_cpu(cpu); |
280a9ca5 DA |
458 | } |
459 | ||
871b72dd | 460 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 461 | { |
f58e1f53 | 462 | pr_debug("CPU%d updated upon resume\n", cpu); |
bb9d3e47 BP |
463 | |
464 | if (apply_microcode_on_target(cpu)) | |
465 | return UCODE_ERROR; | |
871b72dd DA |
466 | |
467 | return UCODE_OK; | |
d45de409 DA |
468 | } |
469 | ||
48e30685 | 470 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 471 | { |
871b72dd | 472 | enum ucode_state ustate; |
9cd4d78e FY |
473 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
474 | ||
43858f57 | 475 | if (uci->valid) |
9cd4d78e | 476 | return UCODE_OK; |
d45de409 | 477 | |
871b72dd DA |
478 | if (collect_cpu_info(cpu)) |
479 | return UCODE_ERROR; | |
d45de409 | 480 | |
871b72dd DA |
481 | /* --dimm. Trigger a delayed update? */ |
482 | if (system_state != SYSTEM_RUNNING) | |
483 | return UCODE_NFOUND; | |
d45de409 | 484 | |
48e30685 BP |
485 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, |
486 | refresh_fw); | |
d45de409 | 487 | |
871b72dd | 488 | if (ustate == UCODE_OK) { |
f58e1f53 | 489 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 490 | apply_microcode_on_target(cpu); |
d45de409 DA |
491 | } |
492 | ||
871b72dd | 493 | return ustate; |
d45de409 DA |
494 | } |
495 | ||
871b72dd | 496 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 497 | { |
871b72dd | 498 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 499 | |
2f99f5c8 | 500 | if (uci->valid) |
bb9d3e47 | 501 | return microcode_resume_cpu(cpu); |
d45de409 | 502 | |
48e30685 | 503 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
504 | } |
505 | ||
8a25a2fd | 506 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 507 | { |
8a25a2fd | 508 | int err, cpu = dev->id; |
3e135d88 PO |
509 | |
510 | if (!cpu_online(cpu)) | |
511 | return 0; | |
512 | ||
f58e1f53 | 513 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 514 | |
8a25a2fd | 515 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
516 | if (err) |
517 | return err; | |
518 | ||
48e30685 | 519 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 520 | return -EINVAL; |
af5c820a RR |
521 | |
522 | return err; | |
3e135d88 PO |
523 | } |
524 | ||
71db87ba | 525 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 526 | { |
8a25a2fd | 527 | int cpu = dev->id; |
3e135d88 PO |
528 | |
529 | if (!cpu_online(cpu)) | |
71db87ba | 530 | return; |
3e135d88 | 531 | |
f58e1f53 | 532 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 533 | microcode_fini_cpu(cpu); |
8a25a2fd | 534 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
535 | } |
536 | ||
8a25a2fd KS |
537 | static struct subsys_interface mc_cpu_interface = { |
538 | .name = "microcode", | |
539 | .subsys = &cpu_subsys, | |
540 | .add_dev = mc_device_add, | |
541 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
542 | }; |
543 | ||
544 | /** | |
545 | * mc_bp_resume - Update boot CPU microcode during resume. | |
546 | */ | |
547 | static void mc_bp_resume(void) | |
3e135d88 | 548 | { |
f3c6ea1b | 549 | int cpu = smp_processor_id(); |
871b72dd | 550 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 551 | |
871b72dd DA |
552 | if (uci->valid && uci->mc) |
553 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 554 | else if (!uci->mc) |
fbae4ba8 | 555 | reload_early_microcode(); |
3e135d88 PO |
556 | } |
557 | ||
f3c6ea1b RW |
558 | static struct syscore_ops mc_syscore_ops = { |
559 | .resume = mc_bp_resume, | |
3e135d88 PO |
560 | }; |
561 | ||
148f9bb8 | 562 | static int |
3e135d88 PO |
563 | mc_cpu_callback(struct notifier_block *nb, unsigned long action, void *hcpu) |
564 | { | |
565 | unsigned int cpu = (unsigned long)hcpu; | |
8a25a2fd | 566 | struct device *dev; |
3e135d88 | 567 | |
8a25a2fd | 568 | dev = get_cpu_device(cpu); |
09c3f0d8 BP |
569 | |
570 | switch (action & ~CPU_TASKS_FROZEN) { | |
3e135d88 | 571 | case CPU_ONLINE: |
871b72dd | 572 | microcode_update_cpu(cpu); |
f58e1f53 | 573 | pr_debug("CPU%d added\n", cpu); |
09c3f0d8 BP |
574 | /* |
575 | * "break" is missing on purpose here because we want to fall | |
576 | * through in order to create the sysfs group. | |
577 | */ | |
578 | ||
579 | case CPU_DOWN_FAILED: | |
8a25a2fd | 580 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
f58e1f53 | 581 | pr_err("Failed to create group for CPU%d\n", cpu); |
3e135d88 | 582 | break; |
09c3f0d8 | 583 | |
3e135d88 | 584 | case CPU_DOWN_PREPARE: |
3e135d88 | 585 | /* Suspend is in progress, only remove the interface */ |
8a25a2fd | 586 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
f58e1f53 | 587 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 588 | break; |
70989449 SB |
589 | |
590 | /* | |
09c3f0d8 BP |
591 | * case CPU_DEAD: |
592 | * | |
70989449 SB |
593 | * When a CPU goes offline, don't free up or invalidate the copy of |
594 | * the microcode in kernel memory, so that we can reuse it when the | |
595 | * CPU comes back online without unnecessarily requesting the userspace | |
596 | * for it again. | |
597 | */ | |
3e135d88 | 598 | } |
09c3f0d8 BP |
599 | |
600 | /* The CPU refused to come up during a system resume */ | |
601 | if (action == CPU_UP_CANCELED_FROZEN) | |
602 | microcode_fini_cpu(cpu); | |
603 | ||
3e135d88 PO |
604 | return NOTIFY_OK; |
605 | } | |
606 | ||
4daa832d | 607 | static struct notifier_block mc_cpu_notifier = { |
4bae1967 | 608 | .notifier_call = mc_cpu_callback, |
3e135d88 PO |
609 | }; |
610 | ||
3d8986bc BP |
611 | static struct attribute *cpu_root_microcode_attrs[] = { |
612 | &dev_attr_reload.attr, | |
613 | NULL | |
614 | }; | |
615 | ||
616 | static struct attribute_group cpu_root_microcode_group = { | |
617 | .name = "microcode", | |
618 | .attrs = cpu_root_microcode_attrs, | |
619 | }; | |
620 | ||
9a2bc335 | 621 | int __init microcode_init(void) |
3e135d88 | 622 | { |
9a2bc335 | 623 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
624 | int error; |
625 | ||
84aba677 | 626 | if (dis_ucode_ldr) |
da63865a | 627 | return -EINVAL; |
65cef131 | 628 | |
18dbc916 DA |
629 | if (c->x86_vendor == X86_VENDOR_INTEL) |
630 | microcode_ops = init_intel_microcode(); | |
82b07865 | 631 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 632 | microcode_ops = init_amd_microcode(); |
283c1f25 | 633 | else |
f58e1f53 | 634 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
635 | |
636 | if (!microcode_ops) | |
18dbc916 | 637 | return -ENODEV; |
3e135d88 | 638 | |
3e135d88 PO |
639 | microcode_pdev = platform_device_register_simple("microcode", -1, |
640 | NULL, 0); | |
bd399063 | 641 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 642 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
643 | |
644 | get_online_cpus(); | |
871b72dd DA |
645 | mutex_lock(µcode_mutex); |
646 | ||
8a25a2fd | 647 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
648 | if (!error) |
649 | perf_check_microcode(); | |
871b72dd | 650 | mutex_unlock(µcode_mutex); |
3e135d88 | 651 | put_online_cpus(); |
871b72dd | 652 | |
bd399063 SB |
653 | if (error) |
654 | goto out_pdev; | |
3e135d88 | 655 | |
3d8986bc BP |
656 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
657 | &cpu_root_microcode_group); | |
658 | ||
659 | if (error) { | |
660 | pr_err("Error creating microcode group!\n"); | |
661 | goto out_driver; | |
662 | } | |
663 | ||
871b72dd DA |
664 | error = microcode_dev_init(); |
665 | if (error) | |
3d8986bc | 666 | goto out_ucode_group; |
871b72dd | 667 | |
f3c6ea1b | 668 | register_syscore_ops(&mc_syscore_ops); |
3e135d88 | 669 | register_hotcpu_notifier(&mc_cpu_notifier); |
8d86f390 | 670 | |
871b72dd | 671 | pr_info("Microcode Update Driver: v" MICROCODE_VERSION |
f58e1f53 | 672 | " <tigran@aivazian.fsnet.co.uk>, Peter Oruba\n"); |
8d86f390 | 673 | |
3e135d88 | 674 | return 0; |
bd399063 | 675 | |
3d8986bc BP |
676 | out_ucode_group: |
677 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
678 | &cpu_root_microcode_group); | |
679 | ||
680 | out_driver: | |
bd399063 SB |
681 | get_online_cpus(); |
682 | mutex_lock(µcode_mutex); | |
683 | ||
ff4b8a57 | 684 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
685 | |
686 | mutex_unlock(µcode_mutex); | |
687 | put_online_cpus(); | |
688 | ||
3d8986bc | 689 | out_pdev: |
bd399063 SB |
690 | platform_device_unregister(microcode_pdev); |
691 | return error; | |
692 | ||
3e135d88 | 693 | } |
2d5be37d | 694 | late_initcall(microcode_init); |