Commit | Line | Data |
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1da177e4 | 1 | #include <linux/init.h> |
23110377 | 2 | #include <linux/io.h> |
1da177e4 | 3 | #include <linux/mm.h> |
23110377 | 4 | |
f25f64ed | 5 | #include <asm/processor-cyrix.h> |
7ebad705 | 6 | #include <asm/processor-flags.h> |
23110377 JSR |
7 | #include <asm/mtrr.h> |
8 | #include <asm/msr.h> | |
9 | ||
1da177e4 LT |
10 | #include "mtrr.h" |
11 | ||
1da177e4 LT |
12 | static void |
13 | cyrix_get_arr(unsigned int reg, unsigned long *base, | |
365bff80 | 14 | unsigned long *size, mtrr_type * type) |
1da177e4 | 15 | { |
1da177e4 | 16 | unsigned char arr, ccr3, rcr, shift; |
23110377 | 17 | unsigned long flags; |
1da177e4 LT |
18 | |
19 | arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */ | |
20 | ||
1da177e4 LT |
21 | local_irq_save(flags); |
22 | ||
23 | ccr3 = getCx86(CX86_CCR3); | |
24 | setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ | |
23110377 JSR |
25 | ((unsigned char *)base)[3] = getCx86(arr); |
26 | ((unsigned char *)base)[2] = getCx86(arr + 1); | |
27 | ((unsigned char *)base)[1] = getCx86(arr + 2); | |
1da177e4 | 28 | rcr = getCx86(CX86_RCR_BASE + reg); |
23110377 | 29 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ |
1da177e4 | 30 | |
1da177e4 | 31 | local_irq_restore(flags); |
23110377 | 32 | |
1da177e4 LT |
33 | shift = ((unsigned char *) base)[1] & 0x0f; |
34 | *base >>= PAGE_SHIFT; | |
35 | ||
23110377 JSR |
36 | /* |
37 | * Power of two, at least 4K on ARR0-ARR6, 256K on ARR7 | |
1da177e4 LT |
38 | * Note: shift==0xf means 4G, this is unsupported. |
39 | */ | |
40 | if (shift) | |
41 | *size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1); | |
42 | else | |
43 | *size = 0; | |
44 | ||
45 | /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */ | |
46 | if (reg < 7) { | |
47 | switch (rcr) { | |
48 | case 1: | |
49 | *type = MTRR_TYPE_UNCACHABLE; | |
50 | break; | |
51 | case 8: | |
52 | *type = MTRR_TYPE_WRBACK; | |
53 | break; | |
54 | case 9: | |
55 | *type = MTRR_TYPE_WRCOMB; | |
56 | break; | |
57 | case 24: | |
58 | default: | |
59 | *type = MTRR_TYPE_WRTHROUGH; | |
60 | break; | |
61 | } | |
62 | } else { | |
63 | switch (rcr) { | |
64 | case 0: | |
65 | *type = MTRR_TYPE_UNCACHABLE; | |
66 | break; | |
67 | case 8: | |
68 | *type = MTRR_TYPE_WRCOMB; | |
69 | break; | |
70 | case 9: | |
71 | *type = MTRR_TYPE_WRBACK; | |
72 | break; | |
73 | case 25: | |
74 | default: | |
75 | *type = MTRR_TYPE_WRTHROUGH; | |
76 | break; | |
77 | } | |
78 | } | |
79 | } | |
80 | ||
23110377 JSR |
81 | /* |
82 | * cyrix_get_free_region - get a free ARR. | |
83 | * | |
84 | * @base: the starting (base) address of the region. | |
85 | * @size: the size (in bytes) of the region. | |
86 | * | |
87 | * Returns: the index of the region on success, else -1 on error. | |
88 | */ | |
1da177e4 | 89 | static int |
365bff80 | 90 | cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) |
1da177e4 | 91 | { |
365bff80 | 92 | unsigned long lbase, lsize; |
23110377 JSR |
93 | mtrr_type ltype; |
94 | int i; | |
1da177e4 | 95 | |
365bff80 JB |
96 | switch (replace_reg) { |
97 | case 7: | |
98 | if (size < 0x40) | |
99 | break; | |
100 | case 6: | |
101 | case 5: | |
102 | case 4: | |
103 | return replace_reg; | |
104 | case 3: | |
365bff80 JB |
105 | case 2: |
106 | case 1: | |
107 | case 0: | |
108 | return replace_reg; | |
109 | } | |
1da177e4 LT |
110 | /* If we are to set up a region >32M then look at ARR7 immediately */ |
111 | if (size > 0x2000) { | |
112 | cyrix_get_arr(7, &lbase, &lsize, <ype); | |
113 | if (lsize == 0) | |
114 | return 7; | |
23110377 | 115 | /* Else try ARR0-ARR6 first */ |
1da177e4 LT |
116 | } else { |
117 | for (i = 0; i < 7; i++) { | |
118 | cyrix_get_arr(i, &lbase, &lsize, <ype); | |
1da177e4 LT |
119 | if (lsize == 0) |
120 | return i; | |
121 | } | |
23110377 JSR |
122 | /* |
123 | * ARR0-ARR6 isn't free | |
124 | * try ARR7 but its size must be at least 256K | |
125 | */ | |
1da177e4 LT |
126 | cyrix_get_arr(i, &lbase, &lsize, <ype); |
127 | if ((lsize == 0) && (size >= 0x40)) | |
128 | return i; | |
129 | } | |
130 | return -ENOSPC; | |
131 | } | |
132 | ||
23110377 | 133 | static u32 cr4, ccr3; |
1da177e4 LT |
134 | |
135 | static void prepare_set(void) | |
136 | { | |
137 | u32 cr0; | |
138 | ||
139 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ | |
23110377 | 140 | if (cpu_has_pge) { |
1da177e4 | 141 | cr4 = read_cr4(); |
17304383 | 142 | write_cr4(cr4 & ~X86_CR4_PGE); |
1da177e4 LT |
143 | } |
144 | ||
23110377 JSR |
145 | /* |
146 | * Disable and flush caches. | |
147 | * Note that wbinvd flushes the TLBs as a side-effect | |
148 | */ | |
7ebad705 | 149 | cr0 = read_cr0() | X86_CR0_CD; |
1da177e4 LT |
150 | wbinvd(); |
151 | write_cr0(cr0); | |
152 | wbinvd(); | |
153 | ||
27b46d76 | 154 | /* Cyrix ARRs - everything else was excluded at the top */ |
1da177e4 LT |
155 | ccr3 = getCx86(CX86_CCR3); |
156 | ||
27b46d76 | 157 | /* Cyrix ARRs - everything else was excluded at the top */ |
1da177e4 | 158 | setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); |
1da177e4 LT |
159 | } |
160 | ||
161 | static void post_set(void) | |
162 | { | |
23110377 | 163 | /* Flush caches and TLBs */ |
1da177e4 LT |
164 | wbinvd(); |
165 | ||
166 | /* Cyrix ARRs - everything else was excluded at the top */ | |
167 | setCx86(CX86_CCR3, ccr3); | |
23110377 JSR |
168 | |
169 | /* Enable caches */ | |
a3d7b7dd | 170 | write_cr0(read_cr0() & ~X86_CR0_CD); |
1da177e4 | 171 | |
23110377 JSR |
172 | /* Restore value of CR4 */ |
173 | if (cpu_has_pge) | |
1da177e4 LT |
174 | write_cr4(cr4); |
175 | } | |
176 | ||
177 | static void cyrix_set_arr(unsigned int reg, unsigned long base, | |
178 | unsigned long size, mtrr_type type) | |
179 | { | |
180 | unsigned char arr, arr_type, arr_size; | |
181 | ||
182 | arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */ | |
183 | ||
184 | /* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */ | |
185 | if (reg >= 7) | |
186 | size >>= 6; | |
187 | ||
188 | size &= 0x7fff; /* make sure arr_size <= 14 */ | |
23110377 JSR |
189 | for (arr_size = 0; size; arr_size++, size >>= 1) |
190 | ; | |
1da177e4 LT |
191 | |
192 | if (reg < 7) { | |
193 | switch (type) { | |
194 | case MTRR_TYPE_UNCACHABLE: | |
195 | arr_type = 1; | |
196 | break; | |
197 | case MTRR_TYPE_WRCOMB: | |
198 | arr_type = 9; | |
199 | break; | |
200 | case MTRR_TYPE_WRTHROUGH: | |
201 | arr_type = 24; | |
202 | break; | |
203 | default: | |
204 | arr_type = 8; | |
205 | break; | |
206 | } | |
207 | } else { | |
208 | switch (type) { | |
209 | case MTRR_TYPE_UNCACHABLE: | |
210 | arr_type = 0; | |
211 | break; | |
212 | case MTRR_TYPE_WRCOMB: | |
213 | arr_type = 8; | |
214 | break; | |
215 | case MTRR_TYPE_WRTHROUGH: | |
216 | arr_type = 25; | |
217 | break; | |
218 | default: | |
219 | arr_type = 9; | |
220 | break; | |
221 | } | |
222 | } | |
223 | ||
224 | prepare_set(); | |
225 | ||
226 | base <<= PAGE_SHIFT; | |
23110377 JSR |
227 | setCx86(arr + 0, ((unsigned char *)&base)[3]); |
228 | setCx86(arr + 1, ((unsigned char *)&base)[2]); | |
229 | setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size); | |
1da177e4 LT |
230 | setCx86(CX86_RCR_BASE + reg, arr_type); |
231 | ||
232 | post_set(); | |
233 | } | |
234 | ||
235 | typedef struct { | |
23110377 JSR |
236 | unsigned long base; |
237 | unsigned long size; | |
238 | mtrr_type type; | |
1da177e4 LT |
239 | } arr_state_t; |
240 | ||
80581c43 | 241 | static arr_state_t arr_state[8] = { |
1da177e4 LT |
242 | {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, |
243 | {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL} | |
244 | }; | |
245 | ||
80581c43 | 246 | static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 }; |
1da177e4 LT |
247 | |
248 | static void cyrix_set_all(void) | |
249 | { | |
250 | int i; | |
251 | ||
252 | prepare_set(); | |
253 | ||
254 | /* the CCRs are not contiguous */ | |
255 | for (i = 0; i < 4; i++) | |
256 | setCx86(CX86_CCR0 + i, ccr_state[i]); | |
257 | for (; i < 7; i++) | |
258 | setCx86(CX86_CCR4 + i, ccr_state[i]); | |
23110377 JSR |
259 | |
260 | for (i = 0; i < 8; i++) { | |
261 | cyrix_set_arr(i, arr_state[i].base, | |
1da177e4 | 262 | arr_state[i].size, arr_state[i].type); |
23110377 | 263 | } |
1da177e4 LT |
264 | |
265 | post_set(); | |
266 | } | |
267 | ||
3b9cfc0a | 268 | static const struct mtrr_ops cyrix_mtrr_ops = { |
1da177e4 | 269 | .vendor = X86_VENDOR_CYRIX, |
1da177e4 LT |
270 | .set_all = cyrix_set_all, |
271 | .set = cyrix_set_arr, | |
272 | .get = cyrix_get_arr, | |
273 | .get_free_region = cyrix_get_free_region, | |
274 | .validate_add_page = generic_validate_add_page, | |
275 | .have_wrcomb = positive_have_wrcomb, | |
276 | }; | |
277 | ||
278 | int __init cyrix_init_mtrr(void) | |
279 | { | |
280 | set_mtrr_ops(&cyrix_mtrr_ops); | |
281 | return 0; | |
282 | } |