Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
dbd51be0 JSR |
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
1da177e4 LT |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). |
32 | */ | |
33 | ||
dbd51be0 JSR |
34 | #define DEBUG |
35 | ||
36 | #include <linux/types.h> /* FIXME: kvm_para.h needs this */ | |
37 | ||
68f202e4 | 38 | #include <linux/stop_machine.h> |
dbd51be0 JSR |
39 | #include <linux/kvm_para.h> |
40 | #include <linux/uaccess.h> | |
1da177e4 | 41 | #include <linux/module.h> |
dbd51be0 | 42 | #include <linux/mutex.h> |
1da177e4 | 43 | #include <linux/init.h> |
dbd51be0 JSR |
44 | #include <linux/sort.h> |
45 | #include <linux/cpu.h> | |
1da177e4 LT |
46 | #include <linux/pci.h> |
47 | #include <linux/smp.h> | |
f3c6ea1b | 48 | #include <linux/syscore_ops.h> |
1da177e4 | 49 | |
dbd51be0 | 50 | #include <asm/processor.h> |
99fc8d42 | 51 | #include <asm/e820.h> |
1da177e4 | 52 | #include <asm/mtrr.h> |
1da177e4 | 53 | #include <asm/msr.h> |
dbd51be0 | 54 | |
1da177e4 LT |
55 | #include "mtrr.h" |
56 | ||
dbd51be0 | 57 | u32 num_var_ranges; |
1da177e4 | 58 | |
b558bc0a | 59 | unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; |
14cc3e2b | 60 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 61 | |
6c5806ca | 62 | u64 size_or_mask, size_and_mask; |
5400743d | 63 | static bool mtrr_aps_delayed_init; |
1da177e4 | 64 | |
3b9cfc0a | 65 | static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM]; |
1da177e4 | 66 | |
3b9cfc0a | 67 | const struct mtrr_ops *mtrr_if; |
1da177e4 LT |
68 | |
69 | static void set_mtrr(unsigned int reg, unsigned long base, | |
70 | unsigned long size, mtrr_type type); | |
71 | ||
3b9cfc0a | 72 | void set_mtrr_ops(const struct mtrr_ops *ops) |
1da177e4 LT |
73 | { |
74 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
75 | mtrr_ops[ops->vendor] = ops; | |
76 | } | |
77 | ||
78 | /* Returns non-zero if we have the write-combining memory type */ | |
79 | static int have_wrcomb(void) | |
80 | { | |
81 | struct pci_dev *dev; | |
dbd51be0 JSR |
82 | |
83 | dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL); | |
84 | if (dev != NULL) { | |
85 | /* | |
86 | * ServerWorks LE chipsets < rev 6 have problems with | |
87 | * write-combining. Don't allow it and leave room for other | |
88 | * chipsets to be tagged | |
89 | */ | |
1da177e4 | 90 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && |
50c31e4a SS |
91 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE && |
92 | dev->revision <= 5) { | |
93 | pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
94 | pci_dev_put(dev); | |
95 | return 0; | |
1da177e4 | 96 | } |
dbd51be0 JSR |
97 | /* |
98 | * Intel 450NX errata # 23. Non ascending cacheline evictions to | |
99 | * write combining memory may resulting in data corruption | |
100 | */ | |
1da177e4 LT |
101 | if (dev->vendor == PCI_VENDOR_ID_INTEL && |
102 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
dbd51be0 | 103 | pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); |
1da177e4 LT |
104 | pci_dev_put(dev); |
105 | return 0; | |
106 | } | |
107 | pci_dev_put(dev); | |
dbd51be0 JSR |
108 | } |
109 | return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0; | |
1da177e4 LT |
110 | } |
111 | ||
112 | /* This function returns the number of variable MTRRs */ | |
113 | static void __init set_num_var_ranges(void) | |
114 | { | |
115 | unsigned long config = 0, dummy; | |
116 | ||
dbd51be0 | 117 | if (use_intel()) |
d9bcc01d | 118 | rdmsr(MSR_MTRRcap, config, dummy); |
dbd51be0 | 119 | else if (is_cpu(AMD)) |
1da177e4 LT |
120 | config = 2; |
121 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
122 | config = 8; | |
dbd51be0 | 123 | |
1da177e4 LT |
124 | num_var_ranges = config & 0xff; |
125 | } | |
126 | ||
127 | static void __init init_table(void) | |
128 | { | |
129 | int i, max; | |
130 | ||
131 | max = num_var_ranges; | |
1da177e4 | 132 | for (i = 0; i < max; i++) |
99fc8d42 | 133 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
134 | } |
135 | ||
136 | struct set_mtrr_data { | |
1da177e4 LT |
137 | unsigned long smp_base; |
138 | unsigned long smp_size; | |
139 | unsigned int smp_reg; | |
140 | mtrr_type smp_type; | |
141 | }; | |
142 | ||
dbd51be0 | 143 | /** |
192d8857 SS |
144 | * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed |
145 | * by all the CPUs. | |
6c550ee4 | 146 | * @info: pointer to mtrr configuration data |
dbd51be0 JSR |
147 | * |
148 | * Returns nothing. | |
149 | */ | |
192d8857 | 150 | static int mtrr_rendezvous_handler(void *info) |
1da177e4 | 151 | { |
4e2947f1 | 152 | #ifdef CONFIG_SMP |
1da177e4 | 153 | struct set_mtrr_data *data = info; |
1da177e4 | 154 | |
192d8857 SS |
155 | /* |
156 | * We use this same function to initialize the mtrrs during boot, | |
157 | * resume, runtime cpu online and on an explicit request to set a | |
158 | * specific MTRR. | |
159 | * | |
160 | * During boot or suspend, the state of the boot cpu's mtrrs has been | |
161 | * saved, and we want to replicate that across all the cpus that come | |
162 | * online (either at the end of boot or resume or during a runtime cpu | |
163 | * online). If we're doing that, @reg is set to something special and on | |
164 | * all the cpu's we do mtrr_if->set_all() (On the logical cpu that | |
165 | * started the boot/resume sequence, this might be a duplicate | |
166 | * set_all()). | |
167 | */ | |
dbd51be0 JSR |
168 | if (data->smp_reg != ~0U) { |
169 | mtrr_if->set(data->smp_reg, data->smp_base, | |
1da177e4 | 170 | data->smp_size, data->smp_type); |
192d8857 | 171 | } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) { |
1da177e4 | 172 | mtrr_if->set_all(); |
dbd51be0 | 173 | } |
1da177e4 | 174 | #endif |
68f202e4 | 175 | return 0; |
4e2947f1 | 176 | } |
1da177e4 | 177 | |
dbd51be0 JSR |
178 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) |
179 | { | |
365bff80 JB |
180 | return type1 == MTRR_TYPE_UNCACHABLE || |
181 | type2 == MTRR_TYPE_UNCACHABLE || | |
182 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
183 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
184 | } | |
185 | ||
1da177e4 LT |
186 | /** |
187 | * set_mtrr - update mtrrs on all processors | |
188 | * @reg: mtrr in question | |
189 | * @base: mtrr base | |
190 | * @size: mtrr size | |
191 | * @type: mtrr type | |
192 | * | |
193 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
dbd51be0 | 194 | * |
68f202e4 | 195 | * 1. Queue work to do the following on all processors: |
1da177e4 | 196 | * 2. Disable Interrupts |
dbd51be0 | 197 | * 3. Wait for all procs to do so |
1da177e4 LT |
198 | * 4. Enter no-fill cache mode |
199 | * 5. Flush caches | |
200 | * 6. Clear PGE bit | |
201 | * 7. Flush all TLBs | |
202 | * 8. Disable all range registers | |
203 | * 9. Update the MTRRs | |
204 | * 10. Enable all range registers | |
205 | * 11. Flush all TLBs and caches again | |
206 | * 12. Enter normal cache mode and reenable caching | |
dbd51be0 | 207 | * 13. Set PGE |
1da177e4 LT |
208 | * 14. Wait for buddies to catch up |
209 | * 15. Enable interrupts. | |
dbd51be0 | 210 | * |
192d8857 SS |
211 | * What does that mean for us? Well, stop_machine() will ensure that |
212 | * the rendezvous handler is started on each CPU. And in lockstep they | |
213 | * do the state transition of disabling interrupts, updating MTRR's | |
214 | * (the CPU vendors may each do it differently, so we call mtrr_if->set() | |
215 | * callback and let them take care of it.) and enabling interrupts. | |
1da177e4 LT |
216 | * |
217 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
218 | * becomes nops. | |
219 | */ | |
dbd51be0 JSR |
220 | static void |
221 | set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) | |
1da177e4 | 222 | { |
192d8857 SS |
223 | struct set_mtrr_data data = { .smp_reg = reg, |
224 | .smp_base = base, | |
225 | .smp_size = size, | |
226 | .smp_type = type | |
227 | }; | |
68f202e4 | 228 | |
192d8857 SS |
229 | stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask); |
230 | } | |
1da177e4 | 231 | |
192d8857 SS |
232 | static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base, |
233 | unsigned long size, mtrr_type type) | |
234 | { | |
235 | struct set_mtrr_data data = { .smp_reg = reg, | |
236 | .smp_base = base, | |
237 | .smp_size = size, | |
238 | .smp_type = type | |
239 | }; | |
240 | ||
241 | stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data, | |
242 | cpu_callout_mask); | |
1da177e4 LT |
243 | } |
244 | ||
245 | /** | |
dbd51be0 JSR |
246 | * mtrr_add_page - Add a memory type region |
247 | * @base: Physical base address of region in pages (in units of 4 kB!) | |
248 | * @size: Physical size of region in pages (4 kB) | |
249 | * @type: Type of MTRR desired | |
250 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 251 | * |
dbd51be0 JSR |
252 | * Memory type region registers control the caching on newer Intel and |
253 | * non Intel processors. This function allows drivers to request an | |
254 | * MTRR is added. The details and hardware specifics of each processor's | |
255 | * implementation are hidden from the caller, but nevertheless the | |
256 | * caller should expect to need to provide a power of two size on an | |
257 | * equivalent power of two boundary. | |
1da177e4 | 258 | * |
dbd51be0 JSR |
259 | * If the region cannot be added either because all regions are in use |
260 | * or the CPU cannot support it a negative value is returned. On success | |
261 | * the register number for this entry is returned, but should be treated | |
262 | * as a cookie only. | |
1da177e4 | 263 | * |
dbd51be0 JSR |
264 | * On a multiprocessor machine the changes are made to all processors. |
265 | * This is required on x86 by the Intel processors. | |
1da177e4 | 266 | * |
dbd51be0 | 267 | * The available types are |
1da177e4 | 268 | * |
dbd51be0 | 269 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 270 | * |
dbd51be0 | 271 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 272 | * |
dbd51be0 | 273 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 274 | * |
dbd51be0 | 275 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 276 | * |
dbd51be0 JSR |
277 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
278 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 279 | */ |
dbd51be0 | 280 | int mtrr_add_page(unsigned long base, unsigned long size, |
2d2ee8de | 281 | unsigned int type, bool increment) |
1da177e4 | 282 | { |
dbd51be0 | 283 | unsigned long lbase, lsize; |
365bff80 | 284 | int i, replace, error; |
1da177e4 | 285 | mtrr_type ltype; |
1da177e4 LT |
286 | |
287 | if (!mtrr_if) | |
288 | return -ENXIO; | |
dbd51be0 JSR |
289 | |
290 | error = mtrr_if->validate_add_page(base, size, type); | |
291 | if (error) | |
1da177e4 LT |
292 | return error; |
293 | ||
294 | if (type >= MTRR_NUM_TYPES) { | |
dbd51be0 | 295 | pr_warning("mtrr: type: %u invalid\n", type); |
1da177e4 LT |
296 | return -EINVAL; |
297 | } | |
298 | ||
dbd51be0 | 299 | /* If the type is WC, check that this processor supports it */ |
1da177e4 | 300 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { |
dbd51be0 | 301 | pr_warning("mtrr: your processor doesn't support write-combining\n"); |
1da177e4 LT |
302 | return -ENOSYS; |
303 | } | |
304 | ||
365bff80 | 305 | if (!size) { |
dbd51be0 | 306 | pr_warning("mtrr: zero sized request\n"); |
365bff80 JB |
307 | return -EINVAL; |
308 | } | |
309 | ||
1da177e4 | 310 | if (base & size_or_mask || size & size_or_mask) { |
dbd51be0 | 311 | pr_warning("mtrr: base or size exceeds the MTRR width\n"); |
1da177e4 LT |
312 | return -EINVAL; |
313 | } | |
314 | ||
315 | error = -EINVAL; | |
365bff80 | 316 | replace = -1; |
1da177e4 | 317 | |
3b520b23 | 318 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 319 | get_online_cpus(); |
dbd51be0 JSR |
320 | |
321 | /* Search for existing MTRR */ | |
14cc3e2b | 322 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
323 | for (i = 0; i < num_var_ranges; ++i) { |
324 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
dbd51be0 JSR |
325 | if (!lsize || base > lbase + lsize - 1 || |
326 | base + size - 1 < lbase) | |
1da177e4 | 327 | continue; |
dbd51be0 JSR |
328 | /* |
329 | * At this point we know there is some kind of | |
330 | * overlap/enclosure | |
331 | */ | |
365bff80 | 332 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
dbd51be0 JSR |
333 | if (base <= lbase && |
334 | base + size - 1 >= lbase + lsize - 1) { | |
365bff80 JB |
335 | /* New region encloses an existing region */ |
336 | if (type == ltype) { | |
337 | replace = replace == -1 ? i : -2; | |
338 | continue; | |
dbd51be0 | 339 | } else if (types_compatible(type, ltype)) |
365bff80 JB |
340 | continue; |
341 | } | |
dbd51be0 JSR |
342 | pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing" |
343 | " 0x%lx000,0x%lx000\n", base, size, lbase, | |
344 | lsize); | |
1da177e4 LT |
345 | goto out; |
346 | } | |
dbd51be0 | 347 | /* New region is enclosed by an existing region */ |
1da177e4 | 348 | if (ltype != type) { |
365bff80 | 349 | if (types_compatible(type, ltype)) |
1da177e4 | 350 | continue; |
dbd51be0 JSR |
351 | pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", |
352 | base, size, mtrr_attrib_to_str(ltype), | |
353 | mtrr_attrib_to_str(type)); | |
1da177e4 LT |
354 | goto out; |
355 | } | |
356 | if (increment) | |
99fc8d42 | 357 | ++mtrr_usage_table[i]; |
1da177e4 LT |
358 | error = i; |
359 | goto out; | |
360 | } | |
dbd51be0 | 361 | /* Search for an empty MTRR */ |
365bff80 | 362 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
363 | if (i >= 0) { |
364 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
365 | if (likely(replace < 0)) { |
366 | mtrr_usage_table[i] = 1; | |
367 | } else { | |
368 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 369 | if (increment) |
99fc8d42 | 370 | mtrr_usage_table[i]++; |
365bff80 JB |
371 | if (unlikely(replace != i)) { |
372 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 373 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
374 | } |
375 | } | |
dbd51be0 JSR |
376 | } else { |
377 | pr_info("mtrr: no more MTRRs available\n"); | |
378 | } | |
1da177e4 LT |
379 | error = i; |
380 | out: | |
14cc3e2b | 381 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 382 | put_online_cpus(); |
1da177e4 LT |
383 | return error; |
384 | } | |
385 | ||
c92c6ffd AM |
386 | static int mtrr_check(unsigned long base, unsigned long size) |
387 | { | |
388 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
dbd51be0 JSR |
389 | pr_warning("mtrr: size and base must be multiples of 4 kiB\n"); |
390 | pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
c92c6ffd AM |
391 | dump_stack(); |
392 | return -1; | |
393 | } | |
394 | return 0; | |
395 | } | |
396 | ||
1da177e4 | 397 | /** |
dbd51be0 JSR |
398 | * mtrr_add - Add a memory type region |
399 | * @base: Physical base address of region | |
400 | * @size: Physical size of region | |
401 | * @type: Type of MTRR desired | |
402 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 403 | * |
dbd51be0 JSR |
404 | * Memory type region registers control the caching on newer Intel and |
405 | * non Intel processors. This function allows drivers to request an | |
406 | * MTRR is added. The details and hardware specifics of each processor's | |
407 | * implementation are hidden from the caller, but nevertheless the | |
408 | * caller should expect to need to provide a power of two size on an | |
409 | * equivalent power of two boundary. | |
1da177e4 | 410 | * |
dbd51be0 JSR |
411 | * If the region cannot be added either because all regions are in use |
412 | * or the CPU cannot support it a negative value is returned. On success | |
413 | * the register number for this entry is returned, but should be treated | |
414 | * as a cookie only. | |
1da177e4 | 415 | * |
dbd51be0 JSR |
416 | * On a multiprocessor machine the changes are made to all processors. |
417 | * This is required on x86 by the Intel processors. | |
1da177e4 | 418 | * |
dbd51be0 | 419 | * The available types are |
1da177e4 | 420 | * |
dbd51be0 | 421 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 422 | * |
dbd51be0 | 423 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 424 | * |
dbd51be0 | 425 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 426 | * |
dbd51be0 | 427 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 428 | * |
dbd51be0 JSR |
429 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
430 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 431 | */ |
dbd51be0 JSR |
432 | int mtrr_add(unsigned long base, unsigned long size, unsigned int type, |
433 | bool increment) | |
1da177e4 | 434 | { |
c92c6ffd | 435 | if (mtrr_check(base, size)) |
1da177e4 | 436 | return -EINVAL; |
1da177e4 LT |
437 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
438 | increment); | |
439 | } | |
dbd51be0 | 440 | EXPORT_SYMBOL(mtrr_add); |
1da177e4 LT |
441 | |
442 | /** | |
dbd51be0 JSR |
443 | * mtrr_del_page - delete a memory type region |
444 | * @reg: Register returned by mtrr_add | |
445 | * @base: Physical base address | |
446 | * @size: Size of region | |
1da177e4 | 447 | * |
dbd51be0 JSR |
448 | * If register is supplied then base and size are ignored. This is |
449 | * how drivers should call it. | |
1da177e4 | 450 | * |
dbd51be0 JSR |
451 | * Releases an MTRR region. If the usage count drops to zero the |
452 | * register is freed and the region returns to default state. | |
453 | * On success the register is returned, on failure a negative error | |
454 | * code. | |
1da177e4 | 455 | */ |
1da177e4 LT |
456 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) |
457 | { | |
458 | int i, max; | |
459 | mtrr_type ltype; | |
365bff80 | 460 | unsigned long lbase, lsize; |
1da177e4 LT |
461 | int error = -EINVAL; |
462 | ||
463 | if (!mtrr_if) | |
464 | return -ENXIO; | |
465 | ||
466 | max = num_var_ranges; | |
3b520b23 | 467 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 468 | get_online_cpus(); |
14cc3e2b | 469 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
470 | if (reg < 0) { |
471 | /* Search for existing MTRR */ | |
472 | for (i = 0; i < max; ++i) { | |
473 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
474 | if (lbase == base && lsize == size) { | |
475 | reg = i; | |
476 | break; | |
477 | } | |
478 | } | |
479 | if (reg < 0) { | |
dbd51be0 JSR |
480 | pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n", |
481 | base, size); | |
1da177e4 LT |
482 | goto out; |
483 | } | |
484 | } | |
485 | if (reg >= max) { | |
dbd51be0 | 486 | pr_warning("mtrr: register: %d too big\n", reg); |
1da177e4 LT |
487 | goto out; |
488 | } | |
1da177e4 LT |
489 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
490 | if (lsize < 1) { | |
dbd51be0 | 491 | pr_warning("mtrr: MTRR %d not used\n", reg); |
1da177e4 LT |
492 | goto out; |
493 | } | |
99fc8d42 | 494 | if (mtrr_usage_table[reg] < 1) { |
dbd51be0 | 495 | pr_warning("mtrr: reg: %d has count=0\n", reg); |
1da177e4 LT |
496 | goto out; |
497 | } | |
99fc8d42 | 498 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
499 | set_mtrr(reg, 0, 0, 0); |
500 | error = reg; | |
501 | out: | |
14cc3e2b | 502 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 503 | put_online_cpus(); |
1da177e4 LT |
504 | return error; |
505 | } | |
dbd51be0 | 506 | |
1da177e4 | 507 | /** |
dbd51be0 JSR |
508 | * mtrr_del - delete a memory type region |
509 | * @reg: Register returned by mtrr_add | |
510 | * @base: Physical base address | |
511 | * @size: Size of region | |
1da177e4 | 512 | * |
dbd51be0 JSR |
513 | * If register is supplied then base and size are ignored. This is |
514 | * how drivers should call it. | |
1da177e4 | 515 | * |
dbd51be0 JSR |
516 | * Releases an MTRR region. If the usage count drops to zero the |
517 | * register is freed and the region returns to default state. | |
518 | * On success the register is returned, on failure a negative error | |
519 | * code. | |
1da177e4 | 520 | */ |
dbd51be0 | 521 | int mtrr_del(int reg, unsigned long base, unsigned long size) |
1da177e4 | 522 | { |
c92c6ffd | 523 | if (mtrr_check(base, size)) |
1da177e4 | 524 | return -EINVAL; |
1da177e4 LT |
525 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
526 | } | |
1da177e4 LT |
527 | EXPORT_SYMBOL(mtrr_del); |
528 | ||
dbd51be0 JSR |
529 | /* |
530 | * HACK ALERT! | |
1da177e4 LT |
531 | * These should be called implicitly, but we can't yet until all the initcall |
532 | * stuff is done... | |
533 | */ | |
1da177e4 LT |
534 | static void __init init_ifs(void) |
535 | { | |
475850c8 | 536 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
537 | amd_init_mtrr(); |
538 | cyrix_init_mtrr(); | |
539 | centaur_init_mtrr(); | |
475850c8 | 540 | #endif |
1da177e4 LT |
541 | } |
542 | ||
3b520b23 SL |
543 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
544 | * MTRR driver doesn't require this | |
545 | */ | |
1da177e4 LT |
546 | struct mtrr_value { |
547 | mtrr_type ltype; | |
548 | unsigned long lbase; | |
365bff80 | 549 | unsigned long lsize; |
1da177e4 LT |
550 | }; |
551 | ||
f0348c43 | 552 | static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; |
1da177e4 | 553 | |
f3c6ea1b | 554 | static int mtrr_save(void) |
1da177e4 LT |
555 | { |
556 | int i; | |
1da177e4 LT |
557 | |
558 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
559 | mtrr_if->get(i, &mtrr_value[i].lbase, |
560 | &mtrr_value[i].lsize, | |
561 | &mtrr_value[i].ltype); | |
1da177e4 LT |
562 | } |
563 | return 0; | |
564 | } | |
565 | ||
f3c6ea1b | 566 | static void mtrr_restore(void) |
1da177e4 LT |
567 | { |
568 | int i; | |
569 | ||
570 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
571 | if (mtrr_value[i].lsize) { |
572 | set_mtrr(i, mtrr_value[i].lbase, | |
573 | mtrr_value[i].lsize, | |
574 | mtrr_value[i].ltype); | |
575 | } | |
1da177e4 | 576 | } |
1da177e4 LT |
577 | } |
578 | ||
579 | ||
580 | ||
f3c6ea1b | 581 | static struct syscore_ops mtrr_syscore_ops = { |
1da177e4 LT |
582 | .suspend = mtrr_save, |
583 | .resume = mtrr_restore, | |
584 | }; | |
585 | ||
0d890355 | 586 | int __initdata changed_by_mtrr_cleanup; |
1da177e4 LT |
587 | |
588 | /** | |
3b520b23 | 589 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 | 590 | * |
dbd51be0 | 591 | * This needs to be called early; before any of the other CPUs are |
1da177e4 | 592 | * initialized (i.e. before smp_init()). |
dbd51be0 | 593 | * |
1da177e4 | 594 | */ |
9ef231a4 | 595 | void __init mtrr_bp_init(void) |
1da177e4 | 596 | { |
95ffa243 | 597 | u32 phys_addr; |
dbd51be0 | 598 | |
1da177e4 LT |
599 | init_ifs(); |
600 | ||
95ffa243 YL |
601 | phys_addr = 32; |
602 | ||
1da177e4 LT |
603 | if (cpu_has_mtrr) { |
604 | mtrr_if = &generic_mtrr_ops; | |
dbd51be0 | 605 | size_or_mask = 0xff000000; /* 36 bits */ |
1da177e4 | 606 | size_and_mask = 0x00f00000; |
95ffa243 | 607 | phys_addr = 36; |
1f2c958a | 608 | |
dbd51be0 JSR |
609 | /* |
610 | * This is an AMD specific MSR, but we assume(hope?) that | |
611 | * Intel will implement it to when they extend the address | |
612 | * bus of the Xeon. | |
613 | */ | |
1f2c958a | 614 | if (cpuid_eax(0x80000000) >= 0x80000008) { |
1f2c958a | 615 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
af9c142d SL |
616 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
617 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
618 | boot_cpu_data.x86 == 0xF && | |
619 | boot_cpu_data.x86_model == 0x3 && | |
620 | (boot_cpu_data.x86_mask == 0x3 || | |
621 | boot_cpu_data.x86_mask == 0x4)) | |
622 | phys_addr = 36; | |
623 | ||
6c5806ca AH |
624 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
625 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
626 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
627 | boot_cpu_data.x86 == 6) { | |
dbd51be0 JSR |
628 | /* |
629 | * VIA C* family have Intel style MTRRs, | |
630 | * but don't support PAE | |
631 | */ | |
632 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1f2c958a | 633 | size_and_mask = 0; |
95ffa243 | 634 | phys_addr = 32; |
1da177e4 LT |
635 | } |
636 | } else { | |
637 | switch (boot_cpu_data.x86_vendor) { | |
638 | case X86_VENDOR_AMD: | |
639 | if (cpu_has_k6_mtrr) { | |
640 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
641 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
642 | size_or_mask = 0xfff00000; /* 32 bits */ | |
643 | size_and_mask = 0; | |
644 | } | |
645 | break; | |
646 | case X86_VENDOR_CENTAUR: | |
647 | if (cpu_has_centaur_mcr) { | |
648 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
649 | size_or_mask = 0xfff00000; /* 32 bits */ | |
650 | size_and_mask = 0; | |
651 | } | |
652 | break; | |
653 | case X86_VENDOR_CYRIX: | |
654 | if (cpu_has_cyrix_arr) { | |
655 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
656 | size_or_mask = 0xfff00000; /* 32 bits */ | |
657 | size_and_mask = 0; | |
658 | } | |
659 | break; | |
660 | default: | |
661 | break; | |
662 | } | |
663 | } | |
1da177e4 LT |
664 | |
665 | if (mtrr_if) { | |
666 | set_num_var_ranges(); | |
667 | init_table(); | |
95ffa243 | 668 | if (use_intel()) { |
3b520b23 | 669 | get_mtrr_state(); |
95ffa243 | 670 | |
12031a62 YL |
671 | if (mtrr_cleanup(phys_addr)) { |
672 | changed_by_mtrr_cleanup = 1; | |
95ffa243 | 673 | mtrr_if->set_all(); |
12031a62 | 674 | } |
95ffa243 | 675 | } |
1da177e4 | 676 | } |
1da177e4 LT |
677 | } |
678 | ||
3b520b23 SL |
679 | void mtrr_ap_init(void) |
680 | { | |
d0af9eed | 681 | if (!use_intel() || mtrr_aps_delayed_init) |
3b520b23 SL |
682 | return; |
683 | /* | |
dbd51be0 JSR |
684 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries |
685 | * changed, but this routine will be called in cpu boot time, | |
686 | * holding the lock breaks it. | |
687 | * | |
688 | * This routine is called in two cases: | |
689 | * | |
690 | * 1. very earily time of software resume, when there absolutely | |
691 | * isn't mtrr entry changes; | |
692 | * | |
693 | * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug | |
694 | * lock to prevent mtrr entry changes | |
3b520b23 | 695 | */ |
192d8857 | 696 | set_mtrr_from_inactive_cpu(~0U, 0, 0, 0); |
3b520b23 SL |
697 | } |
698 | ||
2b1f6278 BK |
699 | /** |
700 | * Save current fixed-range MTRR state of the BSP | |
701 | */ | |
702 | void mtrr_save_state(void) | |
703 | { | |
8691e5a8 | 704 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1); |
2b1f6278 BK |
705 | } |
706 | ||
d0af9eed SS |
707 | void set_mtrr_aps_delayed_init(void) |
708 | { | |
709 | if (!use_intel()) | |
710 | return; | |
711 | ||
5400743d | 712 | mtrr_aps_delayed_init = true; |
d0af9eed SS |
713 | } |
714 | ||
715 | /* | |
f7448548 | 716 | * Delayed MTRR initialization for all AP's |
d0af9eed SS |
717 | */ |
718 | void mtrr_aps_init(void) | |
719 | { | |
720 | if (!use_intel()) | |
721 | return; | |
722 | ||
f7448548 SS |
723 | /* |
724 | * Check if someone has requested the delay of AP MTRR initialization, | |
725 | * by doing set_mtrr_aps_delayed_init(), prior to this point. If not, | |
726 | * then we are done. | |
727 | */ | |
728 | if (!mtrr_aps_delayed_init) | |
729 | return; | |
730 | ||
d0af9eed | 731 | set_mtrr(~0U, 0, 0, 0); |
5400743d | 732 | mtrr_aps_delayed_init = false; |
d0af9eed SS |
733 | } |
734 | ||
735 | void mtrr_bp_restore(void) | |
736 | { | |
737 | if (!use_intel()) | |
738 | return; | |
739 | ||
740 | mtrr_if->set_all(); | |
741 | } | |
742 | ||
3b520b23 SL |
743 | static int __init mtrr_init_finialize(void) |
744 | { | |
745 | if (!mtrr_if) | |
746 | return 0; | |
dbd51be0 | 747 | |
95ffa243 | 748 | if (use_intel()) { |
12031a62 | 749 | if (!changed_by_mtrr_cleanup) |
95ffa243 | 750 | mtrr_state_warn(); |
dbd51be0 | 751 | return 0; |
3b520b23 | 752 | } |
dbd51be0 JSR |
753 | |
754 | /* | |
755 | * The CPU has no MTRR and seems to not support SMP. They have | |
756 | * specific drivers, we use a tricky method to support | |
757 | * suspend/resume for them. | |
758 | * | |
759 | * TBD: is there any system with such CPU which supports | |
760 | * suspend/resume? If no, we should remove the code. | |
761 | */ | |
f3c6ea1b | 762 | register_syscore_ops(&mtrr_syscore_ops); |
dbd51be0 | 763 | |
3b520b23 SL |
764 | return 0; |
765 | } | |
766 | subsys_initcall(mtrr_init_finialize); |