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perf_counter tools: Normalize data using per sample period data
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_counter.c
CommitLineData
241771ef
IM		 1/*
2 * Performance counter x86 architecture code
3 *
98144511
IM		 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
241771ef
IM		 9 *
10 * For licencing details see kernel-base/COPYING
11 */
12
13#include <linux/perf_counter.h>
14#include <linux/capability.h>
15#include <linux/notifier.h>
16#include <linux/hardirq.h>
17#include <linux/kprobes.h>
4ac13294 18#include <linux/module.h>
241771ef
IM		 19#include <linux/kdebug.h>
20#include <linux/sched.h>
d7d59fb3 21#include <linux/uaccess.h>
241771ef 22
241771ef 23#include <asm/apic.h>
d7d59fb3 24#include <asm/stacktrace.h>
4e935e47 25#include <asm/nmi.h>
241771ef 26
862a1a5f 27static u64 perf_counter_mask __read_mostly;
703e937c 28
241771ef 29struct cpu_hw_counters {
862a1a5f 30 struct perf_counter *counters[X86_PMC_IDX_MAX];
43f6201a
RR		 31 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
32 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
4b39fd96 33 unsigned long interrupts;
b0f3f28e 34 int enabled;
241771ef
IM		 35};
36
37/*
5f4ec28f 38 * struct x86_pmu - generic x86 pmu
241771ef 39 */
5f4ec28f 40struct x86_pmu {
faa28ae0
RR		 41 const char *name;
42 int version;
a3288106 43 int (*handle_irq)(struct pt_regs *);
9e35ad38
PZ		 44 void (*disable_all)(void);
45 void (*enable_all)(void);
7c90cc45 46 void (*enable)(struct hw_perf_counter *, int);
d4369891 47 void (*disable)(struct hw_perf_counter *, int);
169e41eb
JSR		 48 unsigned eventsel;
49 unsigned perfctr;
b0f3f28e
PZ		 50 u64 (*event_map)(int);
51 u64 (*raw_event)(u64);
169e41eb 52 int max_events;
0933e5c6
RR		 53 int num_counters;
54 int num_counters_fixed;
55 int counter_bits;
56 u64 counter_mask;
c619b8ff 57 u64 max_period;
9e35ad38 58 u64 intel_ctrl;
b56a3802
JSR		 59};
60
4a06bd85 61static struct x86_pmu x86_pmu __read_mostly;
b56a3802 62
b0f3f28e
PZ		 63static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
64 .enabled = 1,
65};
241771ef 66
b56a3802
JSR		 67/*
68 * Intel PerfMon v3. Used on Core2 and later.
69 */
b0f3f28e 70static const u64 intel_perfmon_event_map[] =
241771ef 71{
f650a672 72 [PERF_COUNT_CPU_CYCLES] = 0x003c,
241771ef
IM		 73 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
f650a672 78 [PERF_COUNT_BUS_CYCLES] = 0x013c,
241771ef
IM		 79};
80
5f4ec28f 81static u64 intel_pmu_event_map(int event)
b56a3802
JSR		 82{
83 return intel_perfmon_event_map[event];
84}
241771ef 85
8326f44d
IM		 86/*
87 * Generalized hw caching related event table, filled
88 * in on a per model basis. A value of 0 means
89 * 'not supported', -1 means 'event makes no sense on
90 * this CPU', any other value means the raw event
91 * ID.
92 */
93
94#define C(x) PERF_COUNT_HW_CACHE_##x
95
96static u64 __read_mostly hw_cache_event_ids
97 [PERF_COUNT_HW_CACHE_MAX]
98 [PERF_COUNT_HW_CACHE_OP_MAX]
99 [PERF_COUNT_HW_CACHE_RESULT_MAX];
100
101static const u64 nehalem_hw_cache_event_ids
102 [PERF_COUNT_HW_CACHE_MAX]
103 [PERF_COUNT_HW_CACHE_OP_MAX]
104 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
105{
106 [ C(L1D) ] = {
107 [ C(OP_READ) ] = {
108 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
109 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
110 },
111 [ C(OP_WRITE) ] = {
112 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
113 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
114 },
115 [ C(OP_PREFETCH) ] = {
116 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
117 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
118 },
119 },
120 [ C(L1I ) ] = {
121 [ C(OP_READ) ] = {
fecc8ac8 122 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
8326f44d
IM		 123 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
124 },
125 [ C(OP_WRITE) ] = {
126 [ C(RESULT_ACCESS) ] = -1,
127 [ C(RESULT_MISS) ] = -1,
128 },
129 [ C(OP_PREFETCH) ] = {
130 [ C(RESULT_ACCESS) ] = 0x0,
131 [ C(RESULT_MISS) ] = 0x0,
132 },
133 },
134 [ C(L2 ) ] = {
135 [ C(OP_READ) ] = {
136 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
137 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
138 },
139 [ C(OP_WRITE) ] = {
140 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
141 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
142 },
143 [ C(OP_PREFETCH) ] = {
144 [ C(RESULT_ACCESS) ] = 0xc024, /* L2_RQSTS.PREFETCHES */
145 [ C(RESULT_MISS) ] = 0x8024, /* L2_RQSTS.PREFETCH_MISS */
146 },
147 },
148 [ C(DTLB) ] = {
149 [ C(OP_READ) ] = {
150 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
151 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
152 },
153 [ C(OP_WRITE) ] = {
154 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
155 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
156 },
157 [ C(OP_PREFETCH) ] = {
158 [ C(RESULT_ACCESS) ] = 0x0,
159 [ C(RESULT_MISS) ] = 0x0,
160 },
161 },
162 [ C(ITLB) ] = {
163 [ C(OP_READ) ] = {
164 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
fecc8ac8 165 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
8326f44d
IM		 166 },
167 [ C(OP_WRITE) ] = {
168 [ C(RESULT_ACCESS) ] = -1,
169 [ C(RESULT_MISS) ] = -1,
170 },
171 [ C(OP_PREFETCH) ] = {
172 [ C(RESULT_ACCESS) ] = -1,
173 [ C(RESULT_MISS) ] = -1,
174 },
175 },
176 [ C(BPU ) ] = {
177 [ C(OP_READ) ] = {
178 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
179 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
180 },
181 [ C(OP_WRITE) ] = {
182 [ C(RESULT_ACCESS) ] = -1,
183 [ C(RESULT_MISS) ] = -1,
184 },
185 [ C(OP_PREFETCH) ] = {
186 [ C(RESULT_ACCESS) ] = -1,
187 [ C(RESULT_MISS) ] = -1,
188 },
189 },
190};
191
192static const u64 core2_hw_cache_event_ids
193 [PERF_COUNT_HW_CACHE_MAX]
194 [PERF_COUNT_HW_CACHE_OP_MAX]
195 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
196{
0312af84
TG		 197 [ C(L1D) ] = {
198 [ C(OP_READ) ] = {
199 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
200 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
201 },
202 [ C(OP_WRITE) ] = {
203 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
204 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
205 },
206 [ C(OP_PREFETCH) ] = {
207 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
208 [ C(RESULT_MISS) ] = 0,
209 },
210 },
211 [ C(L1I ) ] = {
212 [ C(OP_READ) ] = {
213 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
214 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
215 },
216 [ C(OP_WRITE) ] = {
217 [ C(RESULT_ACCESS) ] = -1,
218 [ C(RESULT_MISS) ] = -1,
219 },
220 [ C(OP_PREFETCH) ] = {
221 [ C(RESULT_ACCESS) ] = 0,
222 [ C(RESULT_MISS) ] = 0,
223 },
224 },
225 [ C(L2 ) ] = {
226 [ C(OP_READ) ] = {
227 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
228 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
229 },
230 [ C(OP_WRITE) ] = {
231 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
232 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
233 },
234 [ C(OP_PREFETCH) ] = {
235 [ C(RESULT_ACCESS) ] = 0,
236 [ C(RESULT_MISS) ] = 0,
237 },
238 },
239 [ C(DTLB) ] = {
240 [ C(OP_READ) ] = {
241 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
242 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
243 },
244 [ C(OP_WRITE) ] = {
245 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
246 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
247 },
248 [ C(OP_PREFETCH) ] = {
249 [ C(RESULT_ACCESS) ] = 0,
250 [ C(RESULT_MISS) ] = 0,
251 },
252 },
253 [ C(ITLB) ] = {
254 [ C(OP_READ) ] = {
255 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
256 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
257 },
258 [ C(OP_WRITE) ] = {
259 [ C(RESULT_ACCESS) ] = -1,
260 [ C(RESULT_MISS) ] = -1,
261 },
262 [ C(OP_PREFETCH) ] = {
263 [ C(RESULT_ACCESS) ] = -1,
264 [ C(RESULT_MISS) ] = -1,
265 },
266 },
267 [ C(BPU ) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
270 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
271 },
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = -1,
274 [ C(RESULT_MISS) ] = -1,
275 },
276 [ C(OP_PREFETCH) ] = {
277 [ C(RESULT_ACCESS) ] = -1,
278 [ C(RESULT_MISS) ] = -1,
279 },
280 },
8326f44d
IM		 281};
282
283static const u64 atom_hw_cache_event_ids
284 [PERF_COUNT_HW_CACHE_MAX]
285 [PERF_COUNT_HW_CACHE_OP_MAX]
286 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
287{
ad689220
TG		 288 [ C(L1D) ] = {
289 [ C(OP_READ) ] = {
290 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
291 [ C(RESULT_MISS) ] = 0,
292 },
293 [ C(OP_WRITE) ] = {
fecc8ac8 294 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
ad689220
TG		 295 [ C(RESULT_MISS) ] = 0,
296 },
297 [ C(OP_PREFETCH) ] = {
298 [ C(RESULT_ACCESS) ] = 0x0,
299 [ C(RESULT_MISS) ] = 0,
300 },
301 },
302 [ C(L1I ) ] = {
303 [ C(OP_READ) ] = {
fecc8ac8
YW		 304 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
305 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
ad689220
TG		 306 },
307 [ C(OP_WRITE) ] = {
308 [ C(RESULT_ACCESS) ] = -1,
309 [ C(RESULT_MISS) ] = -1,
310 },
311 [ C(OP_PREFETCH) ] = {
312 [ C(RESULT_ACCESS) ] = 0,
313 [ C(RESULT_MISS) ] = 0,
314 },
315 },
316 [ C(L2 ) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
319 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
320 },
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
323 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
324 },
325 [ C(OP_PREFETCH) ] = {
326 [ C(RESULT_ACCESS) ] = 0,
327 [ C(RESULT_MISS) ] = 0,
328 },
329 },
330 [ C(DTLB) ] = {
331 [ C(OP_READ) ] = {
fecc8ac8 332 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
ad689220
TG		 333 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
334 },
335 [ C(OP_WRITE) ] = {
fecc8ac8 336 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
ad689220
TG		 337 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
338 },
339 [ C(OP_PREFETCH) ] = {
340 [ C(RESULT_ACCESS) ] = 0,
341 [ C(RESULT_MISS) ] = 0,
342 },
343 },
344 [ C(ITLB) ] = {
345 [ C(OP_READ) ] = {
346 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
347 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
348 },
349 [ C(OP_WRITE) ] = {
350 [ C(RESULT_ACCESS) ] = -1,
351 [ C(RESULT_MISS) ] = -1,
352 },
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = -1,
355 [ C(RESULT_MISS) ] = -1,
356 },
357 },
358 [ C(BPU ) ] = {
359 [ C(OP_READ) ] = {
360 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
361 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
362 },
363 [ C(OP_WRITE) ] = {
364 [ C(RESULT_ACCESS) ] = -1,
365 [ C(RESULT_MISS) ] = -1,
366 },
367 [ C(OP_PREFETCH) ] = {
368 [ C(RESULT_ACCESS) ] = -1,
369 [ C(RESULT_MISS) ] = -1,
370 },
371 },
8326f44d
IM		 372};
373
5f4ec28f 374static u64 intel_pmu_raw_event(u64 event)
b0f3f28e 375{
82bae4f8
PZ		 376#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
377#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
ff99be57
PZ		 378#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
379#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
82bae4f8 380#define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
b0f3f28e 381
128f048f 382#define CORE_EVNTSEL_MASK \
b0f3f28e
PZ		 383 (CORE_EVNTSEL_EVENT_MASK | \
384 CORE_EVNTSEL_UNIT_MASK | \
ff99be57
PZ		 385 CORE_EVNTSEL_EDGE_MASK | \
386 CORE_EVNTSEL_INV_MASK | \
b0f3f28e
PZ		 387 CORE_EVNTSEL_COUNTER_MASK)
388
389 return event & CORE_EVNTSEL_MASK;
390}
391
f86748e9
TG		 392static const u64 amd_0f_hw_cache_event_ids
393 [PERF_COUNT_HW_CACHE_MAX]
394 [PERF_COUNT_HW_CACHE_OP_MAX]
395 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
396{
397 [ C(L1D) ] = {
398 [ C(OP_READ) ] = {
399 [ C(RESULT_ACCESS) ] = 0,
400 [ C(RESULT_MISS) ] = 0,
401 },
402 [ C(OP_WRITE) ] = {
403 [ C(RESULT_ACCESS) ] = 0,
404 [ C(RESULT_MISS) ] = 0,
405 },
406 [ C(OP_PREFETCH) ] = {
407 [ C(RESULT_ACCESS) ] = 0,
408 [ C(RESULT_MISS) ] = 0,
409 },
410 },
411 [ C(L1I ) ] = {
412 [ C(OP_READ) ] = {
413 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
414 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
415 },
416 [ C(OP_WRITE) ] = {
417 [ C(RESULT_ACCESS) ] = -1,
418 [ C(RESULT_MISS) ] = -1,
419 },
420 [ C(OP_PREFETCH) ] = {
421 [ C(RESULT_ACCESS) ] = 0,
422 [ C(RESULT_MISS) ] = 0,
423 },
424 },
425 [ C(L2 ) ] = {
426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0,
428 [ C(RESULT_MISS) ] = 0,
429 },
430 [ C(OP_WRITE) ] = {
431 [ C(RESULT_ACCESS) ] = 0,
432 [ C(RESULT_MISS) ] = 0,
433 },
434 [ C(OP_PREFETCH) ] = {
435 [ C(RESULT_ACCESS) ] = 0,
436 [ C(RESULT_MISS) ] = 0,
437 },
438 },
439 [ C(DTLB) ] = {
440 [ C(OP_READ) ] = {
441 [ C(RESULT_ACCESS) ] = 0,
442 [ C(RESULT_MISS) ] = 0,
443 },
444 [ C(OP_WRITE) ] = {
445 [ C(RESULT_ACCESS) ] = 0,
446 [ C(RESULT_MISS) ] = 0,
447 },
448 [ C(OP_PREFETCH) ] = {
449 [ C(RESULT_ACCESS) ] = 0,
450 [ C(RESULT_MISS) ] = 0,
451 },
452 },
453 [ C(ITLB) ] = {
454 [ C(OP_READ) ] = {
455 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
456 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
457 },
458 [ C(OP_WRITE) ] = {
459 [ C(RESULT_ACCESS) ] = -1,
460 [ C(RESULT_MISS) ] = -1,
461 },
462 [ C(OP_PREFETCH) ] = {
463 [ C(RESULT_ACCESS) ] = -1,
464 [ C(RESULT_MISS) ] = -1,
465 },
466 },
467 [ C(BPU ) ] = {
468 [ C(OP_READ) ] = {
469 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
470 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
471 },
472 [ C(OP_WRITE) ] = {
473 [ C(RESULT_ACCESS) ] = -1,
474 [ C(RESULT_MISS) ] = -1,
475 },
476 [ C(OP_PREFETCH) ] = {
477 [ C(RESULT_ACCESS) ] = -1,
478 [ C(RESULT_MISS) ] = -1,
479 },
480 },
481};
482
f87ad35d
JSR		 483/*
484 * AMD Performance Monitor K7 and later.
485 */
b0f3f28e 486static const u64 amd_perfmon_event_map[] =
f87ad35d
JSR		 487{
488 [PERF_COUNT_CPU_CYCLES] = 0x0076,
489 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
490 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
491 [PERF_COUNT_CACHE_MISSES] = 0x0081,
492 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
493 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
494};
495
5f4ec28f 496static u64 amd_pmu_event_map(int event)
f87ad35d
JSR		 497{
498 return amd_perfmon_event_map[event];
499}
500
5f4ec28f 501static u64 amd_pmu_raw_event(u64 event)
b0f3f28e 502{
82bae4f8
PZ		 503#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
504#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
ff99be57
PZ		 505#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
506#define K7_EVNTSEL_INV_MASK 0x000800000ULL
82bae4f8 507#define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
b0f3f28e
PZ		 508
509#define K7_EVNTSEL_MASK \
510 (K7_EVNTSEL_EVENT_MASK | \
511 K7_EVNTSEL_UNIT_MASK | \
ff99be57
PZ		 512 K7_EVNTSEL_EDGE_MASK | \
513 K7_EVNTSEL_INV_MASK | \
b0f3f28e
PZ		 514 K7_EVNTSEL_COUNTER_MASK)
515
516 return event & K7_EVNTSEL_MASK;
517}
518
ee06094f
IM		 519/*
520 * Propagate counter elapsed time into the generic counter.
521 * Can only be executed on the CPU where the counter is active.
522 * Returns the delta events processed.
523 */
4b7bfd0d 524static u64
ee06094f
IM		 525x86_perf_counter_update(struct perf_counter *counter,
526 struct hw_perf_counter *hwc, int idx)
527{
ec3232bd
PZ		 528 int shift = 64 - x86_pmu.counter_bits;
529 u64 prev_raw_count, new_raw_count;
530 s64 delta;
ee06094f 531
ee06094f
IM		 532 /*
533 * Careful: an NMI might modify the previous counter value.
534 *
535 * Our tactic to handle this is to first atomically read and
536 * exchange a new raw count - then add that new-prev delta
537 * count to the generic counter atomically:
538 */
539again:
540 prev_raw_count = atomic64_read(&hwc->prev_count);
541 rdmsrl(hwc->counter_base + idx, new_raw_count);
542
543 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
544 new_raw_count) != prev_raw_count)
545 goto again;
546
547 /*
548 * Now we have the new raw value and have updated the prev
549 * timestamp already. We can now calculate the elapsed delta
550 * (counter-)time and add that to the generic counter.
551 *
552 * Careful, not all hw sign-extends above the physical width
ec3232bd 553 * of the count.
ee06094f 554 */
ec3232bd
PZ		 555 delta = (new_raw_count << shift) - (prev_raw_count << shift);
556 delta >>= shift;
ee06094f
IM		 557
558 atomic64_add(delta, &counter->count);
559 atomic64_sub(delta, &hwc->period_left);
4b7bfd0d
RR		 560
561 return new_raw_count;
ee06094f
IM		 562}
563
ba77813a 564static atomic_t active_counters;
4e935e47
PZ		 565static DEFINE_MUTEX(pmc_reserve_mutex);
566
567static bool reserve_pmc_hardware(void)
568{
569 int i;
570
571 if (nmi_watchdog == NMI_LOCAL_APIC)
572 disable_lapic_nmi_watchdog();
573
0933e5c6 574 for (i = 0; i < x86_pmu.num_counters; i++) {
4a06bd85 575 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
4e935e47
PZ		 576 goto perfctr_fail;
577 }
578
0933e5c6 579 for (i = 0; i < x86_pmu.num_counters; i++) {
4a06bd85 580 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
4e935e47
PZ		 581 goto eventsel_fail;
582 }
583
584 return true;
585
586eventsel_fail:
587 for (i--; i >= 0; i--)
4a06bd85 588 release_evntsel_nmi(x86_pmu.eventsel + i);
4e935e47 589
0933e5c6 590 i = x86_pmu.num_counters;
4e935e47
PZ		 591
592perfctr_fail:
593 for (i--; i >= 0; i--)
4a06bd85 594 release_perfctr_nmi(x86_pmu.perfctr + i);
4e935e47
PZ		 595
596 if (nmi_watchdog == NMI_LOCAL_APIC)
597 enable_lapic_nmi_watchdog();
598
599 return false;
600}
601
602static void release_pmc_hardware(void)
603{
604 int i;
605
0933e5c6 606 for (i = 0; i < x86_pmu.num_counters; i++) {
4a06bd85
RR		 607 release_perfctr_nmi(x86_pmu.perfctr + i);
608 release_evntsel_nmi(x86_pmu.eventsel + i);
4e935e47
PZ		 609 }
610
611 if (nmi_watchdog == NMI_LOCAL_APIC)
612 enable_lapic_nmi_watchdog();
613}
614
615static void hw_perf_counter_destroy(struct perf_counter *counter)
616{
ba77813a 617 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
4e935e47
PZ		 618 release_pmc_hardware();
619 mutex_unlock(&pmc_reserve_mutex);
620 }
621}
622
85cf9dba
RR		 623static inline int x86_pmu_initialized(void)
624{
625 return x86_pmu.handle_irq != NULL;
626}
627
8326f44d
IM		 628static inline int
629set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
630{
631 unsigned int cache_type, cache_op, cache_result;
632 u64 config, val;
633
634 config = attr->config;
635
636 cache_type = (config >> 0) & 0xff;
637 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
638 return -EINVAL;
639
640 cache_op = (config >> 8) & 0xff;
641 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
642 return -EINVAL;
643
644 cache_result = (config >> 16) & 0xff;
645 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
646 return -EINVAL;
647
648 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
649
650 if (val == 0)
651 return -ENOENT;
652
653 if (val == -1)
654 return -EINVAL;
655
656 hwc->config |= val;
657
658 return 0;
659}
660
241771ef 661/*
0d48696f 662 * Setup the hardware configuration for a given attr_type
241771ef 663 */
621a01ea 664static int __hw_perf_counter_init(struct perf_counter *counter)
241771ef 665{
0d48696f 666 struct perf_counter_attr *attr = &counter->attr;
241771ef 667 struct hw_perf_counter *hwc = &counter->hw;
4e935e47 668 int err;
241771ef 669
85cf9dba
RR		 670 if (!x86_pmu_initialized())
671 return -ENODEV;
241771ef 672
4e935e47 673 err = 0;
ba77813a 674 if (!atomic_inc_not_zero(&active_counters)) {
4e935e47 675 mutex_lock(&pmc_reserve_mutex);
ba77813a 676 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
4e935e47
PZ		 677 err = -EBUSY;
678 else
ba77813a 679 atomic_inc(&active_counters);
4e935e47
PZ		 680 mutex_unlock(&pmc_reserve_mutex);
681 }
682 if (err)
683 return err;
684
241771ef 685 /*
0475f9ea 686 * Generate PMC IRQs:
241771ef
IM		 687 * (keep 'enabled' bit clear for now)
688 */
0475f9ea 689 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
241771ef
IM		 690
691 /*
0475f9ea 692 * Count user and OS events unless requested not to.
241771ef 693 */
0d48696f 694 if (!attr->exclude_user)
0475f9ea 695 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
0d48696f 696 if (!attr->exclude_kernel)
241771ef 697 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
0475f9ea 698
bd2b5b12 699 if (!hwc->sample_period) {
b23f3325 700 hwc->sample_period = x86_pmu.max_period;
bd2b5b12
PZ		 701 atomic64_set(&hwc->period_left, hwc->sample_period);
702 }
d2517a49 703
8326f44d 704 counter->destroy = hw_perf_counter_destroy;
241771ef
IM		 705
706 /*
dfa7c899 707 * Raw event type provide the config in the event structure
241771ef 708 */
a21ca2ca
IM		 709 if (attr->type == PERF_TYPE_RAW) {
710 hwc->config |= x86_pmu.raw_event(attr->config);
8326f44d 711 return 0;
241771ef 712 }
241771ef 713
8326f44d
IM		 714 if (attr->type == PERF_TYPE_HW_CACHE)
715 return set_ext_hw_attr(hwc, attr);
716
717 if (attr->config >= x86_pmu.max_events)
718 return -EINVAL;
719 /*
720 * The generic map:
721 */
722 hwc->config |= x86_pmu.event_map(attr->config);
4e935e47 723
241771ef
IM		 724 return 0;
725}
726
9e35ad38 727static void intel_pmu_disable_all(void)
4ac13294 728{
862a1a5f 729 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
241771ef 730}
b56a3802 731
9e35ad38 732static void amd_pmu_disable_all(void)
f87ad35d 733{
b0f3f28e 734 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
9e35ad38
PZ		 735 int idx;
736
737 if (!cpuc->enabled)
738 return;
b0f3f28e 739
b0f3f28e 740 cpuc->enabled = 0;
60b3df9c
PZ		 741 /*
742 * ensure we write the disable before we start disabling the
5f4ec28f
RR		 743 * counters proper, so that amd_pmu_enable_counter() does the
744 * right thing.
60b3df9c 745 */
b0f3f28e 746 barrier();
f87ad35d 747
0933e5c6 748 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
b0f3f28e
PZ		 749 u64 val;
750
43f6201a 751 if (!test_bit(idx, cpuc->active_mask))
4295ee62 752 continue;
f87ad35d 753 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
4295ee62
RR		 754 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
755 continue;
756 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
757 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
f87ad35d 758 }
f87ad35d
JSR		 759}
760
9e35ad38 761void hw_perf_disable(void)
b56a3802 762{
85cf9dba 763 if (!x86_pmu_initialized())
9e35ad38
PZ		 764 return;
765 return x86_pmu.disable_all();
b56a3802 766}
241771ef 767
9e35ad38 768static void intel_pmu_enable_all(void)
b56a3802 769{
9e35ad38 770 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
b56a3802
JSR		 771}
772
9e35ad38 773static void amd_pmu_enable_all(void)
f87ad35d 774{
b0f3f28e 775 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
f87ad35d
JSR		 776 int idx;
777
9e35ad38 778 if (cpuc->enabled)
b0f3f28e
PZ		 779 return;
780
9e35ad38
PZ		 781 cpuc->enabled = 1;
782 barrier();
783
0933e5c6 784 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
4295ee62 785 u64 val;
b0f3f28e 786
43f6201a 787 if (!test_bit(idx, cpuc->active_mask))
4295ee62
RR		 788 continue;
789 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
790 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
791 continue;
792 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
793 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
f87ad35d
JSR		 794 }
795}
796
9e35ad38 797void hw_perf_enable(void)
ee06094f 798{
85cf9dba 799 if (!x86_pmu_initialized())
2b9ff0db 800 return;
9e35ad38 801 x86_pmu.enable_all();
ee06094f 802}
ee06094f 803
19d84dab 804static inline u64 intel_pmu_get_status(void)
b0f3f28e
PZ		 805{
806 u64 status;
807
b7f8859a 808 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
b0f3f28e 809
b7f8859a 810 return status;
b0f3f28e
PZ		 811}
812
dee5d906 813static inline void intel_pmu_ack_status(u64 ack)
b0f3f28e
PZ		 814{
815 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
816}
817
7c90cc45 818static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
b0f3f28e 819{
7c90cc45 820 int err;
7c90cc45
RR		 821 err = checking_wrmsrl(hwc->config_base + idx,
822 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
b0f3f28e
PZ		 823}
824
d4369891 825static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
b0f3f28e 826{
d4369891 827 int err;
d4369891
RR		 828 err = checking_wrmsrl(hwc->config_base + idx,
829 hwc->config);
b0f3f28e
PZ		 830}
831
2f18d1e8 832static inline void
d4369891 833intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
2f18d1e8
IM		 834{
835 int idx = __idx - X86_PMC_IDX_FIXED;
836 u64 ctrl_val, mask;
837 int err;
838
839 mask = 0xfULL << (idx * 4);
840
841 rdmsrl(hwc->config_base, ctrl_val);
842 ctrl_val &= ~mask;
843 err = checking_wrmsrl(hwc->config_base, ctrl_val);
844}
845
7e2ae347 846static inline void
d4369891 847intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
7e2ae347 848{
d4369891
RR		 849 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
850 intel_pmu_disable_fixed(hwc, idx);
851 return;
852 }
853
854 x86_pmu_disable_counter(hwc, idx);
855}
856
857static inline void
858amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
859{
860 x86_pmu_disable_counter(hwc, idx);
7e2ae347
IM		 861}
862
2f18d1e8 863static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
241771ef 864
ee06094f
IM		 865/*
866 * Set the next IRQ period, based on the hwc->period_left value.
867 * To be called with the counter disabled in hw:
868 */
e4abb5d4 869static int
26816c28 870x86_perf_counter_set_period(struct perf_counter *counter,
ee06094f 871 struct hw_perf_counter *hwc, int idx)
241771ef 872{
2f18d1e8 873 s64 left = atomic64_read(&hwc->period_left);
e4abb5d4
PZ		 874 s64 period = hwc->sample_period;
875 int err, ret = 0;
ee06094f 876
ee06094f
IM		 877 /*
878 * If we are way outside a reasoable range then just skip forward:
879 */
880 if (unlikely(left <= -period)) {
881 left = period;
882 atomic64_set(&hwc->period_left, left);
e4abb5d4 883 ret = 1;
ee06094f
IM		 884 }
885
886 if (unlikely(left <= 0)) {
887 left += period;
888 atomic64_set(&hwc->period_left, left);
e4abb5d4 889 ret = 1;
ee06094f 890 }
1c80f4b5
IM		 891 /*
892 * Quirk: certain CPUs dont like it if just 1 event is left:
893 */
894 if (unlikely(left < 2))
895 left = 2;
241771ef 896
e4abb5d4
PZ		 897 if (left > x86_pmu.max_period)
898 left = x86_pmu.max_period;
899
ee06094f
IM		 900 per_cpu(prev_left[idx], smp_processor_id()) = left;
901
902 /*
903 * The hw counter starts counting from this counter offset,
904 * mark it to be able to extra future deltas:
905 */
2f18d1e8 906 atomic64_set(&hwc->prev_count, (u64)-left);
ee06094f 907
2f18d1e8 908 err = checking_wrmsrl(hwc->counter_base + idx,
0933e5c6 909 (u64)(-left) & x86_pmu.counter_mask);
e4abb5d4
PZ		 910
911 return ret;
2f18d1e8
IM		 912}
913
914static inline void
7c90cc45 915intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
2f18d1e8
IM		 916{
917 int idx = __idx - X86_PMC_IDX_FIXED;
918 u64 ctrl_val, bits, mask;
919 int err;
920
921 /*
0475f9ea
PM		 922 * Enable IRQ generation (0x8),
923 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
924 * if requested:
2f18d1e8 925 */
0475f9ea
PM		 926 bits = 0x8ULL;
927 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
928 bits |= 0x2;
2f18d1e8
IM		 929 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
930 bits |= 0x1;
931 bits <<= (idx * 4);
932 mask = 0xfULL << (idx * 4);
933
934 rdmsrl(hwc->config_base, ctrl_val);
935 ctrl_val &= ~mask;
936 ctrl_val |= bits;
937 err = checking_wrmsrl(hwc->config_base, ctrl_val);
7e2ae347
IM		 938}
939
7c90cc45 940static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
7e2ae347 941{
7c90cc45
RR		 942 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
943 intel_pmu_enable_fixed(hwc, idx);
944 return;
945 }
946
947 x86_pmu_enable_counter(hwc, idx);
948}
949
950static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
951{
952 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
953
954 if (cpuc->enabled)
955 x86_pmu_enable_counter(hwc, idx);
2b583d8b 956 else
d4369891 957 x86_pmu_disable_counter(hwc, idx);
241771ef
IM		 958}
959
2f18d1e8
IM		 960static int
961fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
862a1a5f 962{
2f18d1e8
IM		 963 unsigned int event;
964
ef7b3e09 965 if (!x86_pmu.num_counters_fixed)
f87ad35d
JSR		 966 return -1;
967
2f18d1e8
IM		 968 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
969
4a06bd85 970 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
2f18d1e8 971 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
4a06bd85 972 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
2f18d1e8 973 return X86_PMC_IDX_FIXED_CPU_CYCLES;
4a06bd85 974 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
2f18d1e8
IM		 975 return X86_PMC_IDX_FIXED_BUS_CYCLES;
976
862a1a5f
IM		 977 return -1;
978}
979
ee06094f
IM		 980/*
981 * Find a PMC slot for the freshly enabled / scheduled in counter:
982 */
4aeb0b42 983static int x86_pmu_enable(struct perf_counter *counter)
241771ef
IM		 984{
985 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
986 struct hw_perf_counter *hwc = &counter->hw;
2f18d1e8 987 int idx;
241771ef 988
2f18d1e8
IM		 989 idx = fixed_mode_idx(counter, hwc);
990 if (idx >= 0) {
991 /*
992 * Try to get the fixed counter, if that is already taken
993 * then try to get a generic counter:
994 */
43f6201a 995 if (test_and_set_bit(idx, cpuc->used_mask))
2f18d1e8 996 goto try_generic;
0dff86aa 997
2f18d1e8
IM		 998 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
999 /*
1000 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1001 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1002 */
1003 hwc->counter_base =
1004 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
241771ef 1005 hwc->idx = idx;
2f18d1e8
IM		 1006 } else {
1007 idx = hwc->idx;
1008 /* Try to get the previous generic counter again */
43f6201a 1009 if (test_and_set_bit(idx, cpuc->used_mask)) {
2f18d1e8 1010try_generic:
43f6201a 1011 idx = find_first_zero_bit(cpuc->used_mask,
0933e5c6
RR		 1012 x86_pmu.num_counters);
1013 if (idx == x86_pmu.num_counters)
2f18d1e8
IM		 1014 return -EAGAIN;
1015
43f6201a 1016 set_bit(idx, cpuc->used_mask);
2f18d1e8
IM		 1017 hwc->idx = idx;
1018 }
4a06bd85
RR		 1019 hwc->config_base = x86_pmu.eventsel;
1020 hwc->counter_base = x86_pmu.perfctr;
241771ef
IM		 1021 }
1022
c323d95f 1023 perf_counters_lapic_init();
53b441a5 1024
d4369891 1025 x86_pmu.disable(hwc, idx);
241771ef 1026
862a1a5f 1027 cpuc->counters[idx] = counter;
43f6201a 1028 set_bit(idx, cpuc->active_mask);
7e2ae347 1029
26816c28 1030 x86_perf_counter_set_period(counter, hwc, idx);
7c90cc45 1031 x86_pmu.enable(hwc, idx);
95cdd2e7
IM		 1032
1033 return 0;
241771ef
IM		 1034}
1035
a78ac325
PZ		 1036static void x86_pmu_unthrottle(struct perf_counter *counter)
1037{
1038 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1039 struct hw_perf_counter *hwc = &counter->hw;
1040
1041 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1042 cpuc->counters[hwc->idx] != counter))
1043 return;
1044
1045 x86_pmu.enable(hwc, hwc->idx);
1046}
1047
241771ef
IM		 1048void perf_counter_print_debug(void)
1049{
2f18d1e8 1050 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
0dff86aa 1051 struct cpu_hw_counters *cpuc;
5bb9efe3 1052 unsigned long flags;
1e125676
IM		 1053 int cpu, idx;
1054
0933e5c6 1055 if (!x86_pmu.num_counters)
1e125676 1056 return;
241771ef 1057
5bb9efe3 1058 local_irq_save(flags);
241771ef
IM		 1059
1060 cpu = smp_processor_id();
0dff86aa 1061 cpuc = &per_cpu(cpu_hw_counters, cpu);
241771ef 1062
faa28ae0 1063 if (x86_pmu.version >= 2) {
a1ef58f4
JSR		 1064 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1065 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1066 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1067 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1068
1069 pr_info("\n");
1070 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1071 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1072 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1073 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
f87ad35d 1074 }
43f6201a 1075 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
241771ef 1076
0933e5c6 1077 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
4a06bd85
RR		 1078 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1079 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
241771ef 1080
ee06094f 1081 prev_left = per_cpu(prev_left[idx], cpu);
241771ef 1082
a1ef58f4 1083 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
241771ef 1084 cpu, idx, pmc_ctrl);
a1ef58f4 1085 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
241771ef 1086 cpu, idx, pmc_count);
a1ef58f4 1087 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
ee06094f 1088 cpu, idx, prev_left);
241771ef 1089 }
0933e5c6 1090 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
2f18d1e8
IM		 1091 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1092
a1ef58f4 1093 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
2f18d1e8
IM		 1094 cpu, idx, pmc_count);
1095 }
5bb9efe3 1096 local_irq_restore(flags);
241771ef
IM		 1097}
1098
4aeb0b42 1099static void x86_pmu_disable(struct perf_counter *counter)
241771ef
IM		 1100{
1101 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1102 struct hw_perf_counter *hwc = &counter->hw;
6f00cada 1103 int idx = hwc->idx;
241771ef 1104
09534238
RR		 1105 /*
1106 * Must be done before we disable, otherwise the nmi handler
1107 * could reenable again:
1108 */
43f6201a 1109 clear_bit(idx, cpuc->active_mask);
d4369891 1110 x86_pmu.disable(hwc, idx);
241771ef 1111
2f18d1e8
IM		 1112 /*
1113 * Make sure the cleared pointer becomes visible before we
1114 * (potentially) free the counter:
1115 */
527e26af 1116 barrier();
241771ef 1117
ee06094f
IM		 1118 /*
1119 * Drain the remaining delta count out of a counter
1120 * that we are disabling:
1121 */
1122 x86_perf_counter_update(counter, hwc, idx);
09534238 1123 cpuc->counters[idx] = NULL;
43f6201a 1124 clear_bit(idx, cpuc->used_mask);
241771ef
IM		 1125}
1126
7e2ae347 1127/*
ee06094f
IM		 1128 * Save and restart an expired counter. Called by NMI contexts,
1129 * so it has to be careful about preempting normal counter ops:
7e2ae347 1130 */
e4abb5d4 1131static int intel_pmu_save_and_restart(struct perf_counter *counter)
241771ef
IM		 1132{
1133 struct hw_perf_counter *hwc = &counter->hw;
1134 int idx = hwc->idx;
e4abb5d4 1135 int ret;
241771ef 1136
ee06094f 1137 x86_perf_counter_update(counter, hwc, idx);
e4abb5d4 1138 ret = x86_perf_counter_set_period(counter, hwc, idx);
7e2ae347 1139
2f18d1e8 1140 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
7c90cc45 1141 intel_pmu_enable_counter(hwc, idx);
e4abb5d4
PZ		 1142
1143 return ret;
241771ef
IM		 1144}
1145
aaba9801
IM		 1146static void intel_pmu_reset(void)
1147{
1148 unsigned long flags;
1149 int idx;
1150
1151 if (!x86_pmu.num_counters)
1152 return;
1153
1154 local_irq_save(flags);
1155
1156 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1157
1158 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1159 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1160 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1161 }
1162 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1163 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1164 }
1165
1166 local_irq_restore(flags);
1167}
1168
1169
241771ef
IM		 1170/*
1171 * This handler is triggered by the local APIC, so the APIC IRQ handling
1172 * rules apply:
1173 */
a3288106 1174static int intel_pmu_handle_irq(struct pt_regs *regs)
241771ef 1175{
9029a5e3
IM		 1176 struct cpu_hw_counters *cpuc;
1177 struct cpu_hw_counters;
1178 int bit, cpu, loops;
4b39fd96 1179 u64 ack, status;
9029a5e3
IM		 1180
1181 cpu = smp_processor_id();
1182 cpuc = &per_cpu(cpu_hw_counters, cpu);
241771ef 1183
9e35ad38 1184 perf_disable();
19d84dab 1185 status = intel_pmu_get_status();
9e35ad38
PZ		 1186 if (!status) {
1187 perf_enable();
1188 return 0;
1189 }
87b9cf46 1190
9029a5e3 1191 loops = 0;
241771ef 1192again:
9029a5e3
IM		 1193 if (++loops > 100) {
1194 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
34adc806 1195 perf_counter_print_debug();
aaba9801
IM		 1196 intel_pmu_reset();
1197 perf_enable();
9029a5e3
IM		 1198 return 1;
1199 }
1200
d278c484 1201 inc_irq_stat(apic_perf_irqs);
241771ef 1202 ack = status;
2f18d1e8 1203 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
862a1a5f 1204 struct perf_counter *counter = cpuc->counters[bit];
241771ef
IM		 1205
1206 clear_bit(bit, (unsigned long *) &status);
43f6201a 1207 if (!test_bit(bit, cpuc->active_mask))
241771ef
IM		 1208 continue;
1209
e4abb5d4
PZ		 1210 if (!intel_pmu_save_and_restart(counter))
1211 continue;
1212
a3288106 1213 if (perf_counter_overflow(counter, 1, regs, 0))
d4369891 1214 intel_pmu_disable_counter(&counter->hw, bit);
241771ef
IM		 1215 }
1216
dee5d906 1217 intel_pmu_ack_status(ack);
241771ef
IM		 1218
1219 /*
1220 * Repeat if there is more work to be done:
1221 */
19d84dab 1222 status = intel_pmu_get_status();
241771ef
IM		 1223 if (status)
1224 goto again;
b0f3f28e 1225
48e22d56 1226 perf_enable();
9e35ad38
PZ		 1227
1228 return 1;
1b023a96
MG		 1229}
1230
a3288106 1231static int amd_pmu_handle_irq(struct pt_regs *regs)
a29aa8a7 1232{
48e22d56 1233 int cpu, idx, handled = 0;
9029a5e3 1234 struct cpu_hw_counters *cpuc;
a29aa8a7
RR		 1235 struct perf_counter *counter;
1236 struct hw_perf_counter *hwc;
9029a5e3
IM		 1237 u64 val;
1238
1239 cpu = smp_processor_id();
1240 cpuc = &per_cpu(cpu_hw_counters, cpu);
962bf7a6 1241
a29aa8a7 1242 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
43f6201a 1243 if (!test_bit(idx, cpuc->active_mask))
a29aa8a7 1244 continue;
962bf7a6 1245
a29aa8a7
RR		 1246 counter = cpuc->counters[idx];
1247 hwc = &counter->hw;
a4016a79 1248
4b7bfd0d 1249 val = x86_perf_counter_update(counter, hwc, idx);
a29aa8a7 1250 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
48e22d56 1251 continue;
962bf7a6 1252
a29aa8a7 1253 /* counter overflow */
a29aa8a7
RR		 1254 handled = 1;
1255 inc_irq_stat(apic_perf_irqs);
e4abb5d4
PZ		 1256 if (!x86_perf_counter_set_period(counter, hwc, idx))
1257 continue;
1258
a3288106 1259 if (perf_counter_overflow(counter, 1, regs, 0))
a29aa8a7 1260 amd_pmu_disable_counter(hwc, idx);
a29aa8a7 1261 }
962bf7a6 1262
a29aa8a7
RR		 1263 return handled;
1264}
39d81eab 1265
b6276f35
PZ		 1266void smp_perf_pending_interrupt(struct pt_regs *regs)
1267{
1268 irq_enter();
1269 ack_APIC_irq();
1270 inc_irq_stat(apic_pending_irqs);
1271 perf_counter_do_pending();
1272 irq_exit();
1273}
1274
1275void set_perf_counter_pending(void)
1276{
1277 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1278}
1279
c323d95f 1280void perf_counters_lapic_init(void)
241771ef 1281{
85cf9dba 1282 if (!x86_pmu_initialized())
241771ef 1283 return;
85cf9dba 1284
241771ef 1285 /*
c323d95f 1286 * Always use NMI for PMU
241771ef 1287 */
c323d95f 1288 apic_write(APIC_LVTPC, APIC_DM_NMI);
241771ef
IM		 1289}
1290
1291static int __kprobes
1292perf_counter_nmi_handler(struct notifier_block *self,
1293 unsigned long cmd, void *__args)
1294{
1295 struct die_args *args = __args;
1296 struct pt_regs *regs;
b0f3f28e 1297
ba77813a 1298 if (!atomic_read(&active_counters))
63a809a2
PZ		 1299 return NOTIFY_DONE;
1300
b0f3f28e
PZ		 1301 switch (cmd) {
1302 case DIE_NMI:
1303 case DIE_NMI_IPI:
1304 break;
241771ef 1305
b0f3f28e 1306 default:
241771ef 1307 return NOTIFY_DONE;
b0f3f28e 1308 }
241771ef
IM		 1309
1310 regs = args->regs;
1311
1312 apic_write(APIC_LVTPC, APIC_DM_NMI);
a4016a79
PZ		 1313 /*
1314 * Can't rely on the handled return value to say it was our NMI, two
1315 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1316 *
1317 * If the first NMI handles both, the latter will be empty and daze
1318 * the CPU.
1319 */
a3288106 1320 x86_pmu.handle_irq(regs);
241771ef 1321
a4016a79 1322 return NOTIFY_STOP;
241771ef
IM		 1323}
1324
1325static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
5b75af0a
MG		 1326 .notifier_call = perf_counter_nmi_handler,
1327 .next = NULL,
1328 .priority = 1
241771ef
IM		 1329};
1330
5f4ec28f 1331static struct x86_pmu intel_pmu = {
faa28ae0 1332 .name = "Intel",
39d81eab 1333 .handle_irq = intel_pmu_handle_irq,
9e35ad38
PZ		 1334 .disable_all = intel_pmu_disable_all,
1335 .enable_all = intel_pmu_enable_all,
5f4ec28f
RR		 1336 .enable = intel_pmu_enable_counter,
1337 .disable = intel_pmu_disable_counter,
b56a3802
JSR		 1338 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1339 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5f4ec28f
RR		 1340 .event_map = intel_pmu_event_map,
1341 .raw_event = intel_pmu_raw_event,
b56a3802 1342 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
c619b8ff
RR		 1343 /*
1344 * Intel PMCs cannot be accessed sanely above 32 bit width,
1345 * so we install an artificial 1<<31 period regardless of
1346 * the generic counter period:
1347 */
1348 .max_period = (1ULL << 31) - 1,
b56a3802
JSR		 1349};
1350
5f4ec28f 1351static struct x86_pmu amd_pmu = {
faa28ae0 1352 .name = "AMD",
39d81eab 1353 .handle_irq = amd_pmu_handle_irq,
9e35ad38
PZ		 1354 .disable_all = amd_pmu_disable_all,
1355 .enable_all = amd_pmu_enable_all,
5f4ec28f
RR		 1356 .enable = amd_pmu_enable_counter,
1357 .disable = amd_pmu_disable_counter,
f87ad35d
JSR		 1358 .eventsel = MSR_K7_EVNTSEL0,
1359 .perfctr = MSR_K7_PERFCTR0,
5f4ec28f
RR		 1360 .event_map = amd_pmu_event_map,
1361 .raw_event = amd_pmu_raw_event,
f87ad35d 1362 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
0933e5c6
RR		 1363 .num_counters = 4,
1364 .counter_bits = 48,
1365 .counter_mask = (1ULL << 48) - 1,
c619b8ff
RR		 1366 /* use highest bit to detect overflow */
1367 .max_period = (1ULL << 47) - 1,
f87ad35d
JSR		 1368};
1369
72eae04d 1370static int intel_pmu_init(void)
241771ef 1371{
7bb497bd 1372 union cpuid10_edx edx;
241771ef 1373 union cpuid10_eax eax;
703e937c 1374 unsigned int unused;
7bb497bd 1375 unsigned int ebx;
faa28ae0 1376 int version;
241771ef 1377
da1a776b 1378 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
72eae04d 1379 return -ENODEV;
da1a776b 1380
241771ef
IM		 1381 /*
1382 * Check whether the Architectural PerfMon supports
1383 * Branch Misses Retired Event or not.
1384 */
703e937c 1385 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
241771ef 1386 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
72eae04d 1387 return -ENODEV;
241771ef 1388
faa28ae0
RR		 1389 version = eax.split.version_id;
1390 if (version < 2)
72eae04d 1391 return -ENODEV;
7bb497bd 1392
1123e3ad
IM		 1393 x86_pmu = intel_pmu;
1394 x86_pmu.version = version;
1395 x86_pmu.num_counters = eax.split.num_counters;
1396 x86_pmu.counter_bits = eax.split.bit_width;
1397 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
066d7dea
IM		 1398
1399 /*
1400 * Quirk: v2 perfmon does not report fixed-purpose counters, so
1401 * assume at least 3 counters:
1402 */
1123e3ad 1403 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
b56a3802 1404
9e35ad38
PZ		 1405 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1406
8326f44d 1407 /*
1123e3ad 1408 * Install the hw-cache-events table:
8326f44d
IM		 1409 */
1410 switch (boot_cpu_data.x86_model) {
dc81081b
YW		 1411 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1412 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1413 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1414 case 29: /* six-core 45 nm xeon "Dunnington" */
8326f44d 1415 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
820a6442 1416 sizeof(hw_cache_event_ids));
8326f44d 1417
1123e3ad 1418 pr_cont("Core2 events, ");
8326f44d
IM		 1419 break;
1420 default:
1421 case 26:
1422 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
820a6442 1423 sizeof(hw_cache_event_ids));
8326f44d 1424
1123e3ad 1425 pr_cont("Nehalem/Corei7 events, ");
8326f44d
IM		 1426 break;
1427 case 28:
1428 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
820a6442 1429 sizeof(hw_cache_event_ids));
8326f44d 1430
1123e3ad 1431 pr_cont("Atom events, ");
8326f44d
IM		 1432 break;
1433 }
72eae04d 1434 return 0;
b56a3802
JSR		 1435}
1436
72eae04d 1437static int amd_pmu_init(void)
f87ad35d 1438{
4a06bd85 1439 x86_pmu = amd_pmu;
f86748e9
TG		 1440
1441 switch (boot_cpu_data.x86) {
1442 case 0x0f:
1443 case 0x10:
1444 case 0x11:
1445 memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids,
1446 sizeof(hw_cache_event_ids));
1447
1448 pr_cont("AMD Family 0f/10/11 events, ");
1449 break;
1450 }
72eae04d 1451 return 0;
f87ad35d
JSR		 1452}
1453
b56a3802
JSR		 1454void __init init_hw_perf_counters(void)
1455{
72eae04d
RR		 1456 int err;
1457
1123e3ad
IM		 1458 pr_info("Performance Counters: ");
1459
b56a3802
JSR		 1460 switch (boot_cpu_data.x86_vendor) {
1461 case X86_VENDOR_INTEL:
72eae04d 1462 err = intel_pmu_init();
b56a3802 1463 break;
f87ad35d 1464 case X86_VENDOR_AMD:
72eae04d 1465 err = amd_pmu_init();
f87ad35d 1466 break;
4138960a
RR		 1467 default:
1468 return;
b56a3802 1469 }
1123e3ad
IM		 1470 if (err != 0) {
1471 pr_cont("no PMU driver, software counters only.\n");
b56a3802 1472 return;
1123e3ad 1473 }
b56a3802 1474
1123e3ad 1475 pr_cont("%s PMU driver.\n", x86_pmu.name);
faa28ae0 1476
0933e5c6
RR		 1477 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1478 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
241771ef 1479 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
0933e5c6 1480 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
241771ef 1481 }
0933e5c6
RR		 1482 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1483 perf_max_counters = x86_pmu.num_counters;
241771ef 1484
0933e5c6
RR		 1485 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1486 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
703e937c 1487 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
0933e5c6 1488 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
703e937c 1489 }
862a1a5f 1490
0933e5c6
RR		 1491 perf_counter_mask |=
1492 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
241771ef 1493
c323d95f 1494 perf_counters_lapic_init();
241771ef 1495 register_die_notifier(&perf_counter_nmi_notifier);
1123e3ad
IM		 1496
1497 pr_info("... version: %d\n", x86_pmu.version);
1498 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
1499 pr_info("... generic counters: %d\n", x86_pmu.num_counters);
1500 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
1501 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1502 pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed);
1503 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
241771ef 1504}
621a01ea 1505
bb775fc2 1506static inline void x86_pmu_read(struct perf_counter *counter)
ee06094f
IM		 1507{
1508 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1509}
1510
4aeb0b42
RR		 1511static const struct pmu pmu = {
1512 .enable = x86_pmu_enable,
1513 .disable = x86_pmu_disable,
1514 .read = x86_pmu_read,
a78ac325 1515 .unthrottle = x86_pmu_unthrottle,
621a01ea
IM		 1516};
1517
4aeb0b42 1518const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
621a01ea
IM		 1519{
1520 int err;
1521
1522 err = __hw_perf_counter_init(counter);
1523 if (err)
9ea98e19 1524 return ERR_PTR(err);
621a01ea 1525
4aeb0b42 1526 return &pmu;
621a01ea 1527}
d7d59fb3
PZ		 1528
1529/*
1530 * callchain support
1531 */
1532
1533static inline
1534void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1535{
1536 if (entry->nr < MAX_STACK_DEPTH)
1537 entry->ip[entry->nr++] = ip;
1538}
1539
1540static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1541static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1542
1543
1544static void
1545backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1546{
1547 /* Ignore warnings */
1548}
1549
1550static void backtrace_warning(void *data, char *msg)
1551{
1552 /* Ignore warnings */
1553}
1554
1555static int backtrace_stack(void *data, char *name)
1556{
1557 /* Don't bother with IRQ stacks for now */
1558 return -1;
1559}
1560
1561static void backtrace_address(void *data, unsigned long addr, int reliable)
1562{
1563 struct perf_callchain_entry *entry = data;
1564
1565 if (reliable)
1566 callchain_store(entry, addr);
1567}
1568
1569static const struct stacktrace_ops backtrace_ops = {
1570 .warning = backtrace_warning,
1571 .warning_symbol = backtrace_warning_symbol,
1572 .stack = backtrace_stack,
1573 .address = backtrace_address,
1574};
1575
1576static void
1577perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1578{
1579 unsigned long bp;
1580 char *stack;
5872bdb8 1581 int nr = entry->nr;
d7d59fb3
PZ		 1582
1583 callchain_store(entry, instruction_pointer(regs));
1584
1585 stack = ((char *)regs + sizeof(struct pt_regs));
1586#ifdef CONFIG_FRAME_POINTER
1587 bp = frame_pointer(regs);
1588#else
1589 bp = 0;
1590#endif
1591
1592 dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
5872bdb8
PZ		 1593
1594 entry->kernel = entry->nr - nr;
d7d59fb3
PZ		 1595}
1596
1597
1598struct stack_frame {
1599 const void __user *next_fp;
1600 unsigned long return_address;
1601};
1602
1603static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1604{
1605 int ret;
1606
1607 if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1608 return 0;
1609
1610 ret = 1;
1611 pagefault_disable();
1612 if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1613 ret = 0;
1614 pagefault_enable();
1615
1616 return ret;
1617}
1618
1619static void
1620perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1621{
1622 struct stack_frame frame;
1623 const void __user *fp;
5872bdb8 1624 int nr = entry->nr;
d7d59fb3
PZ		 1625
1626 regs = (struct pt_regs *)current->thread.sp0 - 1;
1627 fp = (void __user *)regs->bp;
1628
1629 callchain_store(entry, regs->ip);
1630
1631 while (entry->nr < MAX_STACK_DEPTH) {
1632 frame.next_fp = NULL;
1633 frame.return_address = 0;
1634
1635 if (!copy_stack_frame(fp, &frame))
1636 break;
1637
1638 if ((unsigned long)fp < user_stack_pointer(regs))
1639 break;
1640
1641 callchain_store(entry, frame.return_address);
1642 fp = frame.next_fp;
1643 }
5872bdb8
PZ		 1644
1645 entry->user = entry->nr - nr;
d7d59fb3
PZ		 1646}
1647
1648static void
1649perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1650{
1651 int is_user;
1652
1653 if (!regs)
1654 return;
1655
1656 is_user = user_mode(regs);
1657
1658 if (!current || current->pid == 0)
1659 return;
1660
1661 if (is_user && current->state != TASK_RUNNING)
1662 return;
1663
1664 if (!is_user)
1665 perf_callchain_kernel(regs, entry);
1666
1667 if (current->mm)
1668 perf_callchain_user(regs, entry);
1669}
1670
1671struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1672{
1673 struct perf_callchain_entry *entry;
1674
1675 if (in_nmi())
1676 entry = &__get_cpu_var(nmi_entry);
1677 else
1678 entry = &__get_cpu_var(irq_entry);
1679
1680 entry->nr = 0;
5872bdb8
PZ		 1681 entry->hv = 0;
1682 entry->kernel = 0;
1683 entry->user = 0;
d7d59fb3
PZ		 1684
1685 perf_do_callchain(regs, entry);
1686
1687 return entry;
1688}
Linux kernel - Deliverables
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